2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "ia32_emitter.h"
28 #include "gen_ia32_emitter.h"
29 #include "gen_ia32_regalloc_if.h"
30 #include "ia32_nodes_attr.h"
31 #include "ia32_new_nodes.h"
32 #include "ia32_map_regs.h"
33 #include "bearch_ia32_t.h"
35 #define BLOCK_PREFIX(x) ".L" x
37 #define SNPRINTF_BUF_LEN 128
39 /* global arch_env for lc_printf functions */
40 static const arch_env_t *arch_env = NULL;
42 /** by default, we generate assembler code for the Linux gas */
43 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
46 * Switch to a new section
48 void ia32_switch_section(FILE *F, section_t sec) {
49 static section_t curr_sec = NO_SECTION;
50 static const char *text[ASM_MAX][SECTION_MAX] = {
52 ".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
55 ".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text"
72 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
76 static void ia32_dump_function_object(FILE *F, const char *name)
78 switch (asm_flavour) {
80 fprintf(F, "\t.type\t%s, @function\n", name);
83 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
88 static void ia32_dump_function_size(FILE *F, const char *name)
90 switch (asm_flavour) {
92 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
97 /*************************************************************
99 * (_) | | / _| | | | |
100 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
101 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
102 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
103 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
106 *************************************************************/
108 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
110 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
111 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
112 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
116 * returns true if a node has x87 registers
118 static INLINE int has_x87_register(const ir_node *n) {
119 return is_irn_machine_user(n, 0);
122 /* We always pass the ir_node which is a pointer. */
123 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
124 return lc_arg_type_ptr;
129 * Returns the register at in position pos.
131 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
133 const arch_register_t *reg = NULL;
135 assert(get_irn_arity(irn) > pos && "Invalid IN position");
137 /* The out register of the operator at position pos is the
138 in register we need. */
139 op = get_irn_n(irn, pos);
141 reg = arch_get_irn_register(arch_env, op);
143 assert(reg && "no in register found");
145 /* in case of unknown: just return a register */
146 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
147 reg = &ia32_gp_regs[REG_EAX];
148 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
149 reg = &ia32_xmm_regs[REG_XMM0];
150 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
151 reg = &ia32_vfp_regs[REG_VF0];
157 * Returns the register at out position pos.
159 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
161 const arch_register_t *reg = NULL;
163 /* 1st case: irn is not of mode_T, so it has only */
164 /* one OUT register -> good */
165 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
166 /* Proj with the corresponding projnum for the register */
168 if (get_irn_mode(irn) != mode_T) {
169 reg = arch_get_irn_register(arch_env, irn);
171 else if (is_ia32_irn(irn)) {
172 reg = get_ia32_out_reg(irn, pos);
175 const ir_edge_t *edge;
177 foreach_out_edge(irn, edge) {
178 proj = get_edge_src_irn(edge);
179 assert(is_Proj(proj) && "non-Proj from mode_T node");
180 if (get_Proj_proj(proj) == pos) {
181 reg = arch_get_irn_register(arch_env, proj);
187 assert(reg && "no out register found");
197 * Returns the name of the in register at position pos.
199 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
200 const arch_register_t *reg;
202 if (in_out == IN_REG) {
203 reg = get_in_reg(irn, pos);
205 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
206 /* FIXME: works for binop only */
207 assert(2 <= pos && pos <= 3);
208 reg = get_ia32_attr(irn)->x87[pos - 2];
212 /* destination address mode nodes don't have outputs */
213 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
217 reg = get_out_reg(irn, pos);
218 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
219 reg = get_ia32_attr(irn)->x87[pos + 2];
221 return arch_register_get_name(reg);
225 * Get the register name for a node.
227 static int ia32_get_reg_name(lc_appendable_t *app,
228 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
231 ir_node *irn = arg->v_ptr;
232 int nr = occ->width - 1;
235 return lc_appendable_snadd(app, "(null)", 6);
237 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
239 /* append the stupid % to register names */
240 lc_appendable_chadd(app, '%');
241 return lc_appendable_snadd(app, buf, strlen(buf));
245 * Get the x87 register name for a node.
247 static int ia32_get_x87_name(lc_appendable_t *app,
248 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
251 ir_node *irn = arg->v_ptr;
252 int nr = occ->width - 1;
256 return lc_appendable_snadd(app, "(null)", 6);
258 attr = get_ia32_attr(irn);
259 buf = attr->x87[nr]->name;
260 lc_appendable_chadd(app, '%');
261 return lc_appendable_snadd(app, buf, strlen(buf));
265 * Returns the tarval, offset or scale of an ia32 as a string.
267 static int ia32_const_to_str(lc_appendable_t *app,
268 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
271 ir_node *irn = arg->v_ptr;
274 return lc_arg_append(app, occ, "(null)", 6);
276 if (occ->conversion == 'C') {
277 buf = get_ia32_cnst(irn);
280 buf = get_ia32_am_offs(irn);
283 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
287 * Determines the SSE suffix depending on the mode.
289 static int ia32_get_mode_suffix(lc_appendable_t *app,
290 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
292 ir_node *irn = arg->v_ptr;
293 ir_mode *mode = get_irn_mode(irn);
295 if (mode == mode_T) {
296 mode = (is_ia32_Ld(irn) || is_ia32_St(irn)) ? get_ia32_ls_mode(irn) : get_ia32_res_mode(irn);
300 return lc_arg_append(app, occ, "(null)", 6);
302 if (mode_is_float(mode)) {
303 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
306 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
311 * Return the ia32 printf arg environment.
312 * We use the firm environment with some additional handlers.
314 const lc_arg_env_t *ia32_get_arg_env(void) {
315 static lc_arg_env_t *env = NULL;
317 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
318 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
319 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
320 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
323 /* extend the firm printer */
324 env = firm_get_arg_env();
326 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
327 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
328 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
329 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
330 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
331 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
337 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
338 switch(get_mode_size_bits(mode)) {
340 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
342 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
344 return (char *)arch_register_get_name(reg);
349 * Emits registers and/or address mode of a binary operation.
351 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
352 static char *buf = NULL;
354 /* verify that this function is never called on non-AM supporting operations */
355 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
357 #define PRODUCES_RESULT(n) \
358 (!(is_ia32_St(n) || \
359 is_ia32_Store8Bit(n) || \
360 is_ia32_CondJmp(n) || \
361 is_ia32_xCondJmp(n) || \
362 is_ia32_CmpSet(n) || \
363 is_ia32_xCmpSet(n) || \
364 is_ia32_SwitchJmp(n)))
367 buf = xcalloc(1, SNPRINTF_BUF_LEN);
370 memset(buf, 0, SNPRINTF_BUF_LEN);
373 switch(get_ia32_op_type(n)) {
375 if (is_ia32_ImmConst(n)) {
376 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
378 else if (is_ia32_ImmSymConst(n)) {
379 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
382 const arch_register_t *in1 = get_in_reg(n, 2);
383 const arch_register_t *in2 = get_in_reg(n, 3);
384 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
385 const arch_register_t *in;
388 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
389 out = out ? out : in1;
390 in_name = arch_register_get_name(in);
392 if (is_ia32_emit_cl(n)) {
393 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
397 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
401 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
402 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
403 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
406 if (PRODUCES_RESULT(n)) {
407 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
410 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
415 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
416 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
417 ia32_emit_am(n, env),
418 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
419 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
422 const arch_register_t *in1 = get_in_reg(n, 2);
423 ir_mode *mode = get_ia32_res_mode(n);
426 mode = mode ? mode : get_ia32_ls_mode(n);
427 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
429 if (is_ia32_emit_cl(n)) {
430 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
434 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
438 assert(0 && "unsupported op type");
441 #undef PRODUCES_RESULT
447 * Returns the xxx PTR string for a given mode
449 * @param mode the mode
450 * @param x87_insn if non-zero returns the string for a x87 instruction
451 * else for a SSE instruction
453 static const char *pointer_size(ir_mode *mode, int x87_insn)
456 switch (get_mode_size_bits(mode)) {
457 case 8: return "BYTE PTR";
458 case 16: return "WORD PTR";
459 case 32: return "DWORD PTR";
465 case 96: return "XWORD PTR";
466 default: return NULL;
473 * Emits registers and/or address mode of a binary operation.
475 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
476 static char *buf = NULL;
478 /* verify that this function is never called on non-AM supporting operations */
479 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
482 buf = xcalloc(1, SNPRINTF_BUF_LEN);
485 memset(buf, 0, SNPRINTF_BUF_LEN);
488 switch(get_ia32_op_type(n)) {
490 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
491 ir_mode *mode = get_ia32_ls_mode(n);
492 const char *p = pointer_size(mode, 1);
493 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
496 ia32_attr_t *attr = get_ia32_attr(n);
497 const arch_register_t *in1 = attr->x87[0];
498 const arch_register_t *in2 = attr->x87[1];
499 const arch_register_t *out = attr->x87[2];
500 const arch_register_t *in;
503 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
504 out = out ? out : in1;
505 in_name = arch_register_get_name(in);
507 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
512 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
515 assert(0 && "unsupported op type");
522 * Emits registers and/or address mode of a unary operation.
524 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
525 static char *buf = NULL;
528 buf = xcalloc(1, SNPRINTF_BUF_LEN);
531 memset(buf, 0, SNPRINTF_BUF_LEN);
534 switch(get_ia32_op_type(n)) {
536 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
537 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
540 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
541 /* MulS and Mulh implicitly multiply by EAX */
542 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
545 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
549 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
553 Mulh is emitted via emit_unop
554 imul [MEM] means EDX:EAX <- EAX * [MEM]
556 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
557 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
560 assert(0 && "unsupported op type");
567 * Emits address mode.
569 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
570 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
575 static struct obstack *obst = NULL;
576 ir_mode *mode = get_ia32_ls_mode(n);
578 if (! is_ia32_Lea(n))
579 assert(mode && "AM node must have ls_mode attribute set.");
582 obst = xcalloc(1, sizeof(*obst));
585 obstack_free(obst, NULL);
588 /* obstack_free with NULL results in an uninitialized obstack */
591 p = pointer_size(mode, has_x87_register(n));
593 obstack_printf(obst, "%s ", p);
595 /* emit address mode symconst */
596 if (get_ia32_am_sc(n)) {
597 if (is_ia32_am_sc_sign(n))
598 obstack_printf(obst, "-");
599 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
602 if (am_flav & ia32_B) {
603 obstack_printf(obst, "[");
604 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
608 if (am_flav & ia32_I) {
610 obstack_printf(obst, "+");
613 obstack_printf(obst, "[");
616 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
618 if (am_flav & ia32_S) {
619 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
625 if (am_flav & ia32_O) {
626 s = get_ia32_am_offs(n);
629 /* omit explicit + if there was no base or index */
631 obstack_printf(obst, "[");
636 obstack_printf(obst, s);
642 obstack_printf(obst, "] ");
644 obstack_1grow(obst, '\0');
645 s = obstack_finish(obst);
653 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
655 static char buf[SNPRINTF_BUF_LEN];
656 ir_mode *mode = get_ia32_ls_mode(irn);
657 const char *adr = get_ia32_cnst(irn);
658 const char *pref = pointer_size(mode, has_x87_register(irn));
660 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
665 * Formated print of commands and comments.
667 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
669 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
672 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
674 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
680 * Add a number to a prefix. This number will not be used a second time.
682 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
683 static unsigned long id = 0;
684 snprintf(buf, buflen, "%s%lu", prefix, ++id);
690 /*************************************************
693 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
694 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
695 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
696 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
698 *************************************************/
701 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
704 * coding of conditions
706 struct cmp2conditon_t {
712 * positive conditions for signed compares
714 static const struct cmp2conditon_t cmp2condition_s[] = {
715 { NULL, pn_Cmp_False }, /* always false */
716 { "e", pn_Cmp_Eq }, /* == */
717 { "l", pn_Cmp_Lt }, /* < */
718 { "le", pn_Cmp_Le }, /* <= */
719 { "g", pn_Cmp_Gt }, /* > */
720 { "ge", pn_Cmp_Ge }, /* >= */
721 { "ne", pn_Cmp_Lg }, /* != */
722 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
723 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
724 { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
725 { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
726 { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
727 { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
728 { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
729 { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
730 { NULL, pn_Cmp_True }, /* always true */
734 * positive conditions for unsigned compares
736 static const struct cmp2conditon_t cmp2condition_u[] = {
737 { NULL, pn_Cmp_False }, /* always false */
738 { "e", pn_Cmp_Eq }, /* == */
739 { "b", pn_Cmp_Lt }, /* < */
740 { "be", pn_Cmp_Le }, /* <= */
741 { "a", pn_Cmp_Gt }, /* > */
742 { "ae", pn_Cmp_Ge }, /* >= */
743 { "ne", pn_Cmp_Lg }, /* != */
744 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
745 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
746 { "unordered or ==", pn_Cmp_Ue }, /* Floating point: unordered or == */
747 { "unordered or <", pn_Cmp_Ul }, /* Floating point: unordered or < */
748 { "unordered or <=", pn_Cmp_Ule }, /* Floating point: unordered or <= */
749 { "unordered or >", pn_Cmp_Ug }, /* Floating point: unordered or > */
750 { "unordered or >=", pn_Cmp_Uge }, /* Floating point: unordered or >= */
751 { "unordered or !=", pn_Cmp_Ne }, /* Floating point: unordered or != */
752 { NULL, pn_Cmp_True }, /* always true */
756 * returns the condition code
758 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
760 assert(cmp2condition_s[cmp_code].num == cmp_code);
761 assert(cmp2condition_u[cmp_code].num == cmp_code);
763 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
767 * Returns the target block for a control flow node.
769 static ir_node *get_cfop_target_block(const ir_node *irn) {
770 return get_irn_link(irn);
774 * Returns the target label for a control flow node.
776 static char *get_cfop_target(const ir_node *irn, char *buf) {
777 ir_node *bl = get_cfop_target_block(irn);
779 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
783 /** Return the next block in Block schedule */
784 static ir_node *next_blk_sched(const ir_node *block) {
785 return get_irn_link(block);
789 * Returns the Proj with projection number proj and NOT mode_M
791 static ir_node *get_proj(const ir_node *irn, long proj) {
792 const ir_edge_t *edge;
795 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
797 foreach_out_edge(irn, edge) {
798 src = get_edge_src_irn(edge);
800 assert(is_Proj(src) && "Proj expected");
801 if (get_irn_mode(src) == mode_M)
804 if (get_Proj_proj(src) == proj)
811 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
813 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
814 const ir_node *proj1, *proj2 = NULL;
815 const ir_node *block, *next_bl = NULL;
816 char buf[SNPRINTF_BUF_LEN];
817 char cmd_buf[SNPRINTF_BUF_LEN];
818 char cmnt_buf[SNPRINTF_BUF_LEN];
820 /* get both Proj's */
821 proj1 = get_proj(irn, pn_Cond_true);
822 assert(proj1 && "CondJmp without true Proj");
824 proj2 = get_proj(irn, pn_Cond_false);
825 assert(proj2 && "CondJmp without false Proj");
827 /* for now, the code works for scheduled and non-schedules blocks */
828 block = get_nodes_block(irn);
830 /* we have a block schedule */
831 next_bl = next_blk_sched(block);
833 if (get_cfop_target_block(proj1) == next_bl) {
834 /* exchange both proj's so the second one can be omitted */
835 const ir_node *t = proj1;
840 /* the first Proj must always be created */
841 if (get_Proj_proj(proj1) == pn_Cond_true) {
842 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
843 get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
844 get_cfop_target(proj1, buf));
845 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */");
848 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
849 get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode),
850 ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0)))),
851 get_cfop_target(proj1, buf));
852 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */");
856 /* the second Proj might be a fallthrough */
857 if (get_cfop_target_block(proj2) != next_bl) {
858 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
859 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
863 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf));
869 * Emits code for conditional jump.
871 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
873 char cmd_buf[SNPRINTF_BUF_LEN];
874 char cmnt_buf[SNPRINTF_BUF_LEN];
876 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
877 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
879 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
883 * Emits code for conditional jump with two variables.
885 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
886 CondJmp_emitter(irn, env);
890 * Emits code for conditional test and jump.
892 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
894 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
897 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
898 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
899 char cmd_buf[SNPRINTF_BUF_LEN];
900 char cmnt_buf[SNPRINTF_BUF_LEN];
903 op2 = arch_register_get_name(get_in_reg(irn, 1));
905 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
906 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
909 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
915 * Emits code for conditional test and jump with two variables.
917 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
918 TestJmp_emitter(irn, env);
921 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
923 char cmd_buf[SNPRINTF_BUF_LEN];
924 char cmnt_buf[SNPRINTF_BUF_LEN];
926 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
927 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
929 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
932 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
934 char cmd_buf[SNPRINTF_BUF_LEN];
935 char cmnt_buf[SNPRINTF_BUF_LEN];
937 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
938 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
940 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
944 * Emits code for conditional SSE floating point jump with two variables.
946 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
948 char cmd_buf[SNPRINTF_BUF_LEN];
949 char cmnt_buf[SNPRINTF_BUF_LEN];
951 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
952 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
954 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
959 * Emits code for conditional x87 floating point jump with two variables.
961 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
963 char cmd_buf[SNPRINTF_BUF_LEN];
964 char cmnt_buf[SNPRINTF_BUF_LEN];
965 ia32_attr_t *attr = get_ia32_attr(irn);
966 const char *reg = attr->x87[1]->name;
967 const char *instr = "fcom";
970 switch (get_ia32_pncode(irn)) {
971 case iro_ia32_fcomrJmp:
973 case iro_ia32_fcomJmp:
977 case iro_ia32_fcomrpJmp:
979 case iro_ia32_fcompJmp:
982 case iro_ia32_fcomrppJmp:
984 case iro_ia32_fcomppJmp:
991 set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is));
993 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s", instr, reg);
994 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
996 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
997 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
999 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1000 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1003 finish_CondJmp(F, irn, mode_Is);
1006 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1008 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1009 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
1010 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1012 char cmd_buf[SNPRINTF_BUF_LEN];
1013 char cmnt_buf[SNPRINTF_BUF_LEN];
1014 const arch_register_t *in1, *in2, *out;
1016 out = arch_get_irn_register(env->arch_env, irn);
1017 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2 - is_PsiCondCMov));
1018 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3 - is_PsiCondCMov));
1020 /* we have to emit the cmp first, because the destination register */
1021 /* could be one of the compare registers */
1022 if (is_ia32_CmpCMov(irn)) {
1023 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1025 else if (is_ia32_xCmpCMov(irn)) {
1026 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1028 else if (is_PsiCondCMov) {
1029 /* omit compare because flags are already set by And/Or */
1030 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1033 assert(0 && "unsupported CMov");
1035 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1038 if (REGS_ARE_EQUAL(out, in2)) {
1039 /* best case: default in == out -> do nothing */
1041 else if (REGS_ARE_EQUAL(out, in1)) {
1042 /* true in == out -> need complement compare and exchange true and default in */
1043 ir_node *t = get_irn_n(irn, 2);
1044 set_irn_n(irn, 2, get_irn_n(irn, 3));
1045 set_irn_n(irn, 3, t);
1047 cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
1051 /* out is different from in: need copy default -> out */
1052 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1053 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1057 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1058 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1062 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1063 CMov_emitter(irn, env);
1066 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1067 CMov_emitter(irn, env);
1070 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1071 CMov_emitter(irn, env);
1074 static void Set_emitter(ir_node *irn, ia32_emit_env_t *env) {
1076 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1077 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), ! mode_is_signed(get_irn_mode(get_irn_n(irn, 0))));
1078 const char *instr = "xor";
1079 const char *reg8bit;
1081 char cmd_buf[SNPRINTF_BUF_LEN];
1082 char cmnt_buf[SNPRINTF_BUF_LEN];
1083 const arch_register_t *out;
1085 out = arch_get_irn_register(env->arch_env, irn);
1086 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1088 if (env->isa->opt_arch == arch_pentium_4) {
1089 /* P4 prefers sub r, r, others xor r, r */
1093 if (is_ia32_CmpSet(irn)) {
1094 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1096 else if (is_ia32_xCmpSet(irn)) {
1097 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 0), ia32_emit_binop(irn, env));
1099 else if (is_ia32_PsiCondSet(irn)) {
1100 /* omit compare because flags are already set by And/Or */
1101 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1104 assert(0 && "unsupported Set");
1106 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1109 /* use mov to clear target because it doesn't affect the eflags */
1110 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1111 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1114 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1115 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1119 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1120 Set_emitter(irn, env);
1123 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1124 Set_emitter(irn, env);
1127 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1128 Set_emitter(irn, env);
1131 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1133 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1135 char cmd_buf[SNPRINTF_BUF_LEN];
1136 char cmnt_buf[SNPRINTF_BUF_LEN];
1138 switch (get_ia32_pncode(irn)) {
1139 case pn_Cmp_Leg: /* odered */
1142 case pn_Cmp_Uo: /* unordered */
1145 case pn_Cmp_Ue: /* == */
1148 case pn_Cmp_Ul: /* < */
1151 case pn_Cmp_Ule: /* <= */
1154 case pn_Cmp_Ug: /* > */
1157 case pn_Cmp_Uge: /* >= */
1160 case pn_Cmp_Ne: /* != */
1165 assert(sse_pnc >= 0 && "unsupported floating point compare");
1167 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc);
1168 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn);
1172 /*********************************************************
1175 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1176 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1177 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1178 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1181 *********************************************************/
1183 /* jump table entry (target and corresponding number) */
1184 typedef struct _branch_t {
1189 /* jump table for switch generation */
1190 typedef struct _jmp_tbl_t {
1191 ir_node *defProj; /**< default target */
1192 int min_value; /**< smallest switch case */
1193 int max_value; /**< largest switch case */
1194 int num_branches; /**< number of jumps */
1195 char *label; /**< label of the jump table */
1196 branch_t *branches; /**< jump array */
1200 * Compare two variables of type branch_t. Used to sort all switch cases
1202 static int ia32_cmp_branch_t(const void *a, const void *b) {
1203 branch_t *b1 = (branch_t *)a;
1204 branch_t *b2 = (branch_t *)b;
1206 if (b1->value <= b2->value)
1213 * Emits code for a SwitchJmp (creates a jump table if
1214 * possible otherwise a cmp-jmp cascade). Port from
1217 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1218 unsigned long interval;
1219 char buf[SNPRINTF_BUF_LEN];
1220 int last_value, i, pn;
1223 const ir_edge_t *edge;
1224 const lc_arg_env_t *env = ia32_get_arg_env();
1225 FILE *F = emit_env->out;
1226 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1228 /* fill the table structure */
1229 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1230 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1232 tbl.num_branches = get_irn_n_edges(irn);
1233 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1234 tbl.min_value = INT_MAX;
1235 tbl.max_value = INT_MIN;
1238 /* go over all proj's and collect them */
1239 foreach_out_edge(irn, edge) {
1240 proj = get_edge_src_irn(edge);
1241 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1243 pn = get_Proj_proj(proj);
1245 /* create branch entry */
1246 tbl.branches[i].target = proj;
1247 tbl.branches[i].value = pn;
1249 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1250 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1252 /* check for default proj */
1253 if (pn == get_ia32_pncode(irn)) {
1254 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1261 /* sort the branches by their number */
1262 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1264 /* two-complement's magic make this work without overflow */
1265 interval = tbl.max_value - tbl.min_value;
1267 /* emit the table */
1268 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1269 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1272 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1273 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1276 if (tbl.num_branches > 1) {
1279 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1280 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1283 ia32_switch_section(F, SECTION_RODATA);
1284 fprintf(F, "\t.align 4\n");
1286 fprintf(F, "%s:\n", tbl.label);
1288 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1289 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1292 last_value = tbl.branches[0].value;
1293 for (i = 1; i < tbl.num_branches; ++i) {
1294 while (++last_value < tbl.branches[i].value) {
1295 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1296 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1299 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1300 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1303 ia32_switch_section(F, SECTION_TEXT);
1306 /* one jump is enough */
1307 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1308 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1319 * Emits code for a unconditional jump.
1321 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1322 ir_node *block, *next_bl;
1324 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1326 /* for now, the code works for scheduled and non-schedules blocks */
1327 block = get_nodes_block(irn);
1329 /* we have a block schedule */
1330 next_bl = next_blk_sched(block);
1331 if (get_cfop_target_block(irn) != next_bl) {
1332 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1333 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1337 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1342 /****************************
1345 * _ __ _ __ ___ _ ___
1346 * | '_ \| '__/ _ \| |/ __|
1347 * | |_) | | | (_) | |\__ \
1348 * | .__/|_| \___/| ||___/
1351 ****************************/
1354 * Emits code for a proj -> node
1356 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1357 ir_node *pred = get_Proj_pred(irn);
1359 if (get_irn_op(pred) == op_Start) {
1360 switch(get_Proj_proj(irn)) {
1361 case pn_Start_X_initial_exec:
1370 /**********************************
1373 * | | ___ _ __ _ _| |_) |
1374 * | | / _ \| '_ \| | | | _ <
1375 * | |___| (_) | |_) | |_| | |_) |
1376 * \_____\___/| .__/ \__, |____/
1379 **********************************/
1382 * Emit movsb/w instructions to make mov count divideable by 4
1384 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1385 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1387 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1389 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1390 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1395 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1396 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1400 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1401 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1405 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1406 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1408 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1409 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1417 * Emit rep movsd instruction for memcopy.
1419 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1420 FILE *F = emit_env->out;
1421 tarval *tv = get_ia32_Immop_tarval(irn);
1422 int rem = get_tarval_long(tv);
1423 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1425 emit_CopyB_prolog(F, irn, rem);
1427 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1428 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1433 * Emits unrolled memcopy.
1435 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1436 tarval *tv = get_ia32_Immop_tarval(irn);
1437 int size = get_tarval_long(tv);
1438 FILE *F = emit_env->out;
1439 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1441 emit_CopyB_prolog(F, irn, size & 0x3);
1445 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1446 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1453 /***************************
1457 * | | / _ \| '_ \ \ / /
1458 * | |___| (_) | | | \ V /
1459 * \_____\___/|_| |_|\_/
1461 ***************************/
1464 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1466 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1467 FILE *F = emit_env->out;
1468 const lc_arg_env_t *env = ia32_get_arg_env();
1469 ir_mode *src_mode = get_ia32_src_mode(irn);
1470 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1471 char *from, *to, buf[64];
1472 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1474 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1475 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1477 switch(get_ia32_op_type(irn)) {
1479 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1481 case ia32_AddrModeS:
1482 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1485 assert(0 && "unsupported op type for Conv");
1488 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1489 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1493 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1494 emit_ia32_Conv_with_FP(irn, emit_env);
1497 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1498 emit_ia32_Conv_with_FP(irn, emit_env);
1501 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1502 emit_ia32_Conv_with_FP(irn, emit_env);
1506 * Emits code for an Int conversion.
1508 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1509 FILE *F = emit_env->out;
1510 const lc_arg_env_t *env = ia32_get_arg_env();
1511 char *move_cmd = "movzx";
1512 char *conv_cmd = NULL;
1513 ir_mode *src_mode = get_ia32_src_mode(irn);
1514 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1516 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1517 const arch_register_t *in_reg, *out_reg;
1519 n = get_mode_size_bits(src_mode);
1520 m = get_mode_size_bits(tgt_mode);
1522 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1524 if (n == 8 || m == 8)
1526 else if (n == 16 || m == 16)
1529 assert(0 && "unsupported Conv_I2I");
1532 switch(get_ia32_op_type(irn)) {
1534 in_reg = get_in_reg(irn, 2);
1535 out_reg = get_out_reg(irn, 0);
1537 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1538 REGS_ARE_EQUAL(out_reg, in_reg) &&
1539 mode_is_signed(n < m ? src_mode : tgt_mode))
1541 /* argument and result are both in EAX and */
1542 /* signedness is ok: -> use converts */
1543 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1545 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1546 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1548 /* argument and result are in the same register */
1549 /* and signedness is ok: -> use and with mask */
1550 int mask = (1 << (n < m ? n : m)) - 1;
1551 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1554 /* use move w/o sign extension */
1555 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1556 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1560 case ia32_AddrModeS:
1561 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1562 move_cmd, irn, ia32_emit_am(irn, emit_env));
1565 assert(0 && "unsupported op type for Conv");
1568 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1569 irn, n, src_mode, m, tgt_mode);
1575 * Emits code for an 8Bit Int conversion.
1577 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1578 emit_ia32_Conv_I2I(irn, emit_env);
1582 /*******************************************
1585 * | |__ ___ _ __ ___ __| | ___ ___
1586 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1587 * | |_) | __/ | | | (_) | (_| | __/\__ \
1588 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1590 *******************************************/
1593 * Emits a backend call
1595 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1596 FILE *F = emit_env->out;
1597 entity *ent = be_Call_get_entity(irn);
1598 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1601 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1604 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1607 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1613 * Emits code to increase stack pointer.
1615 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1616 FILE *F = emit_env->out;
1617 unsigned offs = be_get_IncSP_offset(irn);
1618 be_stack_dir_t dir = be_get_IncSP_direction(irn);
1619 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1622 if (dir == be_stack_dir_expand)
1623 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1625 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, offs);
1626 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1629 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1630 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1637 * Emits code to set stack pointer.
1639 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1640 FILE *F = emit_env->out;
1641 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1643 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1644 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1649 * Emits code for Copy/CopyKeep.
1651 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1652 FILE *F = emit_env->out;
1653 const arch_env_t *aenv = emit_env->arch_env;
1654 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1656 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1657 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1660 if (mode_is_float(get_irn_mode(irn)))
1661 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1663 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1664 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1668 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1669 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1672 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1673 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1677 * Emits code for exchange.
1679 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1680 FILE *F = emit_env->out;
1681 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1682 const arch_register_t *in1, *in2;
1683 const arch_register_class_t *cls1, *cls2;
1685 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1686 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1688 cls1 = arch_register_get_class(in1);
1689 cls2 = arch_register_get_class(in2);
1691 assert(cls1 == cls2 && "Register class mismatch at Perm");
1693 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1694 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1696 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1697 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1698 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1700 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1701 assert(0 && "Perm with vfp should not happen");
1703 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1704 assert(0 && "Perm with st(X) should not happen");
1707 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1712 * Emits code for Constant loading.
1714 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1716 char cmd_buf[256], cmnt_buf[256];
1717 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1719 if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
1720 const char *instr = "xor";
1721 if (env->isa->opt_arch == arch_pentium_4) {
1722 /* P4 prefers sub r, r, others xor r, r */
1725 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1726 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1729 if (get_ia32_op_type(n) == ia32_SymConst) {
1730 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1731 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1734 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1735 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1738 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1741 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1743 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1745 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1750 /***********************************************************************************
1753 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1754 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1755 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1756 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1758 ***********************************************************************************/
1761 * Enters the emitter functions for handled nodes into the generic
1762 * pointer of an opcode.
1764 static void ia32_register_emitters(void) {
1766 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1767 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1768 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1769 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1771 /* first clear the generic function pointer for all ops */
1772 clear_irp_opcodes_generic_func();
1774 /* register all emitter functions defined in spec */
1775 ia32_register_spec_emitters();
1777 /* other ia32 emitter functions */
1783 IA32_EMIT(PsiCondCMov);
1785 IA32_EMIT(PsiCondSet);
1786 IA32_EMIT(SwitchJmp);
1789 IA32_EMIT(Conv_I2FP);
1790 IA32_EMIT(Conv_FP2I);
1791 IA32_EMIT(Conv_FP2FP);
1792 IA32_EMIT(Conv_I2I);
1793 IA32_EMIT(Conv_I2I8Bit);
1797 IA32_EMIT(xCmpCMov);
1798 IA32_EMIT(xCondJmp);
1799 IA32_EMIT2(fcomJmp, x87CondJmp);
1800 IA32_EMIT2(fcompJmp, x87CondJmp);
1801 IA32_EMIT2(fcomppJmp, x87CondJmp);
1802 IA32_EMIT2(fcomrJmp, x87CondJmp);
1803 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1804 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1806 /* benode emitter */
1826 * Emits code for a node.
1828 static void ia32_emit_node(const ir_node *irn, void *env) {
1829 ia32_emit_env_t *emit_env = env;
1830 FILE *F = emit_env->out;
1831 ir_op *op = get_irn_op(irn);
1832 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
1834 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
1836 if (op->ops.generic) {
1837 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
1841 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", irn, irn);
1846 * Emits gas alignment directives
1848 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
1849 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
1853 * Emits gas alignment directives for Functions depended on cpu architecture.
1855 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
1856 unsigned align; unsigned maximum_skip;
1858 /* gcc doesn't emit alignment for p4 ?*/
1859 if (cpu == arch_pentium_4)
1864 align = 2; maximum_skip = 3;
1867 align = 4; maximum_skip = 15;
1870 align = 5; maximum_skip = 31;
1873 align = 4; maximum_skip = 15;
1875 ia32_emit_alignment(F, align, maximum_skip);
1879 * Emits gas alignment directives for Labels depended on cpu architecture.
1881 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
1882 unsigned align; unsigned maximum_skip;
1884 /* gcc doesn't emit alignment for p4 ?*/
1885 if (cpu == arch_pentium_4)
1890 align = 2; maximum_skip = 3;
1893 align = 4; maximum_skip = 15;
1896 align = 5; maximum_skip = 7;
1899 align = 4; maximum_skip = 7;
1901 ia32_emit_alignment(F, align, maximum_skip);
1905 * Walks over the nodes in a block connected by scheduling edges
1906 * and emits code for each node.
1908 static void ia32_gen_block(ir_node *block, void *env) {
1909 ia32_emit_env_t *emit_env = env;
1911 int need_label = block != get_irg_start_block(get_irn_irg(block));
1913 if (! is_Block(block))
1916 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
1917 /* if the extended block scheduler is used, only leader blocks need
1919 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
1923 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
1924 fprintf(emit_env->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
1927 sched_foreach(block, irn) {
1928 ia32_emit_node(irn, env);
1933 * Emits code for function start.
1935 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
1936 entity *irg_ent = get_irg_entity(irg);
1937 const char *irg_name = get_entity_ld_name(irg_ent);
1940 ia32_switch_section(F, SECTION_TEXT);
1941 ia32_emit_align_func(F, cpu);
1942 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
1943 fprintf(F, ".globl %s\n", irg_name);
1945 ia32_dump_function_object(F, irg_name);
1946 fprintf(F, "%s:\n", irg_name);
1950 * Emits code for function end
1952 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
1953 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
1955 ia32_dump_function_size(F, irg_name);
1961 * Sets labels for control flow nodes (jump target)
1962 * TODO: Jump optimization
1964 static void ia32_gen_labels(ir_node *block, void *env) {
1966 int n = get_Block_n_cfgpreds(block);
1968 for (n--; n >= 0; n--) {
1969 pred = get_Block_cfgpred(block, n);
1970 set_irn_link(pred, block);
1975 * Main driver. Emits the code for one routine.
1977 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
1978 ia32_emit_env_t emit_env;
1982 emit_env.arch_env = cg->arch_env;
1984 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
1985 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
1987 /* set the global arch_env (needed by print hooks) */
1988 arch_env = cg->arch_env;
1990 ia32_register_emitters();
1992 ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
1993 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
1995 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
1996 int i, n = ARR_LEN(cg->blk_sched);
1998 for (i = 0; i < n;) {
2001 block = cg->blk_sched[i];
2003 next_bl = i < n ? cg->blk_sched[i] : NULL;
2005 /* set here the link. the emitter expects to find the next block here */
2006 set_irn_link(block, next_bl);
2007 ia32_gen_block(block, &emit_env);
2011 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2012 in the block schedule. As this number should NEVER be equal the next block,
2013 we does not need a clear block link here. */
2014 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2017 ia32_emit_func_epilog(F, irg);