2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
42 #include "raw_bitset.h"
45 #include "../besched_t.h"
46 #include "../benode_t.h"
48 #include "../be_dbgout.h"
49 #include "../beemitter.h"
50 #include "../begnuas.h"
51 #include "../beirg_t.h"
52 #include "../be_dbgout.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
72 static char pic_base_label[128];
73 static ir_label_t exc_label_id;
74 static int mark_spill_reload = 0;
76 /** Return the next block in Block schedule */
77 static ir_node *get_prev_block_sched(const ir_node *block)
79 return get_irn_link(block);
82 static int is_fallthrough(const ir_node *cfgpred)
86 if (!is_Proj(cfgpred))
88 pred = get_Proj_pred(cfgpred);
89 if (is_ia32_SwitchJmp(pred))
95 static int block_needs_label(const ir_node *block)
98 int n_cfgpreds = get_Block_n_cfgpreds(block);
100 if (n_cfgpreds == 0) {
102 } else if (n_cfgpreds == 1) {
103 ir_node *cfgpred = get_Block_cfgpred(block, 0);
104 ir_node *cfgpred_block = get_nodes_block(cfgpred);
106 if (get_prev_block_sched(block) == cfgpred_block
107 && is_fallthrough(cfgpred)) {
116 * Returns the register at in position pos.
118 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
121 const arch_register_t *reg = NULL;
123 assert(get_irn_arity(irn) > pos && "Invalid IN position");
125 /* The out register of the operator at position pos is the
126 in register we need. */
127 op = get_irn_n(irn, pos);
129 reg = arch_get_irn_register(op);
131 assert(reg && "no in register found");
133 if (reg == &ia32_gp_regs[REG_GP_NOREG])
134 panic("trying to emit noreg for %+F input %d", irn, pos);
136 /* in case of unknown register: just return a valid register */
137 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
138 const arch_register_req_t *req = arch_get_register_req(irn, pos);
140 if (arch_register_req_is(req, limited)) {
141 /* in case of limited requirements: get the first allowed register */
142 unsigned idx = rbitset_next(req->limited, 0, 1);
143 reg = arch_register_for_index(req->cls, idx);
145 /* otherwise get first register in class */
146 reg = arch_register_for_index(req->cls, 0);
154 * Returns the register at out position pos.
156 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
159 const arch_register_t *reg = NULL;
161 /* 1st case: irn is not of mode_T, so it has only */
162 /* one OUT register -> good */
163 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
164 /* Proj with the corresponding projnum for the register */
166 if (get_irn_mode(irn) != mode_T) {
168 reg = arch_get_irn_register(irn);
169 } else if (is_ia32_irn(irn)) {
170 reg = arch_irn_get_register(irn, pos);
172 const ir_edge_t *edge;
174 foreach_out_edge(irn, edge) {
175 proj = get_edge_src_irn(edge);
176 assert(is_Proj(proj) && "non-Proj from mode_T node");
177 if (get_Proj_proj(proj) == pos) {
178 reg = arch_get_irn_register(proj);
184 assert(reg && "no out register found");
189 * Add a number to a prefix. This number will not be used a second time.
191 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
193 static unsigned long id = 0;
194 snprintf(buf, buflen, "%s%lu", prefix, ++id);
198 /*************************************************************
200 * (_) | | / _| | | | |
201 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
202 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
203 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
204 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
207 *************************************************************/
209 static void emit_8bit_register(const arch_register_t *reg)
211 const char *reg_name = arch_register_get_name(reg);
214 be_emit_char(reg_name[1]);
218 static void emit_16bit_register(const arch_register_t *reg)
220 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
223 be_emit_string(reg_name);
226 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
228 const char *reg_name;
231 int size = get_mode_size_bits(mode);
233 case 8: emit_8bit_register(reg); return;
234 case 16: emit_16bit_register(reg); return;
236 assert(mode_is_float(mode) || size == 32);
239 reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name);
245 void ia32_emit_source_register(const ir_node *node, int pos)
247 const arch_register_t *reg = get_in_reg(node, pos);
249 emit_register(reg, NULL);
252 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
256 set_entity_backend_marked(entity, 1);
257 id = get_entity_ld_ident(entity);
260 if (get_entity_owner(entity) == get_tls_type()) {
261 if (get_entity_visibility(entity) == visibility_external_allocated) {
262 be_emit_cstring("@INDNTPOFF");
264 be_emit_cstring("@NTPOFF");
268 if (!no_pic_adjust && do_pic) {
269 /* TODO: only do this when necessary */
271 be_emit_string(pic_base_label);
275 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
277 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
279 if (attr->symconst != NULL) {
282 ia32_emit_entity(attr->symconst, 0);
284 if (attr->symconst == NULL || attr->offset != 0) {
285 if (attr->symconst != NULL) {
286 be_emit_irprintf("%+d", attr->offset);
288 be_emit_irprintf("0x%X", attr->offset);
293 static void emit_ia32_Immediate(const ir_node *node)
296 emit_ia32_Immediate_no_prefix(node);
299 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
301 const arch_register_t *reg;
302 ir_node *in = get_irn_n(node, pos);
303 if (is_ia32_Immediate(in)) {
304 emit_ia32_Immediate(in);
308 reg = get_in_reg(node, pos);
309 emit_8bit_register(reg);
312 void ia32_emit_dest_register(const ir_node *node, int pos)
314 const arch_register_t *reg = get_out_reg(node, pos);
316 emit_register(reg, NULL);
319 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
321 const arch_register_t *reg = get_out_reg(node, pos);
323 emit_register(reg, mode_Bu);
326 void ia32_emit_x87_register(const ir_node *node, int pos)
328 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
332 be_emit_string(attr->x87[pos]->name);
335 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
337 assert(mode_is_int(mode) || mode_is_reference(mode));
338 switch (get_mode_size_bits(mode)) {
339 case 8: be_emit_char('b'); return;
340 case 16: be_emit_char('w'); return;
341 case 32: be_emit_char('l'); return;
342 /* gas docu says q is the suffix but gcc, objdump and icc use ll
344 case 64: be_emit_cstring("ll"); return;
346 panic("Can't output mode_suffix for %+F", mode);
349 void ia32_emit_mode_suffix(const ir_node *node)
351 ir_mode *mode = get_ia32_ls_mode(node);
355 ia32_emit_mode_suffix_mode(mode);
358 void ia32_emit_x87_mode_suffix(const ir_node *node)
362 /* we only need to emit the mode on address mode */
363 if (get_ia32_op_type(node) == ia32_Normal)
366 mode = get_ia32_ls_mode(node);
367 assert(mode != NULL);
369 if (mode_is_float(mode)) {
370 switch (get_mode_size_bits(mode)) {
371 case 32: be_emit_char('s'); return;
372 case 64: be_emit_char('l'); return;
374 case 96: be_emit_char('t'); return;
377 assert(mode_is_int(mode));
378 switch (get_mode_size_bits(mode)) {
379 case 16: be_emit_char('s'); return;
380 case 32: be_emit_char('l'); return;
381 /* gas docu says q is the suffix but gcc, objdump and icc use ll
383 case 64: be_emit_cstring("ll"); return;
386 panic("Can't output mode_suffix for %+F", mode);
389 static char get_xmm_mode_suffix(ir_mode *mode)
391 assert(mode_is_float(mode));
392 switch(get_mode_size_bits(mode)) {
395 default: panic("Invalid XMM mode");
399 void ia32_emit_xmm_mode_suffix(const ir_node *node)
401 ir_mode *mode = get_ia32_ls_mode(node);
402 assert(mode != NULL);
404 be_emit_char(get_xmm_mode_suffix(mode));
407 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
409 ir_mode *mode = get_ia32_ls_mode(node);
410 assert(mode != NULL);
411 be_emit_char(get_xmm_mode_suffix(mode));
414 void ia32_emit_extend_suffix(const ir_mode *mode)
416 if (get_mode_size_bits(mode) == 32)
418 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
421 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
423 ir_node *in = get_irn_n(node, pos);
424 if (is_ia32_Immediate(in)) {
425 emit_ia32_Immediate(in);
427 const ir_mode *mode = get_ia32_ls_mode(node);
428 const arch_register_t *reg = get_in_reg(node, pos);
429 emit_register(reg, mode);
434 * Returns the target block for a control flow node.
436 static ir_node *get_cfop_target_block(const ir_node *irn)
438 assert(get_irn_mode(irn) == mode_X);
439 return get_irn_link(irn);
443 * Emits a block label for the given block.
445 static void ia32_emit_block_name(const ir_node *block)
447 if (has_Block_label(block)) {
448 be_emit_string(be_gas_block_label_prefix());
449 be_emit_irprintf("%lu", get_Block_label(block));
451 be_emit_cstring(BLOCK_PREFIX);
452 be_emit_irprintf("%ld", get_irn_node_nr(block));
457 * Emits the target label for a control flow node.
459 static void ia32_emit_cfop_target(const ir_node *node)
461 ir_node *block = get_cfop_target_block(node);
462 ia32_emit_block_name(block);
466 * positive conditions for signed compares
468 static const char *const cmp2condition_s[] = {
469 NULL, /* always false */
476 NULL /* always true */
480 * positive conditions for unsigned compares
482 static const char *const cmp2condition_u[] = {
483 NULL, /* always false */
490 NULL /* always true */
493 static void ia32_emit_cmp_suffix(int pnc)
497 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
498 str = cmp2condition_u[pnc & 7];
500 str = cmp2condition_s[pnc & 7];
506 typedef enum ia32_emit_mod_t {
507 EMIT_RESPECT_LS = 1U << 0,
508 EMIT_ALTERNATE_AM = 1U << 1
512 * fmt parameter output
513 * ---- ---------------------- ---------------------------------------------
515 * %AM <node> address mode of the node
516 * %AR const arch_register_t* address mode of the node or register
517 * %ASx <node> address mode of the node or source register x
518 * %Dx <node> destination register x
519 * %I <node> immediate of the node
520 * %L <node> control flow target of the node
521 * %M <node> mode suffix of the node
522 * %P int condition code
523 * %R const arch_register_t* register
524 * %Sx <node> source register x
525 * %s const char* string
526 * %u unsigned int unsigned int
529 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
530 * * modifier does not prefix immediates with $, but AM with *
532 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
538 const char *start = fmt;
539 ia32_emit_mod_t mod = 0;
541 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
544 be_emit_string_len(start, fmt - start);
548 be_emit_finish_line_gas(node);
560 mod |= EMIT_ALTERNATE_AM;
565 mod |= EMIT_RESPECT_LS;
577 if (mod & EMIT_ALTERNATE_AM)
583 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
584 if (mod & EMIT_ALTERNATE_AM)
586 if (get_ia32_op_type(node) == ia32_AddrModeS) {
589 emit_register(reg, NULL);
595 if (get_ia32_op_type(node) == ia32_AddrModeS) {
596 if (mod & EMIT_ALTERNATE_AM)
601 assert(get_ia32_op_type(node) == ia32_Normal);
606 default: goto unknown;
613 const arch_register_t *reg;
615 if (*fmt < '0' || '9' <= *fmt)
619 reg = get_out_reg(node, pos);
620 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
625 if (!(mod & EMIT_ALTERNATE_AM))
627 emit_ia32_Immediate_no_prefix(node);
631 ia32_emit_cfop_target(node);
635 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
640 int pnc = va_arg(ap, int);
641 ia32_emit_cmp_suffix(pnc);
646 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
647 emit_register(reg, NULL);
656 if (*fmt < '0' || '9' <= *fmt)
660 in = get_irn_n(node, pos);
661 if (is_ia32_Immediate(in)) {
662 if (!(mod & EMIT_ALTERNATE_AM))
664 emit_ia32_Immediate_no_prefix(in);
666 const arch_register_t *reg;
668 if (mod & EMIT_ALTERNATE_AM)
670 reg = get_in_reg(node, pos);
671 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
677 const char *str = va_arg(ap, const char*);
683 unsigned num = va_arg(ap, unsigned);
684 be_emit_irprintf("%u", num);
690 panic("unknown conversion");
698 * Emits registers and/or address mode of a binary operation.
700 void ia32_emit_binop(const ir_node *node)
702 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
703 ia32_emitf(node, "%#S4, %#AS3");
705 ia32_emitf(node, "%#AS4, %#S3");
710 * Emits registers and/or address mode of a binary operation.
712 void ia32_emit_x87_binop(const ir_node *node)
714 switch(get_ia32_op_type(node)) {
717 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
718 const arch_register_t *in1 = x87_attr->x87[0];
719 const arch_register_t *in = x87_attr->x87[1];
720 const arch_register_t *out = x87_attr->x87[2];
724 } else if (out == in) {
729 be_emit_string(arch_register_get_name(in));
730 be_emit_cstring(", %");
731 be_emit_string(arch_register_get_name(out));
739 assert(0 && "unsupported op type");
744 * Emits registers and/or address mode of a unary operation.
746 void ia32_emit_unop(const ir_node *node, int pos)
750 ia32_emitf(node, fmt);
754 * Emits address mode.
756 void ia32_emit_am(const ir_node *node)
758 ir_entity *ent = get_ia32_am_sc(node);
759 int offs = get_ia32_am_offs_int(node);
760 ir_node *base = get_irn_n(node, n_ia32_base);
761 int has_base = !is_ia32_NoReg_GP(base);
762 ir_node *index = get_irn_n(node, n_ia32_index);
763 int has_index = !is_ia32_NoReg_GP(index);
765 /* just to be sure... */
766 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
770 if (is_ia32_am_sc_sign(node))
772 ia32_emit_entity(ent, 0);
775 /* also handle special case if nothing is set */
776 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
778 be_emit_irprintf("%+d", offs);
780 be_emit_irprintf("%d", offs);
784 if (has_base || has_index) {
789 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
790 emit_register(reg, NULL);
793 /* emit index + scale */
795 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
798 emit_register(reg, NULL);
800 scale = get_ia32_am_scale(node);
802 be_emit_irprintf(",%d", 1 << scale);
809 static void emit_ia32_IMul(const ir_node *node)
811 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
812 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
814 /* do we need the 3-address form? */
815 if (is_ia32_NoReg_GP(left) ||
816 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
817 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
819 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
824 * walks up a tree of copies/perms/spills/reloads to find the original value
825 * that is moved around
827 static ir_node *find_original_value(ir_node *node)
829 if (irn_visited(node))
832 mark_irn_visited(node);
833 if (be_is_Copy(node)) {
834 return find_original_value(be_get_Copy_op(node));
835 } else if (be_is_CopyKeep(node)) {
836 return find_original_value(be_get_CopyKeep_op(node));
837 } else if (is_Proj(node)) {
838 ir_node *pred = get_Proj_pred(node);
839 if (be_is_Perm(pred)) {
840 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
841 } else if (be_is_MemPerm(pred)) {
842 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
843 } else if (is_ia32_Load(pred)) {
844 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
848 } else if (is_ia32_Store(node)) {
849 return find_original_value(get_irn_n(node, n_ia32_Store_val));
850 } else if (is_Phi(node)) {
852 arity = get_irn_arity(node);
853 for (i = 0; i < arity; ++i) {
854 ir_node *in = get_irn_n(node, i);
855 ir_node *res = find_original_value(in);
866 static int determine_final_pnc(const ir_node *node, int flags_pos,
869 ir_node *flags = get_irn_n(node, flags_pos);
870 const ia32_attr_t *flags_attr;
871 flags = skip_Proj(flags);
873 if (is_ia32_Sahf(flags)) {
874 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
875 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
876 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
877 inc_irg_visited(current_ir_graph);
878 cmp = find_original_value(cmp);
880 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
881 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
884 flags_attr = get_ia32_attr_const(cmp);
885 if (flags_attr->data.ins_permuted)
886 pnc = get_mirrored_pnc(pnc);
887 pnc |= ia32_pn_Cmp_float;
888 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
889 || is_ia32_Fucompi(flags)) {
890 flags_attr = get_ia32_attr_const(flags);
892 if (flags_attr->data.ins_permuted)
893 pnc = get_mirrored_pnc(pnc);
894 pnc |= ia32_pn_Cmp_float;
896 flags_attr = get_ia32_attr_const(flags);
898 if (flags_attr->data.ins_permuted)
899 pnc = get_mirrored_pnc(pnc);
900 if (flags_attr->data.cmp_unsigned)
901 pnc |= ia32_pn_Cmp_unsigned;
907 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
909 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
910 return get_negated_pnc(pnc, mode);
913 void ia32_emit_cmp_suffix_node(const ir_node *node,
916 const ia32_attr_t *attr = get_ia32_attr_const(node);
918 pn_Cmp pnc = get_ia32_condcode(node);
920 pnc = determine_final_pnc(node, flags_pos, pnc);
921 if (attr->data.ins_permuted)
922 pnc = ia32_get_negated_pnc(pnc);
924 ia32_emit_cmp_suffix(pnc);
928 * Emits an exception label for a given node.
930 static void ia32_emit_exc_label(const ir_node *node)
932 be_emit_string(be_gas_insn_label_prefix());
933 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
937 * Returns the Proj with projection number proj and NOT mode_M
939 static ir_node *get_proj(const ir_node *node, long proj)
941 const ir_edge_t *edge;
944 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
946 foreach_out_edge(node, edge) {
947 src = get_edge_src_irn(edge);
949 assert(is_Proj(src) && "Proj expected");
950 if (get_irn_mode(src) == mode_M)
953 if (get_Proj_proj(src) == proj)
959 static int can_be_fallthrough(const ir_node *node)
961 ir_node *target_block = get_cfop_target_block(node);
962 ir_node *block = get_nodes_block(node);
963 return get_prev_block_sched(target_block) == block;
967 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
969 static void emit_ia32_Jcc(const ir_node *node)
971 int need_parity_label = 0;
972 const ir_node *proj_true;
973 const ir_node *proj_false;
974 const ir_node *block;
975 pn_Cmp pnc = get_ia32_condcode(node);
977 pnc = determine_final_pnc(node, 0, pnc);
980 proj_true = get_proj(node, pn_ia32_Jcc_true);
981 assert(proj_true && "Jcc without true Proj");
983 proj_false = get_proj(node, pn_ia32_Jcc_false);
984 assert(proj_false && "Jcc without false Proj");
986 block = get_nodes_block(node);
988 if (can_be_fallthrough(proj_true)) {
989 /* exchange both proj's so the second one can be omitted */
990 const ir_node *t = proj_true;
992 proj_true = proj_false;
994 pnc = ia32_get_negated_pnc(pnc);
997 if (pnc & ia32_pn_Cmp_float) {
998 /* Some floating point comparisons require a test of the parity flag,
999 * which indicates that the result is unordered */
1002 ia32_emitf(proj_true, "\tjp %L\n");
1007 ia32_emitf(proj_true, "\tjnp %L\n");
1013 /* we need a local label if the false proj is a fallthrough
1014 * as the falseblock might have no label emitted then */
1015 if (can_be_fallthrough(proj_false)) {
1016 need_parity_label = 1;
1017 ia32_emitf(proj_false, "\tjp 1f\n");
1019 ia32_emitf(proj_false, "\tjp %L\n");
1026 ia32_emitf(proj_true, "\tjp %L\n");
1034 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1037 if (need_parity_label) {
1038 ia32_emitf(NULL, "1:\n");
1041 /* the second Proj might be a fallthrough */
1042 if (can_be_fallthrough(proj_false)) {
1043 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1045 ia32_emitf(proj_false, "\tjmp %L\n");
1049 static void emit_ia32_CMov(const ir_node *node)
1051 const ia32_attr_t *attr = get_ia32_attr_const(node);
1052 int ins_permuted = attr->data.ins_permuted;
1053 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1054 pn_Cmp pnc = get_ia32_condcode(node);
1055 const arch_register_t *in_true;
1056 const arch_register_t *in_false;
1058 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1060 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1061 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1063 /* should be same constraint fullfilled? */
1064 if (out == in_false) {
1065 /* yes -> nothing to do */
1066 } else if (out == in_true) {
1067 const arch_register_t *tmp;
1069 assert(get_ia32_op_type(node) == ia32_Normal);
1071 ins_permuted = !ins_permuted;
1078 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1082 pnc = ia32_get_negated_pnc(pnc);
1084 /* TODO: handling of Nans isn't correct yet */
1086 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1089 /*********************************************************
1092 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1093 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1094 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1095 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1098 *********************************************************/
1100 /* jump table entry (target and corresponding number) */
1101 typedef struct _branch_t {
1106 /* jump table for switch generation */
1107 typedef struct _jmp_tbl_t {
1108 ir_node *defProj; /**< default target */
1109 long min_value; /**< smallest switch case */
1110 long max_value; /**< largest switch case */
1111 long num_branches; /**< number of jumps */
1112 char *label; /**< label of the jump table */
1113 branch_t *branches; /**< jump array */
1117 * Compare two variables of type branch_t. Used to sort all switch cases
1119 static int ia32_cmp_branch_t(const void *a, const void *b)
1121 branch_t *b1 = (branch_t *)a;
1122 branch_t *b2 = (branch_t *)b;
1124 if (b1->value <= b2->value)
1131 * Emits code for a SwitchJmp (creates a jump table if
1132 * possible otherwise a cmp-jmp cascade). Port from
1135 static void emit_ia32_SwitchJmp(const ir_node *node)
1137 unsigned long interval;
1143 const ir_edge_t *edge;
1145 /* fill the table structure */
1146 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1147 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1149 tbl.num_branches = get_irn_n_edges(node) - 1;
1150 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1151 tbl.min_value = INT_MAX;
1152 tbl.max_value = INT_MIN;
1154 default_pn = get_ia32_condcode(node);
1156 /* go over all proj's and collect them */
1157 foreach_out_edge(node, edge) {
1158 proj = get_edge_src_irn(edge);
1159 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1161 pnc = get_Proj_proj(proj);
1163 /* check for default proj */
1164 if (pnc == default_pn) {
1165 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1168 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1169 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1171 /* create branch entry */
1172 tbl.branches[i].target = proj;
1173 tbl.branches[i].value = pnc;
1178 assert(i == tbl.num_branches);
1180 /* sort the branches by their number */
1181 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1183 /* two-complement's magic make this work without overflow */
1184 interval = tbl.max_value - tbl.min_value;
1186 /* emit the table */
1187 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1188 ia32_emitf(tbl.defProj, "\tja %L\n");
1190 if (tbl.num_branches > 1) {
1192 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1194 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1195 ia32_emitf(NULL, "\t.align 4\n");
1196 ia32_emitf(NULL, "%s:\n", tbl.label);
1198 last_value = tbl.branches[0].value;
1199 for (i = 0; i != tbl.num_branches; ++i) {
1200 while (last_value != tbl.branches[i].value) {
1201 ia32_emitf(tbl.defProj, ".long %L\n");
1204 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1207 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1209 /* one jump is enough */
1210 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1220 * Emits code for a unconditional jump.
1222 static void emit_Jmp(const ir_node *node)
1226 /* for now, the code works for scheduled and non-schedules blocks */
1227 block = get_nodes_block(node);
1229 /* we have a block schedule */
1230 if (can_be_fallthrough(node)) {
1231 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1233 ia32_emitf(node, "\tjmp %L\n");
1238 * Emit an inline assembler operand.
1240 * @param node the ia32_ASM node
1241 * @param s points to the operand (a %c)
1243 * @return pointer to the first char in s NOT in the current operand
1245 static const char* emit_asm_operand(const ir_node *node, const char *s)
1247 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1248 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1250 const arch_register_t *reg;
1251 const ia32_asm_reg_t *asm_regs = attr->register_map;
1252 const ia32_asm_reg_t *asm_reg;
1253 const char *reg_name;
1262 /* parse modifiers */
1265 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1290 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1297 sscanf(s, "%d%n", &num, &p);
1299 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1306 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1308 "Error: Custom assembler references invalid input/output (%+F)\n",
1312 asm_reg = & asm_regs[num];
1313 assert(asm_reg->valid);
1316 if (asm_reg->use_input == 0) {
1317 reg = get_out_reg(node, asm_reg->inout_pos);
1319 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1321 /* might be an immediate value */
1322 if (is_ia32_Immediate(pred)) {
1323 emit_ia32_Immediate(pred);
1326 reg = get_in_reg(node, asm_reg->inout_pos);
1330 "Warning: no register assigned for %d asm op (%+F)\n",
1335 if (asm_reg->memory) {
1340 if (modifier != 0) {
1344 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1347 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1350 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1353 panic("Invalid asm op modifier");
1355 be_emit_string(reg_name);
1357 emit_register(reg, asm_reg->mode);
1360 if (asm_reg->memory) {
1368 * Emits code for an ASM pseudo op.
1370 static void emit_ia32_Asm(const ir_node *node)
1372 const void *gen_attr = get_irn_generic_attr_const(node);
1373 const ia32_asm_attr_t *attr
1374 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1375 ident *asm_text = attr->asm_text;
1376 const char *s = get_id_str(asm_text);
1378 ia32_emitf(node, "#APP\t\n");
1385 s = emit_asm_operand(node, s);
1391 ia32_emitf(NULL, "\n#NO_APP\n");
1394 /**********************************
1397 * | | ___ _ __ _ _| |_) |
1398 * | | / _ \| '_ \| | | | _ <
1399 * | |___| (_) | |_) | |_| | |_) |
1400 * \_____\___/| .__/ \__, |____/
1403 **********************************/
1406 * Emit movsb/w instructions to make mov count divideable by 4
1408 static void emit_CopyB_prolog(unsigned size)
1411 ia32_emitf(NULL, "\tmovsb\n");
1413 ia32_emitf(NULL, "\tmovsw\n");
1417 * Emit rep movsd instruction for memcopy.
1419 static void emit_ia32_CopyB(const ir_node *node)
1421 unsigned size = get_ia32_copyb_size(node);
1423 emit_CopyB_prolog(size);
1424 ia32_emitf(node, "\trep movsd\n");
1428 * Emits unrolled memcopy.
1430 static void emit_ia32_CopyB_i(const ir_node *node)
1432 unsigned size = get_ia32_copyb_size(node);
1434 emit_CopyB_prolog(size);
1438 ia32_emitf(NULL, "\tmovsd\n");
1444 /***************************
1448 * | | / _ \| '_ \ \ / /
1449 * | |___| (_) | | | \ V /
1450 * \_____\___/|_| |_|\_/
1452 ***************************/
1455 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1457 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1460 ir_mode *ls_mode = get_ia32_ls_mode(node);
1461 int ls_bits = get_mode_size_bits(ls_mode);
1462 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1464 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1467 static void emit_ia32_Conv_I2FP(const ir_node *node)
1469 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1472 static void emit_ia32_Conv_FP2I(const ir_node *node)
1474 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1477 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1479 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1483 * Emits code for an Int conversion.
1485 static void emit_ia32_Conv_I2I(const ir_node *node)
1487 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1488 int signed_mode = mode_is_signed(smaller_mode);
1489 const char *sign_suffix;
1491 assert(!mode_is_float(smaller_mode));
1493 sign_suffix = signed_mode ? "s" : "z";
1494 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1500 static void emit_ia32_Call(const ir_node *node)
1502 /* Special case: Call must not have its immediates prefixed by $, instead
1503 * address mode is prefixed by *. */
1504 ia32_emitf(node, "\tcall %*AS3\n");
1508 /*******************************************
1511 * | |__ ___ _ __ ___ __| | ___ ___
1512 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1513 * | |_) | __/ | | | (_) | (_| | __/\__ \
1514 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1516 *******************************************/
1519 * Emits code to increase stack pointer.
1521 static void emit_be_IncSP(const ir_node *node)
1523 int offs = be_get_IncSP_offset(node);
1529 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1531 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1536 * Emits code for Copy/CopyKeep.
1538 static void Copy_emitter(const ir_node *node, const ir_node *op)
1540 const arch_register_t *in = arch_get_irn_register(op);
1541 const arch_register_t *out = arch_get_irn_register(node);
1546 if (is_unknown_reg(in))
1548 /* copies of vf nodes aren't real... */
1549 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1552 if (get_irn_mode(node) == mode_E) {
1553 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1555 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1559 static void emit_be_Copy(const ir_node *node)
1561 Copy_emitter(node, be_get_Copy_op(node));
1564 static void emit_be_CopyKeep(const ir_node *node)
1566 Copy_emitter(node, be_get_CopyKeep_op(node));
1570 * Emits code for exchange.
1572 static void emit_be_Perm(const ir_node *node)
1574 const arch_register_t *in0, *in1;
1575 const arch_register_class_t *cls0, *cls1;
1577 in0 = arch_get_irn_register(get_irn_n(node, 0));
1578 in1 = arch_get_irn_register(get_irn_n(node, 1));
1580 cls0 = arch_register_get_class(in0);
1581 cls1 = arch_register_get_class(in1);
1583 assert(cls0 == cls1 && "Register class mismatch at Perm");
1585 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1586 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1587 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1588 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1589 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1590 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1591 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1593 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1596 panic("unexpected register class in be_Perm (%+F)", node);
1601 * Emits code for Constant loading.
1603 static void emit_ia32_Const(const ir_node *node)
1605 ia32_emitf(node, "\tmovl %I, %D0\n");
1609 * Emits code to load the TLS base
1611 static void emit_ia32_LdTls(const ir_node *node)
1613 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1616 /* helper function for emit_ia32_Minus64Bit */
1617 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1619 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1622 /* helper function for emit_ia32_Minus64Bit */
1623 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1625 ia32_emitf(node, "\tnegl %R\n", reg);
1628 /* helper function for emit_ia32_Minus64Bit */
1629 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1631 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1634 /* helper function for emit_ia32_Minus64Bit */
1635 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1637 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1640 /* helper function for emit_ia32_Minus64Bit */
1641 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1643 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1646 /* helper function for emit_ia32_Minus64Bit */
1647 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1649 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1652 static void emit_ia32_Minus64Bit(const ir_node *node)
1654 const arch_register_t *in_lo = get_in_reg(node, 0);
1655 const arch_register_t *in_hi = get_in_reg(node, 1);
1656 const arch_register_t *out_lo = get_out_reg(node, 0);
1657 const arch_register_t *out_hi = get_out_reg(node, 1);
1659 if (out_lo == in_lo) {
1660 if (out_hi != in_hi) {
1661 /* a -> a, b -> d */
1664 /* a -> a, b -> b */
1667 } else if (out_lo == in_hi) {
1668 if (out_hi == in_lo) {
1669 /* a -> b, b -> a */
1670 emit_xchg(node, in_lo, in_hi);
1673 /* a -> b, b -> d */
1674 emit_mov(node, in_hi, out_hi);
1675 emit_mov(node, in_lo, out_lo);
1679 if (out_hi == in_lo) {
1680 /* a -> c, b -> a */
1681 emit_mov(node, in_lo, out_lo);
1683 } else if (out_hi == in_hi) {
1684 /* a -> c, b -> b */
1685 emit_mov(node, in_lo, out_lo);
1688 /* a -> c, b -> d */
1689 emit_mov(node, in_lo, out_lo);
1695 emit_neg( node, out_hi);
1696 emit_neg( node, out_lo);
1697 emit_sbb0(node, out_hi);
1701 emit_zero(node, out_hi);
1702 emit_neg( node, out_lo);
1703 emit_sbb( node, in_hi, out_hi);
1706 static void emit_ia32_GetEIP(const ir_node *node)
1708 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1709 ia32_emitf(NULL, "%s:\n", pic_base_label);
1710 ia32_emitf(node, "\tpopl %D0\n");
1713 static void emit_be_Return(const ir_node *node)
1715 unsigned pop = be_Return_get_pop(node);
1717 if (pop > 0 || be_Return_get_emit_pop(node)) {
1718 ia32_emitf(node, "\tret $%u\n", pop);
1720 ia32_emitf(node, "\tret\n");
1724 static void emit_Nothing(const ir_node *node)
1730 /***********************************************************************************
1733 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1734 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1735 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1736 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1738 ***********************************************************************************/
1741 * Enters the emitter functions for handled nodes into the generic
1742 * pointer of an opcode.
1744 static void ia32_register_emitters(void)
1746 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1747 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1748 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1749 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1750 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1751 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1753 /* first clear the generic function pointer for all ops */
1754 clear_irp_opcodes_generic_func();
1756 /* register all emitter functions defined in spec */
1757 ia32_register_spec_emitters();
1759 /* other ia32 emitter functions */
1760 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1765 IA32_EMIT(Conv_FP2FP);
1766 IA32_EMIT(Conv_FP2I);
1767 IA32_EMIT(Conv_I2FP);
1768 IA32_EMIT(Conv_I2I);
1775 IA32_EMIT(Minus64Bit);
1776 IA32_EMIT(SwitchJmp);
1778 /* benode emitter */
1801 typedef void (*emit_func_ptr) (const ir_node *);
1804 * Assign and emit an exception label if the current instruction can fail.
1806 static void ia32_assign_exc_label(ir_node *node)
1808 /* assign a new ID to the instruction */
1809 set_ia32_exc_label_id(node, ++exc_label_id);
1811 ia32_emit_exc_label(node);
1813 be_emit_pad_comment();
1814 be_emit_cstring("/* exception to Block ");
1815 ia32_emit_cfop_target(node);
1816 be_emit_cstring(" */\n");
1817 be_emit_write_line();
1821 * Emits code for a node.
1823 static void ia32_emit_node(ir_node *node)
1825 ir_op *op = get_irn_op(node);
1827 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1829 if (is_ia32_irn(node)) {
1830 if (get_ia32_exc_label(node)) {
1831 /* emit the exception label of this instruction */
1832 ia32_assign_exc_label(node);
1834 if (mark_spill_reload) {
1835 if (is_ia32_is_spill(node)) {
1836 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1838 if (is_ia32_is_reload(node)) {
1839 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1841 if (is_ia32_is_remat(node)) {
1842 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1846 if (op->ops.generic) {
1847 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1849 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1854 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1860 * Emits gas alignment directives
1862 static void ia32_emit_alignment(unsigned align, unsigned skip)
1864 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1868 * Emits gas alignment directives for Labels depended on cpu architecture.
1870 static void ia32_emit_align_label(void)
1872 unsigned align = ia32_cg_config.label_alignment;
1873 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1874 ia32_emit_alignment(align, maximum_skip);
1878 * Test whether a block should be aligned.
1879 * For cpus in the P4/Athlon class it is useful to align jump labels to
1880 * 16 bytes. However we should only do that if the alignment nops before the
1881 * label aren't executed more often than we have jumps to the label.
1883 static int should_align_block(const ir_node *block)
1885 static const double DELTA = .0001;
1886 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1887 ir_node *prev = get_prev_block_sched(block);
1889 double prev_freq = 0; /**< execfreq of the fallthrough block */
1890 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1893 if (exec_freq == NULL)
1895 if (ia32_cg_config.label_alignment_factor <= 0)
1898 block_freq = get_block_execfreq(exec_freq, block);
1899 if (block_freq < DELTA)
1902 n_cfgpreds = get_Block_n_cfgpreds(block);
1903 for(i = 0; i < n_cfgpreds; ++i) {
1904 const ir_node *pred = get_Block_cfgpred_block(block, i);
1905 double pred_freq = get_block_execfreq(exec_freq, pred);
1908 prev_freq += pred_freq;
1910 jmp_freq += pred_freq;
1914 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1917 jmp_freq /= prev_freq;
1919 return jmp_freq > ia32_cg_config.label_alignment_factor;
1923 * Emit the block header for a block.
1925 * @param block the block
1926 * @param prev_block the previous block
1928 static void ia32_emit_block_header(ir_node *block)
1930 ir_graph *irg = current_ir_graph;
1931 int need_label = block_needs_label(block);
1933 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1935 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
1938 if (ia32_cg_config.label_alignment > 0) {
1939 /* align the current block if:
1940 * a) if should be aligned due to its execution frequency
1941 * b) there is no fall-through here
1943 if (should_align_block(block)) {
1944 ia32_emit_align_label();
1946 /* if the predecessor block has no fall-through,
1947 we can always align the label. */
1949 int has_fallthrough = 0;
1951 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1952 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1953 if (can_be_fallthrough(cfg_pred)) {
1954 has_fallthrough = 1;
1959 if (!has_fallthrough)
1960 ia32_emit_align_label();
1964 if (need_label || has_Block_label(block)) {
1965 ia32_emit_block_name(block);
1968 be_emit_pad_comment();
1969 be_emit_cstring(" /* ");
1971 be_emit_cstring("\t/* ");
1972 ia32_emit_block_name(block);
1973 be_emit_cstring(": ");
1976 be_emit_cstring("preds:");
1978 /* emit list of pred blocks in comment */
1979 arity = get_irn_arity(block);
1980 for (i = 0; i < arity; ++i) {
1981 ir_node *predblock = get_Block_cfgpred_block(block, i);
1982 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1984 if (exec_freq != NULL) {
1985 be_emit_irprintf(" freq: %f",
1986 get_block_execfreq(exec_freq, block));
1988 be_emit_cstring(" */\n");
1989 be_emit_write_line();
1993 * Walks over the nodes in a block connected by scheduling edges
1994 * and emits code for each node.
1996 static void ia32_gen_block(ir_node *block)
2000 ia32_emit_block_header(block);
2002 /* emit the contents of the block */
2003 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2004 sched_foreach(block, node) {
2005 ia32_emit_node(node);
2009 typedef struct exc_entry {
2010 ir_node *exc_instr; /** The instruction that can issue an exception. */
2011 ir_node *block; /** The block to call then. */
2016 * Sets labels for control flow nodes (jump target).
2017 * Links control predecessors to there destination blocks.
2019 static void ia32_gen_labels(ir_node *block, void *data)
2021 exc_entry **exc_list = data;
2025 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2026 pred = get_Block_cfgpred(block, n);
2027 set_irn_link(pred, block);
2029 pred = skip_Proj(pred);
2030 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2035 ARR_APP1(exc_entry, *exc_list, e);
2036 set_irn_link(pred, block);
2042 * Compare two exception_entries.
2044 static int cmp_exc_entry(const void *a, const void *b)
2046 const exc_entry *ea = a;
2047 const exc_entry *eb = b;
2049 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2055 * Main driver. Emits the code for one routine.
2057 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2059 ir_entity *entity = get_irg_entity(irg);
2060 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2065 do_pic = cg->birg->main_env->options->pic;
2067 ia32_register_emitters();
2069 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2071 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2072 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2074 /* we use links to point to target blocks */
2075 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2076 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2078 /* initialize next block links */
2079 n = ARR_LEN(cg->blk_sched);
2080 for (i = 0; i < n; ++i) {
2081 ir_node *block = cg->blk_sched[i];
2082 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2084 set_irn_link(block, prev);
2087 for (i = 0; i < n; ++i) {
2088 ir_node *block = cg->blk_sched[i];
2090 ia32_gen_block(block);
2093 be_gas_emit_function_epilog(entity);
2094 be_dbg_method_end();
2096 be_emit_write_line();
2098 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2100 /* Sort the exception table using the exception label id's.
2101 Those are ascending with ascending addresses. */
2102 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2106 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2107 be_emit_cstring("\t.long ");
2108 ia32_emit_exc_label(exc_list[i].exc_instr);
2110 be_emit_cstring("\t.long ");
2111 ia32_emit_block_name(exc_list[i].block);
2115 DEL_ARR_F(exc_list);
2118 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2119 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2123 void ia32_init_emitter(void)
2125 lc_opt_entry_t *be_grp;
2126 lc_opt_entry_t *ia32_grp;
2128 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2129 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2131 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2133 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");