2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
43 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../benode.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
73 static char pic_base_label[128];
74 static ir_label_t exc_label_id;
75 static int mark_spill_reload = 0;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 /** Checks if the current block is a fall-through target. */
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
99 * returns non-zero if the given block needs a label
100 * because of being a jump-target (and not a fall-through)
102 static int block_needs_label(const ir_node *block)
105 int n_cfgpreds = get_Block_n_cfgpreds(block);
107 if (has_Block_entity(block))
110 if (n_cfgpreds == 0) {
112 } else if (n_cfgpreds == 1) {
113 ir_node *cfgpred = get_Block_cfgpred(block, 0);
114 ir_node *cfgpred_block = get_nodes_block(cfgpred);
116 if (get_prev_block_sched(block) == cfgpred_block
117 && is_fallthrough(cfgpred)) {
126 * Returns the register at in position pos.
128 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
131 const arch_register_t *reg = NULL;
133 assert(get_irn_arity(irn) > pos && "Invalid IN position");
135 /* The out register of the operator at position pos is the
136 in register we need. */
137 op = get_irn_n(irn, pos);
139 reg = arch_get_irn_register(op);
141 assert(reg && "no in register found");
143 if (reg == &ia32_gp_regs[REG_GP_NOREG])
144 panic("trying to emit noreg for %+F input %d", irn, pos);
146 /* in case of unknown register: just return a valid register */
147 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
148 const arch_register_req_t *req = arch_get_register_req(irn, pos);
150 if (arch_register_req_is(req, limited)) {
151 /* in case of limited requirements: get the first allowed register */
152 unsigned idx = rbitset_next(req->limited, 0, 1);
153 reg = arch_register_for_index(req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%lu", prefix, ++id);
208 /*************************************************************
210 * (_) | | / _| | | | |
211 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
212 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
213 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
214 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
217 *************************************************************/
220 * Emit the name of the 8bit low register
222 static void emit_8bit_register(const arch_register_t *reg)
224 const char *reg_name = arch_register_get_name(reg);
227 be_emit_char(reg_name[1]);
232 * Emit the name of the 8bit high register
234 static void emit_8bit_register_high(const arch_register_t *reg)
236 const char *reg_name = arch_register_get_name(reg);
239 be_emit_char(reg_name[1]);
243 static void emit_16bit_register(const arch_register_t *reg)
245 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
248 be_emit_string(reg_name);
252 * emit a register, possible shortened by a mode
254 * @param reg the register
255 * @param mode the mode of the register or NULL for full register
257 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
259 const char *reg_name;
262 int size = get_mode_size_bits(mode);
264 case 8: emit_8bit_register(reg); return;
265 case 16: emit_16bit_register(reg); return;
267 assert(mode_is_float(mode) || size == 32);
270 reg_name = arch_register_get_name(reg);
273 be_emit_string(reg_name);
276 void ia32_emit_source_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_in_reg(node, pos);
280 emit_register(reg, NULL);
283 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
285 set_entity_backend_marked(entity, 1);
286 be_gas_emit_entity(entity);
288 if (get_entity_owner(entity) == get_tls_type()) {
289 if (get_entity_visibility(entity) == visibility_external_allocated) {
290 be_emit_cstring("@INDNTPOFF");
292 be_emit_cstring("@NTPOFF");
296 if (do_pic && !no_pic_adjust) {
298 be_emit_string(pic_base_label);
302 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
304 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
306 if (attr->symconst != NULL) {
309 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
311 if (attr->symconst == NULL || attr->offset != 0) {
312 if (attr->symconst != NULL) {
313 be_emit_irprintf("%+d", attr->offset);
315 be_emit_irprintf("0x%X", attr->offset);
320 static void emit_ia32_Immediate(const ir_node *node)
323 emit_ia32_Immediate_no_prefix(node);
326 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
328 const arch_register_t *reg;
329 const ir_node *in = get_irn_n(node, pos);
330 if (is_ia32_Immediate(in)) {
331 emit_ia32_Immediate(in);
335 reg = get_in_reg(node, pos);
336 emit_8bit_register(reg);
339 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_in_reg(node, pos);
342 emit_8bit_register_high(reg);
345 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
347 const arch_register_t *reg;
348 const ir_node *in = get_irn_n(node, pos);
349 if (is_ia32_Immediate(in)) {
350 emit_ia32_Immediate(in);
354 reg = get_in_reg(node, pos);
355 emit_16bit_register(reg);
358 void ia32_emit_dest_register(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, NULL);
365 void ia32_emit_dest_register_size(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, get_ia32_ls_mode(node));
372 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
374 const arch_register_t *reg = get_out_reg(node, pos);
376 emit_register(reg, mode_Bu);
379 void ia32_emit_x87_register(const ir_node *node, int pos)
381 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
385 be_emit_string(attr->x87[pos]->name);
388 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
390 assert(mode_is_int(mode) || mode_is_reference(mode));
391 switch (get_mode_size_bits(mode)) {
392 case 8: be_emit_char('b'); return;
393 case 16: be_emit_char('w'); return;
394 case 32: be_emit_char('l'); return;
395 /* gas docu says q is the suffix but gcc, objdump and icc use ll
397 case 64: be_emit_cstring("ll"); return;
399 panic("Can't output mode_suffix for %+F", mode);
402 void ia32_emit_mode_suffix(const ir_node *node)
404 ir_mode *mode = get_ia32_ls_mode(node);
408 ia32_emit_mode_suffix_mode(mode);
411 void ia32_emit_x87_mode_suffix(const ir_node *node)
415 /* we only need to emit the mode on address mode */
416 if (get_ia32_op_type(node) == ia32_Normal)
419 mode = get_ia32_ls_mode(node);
420 assert(mode != NULL);
422 if (mode_is_float(mode)) {
423 switch (get_mode_size_bits(mode)) {
424 case 32: be_emit_char('s'); return;
425 case 64: be_emit_char('l'); return;
427 case 96: be_emit_char('t'); return;
430 assert(mode_is_int(mode));
431 switch (get_mode_size_bits(mode)) {
432 case 16: be_emit_char('s'); return;
433 case 32: be_emit_char('l'); return;
434 /* gas docu says q is the suffix but gcc, objdump and icc use ll
436 case 64: be_emit_cstring("ll"); return;
439 panic("Can't output mode_suffix for %+F", mode);
442 static char get_xmm_mode_suffix(ir_mode *mode)
444 assert(mode_is_float(mode));
445 switch(get_mode_size_bits(mode)) {
448 default: panic("Invalid XMM mode");
452 void ia32_emit_xmm_mode_suffix(const ir_node *node)
454 ir_mode *mode = get_ia32_ls_mode(node);
455 assert(mode != NULL);
457 be_emit_char(get_xmm_mode_suffix(mode));
460 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
462 ir_mode *mode = get_ia32_ls_mode(node);
463 assert(mode != NULL);
464 be_emit_char(get_xmm_mode_suffix(mode));
467 void ia32_emit_extend_suffix(const ir_node *node)
469 ir_mode *mode = get_ia32_ls_mode(node);
470 if (get_mode_size_bits(mode) == 32)
472 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
473 ia32_emit_mode_suffix_mode(mode);
476 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
478 ir_node *in = get_irn_n(node, pos);
479 if (is_ia32_Immediate(in)) {
480 emit_ia32_Immediate(in);
482 const ir_mode *mode = get_ia32_ls_mode(node);
483 const arch_register_t *reg = get_in_reg(node, pos);
484 emit_register(reg, mode);
489 * Returns the target block for a control flow node.
491 static ir_node *get_cfop_target_block(const ir_node *irn)
493 assert(get_irn_mode(irn) == mode_X);
494 return get_irn_link(irn);
498 * Emits a block label for the given block.
500 static void ia32_emit_block_name(const ir_node *block)
502 if (has_Block_entity(block)) {
503 ir_entity *entity = get_Block_entity(block);
504 be_gas_emit_entity(entity);
506 be_emit_cstring(BLOCK_PREFIX);
507 be_emit_irprintf("%ld", get_irn_node_nr(block));
512 * Emits the target label for a control flow node.
514 static void ia32_emit_cfop_target(const ir_node *node)
516 ir_node *block = get_cfop_target_block(node);
517 ia32_emit_block_name(block);
521 * positive conditions for signed compares
523 static const char *const cmp2condition_s[] = {
524 NULL, /* always false */
531 NULL /* always true */
535 * positive conditions for unsigned compares
537 static const char *const cmp2condition_u[] = {
538 NULL, /* always false */
545 NULL /* always true */
549 * Emit the suffix for a compare instruction.
551 static void ia32_emit_cmp_suffix(int pnc)
555 if (pnc == ia32_pn_Cmp_parity) {
559 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
560 str = cmp2condition_u[pnc & 7];
562 str = cmp2condition_s[pnc & 7];
568 typedef enum ia32_emit_mod_t {
569 EMIT_RESPECT_LS = 1U << 0,
570 EMIT_ALTERNATE_AM = 1U << 1,
575 * Emits address mode.
577 void ia32_emit_am(const ir_node *node)
579 ir_entity *ent = get_ia32_am_sc(node);
580 int offs = get_ia32_am_offs_int(node);
581 ir_node *base = get_irn_n(node, n_ia32_base);
582 int has_base = !is_ia32_NoReg_GP(base);
583 ir_node *index = get_irn_n(node, n_ia32_index);
584 int has_index = !is_ia32_NoReg_GP(index);
586 /* just to be sure... */
587 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
591 const ia32_attr_t *attr = get_ia32_attr_const(node);
592 if (is_ia32_am_sc_sign(node))
594 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
597 /* also handle special case if nothing is set */
598 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
600 be_emit_irprintf("%+d", offs);
602 be_emit_irprintf("%d", offs);
606 if (has_base || has_index) {
611 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
612 emit_register(reg, NULL);
615 /* emit index + scale */
617 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
620 emit_register(reg, NULL);
622 scale = get_ia32_am_scale(node);
624 be_emit_irprintf(",%d", 1 << scale);
632 * fmt parameter output
633 * ---- ---------------------- ---------------------------------------------
635 * %AM <node> address mode of the node
636 * %AR const arch_register_t* address mode of the node or register
637 * %ASx <node> address mode of the node or source register x
638 * %Dx <node> destination register x
639 * %I <node> immediate of the node
640 * %L <node> control flow target of the node
641 * %M <node> mode suffix of the node
642 * %P int condition code
643 * %R const arch_register_t* register
644 * %Sx <node> source register x
645 * %s const char* string
646 * %u unsigned int unsigned int
647 * %d signed int signed int
650 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
651 * * modifier does not prefix immediates with $, but AM with *
652 * l modifier for %lu and %ld
654 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
660 const char *start = fmt;
661 ia32_emit_mod_t mod = 0;
663 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
666 be_emit_string_len(start, fmt - start);
670 be_emit_finish_line_gas(node);
682 mod |= EMIT_ALTERNATE_AM;
687 mod |= EMIT_RESPECT_LS;
704 if (mod & EMIT_ALTERNATE_AM)
711 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
712 if (mod & EMIT_ALTERNATE_AM)
714 if (get_ia32_op_type(node) == ia32_AddrModeS) {
717 emit_register(reg, NULL);
723 if (get_ia32_op_type(node) == ia32_AddrModeS) {
724 if (mod & EMIT_ALTERNATE_AM)
729 assert(get_ia32_op_type(node) == ia32_Normal);
734 default: goto unknown;
741 const arch_register_t *reg;
743 if (*fmt < '0' || '9' <= *fmt)
747 reg = get_out_reg(node, pos);
748 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
753 if (!(mod & EMIT_ALTERNATE_AM))
755 emit_ia32_Immediate_no_prefix(node);
759 ia32_emit_cfop_target(node);
763 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
768 int pnc = va_arg(ap, int);
769 ia32_emit_cmp_suffix(pnc);
774 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
775 emit_register(reg, NULL);
784 if (*fmt < '0' || '9' <= *fmt)
788 in = get_irn_n(node, pos);
789 if (is_ia32_Immediate(in)) {
790 if (!(mod & EMIT_ALTERNATE_AM))
792 emit_ia32_Immediate_no_prefix(in);
794 const arch_register_t *reg;
796 if (mod & EMIT_ALTERNATE_AM)
798 reg = get_in_reg(node, pos);
799 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
805 const char *str = va_arg(ap, const char*);
811 if (mod & EMIT_LONG) {
812 unsigned long num = va_arg(ap, unsigned long);
813 be_emit_irprintf("%lu", num);
815 unsigned num = va_arg(ap, unsigned);
816 be_emit_irprintf("%u", num);
821 if (mod & EMIT_LONG) {
822 long num = va_arg(ap, long);
823 be_emit_irprintf("%ld", num);
825 int num = va_arg(ap, int);
826 be_emit_irprintf("%d", num);
832 panic("unknown format conversion in ia32_emitf()");
840 * Emits registers and/or address mode of a binary operation.
842 void ia32_emit_binop(const ir_node *node)
844 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
845 ia32_emitf(node, "%#S4, %#AS3");
847 ia32_emitf(node, "%#AS4, %#S3");
852 * Emits registers and/or address mode of a binary operation.
854 void ia32_emit_x87_binop(const ir_node *node)
856 switch(get_ia32_op_type(node)) {
859 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
860 const arch_register_t *in1 = x87_attr->x87[0];
861 const arch_register_t *in = x87_attr->x87[1];
862 const arch_register_t *out = x87_attr->x87[2];
866 } else if (out == in) {
871 be_emit_string(arch_register_get_name(in));
872 be_emit_cstring(", %");
873 be_emit_string(arch_register_get_name(out));
881 assert(0 && "unsupported op type");
886 * Emits registers and/or address mode of a unary operation.
888 void ia32_emit_unop(const ir_node *node, int pos)
892 ia32_emitf(node, fmt);
895 static void emit_ia32_IMul(const ir_node *node)
897 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
898 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
900 /* do we need the 3-address form? */
901 if (is_ia32_NoReg_GP(left) ||
902 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
903 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
905 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
910 * walks up a tree of copies/perms/spills/reloads to find the original value
911 * that is moved around
913 static ir_node *find_original_value(ir_node *node)
915 if (irn_visited(node))
918 mark_irn_visited(node);
919 if (be_is_Copy(node)) {
920 return find_original_value(be_get_Copy_op(node));
921 } else if (be_is_CopyKeep(node)) {
922 return find_original_value(be_get_CopyKeep_op(node));
923 } else if (is_Proj(node)) {
924 ir_node *pred = get_Proj_pred(node);
925 if (be_is_Perm(pred)) {
926 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
927 } else if (be_is_MemPerm(pred)) {
928 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
929 } else if (is_ia32_Load(pred)) {
930 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
934 } else if (is_ia32_Store(node)) {
935 return find_original_value(get_irn_n(node, n_ia32_Store_val));
936 } else if (is_Phi(node)) {
938 arity = get_irn_arity(node);
939 for (i = 0; i < arity; ++i) {
940 ir_node *in = get_irn_n(node, i);
941 ir_node *res = find_original_value(in);
952 static int determine_final_pnc(const ir_node *node, int flags_pos,
955 ir_node *flags = get_irn_n(node, flags_pos);
956 const ia32_attr_t *flags_attr;
957 flags = skip_Proj(flags);
959 if (is_ia32_Sahf(flags)) {
960 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
961 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
962 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
963 inc_irg_visited(current_ir_graph);
964 cmp = find_original_value(cmp);
966 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
967 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
970 flags_attr = get_ia32_attr_const(cmp);
971 if (flags_attr->data.ins_permuted)
972 pnc = get_mirrored_pnc(pnc);
973 pnc |= ia32_pn_Cmp_float;
974 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
975 || is_ia32_Fucompi(flags)) {
976 flags_attr = get_ia32_attr_const(flags);
978 if (flags_attr->data.ins_permuted)
979 pnc = get_mirrored_pnc(pnc);
980 pnc |= ia32_pn_Cmp_float;
982 flags_attr = get_ia32_attr_const(flags);
984 if (flags_attr->data.ins_permuted)
985 pnc = get_mirrored_pnc(pnc);
986 if (flags_attr->data.cmp_unsigned)
987 pnc |= ia32_pn_Cmp_unsigned;
993 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
995 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
996 return get_negated_pnc(pnc, mode);
999 void ia32_emit_cmp_suffix_node(const ir_node *node,
1002 const ia32_attr_t *attr = get_ia32_attr_const(node);
1004 pn_Cmp pnc = get_ia32_condcode(node);
1006 pnc = determine_final_pnc(node, flags_pos, pnc);
1007 if (attr->data.ins_permuted)
1008 pnc = ia32_get_negated_pnc(pnc);
1010 ia32_emit_cmp_suffix(pnc);
1014 * Emits an exception label for a given node.
1016 static void ia32_emit_exc_label(const ir_node *node)
1018 be_emit_string(be_gas_insn_label_prefix());
1019 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1023 * Returns the Proj with projection number proj and NOT mode_M
1025 static ir_node *get_proj(const ir_node *node, long proj)
1027 const ir_edge_t *edge;
1030 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1032 foreach_out_edge(node, edge) {
1033 src = get_edge_src_irn(edge);
1035 assert(is_Proj(src) && "Proj expected");
1036 if (get_irn_mode(src) == mode_M)
1039 if (get_Proj_proj(src) == proj)
1045 static int can_be_fallthrough(const ir_node *node)
1047 ir_node *target_block = get_cfop_target_block(node);
1048 ir_node *block = get_nodes_block(node);
1049 return get_prev_block_sched(target_block) == block;
1053 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1055 static void emit_ia32_Jcc(const ir_node *node)
1057 int need_parity_label = 0;
1058 const ir_node *proj_true;
1059 const ir_node *proj_false;
1060 const ir_node *block;
1061 pn_Cmp pnc = get_ia32_condcode(node);
1063 pnc = determine_final_pnc(node, 0, pnc);
1065 /* get both Projs */
1066 proj_true = get_proj(node, pn_ia32_Jcc_true);
1067 assert(proj_true && "Jcc without true Proj");
1069 proj_false = get_proj(node, pn_ia32_Jcc_false);
1070 assert(proj_false && "Jcc without false Proj");
1072 block = get_nodes_block(node);
1074 if (can_be_fallthrough(proj_true)) {
1075 /* exchange both proj's so the second one can be omitted */
1076 const ir_node *t = proj_true;
1078 proj_true = proj_false;
1080 pnc = ia32_get_negated_pnc(pnc);
1083 if (pnc & ia32_pn_Cmp_float) {
1084 /* Some floating point comparisons require a test of the parity flag,
1085 * which indicates that the result is unordered */
1088 ia32_emitf(proj_true, "\tjp %L\n");
1093 ia32_emitf(proj_true, "\tjnp %L\n");
1099 /* we need a local label if the false proj is a fallthrough
1100 * as the falseblock might have no label emitted then */
1101 if (can_be_fallthrough(proj_false)) {
1102 need_parity_label = 1;
1103 ia32_emitf(proj_false, "\tjp 1f\n");
1105 ia32_emitf(proj_false, "\tjp %L\n");
1112 ia32_emitf(proj_true, "\tjp %L\n");
1120 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1123 if (need_parity_label) {
1124 ia32_emitf(NULL, "1:\n");
1127 /* the second Proj might be a fallthrough */
1128 if (can_be_fallthrough(proj_false)) {
1129 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1131 ia32_emitf(proj_false, "\tjmp %L\n");
1135 static void emit_ia32_CMov(const ir_node *node)
1137 const ia32_attr_t *attr = get_ia32_attr_const(node);
1138 int ins_permuted = attr->data.ins_permuted;
1139 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1140 pn_Cmp pnc = get_ia32_condcode(node);
1141 const arch_register_t *in_true;
1142 const arch_register_t *in_false;
1144 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1146 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1147 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1149 /* should be same constraint fullfilled? */
1150 if (out == in_false) {
1151 /* yes -> nothing to do */
1152 } else if (out == in_true) {
1153 const arch_register_t *tmp;
1155 assert(get_ia32_op_type(node) == ia32_Normal);
1157 ins_permuted = !ins_permuted;
1164 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1168 pnc = ia32_get_negated_pnc(pnc);
1170 /* TODO: handling of Nans isn't correct yet */
1172 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1175 /*********************************************************
1178 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1179 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1180 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1181 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1184 *********************************************************/
1186 /* jump table entry (target and corresponding number) */
1187 typedef struct _branch_t {
1192 /* jump table for switch generation */
1193 typedef struct _jmp_tbl_t {
1194 ir_node *defProj; /**< default target */
1195 long min_value; /**< smallest switch case */
1196 long max_value; /**< largest switch case */
1197 long num_branches; /**< number of jumps */
1198 char *label; /**< label of the jump table */
1199 branch_t *branches; /**< jump array */
1203 * Compare two variables of type branch_t. Used to sort all switch cases
1205 static int ia32_cmp_branch_t(const void *a, const void *b)
1207 branch_t *b1 = (branch_t *)a;
1208 branch_t *b2 = (branch_t *)b;
1210 if (b1->value <= b2->value)
1217 * Emits code for a SwitchJmp (creates a jump table if
1218 * possible otherwise a cmp-jmp cascade). Port from
1221 static void emit_ia32_SwitchJmp(const ir_node *node)
1223 unsigned long interval;
1229 const ir_edge_t *edge;
1231 /* fill the table structure */
1232 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1233 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1235 tbl.num_branches = get_irn_n_edges(node) - 1;
1236 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1237 tbl.min_value = INT_MAX;
1238 tbl.max_value = INT_MIN;
1240 default_pn = get_ia32_condcode(node);
1242 /* go over all proj's and collect them */
1243 foreach_out_edge(node, edge) {
1244 proj = get_edge_src_irn(edge);
1245 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1247 pnc = get_Proj_proj(proj);
1249 /* check for default proj */
1250 if (pnc == default_pn) {
1251 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1254 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1255 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1257 /* create branch entry */
1258 tbl.branches[i].target = proj;
1259 tbl.branches[i].value = pnc;
1264 assert(i == tbl.num_branches);
1266 /* sort the branches by their number */
1267 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1269 /* two-complement's magic make this work without overflow */
1270 interval = tbl.max_value - tbl.min_value;
1272 /* emit the table */
1273 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1274 ia32_emitf(tbl.defProj, "\tja %L\n");
1276 if (tbl.num_branches > 1) {
1278 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1280 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1281 ia32_emitf(NULL, "\t.align 4\n");
1282 ia32_emitf(NULL, "%s:\n", tbl.label);
1284 last_value = tbl.branches[0].value;
1285 for (i = 0; i != tbl.num_branches; ++i) {
1286 while (last_value != tbl.branches[i].value) {
1287 ia32_emitf(tbl.defProj, ".long %L\n");
1290 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1293 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1295 /* one jump is enough */
1296 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1306 * Emits code for a unconditional jump.
1308 static void emit_ia32_Jmp(const ir_node *node)
1312 /* for now, the code works for scheduled and non-schedules blocks */
1313 block = get_nodes_block(node);
1315 /* we have a block schedule */
1316 if (can_be_fallthrough(node)) {
1317 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1319 ia32_emitf(node, "\tjmp %L\n");
1324 * Emit an inline assembler operand.
1326 * @param node the ia32_ASM node
1327 * @param s points to the operand (a %c)
1329 * @return pointer to the first char in s NOT in the current operand
1331 static const char* emit_asm_operand(const ir_node *node, const char *s)
1333 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1334 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1336 const arch_register_t *reg;
1337 const ia32_asm_reg_t *asm_regs = attr->register_map;
1338 const ia32_asm_reg_t *asm_reg;
1339 const char *reg_name;
1348 /* parse modifiers */
1351 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1376 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1383 sscanf(s, "%d%n", &num, &p);
1385 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1392 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1394 "Error: Custom assembler references invalid input/output (%+F)\n",
1398 asm_reg = & asm_regs[num];
1399 assert(asm_reg->valid);
1402 if (asm_reg->use_input == 0) {
1403 reg = get_out_reg(node, asm_reg->inout_pos);
1405 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1407 /* might be an immediate value */
1408 if (is_ia32_Immediate(pred)) {
1409 emit_ia32_Immediate(pred);
1412 reg = get_in_reg(node, asm_reg->inout_pos);
1416 "Warning: no register assigned for %d asm op (%+F)\n",
1421 if (asm_reg->memory) {
1426 if (modifier != 0) {
1430 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1433 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1436 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1439 panic("Invalid asm op modifier");
1441 be_emit_string(reg_name);
1443 emit_register(reg, asm_reg->mode);
1446 if (asm_reg->memory) {
1454 * Emits code for an ASM pseudo op.
1456 static void emit_ia32_Asm(const ir_node *node)
1458 const void *gen_attr = get_irn_generic_attr_const(node);
1459 const ia32_asm_attr_t *attr
1460 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1461 ident *asm_text = attr->asm_text;
1462 const char *s = get_id_str(asm_text);
1464 ia32_emitf(node, "#APP\t\n");
1471 s = emit_asm_operand(node, s);
1477 ia32_emitf(NULL, "\n#NO_APP\n");
1480 /**********************************
1483 * | | ___ _ __ _ _| |_) |
1484 * | | / _ \| '_ \| | | | _ <
1485 * | |___| (_) | |_) | |_| | |_) |
1486 * \_____\___/| .__/ \__, |____/
1489 **********************************/
1492 * Emit movsb/w instructions to make mov count divideable by 4
1494 static void emit_CopyB_prolog(unsigned size)
1497 ia32_emitf(NULL, "\tmovsb\n");
1499 ia32_emitf(NULL, "\tmovsw\n");
1503 * Emit rep movsd instruction for memcopy.
1505 static void emit_ia32_CopyB(const ir_node *node)
1507 unsigned size = get_ia32_copyb_size(node);
1509 emit_CopyB_prolog(size);
1510 ia32_emitf(node, "\trep movsd\n");
1514 * Emits unrolled memcopy.
1516 static void emit_ia32_CopyB_i(const ir_node *node)
1518 unsigned size = get_ia32_copyb_size(node);
1520 emit_CopyB_prolog(size);
1524 ia32_emitf(NULL, "\tmovsd\n");
1530 /***************************
1534 * | | / _ \| '_ \ \ / /
1535 * | |___| (_) | | | \ V /
1536 * \_____\___/|_| |_|\_/
1538 ***************************/
1541 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1543 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1546 ir_mode *ls_mode = get_ia32_ls_mode(node);
1547 int ls_bits = get_mode_size_bits(ls_mode);
1548 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1550 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1553 static void emit_ia32_Conv_I2FP(const ir_node *node)
1555 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1558 static void emit_ia32_Conv_FP2I(const ir_node *node)
1560 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1563 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1565 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1569 * Emits code for an Int conversion.
1571 static void emit_ia32_Conv_I2I(const ir_node *node)
1573 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1574 int signed_mode = mode_is_signed(smaller_mode);
1575 const char *sign_suffix;
1577 assert(!mode_is_float(smaller_mode));
1579 sign_suffix = signed_mode ? "s" : "z";
1580 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1586 static void emit_ia32_Call(const ir_node *node)
1588 /* Special case: Call must not have its immediates prefixed by $, instead
1589 * address mode is prefixed by *. */
1590 ia32_emitf(node, "\tcall %*AS3\n");
1594 /*******************************************
1597 * | |__ ___ _ __ ___ __| | ___ ___
1598 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1599 * | |_) | __/ | | | (_) | (_| | __/\__ \
1600 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1602 *******************************************/
1605 * Emits code to increase stack pointer.
1607 static void emit_be_IncSP(const ir_node *node)
1609 int offs = be_get_IncSP_offset(node);
1615 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1617 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1621 static inline bool is_unknown_reg(const arch_register_t *reg)
1623 if(reg == &ia32_gp_regs[REG_GP_UKNWN]
1624 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1625 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1632 * Emits code for Copy/CopyKeep.
1634 static void Copy_emitter(const ir_node *node, const ir_node *op)
1636 const arch_register_t *in = arch_get_irn_register(op);
1637 const arch_register_t *out = arch_get_irn_register(node);
1642 if (is_unknown_reg(in))
1644 /* copies of vf nodes aren't real... */
1645 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1648 if (get_irn_mode(node) == mode_E) {
1649 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1651 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1655 static void emit_be_Copy(const ir_node *node)
1657 Copy_emitter(node, be_get_Copy_op(node));
1660 static void emit_be_CopyKeep(const ir_node *node)
1662 Copy_emitter(node, be_get_CopyKeep_op(node));
1666 * Emits code for exchange.
1668 static void emit_be_Perm(const ir_node *node)
1670 const arch_register_t *in0, *in1;
1671 const arch_register_class_t *cls0, *cls1;
1673 in0 = arch_get_irn_register(get_irn_n(node, 0));
1674 in1 = arch_get_irn_register(get_irn_n(node, 1));
1676 cls0 = arch_register_get_class(in0);
1677 cls1 = arch_register_get_class(in1);
1679 assert(cls0 == cls1 && "Register class mismatch at Perm");
1681 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1682 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1683 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1684 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1685 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1686 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1687 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1689 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1692 panic("unexpected register class in be_Perm (%+F)", node);
1697 * Emits code for Constant loading.
1699 static void emit_ia32_Const(const ir_node *node)
1701 ia32_emitf(node, "\tmovl %I, %D0\n");
1705 * Emits code to load the TLS base
1707 static void emit_ia32_LdTls(const ir_node *node)
1709 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1712 /* helper function for emit_ia32_Minus64Bit */
1713 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1715 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1718 /* helper function for emit_ia32_Minus64Bit */
1719 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1721 ia32_emitf(node, "\tnegl %R\n", reg);
1724 /* helper function for emit_ia32_Minus64Bit */
1725 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1727 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1730 /* helper function for emit_ia32_Minus64Bit */
1731 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1733 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1736 /* helper function for emit_ia32_Minus64Bit */
1737 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1739 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1742 /* helper function for emit_ia32_Minus64Bit */
1743 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1745 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1748 static void emit_ia32_Minus64Bit(const ir_node *node)
1750 const arch_register_t *in_lo = get_in_reg(node, 0);
1751 const arch_register_t *in_hi = get_in_reg(node, 1);
1752 const arch_register_t *out_lo = get_out_reg(node, 0);
1753 const arch_register_t *out_hi = get_out_reg(node, 1);
1755 if (out_lo == in_lo) {
1756 if (out_hi != in_hi) {
1757 /* a -> a, b -> d */
1760 /* a -> a, b -> b */
1763 } else if (out_lo == in_hi) {
1764 if (out_hi == in_lo) {
1765 /* a -> b, b -> a */
1766 emit_xchg(node, in_lo, in_hi);
1769 /* a -> b, b -> d */
1770 emit_mov(node, in_hi, out_hi);
1771 emit_mov(node, in_lo, out_lo);
1775 if (out_hi == in_lo) {
1776 /* a -> c, b -> a */
1777 emit_mov(node, in_lo, out_lo);
1779 } else if (out_hi == in_hi) {
1780 /* a -> c, b -> b */
1781 emit_mov(node, in_lo, out_lo);
1784 /* a -> c, b -> d */
1785 emit_mov(node, in_lo, out_lo);
1791 emit_neg( node, out_hi);
1792 emit_neg( node, out_lo);
1793 emit_sbb0(node, out_hi);
1797 emit_zero(node, out_hi);
1798 emit_neg( node, out_lo);
1799 emit_sbb( node, in_hi, out_hi);
1802 static void emit_ia32_GetEIP(const ir_node *node)
1804 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1805 ia32_emitf(NULL, "%s:\n", pic_base_label);
1806 ia32_emitf(node, "\tpopl %D0\n");
1809 static void emit_ia32_ClimbFrame(const ir_node *node)
1811 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1813 ia32_emitf(node, "\tmovl %S0, %D0\n");
1814 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1815 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1816 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1817 ia32_emitf(node, "\tdec %S1\n");
1818 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1821 static void emit_be_Return(const ir_node *node)
1823 unsigned pop = be_Return_get_pop(node);
1825 if (pop > 0 || be_Return_get_emit_pop(node)) {
1826 ia32_emitf(node, "\tret $%u\n", pop);
1828 ia32_emitf(node, "\tret\n");
1832 static void emit_Nothing(const ir_node *node)
1838 /***********************************************************************************
1841 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1842 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1843 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1844 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1846 ***********************************************************************************/
1849 * Enters the emitter functions for handled nodes into the generic
1850 * pointer of an opcode.
1852 static void ia32_register_emitters(void)
1854 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1855 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1856 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1857 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1858 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1859 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1861 /* first clear the generic function pointer for all ops */
1862 clear_irp_opcodes_generic_func();
1864 /* register all emitter functions defined in spec */
1865 ia32_register_spec_emitters();
1867 /* other ia32 emitter functions */
1868 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1873 IA32_EMIT(Conv_FP2FP);
1874 IA32_EMIT(Conv_FP2I);
1875 IA32_EMIT(Conv_I2FP);
1876 IA32_EMIT(Conv_I2I);
1883 IA32_EMIT(Minus64Bit);
1884 IA32_EMIT(SwitchJmp);
1885 IA32_EMIT(ClimbFrame);
1888 /* benode emitter */
1909 typedef void (*emit_func_ptr) (const ir_node *);
1912 * Assign and emit an exception label if the current instruction can fail.
1914 static void ia32_assign_exc_label(ir_node *node)
1916 /* assign a new ID to the instruction */
1917 set_ia32_exc_label_id(node, ++exc_label_id);
1919 ia32_emit_exc_label(node);
1921 be_emit_pad_comment();
1922 be_emit_cstring("/* exception to Block ");
1923 ia32_emit_cfop_target(node);
1924 be_emit_cstring(" */\n");
1925 be_emit_write_line();
1929 * Emits code for a node.
1931 static void ia32_emit_node(ir_node *node)
1933 ir_op *op = get_irn_op(node);
1935 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1937 if (is_ia32_irn(node)) {
1938 if (get_ia32_exc_label(node)) {
1939 /* emit the exception label of this instruction */
1940 ia32_assign_exc_label(node);
1942 if (mark_spill_reload) {
1943 if (is_ia32_is_spill(node)) {
1944 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1946 if (is_ia32_is_reload(node)) {
1947 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1949 if (is_ia32_is_remat(node)) {
1950 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1954 if (op->ops.generic) {
1955 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1957 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1962 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1968 * Emits gas alignment directives
1970 static void ia32_emit_alignment(unsigned align, unsigned skip)
1972 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1976 * Emits gas alignment directives for Labels depended on cpu architecture.
1978 static void ia32_emit_align_label(void)
1980 unsigned align = ia32_cg_config.label_alignment;
1981 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1982 ia32_emit_alignment(align, maximum_skip);
1986 * Test whether a block should be aligned.
1987 * For cpus in the P4/Athlon class it is useful to align jump labels to
1988 * 16 bytes. However we should only do that if the alignment nops before the
1989 * label aren't executed more often than we have jumps to the label.
1991 static int should_align_block(const ir_node *block)
1993 static const double DELTA = .0001;
1994 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1995 ir_node *prev = get_prev_block_sched(block);
1997 double prev_freq = 0; /**< execfreq of the fallthrough block */
1998 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2001 if (exec_freq == NULL)
2003 if (ia32_cg_config.label_alignment_factor <= 0)
2006 block_freq = get_block_execfreq(exec_freq, block);
2007 if (block_freq < DELTA)
2010 n_cfgpreds = get_Block_n_cfgpreds(block);
2011 for(i = 0; i < n_cfgpreds; ++i) {
2012 const ir_node *pred = get_Block_cfgpred_block(block, i);
2013 double pred_freq = get_block_execfreq(exec_freq, pred);
2016 prev_freq += pred_freq;
2018 jmp_freq += pred_freq;
2022 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2025 jmp_freq /= prev_freq;
2027 return jmp_freq > ia32_cg_config.label_alignment_factor;
2031 * Emit the block header for a block.
2033 * @param block the block
2034 * @param prev_block the previous block
2036 static void ia32_emit_block_header(ir_node *block)
2038 ir_graph *irg = current_ir_graph;
2039 int need_label = block_needs_label(block);
2041 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2043 if (block == get_irg_end_block(irg))
2046 if (ia32_cg_config.label_alignment > 0) {
2047 /* align the current block if:
2048 * a) if should be aligned due to its execution frequency
2049 * b) there is no fall-through here
2051 if (should_align_block(block)) {
2052 ia32_emit_align_label();
2054 /* if the predecessor block has no fall-through,
2055 we can always align the label. */
2057 int has_fallthrough = 0;
2059 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2060 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2061 if (can_be_fallthrough(cfg_pred)) {
2062 has_fallthrough = 1;
2067 if (!has_fallthrough)
2068 ia32_emit_align_label();
2073 ia32_emit_block_name(block);
2076 be_emit_pad_comment();
2077 be_emit_cstring(" /* ");
2079 be_emit_cstring("\t/* ");
2080 ia32_emit_block_name(block);
2081 be_emit_cstring(": ");
2084 be_emit_cstring("preds:");
2086 /* emit list of pred blocks in comment */
2087 arity = get_irn_arity(block);
2089 be_emit_cstring(" none");
2091 for (i = 0; i < arity; ++i) {
2092 ir_node *predblock = get_Block_cfgpred_block(block, i);
2093 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2096 if (exec_freq != NULL) {
2097 be_emit_irprintf(", freq: %f",
2098 get_block_execfreq(exec_freq, block));
2100 be_emit_cstring(" */\n");
2101 be_emit_write_line();
2105 * Walks over the nodes in a block connected by scheduling edges
2106 * and emits code for each node.
2108 static void ia32_gen_block(ir_node *block)
2112 ia32_emit_block_header(block);
2114 /* emit the contents of the block */
2115 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2116 sched_foreach(block, node) {
2117 ia32_emit_node(node);
2121 typedef struct exc_entry {
2122 ir_node *exc_instr; /** The instruction that can issue an exception. */
2123 ir_node *block; /** The block to call then. */
2128 * Sets labels for control flow nodes (jump target).
2129 * Links control predecessors to there destination blocks.
2131 static void ia32_gen_labels(ir_node *block, void *data)
2133 exc_entry **exc_list = data;
2137 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2138 pred = get_Block_cfgpred(block, n);
2139 set_irn_link(pred, block);
2141 pred = skip_Proj(pred);
2142 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2147 ARR_APP1(exc_entry, *exc_list, e);
2148 set_irn_link(pred, block);
2154 * Compare two exception_entries.
2156 static int cmp_exc_entry(const void *a, const void *b)
2158 const exc_entry *ea = a;
2159 const exc_entry *eb = b;
2161 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2167 * Main driver. Emits the code for one routine.
2169 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2171 ir_entity *entity = get_irg_entity(irg);
2172 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2177 do_pic = cg->birg->main_env->options->pic;
2179 ia32_register_emitters();
2181 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2183 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2184 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2186 /* we use links to point to target blocks */
2187 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2188 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2190 /* initialize next block links */
2191 n = ARR_LEN(cg->blk_sched);
2192 for (i = 0; i < n; ++i) {
2193 ir_node *block = cg->blk_sched[i];
2194 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2196 set_irn_link(block, prev);
2199 for (i = 0; i < n; ++i) {
2200 ir_node *block = cg->blk_sched[i];
2202 ia32_gen_block(block);
2205 be_gas_emit_function_epilog(entity);
2206 be_dbg_method_end();
2208 be_emit_write_line();
2210 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2212 /* Sort the exception table using the exception label id's.
2213 Those are ascending with ascending addresses. */
2214 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2218 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2219 be_emit_cstring("\t.long ");
2220 ia32_emit_exc_label(exc_list[i].exc_instr);
2222 be_emit_cstring("\t.long ");
2223 ia32_emit_block_name(exc_list[i].block);
2227 DEL_ARR_F(exc_list);
2230 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2231 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2235 /* ==== Experimental binary emitter ==== */
2237 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2238 static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2239 static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2240 static unsigned char pnc_map_signed[8];
2241 static unsigned char pnc_map_unsigned[8];
2243 static void build_reg_map(void)
2245 reg_gp_map[REG_EAX] = 0x0;
2246 reg_gp_map[REG_ECX] = 0x1;
2247 reg_gp_map[REG_EDX] = 0x2;
2248 reg_gp_map[REG_EBX] = 0x3;
2249 reg_gp_map[REG_ESP] = 0x4;
2250 reg_gp_map[REG_EBP] = 0x5;
2251 reg_gp_map[REG_ESI] = 0x6;
2252 reg_gp_map[REG_EDI] = 0x7;
2254 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2255 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2256 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2257 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2258 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2259 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2261 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2262 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2263 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2264 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2265 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2266 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2269 static unsigned char pnc2cc(int pnc)
2272 if (pnc == ia32_pn_Cmp_parity) {
2274 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2275 cc = pnc_map_unsigned[pnc & 0x07];
2277 cc = pnc_map_signed[pnc & 0x07];
2283 /** Sign extension bit values for binops */
2285 UNSIGNED_IMM = 0, /**< unsigned immediate */
2286 SIGNEXT_IMM = 2, /**< sign extended immediate */
2289 /** The mod encoding of the ModR/M */
2291 MOD_IND = 0x00, /**< [reg1] */
2292 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2293 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2294 MOD_REG = 0xC0 /**< reg1 */
2297 /** create R/M encoding for ModR/M */
2298 #define ENC_RM(x) (x)
2299 /** create REG encoding for ModR/M */
2300 #define ENC_REG(x) ((x) << 3)
2302 /** create encoding for a SIB byte */
2303 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2305 /* Node: The following routines are supposed to append bytes, words, dwords
2306 to the output stream.
2307 Currently the implementation is stupid in that it still creates output
2308 for an "assembler" in the form of .byte, .long
2309 We will change this when enough infrastructure is there to create complete
2310 machine code in memory/object files */
2312 static void bemit8(const unsigned char byte)
2314 be_emit_irprintf("\t.byte 0x%x\n", byte);
2315 be_emit_write_line();
2318 static void bemit16(const unsigned short u16)
2320 be_emit_irprintf("\t.word 0x%x\n", u16);
2321 be_emit_write_line();
2324 static void bemit32(const unsigned u32)
2326 be_emit_irprintf("\t.long 0x%x\n", u32);
2327 be_emit_write_line();
2331 * Emit address of an entity. If @p is_relative is true then a relative
2332 * offset from behind the address to the entity is created.
2334 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2337 if (entity == NULL) {
2346 /* the final version should remember the position in the bytestream
2347 and patch it with the correct address at linktime... */
2348 be_emit_cstring("\t.long ");
2351 set_entity_backend_marked(entity, 1);
2352 be_gas_emit_entity(entity);
2355 be_emit_cstring("-.");
2359 be_emit_irprintf("%+d", offset);
2362 be_emit_write_line();
2365 static void bemit_jmp_destination(const ir_node *dest_block)
2367 be_emit_cstring("\t.long ");
2368 ia32_emit_block_name(dest_block);
2369 be_emit_cstring(" - . - 4\n");
2370 be_emit_write_line();
2373 /* end emit routines, all emitters following here should only use the functions
2376 /** Create a ModR/M byte for src1,src2 registers */
2377 static void bemit_modrr(const arch_register_t *src1,
2378 const arch_register_t *src2)
2380 unsigned char modrm = MOD_REG;
2381 modrm |= ENC_RM(reg_gp_map[src1->index]);
2382 modrm |= ENC_REG(reg_gp_map[src2->index]);
2386 /** Create a ModR/M byte for one register and extension */
2387 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2389 unsigned char modrm = MOD_REG;
2391 modrm |= ENC_RM(reg_gp_map[reg->index]);
2392 modrm |= ENC_REG(ext);
2397 * Calculate the size of an signed immediate in bytes.
2399 * @param offset an offset
2401 static unsigned get_signed_imm_size(int offset)
2403 if (-128 <= offset && offset < 128) {
2405 } else if (-32768 <= offset && offset < 32768) {
2413 * Emit an address mode.
2415 * @param reg content of the reg field: either a register index or an opcode extension
2416 * @param node the node
2418 static void bemit_mod_am(unsigned reg, const ir_node *node)
2420 ir_entity *ent = get_ia32_am_sc(node);
2421 int offs = get_ia32_am_offs_int(node);
2422 ir_node *base = get_irn_n(node, n_ia32_base);
2423 int has_base = !is_ia32_NoReg_GP(base);
2424 ir_node *index = get_irn_n(node, n_ia32_index);
2425 int has_index = !is_ia32_NoReg_GP(index);
2428 unsigned emitoffs = 0;
2429 bool emitsib = false;
2432 /* set the mod part depending on displacement */
2434 modrm |= MOD_IND_WORD_OFS;
2436 } else if (offs == 0) {
2439 } else if (-128 <= offs && offs < 128) {
2440 modrm |= MOD_IND_BYTE_OFS;
2443 modrm |= MOD_IND_WORD_OFS;
2448 const arch_register_t *base_reg = arch_get_irn_register(base);
2449 base_enc = reg_gp_map[base_reg->index];
2451 /* Use the EBP encoding + MOD_IND if NO base register. There is
2452 * always a 32bit offset present in this case. */
2458 /* Determine if we need a SIB byte. */
2460 const arch_register_t *reg_index = arch_get_irn_register(index);
2461 int scale = get_ia32_am_scale(node);
2463 /* R/M set to ESP means SIB in 32bit mode. */
2464 modrm |= ENC_RM(0x04);
2465 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2467 } else if (base_enc == 0x04) {
2468 /* for the above reason we are forced to emit a SIB when base is ESP.
2469 * Only the base is used, index must be ESP too, which means no index.
2471 modrm |= ENC_RM(0x04);
2472 sib = ENC_SIB(0, 0x04, 0x04);
2475 modrm |= ENC_RM(base_enc);
2478 /* We are forced to emit an 8bit offset as EBP base without offset is a
2479 * special case for SIB without base register. */
2480 if (base_enc == 0x05 && emitoffs == 0) {
2481 modrm |= MOD_IND_BYTE_OFS;
2485 modrm |= ENC_REG(reg);
2491 /* emit displacement */
2492 if (emitoffs == 8) {
2493 bemit8((unsigned) offs);
2494 } else if (emitoffs == 32) {
2495 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2500 * Emit a binop with a immediate operand.
2502 * @param node the node to emit
2503 * @param opcode_eax the opcode for the op eax, imm variant
2504 * @param opcode the opcode for the reg, imm variant
2505 * @param ruval the opcode extension for opcode
2507 static void bemit_binop_with_imm(
2508 const ir_node *node,
2509 unsigned char opcode_ax,
2510 unsigned char opcode, unsigned char ruval)
2512 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2513 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2514 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2517 /* Some instructions (test) have no short form with 32bit value + 8bit
2519 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2522 /* check for sign extension */
2523 size = get_signed_imm_size(attr->offset);
2528 bemit8(opcode | SIGNEXT_IMM);
2529 /* cmp has this special mode */
2530 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2531 bemit_mod_am(ruval, node);
2533 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2534 bemit_modru(reg, ruval);
2536 bemit8((unsigned char)attr->offset);
2540 /* check for eax variant: this variant is shorter for 32bit immediates only */
2541 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2543 bemit_mod_am(ruval, node);
2545 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2546 if (reg->index == REG_EAX) {
2550 bemit_modru(reg, ruval);
2553 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2556 panic("invalid imm size?!?");
2562 static void bemit_binop_2(const ir_node *node, unsigned code)
2564 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2566 if (get_ia32_op_type(node) == ia32_Normal) {
2567 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2568 bemit_modrr(op2, out);
2570 bemit_mod_am(reg_gp_map[out->index], node);
2577 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2579 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2580 if (is_ia32_Immediate(right)) {
2581 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2583 bemit_binop_2(node, opcodes[0]);
2590 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2593 if (get_ia32_op_type(node) == ia32_Normal) {
2594 const arch_register_t *in = get_in_reg(node, input);
2595 bemit_modru(in, ext);
2597 bemit_mod_am(ext, node);
2601 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2603 const arch_register_t *out = get_out_reg(node, 0);
2604 bemit_unop(node, code, reg_gp_map[out->index], input);
2607 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2609 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2612 bemit8(size == 8 ? code : code + 1);
2613 bemit_mod_am(ext, node);
2616 static void bemit_immediate(const ir_node *node, bool relative)
2618 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2619 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2622 static void bemit_copy(const ir_node *copy)
2624 const arch_register_t *in = get_in_reg(copy, 0);
2625 const arch_register_t *out = get_out_reg(copy, 0);
2627 if (in == out || is_unknown_reg(in))
2629 /* copies of vf nodes aren't real... */
2630 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2633 if (get_irn_mode(copy) == mode_E) {
2636 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2638 bemit_modrr(in, out);
2642 static void bemit_perm(const ir_node *node)
2644 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2645 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2646 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2648 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2650 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2651 if (in0->index == REG_EAX) {
2652 bemit8(0x90 + reg_gp_map[in1->index]);
2653 } else if (in1->index == REG_EAX) {
2654 bemit8(0x90 + reg_gp_map[in0->index]);
2657 bemit_modrr(in0, in1);
2659 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2660 panic("unimplemented"); // TODO implement
2661 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2662 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2663 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2664 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2666 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2669 panic("unexpected register class in be_Perm (%+F)", node);
2673 static void bemit_xor0(const ir_node *node)
2675 const arch_register_t *out = get_out_reg(node, 0);
2677 bemit_modrr(out, out);
2680 static void bemit_mov_const(const ir_node *node)
2682 const arch_register_t *out = get_out_reg(node, 0);
2683 bemit8(0xB8 + reg_gp_map[out->index]);
2684 bemit_immediate(node, false);
2688 * Creates a function for a Binop with 3 possible encodings.
2690 #define BINOP(op, op0, op1, op2, op2_ext) \
2691 static void bemit_ ## op(const ir_node *node) { \
2692 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2693 bemit_binop(node, op ## _codes); \
2696 /* insn def eax,imm imm */
2697 BINOP(add, 0x03, 0x05, 0x81, 0)
2698 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2699 BINOP(adc, 0x13, 0x15, 0x81, 2)
2700 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2701 BINOP(and, 0x23, 0x25, 0x81, 4)
2702 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2703 BINOP(xor, 0x33, 0x35, 0x81, 6)
2704 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2706 #define BINOPMEM(op, ext) \
2707 static void bemit_##op(const ir_node *node) \
2709 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2712 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2713 if (is_ia32_Immediate(val)) { \
2714 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2715 int offset = attr->offset; \
2716 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2718 bemit_mod_am(ext, node); \
2722 bemit_mod_am(ext, node); \
2726 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2730 bemit8(ext << 3 | 1); \
2731 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2735 static void bemit_##op##8bit(const ir_node *node) \
2737 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2738 if (is_ia32_Immediate(val)) { \
2740 bemit_mod_am(ext, node); \
2741 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2744 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2756 * Creates a function for an Unop with code /ext encoding.
2758 #define UNOP(op, code, ext, input) \
2759 static void bemit_ ## op(const ir_node *node) { \
2760 bemit_unop(node, code, ext, input); \
2763 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2764 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2765 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2766 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2767 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2768 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2770 /* TODO: am support for IJmp */
2771 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2773 #define SHIFT(op, ext) \
2774 static void bemit_##op(const ir_node *node) \
2776 const arch_register_t *out = get_out_reg(node, 0); \
2777 ir_node *count = get_irn_n(node, 1); \
2778 if (is_ia32_Immediate(count)) { \
2779 int offset = get_ia32_immediate_attr_const(count)->offset; \
2780 if (offset == 1) { \
2782 bemit_modru(out, ext); \
2785 bemit_modru(out, ext); \
2790 bemit_modru(out, ext); \
2794 static void bemit_##op##mem(const ir_node *node) \
2796 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2799 ir_node *count = get_irn_n(node, 1); \
2800 if (is_ia32_Immediate(count)) { \
2801 int offset = get_ia32_immediate_attr_const(count)->offset; \
2802 if (offset == 1) { \
2803 bemit8(size == 1 ? 0xD0 : 0xD1); \
2804 bemit_mod_am(ext, node); \
2806 bemit8(size == 1 ? 0xC0 : 0xC1); \
2807 bemit_mod_am(ext, node); \
2811 bemit8(size == 1 ? 0xD2 : 0xD3); \
2812 bemit_mod_am(ext, node); \
2822 static void bemit_shld(const ir_node *node)
2824 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2825 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2826 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2828 if (is_ia32_Immediate(count)) {
2830 bemit_modrr(out, in);
2831 bemit8(get_ia32_immediate_attr_const(count)->offset);
2834 bemit_modrr(out, in);
2838 static void bemit_shrd(const ir_node *node)
2840 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2841 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2842 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2844 if (is_ia32_Immediate(count)) {
2846 bemit_modrr(out, in);
2847 bemit8(get_ia32_immediate_attr_const(count)->offset);
2850 bemit_modrr(out, in);
2854 static void bemit_cmov(const ir_node *node)
2856 const ia32_attr_t *attr = get_ia32_attr_const(node);
2857 int ins_permuted = attr->data.ins_permuted;
2858 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2859 pn_Cmp pnc = get_ia32_condcode(node);
2860 const arch_register_t *in_true;
2861 const arch_register_t *in_false;
2863 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
2865 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
2866 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
2868 /* should be same constraint fullfilled? */
2869 if (out == in_false) {
2870 /* yes -> nothing to do */
2871 } else if (out == in_true) {
2872 assert(get_ia32_op_type(node) == ia32_Normal);
2873 ins_permuted = !ins_permuted;
2877 bemit8(0x8B); // mov %in_false, %out
2878 bemit_modrr(in_false, out);
2882 pnc = ia32_get_negated_pnc(pnc);
2884 /* TODO: handling of Nans isn't correct yet */
2887 bemit8(0x40 + pnc2cc(pnc));
2888 if (get_ia32_op_type(node) == ia32_Normal) {
2889 bemit_modrr(in_true, out);
2891 bemit_mod_am(reg_gp_map[out->index], node);
2895 static void bemit_cmp(const ir_node *node)
2897 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2903 right = get_irn_n(node, n_ia32_binary_right);
2904 if (is_ia32_Immediate(right)) {
2905 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2906 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2907 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2910 if (attr->symconst != NULL) {
2913 /* check for sign extension */
2914 size = get_signed_imm_size(attr->offset);
2919 bemit8(0x81 | SIGNEXT_IMM);
2920 /* cmp has this special mode */
2921 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2922 bemit_mod_am(7, node);
2924 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2925 bemit_modru(reg, 7);
2927 bemit8((unsigned char)attr->offset);
2931 /* check for eax variant: this variant is shorter for 32bit immediates only */
2932 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2934 bemit_mod_am(7, node);
2936 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2937 if (reg->index == REG_EAX) {
2941 bemit_modru(reg, 7);
2944 if (ls_size == 16) {
2945 bemit16(attr->offset);
2947 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2951 panic("invalid imm size?!?");
2953 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2955 if (get_ia32_op_type(node) == ia32_Normal) {
2956 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2957 bemit_modrr(op2, out);
2959 bemit_mod_am(reg_gp_map[out->index], node);
2964 static void bemit_cmp8bit(const ir_node *node)
2966 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2967 if (is_ia32_Immediate(right)) {
2968 if (get_ia32_op_type(node) == ia32_Normal) {
2969 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2970 if (out->index == REG_EAX) {
2974 bemit_modru(out, 7);
2978 bemit_mod_am(7, node);
2980 bemit8(get_ia32_immediate_attr_const(right)->offset);
2983 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2984 if (get_ia32_op_type(node) == ia32_Normal) {
2985 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2986 bemit_modrr(out, in);
2988 bemit_mod_am(reg_gp_map[out->index], node);
2993 static void bemit_test8bit(const ir_node *node)
2995 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2996 if (is_ia32_Immediate(right)) {
2997 if (get_ia32_op_type(node) == ia32_Normal) {
2998 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2999 if (out->index == REG_EAX) {
3003 bemit_modru(out, 0);
3007 bemit_mod_am(0, node);
3009 bemit8(get_ia32_immediate_attr_const(right)->offset);
3012 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3013 if (get_ia32_op_type(node) == ia32_Normal) {
3014 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3015 bemit_modrr(out, in);
3017 bemit_mod_am(reg_gp_map[out->index], node);
3022 static void bemit_imul(const ir_node *node)
3024 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3025 /* Do we need the immediate form? */
3026 if (is_ia32_Immediate(right)) {
3027 int imm = get_ia32_immediate_attr_const(right)->offset;
3028 if (get_signed_imm_size(imm) == 1) {
3029 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3032 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3037 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3041 static void bemit_dec(const ir_node *node)
3043 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3044 bemit8(0x48 + reg_gp_map[out->index]);
3047 static void bemit_inc(const ir_node *node)
3049 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3050 bemit8(0x40 + reg_gp_map[out->index]);
3053 #define UNOPMEM(op, code, ext) \
3054 static void bemit_##op(const ir_node *node) \
3056 bemit_unop_mem(node, code, ext); \
3059 UNOPMEM(notmem, 0xF6, 2)
3060 UNOPMEM(negmem, 0xF6, 3)
3061 UNOPMEM(incmem, 0xFE, 0)
3062 UNOPMEM(decmem, 0xFE, 1)
3064 static void bemit_set(const ir_node *node)
3070 pnc = get_ia32_condcode(node);
3071 pnc = determine_final_pnc(node, n_ia32_Set_eflags, pnc);
3072 if (get_ia32_attr_const(node)->data.ins_permuted)
3073 pnc = ia32_get_negated_pnc(pnc);
3075 bemit8(0x90 + pnc2cc(pnc));
3076 bemit_modru(get_out_reg(node, pn_ia32_Set_res), 2);
3079 static void bemit_ldtls(const ir_node *node)
3081 const arch_register_t *out = get_out_reg(node, 0);
3083 bemit8(0x65); // gs:
3084 if (out->index == REG_EAX) {
3085 bemit8(0xA1); // movl 0, %eax
3087 bemit8(0x8B); // movl 0, %reg
3088 bemit8(MOD_IND | ENC_REG(out->index) | ENC_RM(0x05));
3096 static void bemit_lea(const ir_node *node)
3098 const arch_register_t *out = get_out_reg(node, 0);
3100 bemit_mod_am(reg_gp_map[out->index], node);
3104 * Emit a single opcode.
3106 #define EMIT_SINGLEOP(op, code) \
3107 static void bemit_ ## op(const ir_node *node) { \
3112 //EMIT_SINGLEOP(daa, 0x27)
3113 //EMIT_SINGLEOP(das, 0x2F)
3114 //EMIT_SINGLEOP(aaa, 0x37)
3115 //EMIT_SINGLEOP(aas, 0x3F)
3116 //EMIT_SINGLEOP(nop, 0x90)
3117 EMIT_SINGLEOP(cwtl, 0x98)
3118 EMIT_SINGLEOP(cltd, 0x99)
3119 //EMIT_SINGLEOP(fwait, 0x9B)
3120 EMIT_SINGLEOP(sahf, 0x9E)
3121 //EMIT_SINGLEOP(popf, 0x9D)
3122 EMIT_SINGLEOP(leave, 0xC9)
3123 EMIT_SINGLEOP(int3, 0xCC)
3124 //EMIT_SINGLEOP(iret, 0xCF)
3125 //EMIT_SINGLEOP(xlat, 0xD7)
3126 //EMIT_SINGLEOP(lock, 0xF0)
3127 EMIT_SINGLEOP(rep, 0xF3)
3128 //EMIT_SINGLEOP(halt, 0xF4)
3129 EMIT_SINGLEOP(cmc, 0xF5)
3130 EMIT_SINGLEOP(stc, 0xF9)
3131 //EMIT_SINGLEOP(cli, 0xFA)
3132 //EMIT_SINGLEOP(sti, 0xFB)
3133 //EMIT_SINGLEOP(std, 0xFD)
3136 * Emits a MOV out, [MEM].
3138 static void bemit_load(const ir_node *node)
3140 const arch_register_t *out = get_out_reg(node, 0);
3142 if (out->index == REG_EAX) {
3143 ir_node *base = get_irn_n(node, n_ia32_base);
3144 int has_base = !is_ia32_NoReg_GP(base);
3145 ir_node *index = get_irn_n(node, n_ia32_index);
3146 int has_index = !is_ia32_NoReg_GP(index);
3147 if (!has_base && !has_index) {
3148 ir_entity *ent = get_ia32_am_sc(node);
3149 int offs = get_ia32_am_offs_int(node);
3150 /* load from constant address to EAX can be encoded
3153 bemit_entity(ent, 0, offs, false);
3158 bemit_mod_am(reg_gp_map[out->index], node);
3162 * Emits a MOV [mem], in.
3164 static void bemit_store(const ir_node *node)
3166 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3167 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3169 if (is_ia32_Immediate(value)) {
3172 bemit_mod_am(0, node);
3173 bemit8(get_ia32_immediate_attr_const(value)->offset);
3174 } else if (size == 16) {
3177 bemit_mod_am(0, node);
3178 bemit16(get_ia32_immediate_attr_const(value)->offset);
3181 bemit_mod_am(0, node);
3182 bemit_immediate(value, false);
3185 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3187 if (in->index == REG_EAX) {
3188 ir_node *base = get_irn_n(node, n_ia32_base);
3189 int has_base = !is_ia32_NoReg_GP(base);
3190 ir_node *index = get_irn_n(node, n_ia32_index);
3191 int has_index = !is_ia32_NoReg_GP(index);
3192 if (!has_base && !has_index) {
3193 ir_entity *ent = get_ia32_am_sc(node);
3194 int offs = get_ia32_am_offs_int(node);
3195 /* store to constant address from EAX can be encoded as
3196 * 0xA2/0xA3 [offset]*/
3204 bemit_entity(ent, 0, offs, false);
3216 bemit_mod_am(reg_gp_map[in->index], node);
3220 static void bemit_conv_i2i(const ir_node *node)
3222 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3231 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3232 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3233 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3239 static void bemit_push(const ir_node *node)
3241 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3243 if (is_ia32_Immediate(value)) {
3244 const ia32_immediate_attr_t *attr
3245 = get_ia32_immediate_attr_const(value);
3246 unsigned size = get_signed_imm_size(attr->offset);
3252 bemit8((unsigned char)attr->offset);
3257 bemit_immediate(value, false);
3260 } else if (is_ia32_NoReg_GP(value)) {
3262 bemit_mod_am(6, node);
3264 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3265 bemit8(0x50 + reg_gp_map[reg->index]);
3272 static void bemit_pop(const ir_node *node)
3274 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3275 bemit8(0x58 + reg_gp_map[reg->index]);
3278 static void bemit_popmem(const ir_node *node)
3281 bemit_mod_am(0, node);
3284 static void bemit_call(const ir_node *node)
3286 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3288 if (is_ia32_Immediate(proc)) {
3290 bemit_immediate(proc, true);
3292 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3296 static void bemit_jmp(const ir_node *dest_block)
3299 bemit_jmp_destination(dest_block);
3302 static void bemit_jump(const ir_node *node)
3304 if (can_be_fallthrough(node))
3307 bemit_jmp(get_cfop_target_block(node));
3310 static void bemit_jcc(int pnc, const ir_node *dest_block)
3312 unsigned char cc = pnc2cc(pnc);
3315 bemit_jmp_destination(dest_block);
3318 static void bemit_jp(bool odd, const ir_node *dest_block)
3322 bemit_jmp_destination(dest_block);
3325 static void bemit_ia32_jcc(const ir_node *node)
3327 int pnc = get_ia32_condcode(node);
3328 const ir_node *proj_true;
3329 const ir_node *proj_false;
3330 const ir_node *dest_true;
3331 const ir_node *dest_false;
3332 const ir_node *block;
3334 pnc = determine_final_pnc(node, 0, pnc);
3336 /* get both Projs */
3337 proj_true = get_proj(node, pn_ia32_Jcc_true);
3338 assert(proj_true && "Jcc without true Proj");
3340 proj_false = get_proj(node, pn_ia32_Jcc_false);
3341 assert(proj_false && "Jcc without false Proj");
3343 block = get_nodes_block(node);
3345 if (can_be_fallthrough(proj_true)) {
3346 /* exchange both proj's so the second one can be omitted */
3347 const ir_node *t = proj_true;
3349 proj_true = proj_false;
3351 pnc = ia32_get_negated_pnc(pnc);
3354 dest_true = get_cfop_target_block(proj_true);
3355 dest_false = get_cfop_target_block(proj_false);
3357 if (pnc & ia32_pn_Cmp_float) {
3358 /* Some floating point comparisons require a test of the parity flag,
3359 * which indicates that the result is unordered */
3362 bemit_jp(false, dest_true);
3367 bemit_jp(true, dest_true);
3373 /* we need a local label if the false proj is a fallthrough
3374 * as the falseblock might have no label emitted then */
3375 if (can_be_fallthrough(proj_false)) {
3377 bemit8(0x06); // jp + 6
3379 bemit_jp(false, dest_false);
3386 bemit_jp(false, dest_true);
3394 bemit_jcc(pnc, dest_true);
3397 /* the second Proj might be a fallthrough */
3398 if (can_be_fallthrough(proj_false)) {
3399 /* it's a fallthrough */
3401 bemit_jmp(dest_false);
3408 static void bemit_return(const ir_node *node)
3410 unsigned pop = be_Return_get_pop(node);
3411 if (pop > 0 || be_Return_get_emit_pop(node)) {
3413 assert(pop <= 0xffff);
3420 static void bemit_subsp(const ir_node *node)
3422 const arch_register_t *out;
3425 /* mov %esp, %out */
3427 out = get_out_reg(node, 1);
3428 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3431 static void bemit_incsp(const ir_node *node)
3434 const arch_register_t *reg;
3438 offs = be_get_IncSP_offset(node);
3449 size = get_signed_imm_size(offs);
3450 bemit8(size == 1 ? 0x83 : 0x81);
3452 reg = get_out_reg(node, 0);
3453 bemit_modru(reg, ext);
3462 static void bemit_copybi(const ir_node *node)
3464 unsigned size = get_ia32_copyb_size(node);
3466 bemit8(0xA4); // movsb
3469 bemit8(0xA5); // movsw
3473 bemit8(0xA5); // movsl
3477 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3479 if (get_ia32_op_type(node) == ia32_Normal) {
3480 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3481 const arch_register_t *in1 = x87_attr->x87[0];
3482 const arch_register_t *in = x87_attr->x87[1];
3483 const arch_register_t *out = x87_attr->x87[2];
3487 } else if (out == in) {
3491 if (out->index == 0) {
3493 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3496 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3499 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3504 bemit_mod_am(code, node);
3508 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3510 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3511 const arch_register_t *out = x87_attr->x87[2];
3513 bemit8(code + out->index);
3516 static void bemit_fabs(const ir_node *node)
3524 static void bemit_fadd(const ir_node *node)
3526 bemit_fbinop(node, 0, 0);
3529 static void bemit_faddp(const ir_node *node)
3531 bemit_fbinopp(node, 0xC0);
3534 static void bemit_fchs(const ir_node *node)
3542 static void bemit_fdiv(const ir_node *node)
3544 bemit_fbinop(node, 6, 7);
3547 static void bemit_fdivp(const ir_node *node)
3549 bemit_fbinopp(node, 0xF8);
3552 static void bemit_fdivr(const ir_node *node)
3554 bemit_fbinop(node, 7, 6);
3557 static void bemit_fdivrp(const ir_node *node)
3559 bemit_fbinopp(node, 0xF0);
3562 static void bemit_fild(const ir_node *node)
3564 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3566 bemit8(0xDF); // filds
3567 bemit_mod_am(0, node);
3571 bemit8(0xDB); // fildl
3572 bemit_mod_am(0, node);
3576 bemit8(0xDF); // fildll
3577 bemit_mod_am(5, node);
3581 panic("invalid mode size");
3585 static void bemit_fist(const ir_node *node)
3587 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3589 bemit8(0xDF); // fists
3593 bemit8(0xDB); // fistl
3597 panic("invalid mode size");
3599 bemit_mod_am(2, node);
3602 static void bemit_fistp(const ir_node *node)
3604 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3606 bemit8(0xDF); // fistps
3607 bemit_mod_am(3, node);
3611 bemit8(0xDB); // fistpl
3612 bemit_mod_am(3, node);
3616 bemit8(0xDF); // fistpll
3617 bemit_mod_am(7, node);
3621 panic("invalid mode size");
3625 static void bemit_fld(const ir_node *node)
3627 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3629 bemit8(0xD9); // flds
3630 bemit_mod_am(0, node);
3634 bemit8(0xDD); // fldl
3635 bemit_mod_am(0, node);
3640 bemit8(0xDB); // fldt
3641 bemit_mod_am(5, node);
3645 panic("invalid mode size");
3649 static void bemit_fld1(const ir_node *node)
3653 bemit8(0xE8); // fld1
3656 static void bemit_fldcw(const ir_node *node)
3658 bemit8(0xD9); // fldcw
3659 bemit_mod_am(5, node);
3662 static void bemit_fldz(const ir_node *node)
3666 bemit8(0xEE); // fldz
3669 static void bemit_fmul(const ir_node *node)
3671 bemit_fbinop(node, 1, 1);
3674 static void bemit_fmulp(const ir_node *node)
3676 bemit_fbinopp(node, 0xC8);
3679 static void bemit_fpop(const ir_node *node)
3681 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3683 bemit8(0xD8 + attr->x87[0]->index);
3686 static void bemit_fpush(const ir_node *node)
3688 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3690 bemit8(0xC0 + attr->x87[0]->index);
3693 static void bemit_fpushcopy(const ir_node *node)
3695 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3697 bemit8(0xC0 + attr->x87[0]->index);
3700 static void bemit_fst(const ir_node *node)
3702 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3704 bemit8(0xD9); // fsts
3708 bemit8(0xDD); // fstl
3712 panic("invalid mode size");
3714 bemit_mod_am(2, node);
3717 static void bemit_fstp(const ir_node *node)
3719 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3721 bemit8(0xD9); // fstps
3722 bemit_mod_am(3, node);
3726 bemit8(0xDD); // fstpl
3727 bemit_mod_am(3, node);
3732 bemit8(0xDB); // fstpt
3733 bemit_mod_am(7, node);
3737 panic("invalid mode size");
3741 static void bemit_fsub(const ir_node *node)
3743 bemit_fbinop(node, 4, 5);
3746 static void bemit_fsubp(const ir_node *node)
3748 bemit_fbinopp(node, 0xE8);
3751 static void bemit_fsubr(const ir_node *node)
3753 bemit_fbinop(node, 5, 4);
3756 static void bemit_fsubrp(const ir_node *node)
3758 bemit_fbinopp(node, 0xE0);
3761 static void bemit_fnstcw(const ir_node *node)
3763 bemit8(0xD9); // fnstcw
3764 bemit_mod_am(7, node);
3767 static void bemit_fnstsw(void)
3769 bemit8(0xDF); // fnstsw %ax
3773 static void bemit_ftstfnstsw(const ir_node *node)
3777 bemit8(0xD9); // ftst
3782 static void bemit_fucomi(const ir_node *node)
3784 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3785 bemit8(0xDB); // fucomi
3786 bemit8(0xE8 + attr->x87[1]->index);
3789 static void bemit_fucomip(const ir_node *node)
3791 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3792 bemit8(0xDF); // fucomip
3793 bemit8(0xE8 + attr->x87[1]->index);
3796 static void bemit_fucomfnstsw(const ir_node *node)
3798 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3799 bemit8(0xDD); // fucom
3800 bemit8(0xE0 + attr->x87[1]->index);
3804 static void bemit_fucompfnstsw(const ir_node *node)
3806 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3807 bemit8(0xDD); // fucomp
3808 bemit8(0xE8 + attr->x87[1]->index);
3812 static void bemit_fucomppfnstsw(const ir_node *node)
3816 bemit8(0xDA); // fucompp
3821 static void bemit_fxch(const ir_node *node)
3823 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3825 bemit8(0xC8 + attr->x87[0]->index);
3829 * The type of a emitter function.
3831 typedef void (*emit_func) (const ir_node *);
3834 * Set a node emitter. Make it a bit more type safe.
3836 static void register_emitter(ir_op *op, emit_func func)
3838 op->ops.generic = (op_func) func;
3841 static void ia32_register_binary_emitters(void)
3843 /* first clear the generic function pointer for all ops */
3844 clear_irp_opcodes_generic_func();
3846 /* benode emitter */
3847 register_emitter(op_be_Copy, bemit_copy);
3848 register_emitter(op_be_CopyKeep, bemit_copy);
3849 register_emitter(op_be_IncSP, bemit_incsp);
3850 register_emitter(op_be_Perm, bemit_perm);
3851 register_emitter(op_be_Return, bemit_return);
3852 register_emitter(op_ia32_Adc, bemit_adc);
3853 register_emitter(op_ia32_Add, bemit_add);
3854 register_emitter(op_ia32_AddMem, bemit_addmem);
3855 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3856 register_emitter(op_ia32_And, bemit_and);
3857 register_emitter(op_ia32_AndMem, bemit_andmem);
3858 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3859 register_emitter(op_ia32_Breakpoint, bemit_int3);
3860 register_emitter(op_ia32_CMov, bemit_cmov);
3861 register_emitter(op_ia32_Call, bemit_call);
3862 register_emitter(op_ia32_Cltd, bemit_cltd);
3863 register_emitter(op_ia32_Cmc, bemit_cmc);
3864 register_emitter(op_ia32_Cmp, bemit_cmp);
3865 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3866 register_emitter(op_ia32_Const, bemit_mov_const);
3867 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3868 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3869 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3870 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3871 register_emitter(op_ia32_Dec, bemit_dec);
3872 register_emitter(op_ia32_DecMem, bemit_decmem);
3873 register_emitter(op_ia32_Div, bemit_div);
3874 register_emitter(op_ia32_FldCW, bemit_fldcw);
3875 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3876 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3877 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3878 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3879 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3880 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3881 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3882 register_emitter(op_ia32_IDiv, bemit_idiv);
3883 register_emitter(op_ia32_IJmp, bemit_ijmp);
3884 register_emitter(op_ia32_IMul, bemit_imul);
3885 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3886 register_emitter(op_ia32_Inc, bemit_inc);
3887 register_emitter(op_ia32_IncMem, bemit_incmem);
3888 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3889 register_emitter(op_ia32_Jmp, bemit_jump);
3890 register_emitter(op_ia32_LdTls, bemit_ldtls);
3891 register_emitter(op_ia32_Lea, bemit_lea);
3892 register_emitter(op_ia32_Leave, bemit_leave);
3893 register_emitter(op_ia32_Load, bemit_load);
3894 register_emitter(op_ia32_Mul, bemit_mul);
3895 register_emitter(op_ia32_Neg, bemit_neg);
3896 register_emitter(op_ia32_NegMem, bemit_negmem);
3897 register_emitter(op_ia32_Not, bemit_not);
3898 register_emitter(op_ia32_NotMem, bemit_notmem);
3899 register_emitter(op_ia32_Or, bemit_or);
3900 register_emitter(op_ia32_OrMem, bemit_ormem);
3901 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3902 register_emitter(op_ia32_Pop, bemit_pop);
3903 register_emitter(op_ia32_PopEbp, bemit_pop);
3904 register_emitter(op_ia32_PopMem, bemit_popmem);
3905 register_emitter(op_ia32_Push, bemit_push);
3906 register_emitter(op_ia32_RepPrefix, bemit_rep);
3907 register_emitter(op_ia32_Rol, bemit_rol);
3908 register_emitter(op_ia32_RolMem, bemit_rolmem);
3909 register_emitter(op_ia32_Ror, bemit_ror);
3910 register_emitter(op_ia32_RorMem, bemit_rormem);
3911 register_emitter(op_ia32_Sahf, bemit_sahf);
3912 register_emitter(op_ia32_Sar, bemit_sar);
3913 register_emitter(op_ia32_SarMem, bemit_sarmem);
3914 register_emitter(op_ia32_Sbb, bemit_sbb);
3915 register_emitter(op_ia32_Set, bemit_set);
3916 register_emitter(op_ia32_Shl, bemit_shl);
3917 register_emitter(op_ia32_ShlD, bemit_shld);
3918 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3919 register_emitter(op_ia32_Shr, bemit_shr);
3920 register_emitter(op_ia32_ShrD, bemit_shrd);
3921 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3922 register_emitter(op_ia32_Stc, bemit_stc);
3923 register_emitter(op_ia32_Store, bemit_store);
3924 register_emitter(op_ia32_Store8Bit, bemit_store);
3925 register_emitter(op_ia32_Sub, bemit_sub);
3926 register_emitter(op_ia32_SubMem, bemit_submem);
3927 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3928 register_emitter(op_ia32_SubSP, bemit_subsp);
3929 register_emitter(op_ia32_Test, bemit_test);
3930 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3931 register_emitter(op_ia32_Xor, bemit_xor);
3932 register_emitter(op_ia32_Xor0, bemit_xor0);
3933 register_emitter(op_ia32_XorMem, bemit_xormem);
3934 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3935 register_emitter(op_ia32_fabs, bemit_fabs);
3936 register_emitter(op_ia32_fadd, bemit_fadd);
3937 register_emitter(op_ia32_faddp, bemit_faddp);
3938 register_emitter(op_ia32_fchs, bemit_fchs);
3939 register_emitter(op_ia32_fdiv, bemit_fdiv);
3940 register_emitter(op_ia32_fdivp, bemit_fdivp);
3941 register_emitter(op_ia32_fdivr, bemit_fdivr);
3942 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3943 register_emitter(op_ia32_fild, bemit_fild);
3944 register_emitter(op_ia32_fist, bemit_fist);
3945 register_emitter(op_ia32_fistp, bemit_fistp);
3946 register_emitter(op_ia32_fld, bemit_fld);
3947 register_emitter(op_ia32_fld1, bemit_fld1);
3948 register_emitter(op_ia32_fldz, bemit_fldz);
3949 register_emitter(op_ia32_fmul, bemit_fmul);
3950 register_emitter(op_ia32_fmulp, bemit_fmulp);
3951 register_emitter(op_ia32_fpop, bemit_fpop);
3952 register_emitter(op_ia32_fpush, bemit_fpush);
3953 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3954 register_emitter(op_ia32_fst, bemit_fst);
3955 register_emitter(op_ia32_fstp, bemit_fstp);
3956 register_emitter(op_ia32_fsub, bemit_fsub);
3957 register_emitter(op_ia32_fsubp, bemit_fsubp);
3958 register_emitter(op_ia32_fsubr, bemit_fsubr);
3959 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3960 register_emitter(op_ia32_fxch, bemit_fxch);
3962 /* ignore the following nodes */
3963 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3964 register_emitter(op_be_Barrier, emit_Nothing);
3965 register_emitter(op_be_Keep, emit_Nothing);
3966 register_emitter(op_be_Start, emit_Nothing);
3967 register_emitter(op_Phi, emit_Nothing);
3968 register_emitter(op_Start, emit_Nothing);
3971 static void gen_binary_block(ir_node *block)
3975 ia32_emit_block_header(block);
3977 /* emit the contents of the block */
3978 sched_foreach(block, node) {
3979 ia32_emit_node(node);
3983 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
3985 ir_entity *entity = get_irg_entity(irg);
3991 ia32_register_binary_emitters();
3993 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
3995 /* we use links to point to target blocks */
3996 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3997 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3999 /* initialize next block links */
4000 n = ARR_LEN(cg->blk_sched);
4001 for (i = 0; i < n; ++i) {
4002 ir_node *block = cg->blk_sched[i];
4003 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4005 set_irn_link(block, prev);
4008 for (i = 0; i < n; ++i) {
4009 ir_node *block = cg->blk_sched[i];
4010 gen_binary_block(block);
4013 be_gas_emit_function_epilog(entity);
4014 be_dbg_method_end();
4016 be_emit_write_line();
4018 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4024 void ia32_init_emitter(void)
4026 lc_opt_entry_t *be_grp;
4027 lc_opt_entry_t *ia32_grp;
4029 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4030 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4032 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4036 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");