2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 if(reg == &ia32_gp_regs[REG_GP_NOREG])
90 panic("trying to emit noreg");
92 /* in case of unknown register: just return a valid register */
93 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
94 const arch_register_req_t *req;
96 /* ask for the requirements */
97 req = arch_get_register_req(arch_env, irn, pos);
99 if (arch_register_req_is(req, limited)) {
100 /* in case of limited requirements: get the first allowed register */
101 unsigned idx = rbitset_next(req->limited, 0, 1);
102 reg = arch_register_for_index(req->cls, idx);
104 /* otherwise get first register in class */
105 reg = arch_register_for_index(req->cls, 0);
113 * Returns the register at out position pos.
116 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
119 const arch_env_t *arch_env = env->arch_env;
121 const arch_register_t *reg = NULL;
123 /* 1st case: irn is not of mode_T, so it has only */
124 /* one OUT register -> good */
125 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
126 /* Proj with the corresponding projnum for the register */
128 if (get_irn_mode(irn) != mode_T) {
129 reg = arch_get_irn_register(arch_env, irn);
130 } else if (is_ia32_irn(irn)) {
131 reg = get_ia32_out_reg(irn, pos);
133 const ir_edge_t *edge;
135 foreach_out_edge(irn, edge) {
136 proj = get_edge_src_irn(edge);
137 assert(is_Proj(proj) && "non-Proj from mode_T node");
138 if (get_Proj_proj(proj) == pos) {
139 reg = arch_get_irn_register(arch_env, proj);
145 assert(reg && "no out register found");
150 * Determine the gnu assembler suffix that indicates a mode
153 char get_mode_suffix(const ir_mode *mode) {
154 if(mode_is_float(mode)) {
155 switch(get_mode_size_bits(mode)) {
165 assert(mode_is_int(mode) || mode_is_reference(mode));
166 switch(get_mode_size_bits(mode)) {
177 panic("Can't output mode_suffix for %+F\n", mode);
181 int produces_result(const ir_node *node) {
183 !is_ia32_CmpSet(node) &&
184 !is_ia32_CondJmp(node) &&
186 !is_ia32_SwitchJmp(node) &&
187 !is_ia32_TestJmp(node) &&
188 !is_ia32_xCmpSet(node) &&
189 !is_ia32_xCondJmp(node) &&
190 !is_ia32_CmpCMov(node) &&
191 !is_ia32_TestCMov(node) &&
192 !is_ia32_CmpSet(node) && /* this is correct, the Cmp has no result */
193 !is_ia32_TestSet(node);
197 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
198 const arch_register_t *reg) {
199 switch(get_mode_size_bits(mode)) {
201 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
203 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
205 return (char *)arch_register_get_name(reg);
210 * Add a number to a prefix. This number will not be used a second time.
213 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
214 static unsigned long id = 0;
215 snprintf(buf, buflen, "%s%lu", prefix, ++id);
219 /*************************************************************
221 * (_) | | / _| | | | |
222 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
223 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
224 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
225 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
228 *************************************************************/
230 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
231 // be_emit_env_t* so we cheat a bit...
232 #define be_emit_char(env,c) be_emit_char(env->emit,c)
233 #define be_emit_string(env,s) be_emit_string(env->emit,s)
234 #undef be_emit_cstring
235 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
236 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
237 #define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
238 #define be_emit_write_line(env) be_emit_write_line(env->emit)
239 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
240 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
242 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
244 const arch_register_t *reg = get_in_reg(env, node, pos);
245 const char *reg_name = arch_register_get_name(reg);
247 assert(pos < get_irn_arity(node));
249 be_emit_char(env, '%');
250 be_emit_string(env, reg_name);
253 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
254 const arch_register_t *reg = get_out_reg(env, node, pos);
255 const char *reg_name = arch_register_get_name(reg);
257 be_emit_char(env, '%');
258 be_emit_string(env, reg_name);
261 static void ia32_emit_register(ia32_emit_env_t *env, const arch_register_t *reg)
263 const char *reg_name = arch_register_get_name(reg);
265 be_emit_char(env, '%');
266 be_emit_string(env, reg_name);
269 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
271 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
274 be_emit_char(env, '%');
275 be_emit_string(env, attr->x87[pos]->name);
278 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
284 be_emit_char(env, '$');
286 switch(get_ia32_immop_type(node)) {
288 tv = get_ia32_Immop_tarval(node);
289 be_emit_tarval(env, tv);
291 case ia32_ImmSymConst:
292 ent = get_ia32_Immop_symconst(node);
293 set_entity_backend_marked(ent, 1);
294 id = get_entity_ld_ident(ent);
295 be_emit_ident(env, id);
302 be_emit_string(env, "BAD");
307 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
309 be_emit_char(env, get_mode_suffix(mode));
312 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
314 ir_mode *mode = get_ia32_ls_mode(node);
318 ia32_emit_mode_suffix_mode(env, mode);
321 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
323 ir_mode *mode = get_ia32_ls_mode(node);
325 ia32_emit_mode_suffix_mode(env, mode);
329 char get_xmm_mode_suffix(ir_mode *mode)
331 assert(mode_is_float(mode));
332 switch(get_mode_size_bits(mode)) {
343 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
345 ir_mode *mode = get_ia32_ls_mode(node);
346 assert(mode != NULL);
347 be_emit_char(env, 's');
348 be_emit_char(env, get_xmm_mode_suffix(mode));
351 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
353 ir_mode *mode = get_ia32_ls_mode(node);
354 assert(mode != NULL);
355 be_emit_char(env, get_xmm_mode_suffix(mode));
358 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
360 if(get_mode_size_bits(mode) == 32)
362 if(mode_is_signed(mode)) {
363 be_emit_char(env, 's');
365 be_emit_char(env, 'z');
370 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
372 switch (be_gas_flavour) {
373 case GAS_FLAVOUR_NORMAL:
374 be_emit_cstring(env, "\t.type\t");
375 be_emit_string(env, name);
376 be_emit_cstring(env, ", @function\n");
377 be_emit_write_line(env);
379 case GAS_FLAVOUR_MINGW:
380 be_emit_cstring(env, "\t.def\t");
381 be_emit_string(env, name);
382 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
383 be_emit_write_line(env);
391 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
393 switch (be_gas_flavour) {
394 case GAS_FLAVOUR_NORMAL:
395 be_emit_cstring(env, "\t.size\t");
396 be_emit_string(env, name);
397 be_emit_cstring(env, ", .-");
398 be_emit_string(env, name);
399 be_emit_char(env, '\n');
400 be_emit_write_line(env);
409 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node);
412 * Emits registers and/or address mode of a binary operation.
414 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
416 const ir_node *right_op = get_irn_n(node, 3);
418 switch(get_ia32_op_type(node)) {
420 if(is_ia32_Immediate(right_op)) {
421 emit_ia32_Immediate(env, right_op);
422 be_emit_cstring(env, ", ");
423 ia32_emit_source_register(env, node, 2);
425 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
426 ia32_emit_immediate(env, node);
427 be_emit_cstring(env, ", ");
428 ia32_emit_source_register(env, node, 2);
430 const arch_register_t *in1 = get_in_reg(env, node, 2);
431 const arch_register_t *in2 = get_in_reg(env, node, 3);
432 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
433 const arch_register_t *in;
436 in = out ? ((out == in2) ? in1 : in2) : in2;
437 out = out ? out : in1;
438 in_name = arch_register_get_name(in);
440 if (is_ia32_emit_cl(node)) {
441 assert(in == &ia32_gp_regs[REG_ECX]);
445 be_emit_char(env, '%');
446 be_emit_string(env, in_name);
447 be_emit_cstring(env, ", %");
448 be_emit_string(env, arch_register_get_name(out));
452 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
453 assert(!produces_result(node) &&
454 "Source AM with Const must not produce result");
455 ia32_emit_immediate(env, node);
456 be_emit_cstring(env, ", ");
457 ia32_emit_am(env, node);
458 } else if(is_ia32_Immediate(right_op)) {
459 assert(!produces_result(node) &&
460 "Source AM with Const must not produce result");
462 emit_ia32_Immediate(env, right_op);
463 be_emit_cstring(env, ", ");
464 ia32_emit_am(env, node);
465 } else if (produces_result(node)) {
466 ia32_emit_am(env, node);
467 be_emit_cstring(env, ", ");
468 ia32_emit_dest_register(env, node, 0);
470 ia32_emit_am(env, node);
471 be_emit_cstring(env, ", ");
472 ia32_emit_source_register(env, node, 2);
476 right_pos = get_irn_arity(node) >= 5 ? 3 : 2;
477 right_op = get_irn_n(node, right_pos);
478 if(is_ia32_Immediate(right_op)) {
479 emit_ia32_Immediate(env, right_op);
480 be_emit_cstring(env, ", ");
481 ia32_emit_am(env, node);
483 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
484 ia32_emit_immediate(env, node);
485 be_emit_cstring(env, ", ");
486 ia32_emit_am(env, node);
488 const arch_register_t *in1 = get_in_reg(env, node, right_pos);
489 ir_mode *mode = get_ia32_ls_mode(node);
492 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
494 if (is_ia32_emit_cl(node)) {
495 assert(in1 == &ia32_gp_regs[REG_ECX]);
499 be_emit_char(env, '%');
500 be_emit_string(env, in_name);
501 be_emit_cstring(env, ", ");
502 ia32_emit_am(env, node);
506 assert(0 && "unsupported op type");
511 * Emits registers and/or address mode of a binary operation.
513 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
514 switch(get_ia32_op_type(node)) {
516 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
517 // should not happen...
520 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
521 const arch_register_t *in1 = x87_attr->x87[0];
522 const arch_register_t *in2 = x87_attr->x87[1];
523 const arch_register_t *out = x87_attr->x87[2];
524 const arch_register_t *in;
526 in = out ? ((out == in2) ? in1 : in2) : in2;
527 out = out ? out : in1;
529 be_emit_char(env, '%');
530 be_emit_string(env, arch_register_get_name(in));
531 be_emit_cstring(env, ", %");
532 be_emit_string(env, arch_register_get_name(out));
537 ia32_emit_am(env, node);
540 assert(0 && "unsupported op type");
544 void ia32_emit_am_or_dest_register(ia32_emit_env_t *env, const ir_node *node,
546 if(get_ia32_op_type(node) == ia32_Normal) {
547 ia32_emit_dest_register(env, node, pos);
549 assert(get_ia32_op_type(node) == ia32_AddrModeD);
550 ia32_emit_am(env, node);
555 * Emits registers and/or address mode of a unary operation.
557 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node, int pos) {
560 switch(get_ia32_op_type(node)) {
562 op = get_irn_n(node, pos);
563 if (is_ia32_Immediate(op)) {
564 emit_ia32_Immediate(env, op);
565 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
566 ia32_emit_immediate(env, node);
568 ia32_emit_source_register(env, node, pos);
573 ia32_emit_am(env, node);
576 assert(0 && "unsupported op type");
581 * Emits address mode.
583 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
584 ir_entity *ent = get_ia32_am_sc(node);
585 int offs = get_ia32_am_offs_int(node);
586 ir_node *base = get_irn_n(node, 0);
587 int has_base = !is_ia32_NoReg_GP(base);
588 ir_node *index = get_irn_n(node, 1);
589 int has_index = !is_ia32_NoReg_GP(index);
591 /* just to be sure... */
592 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
598 set_entity_backend_marked(ent, 1);
599 id = get_entity_ld_ident(ent);
600 if (is_ia32_am_sc_sign(node))
601 be_emit_char(env, '-');
602 be_emit_ident(env, id);
604 if(get_entity_owner(ent) == get_tls_type()) {
605 if (get_entity_visibility(ent) == visibility_external_allocated) {
606 be_emit_cstring(env, "@INDNTPOFF");
608 be_emit_cstring(env, "@NTPOFF");
615 be_emit_irprintf(env->emit, "%+d", offs);
617 be_emit_irprintf(env->emit, "%d", offs);
621 if (has_base || has_index) {
622 be_emit_char(env, '(');
626 ia32_emit_source_register(env, node, 0);
629 /* emit index + scale */
632 be_emit_char(env, ',');
633 ia32_emit_source_register(env, node, 1);
635 scale = get_ia32_am_scale(node);
637 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
640 be_emit_char(env, ')');
644 /*************************************************
647 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
648 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
649 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
650 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
652 *************************************************/
655 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
658 * coding of conditions
660 struct cmp2conditon_t {
666 * positive conditions for signed compares
669 const struct cmp2conditon_t cmp2condition_s[] = {
670 { NULL, pn_Cmp_False }, /* always false */
671 { "e", pn_Cmp_Eq }, /* == */
672 { "l", pn_Cmp_Lt }, /* < */
673 { "le", pn_Cmp_Le }, /* <= */
674 { "g", pn_Cmp_Gt }, /* > */
675 { "ge", pn_Cmp_Ge }, /* >= */
676 { "ne", pn_Cmp_Lg }, /* != */
677 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
681 * positive conditions for unsigned compares
684 const struct cmp2conditon_t cmp2condition_u[] = {
685 { NULL, pn_Cmp_False }, /* always false */
686 { "e", pn_Cmp_Eq }, /* == */
687 { "b", pn_Cmp_Lt }, /* < */
688 { "be", pn_Cmp_Le }, /* <= */
689 { "a", pn_Cmp_Gt }, /* > */
690 { "ae", pn_Cmp_Ge }, /* >= */
691 { "ne", pn_Cmp_Lg }, /* != */
692 { NULL, pn_Cmp_True }, /* always true */
696 * returns the condition code
699 const char *get_cmp_suffix(pn_Cmp cmp_code)
701 assert( (cmp2condition_s[cmp_code & 7].num) == (cmp_code & 7));
702 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
704 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
705 return cmp2condition_u[cmp_code & 7].name;
707 return cmp2condition_s[cmp_code & 7].name;
711 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
713 be_emit_string(env, get_cmp_suffix(pnc));
718 * Returns the target block for a control flow node.
721 ir_node *get_cfop_target_block(const ir_node *irn) {
722 return get_irn_link(irn);
726 * Emits a block label for the given block.
729 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
731 be_emit_cstring(env, BLOCK_PREFIX);
732 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
736 * Emits the target label for a control flow node.
739 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
740 ir_node *block = get_cfop_target_block(node);
742 ia32_emit_block_name(env, block);
745 /** Return the next block in Block schedule */
746 static ir_node *next_blk_sched(const ir_node *block) {
747 return get_irn_link(block);
751 * Returns the Proj with projection number proj and NOT mode_M
754 ir_node *get_proj(const ir_node *node, long proj) {
755 const ir_edge_t *edge;
758 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
760 foreach_out_edge(node, edge) {
761 src = get_edge_src_irn(edge);
763 assert(is_Proj(src) && "Proj expected");
764 if (get_irn_mode(src) == mode_M)
767 if (get_Proj_proj(src) == proj)
774 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
777 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
779 const ir_node *proj_true;
780 const ir_node *proj_false;
781 const ir_node *block;
782 const ir_node *next_block;
785 /* get both Proj's */
786 proj_true = get_proj(node, pn_Cond_true);
787 assert(proj_true && "CondJmp without true Proj");
789 proj_false = get_proj(node, pn_Cond_false);
790 assert(proj_false && "CondJmp without false Proj");
792 /* for now, the code works for scheduled and non-schedules blocks */
793 block = get_nodes_block(node);
795 /* we have a block schedule */
796 next_block = next_blk_sched(block);
798 if (get_cfop_target_block(proj_true) == next_block) {
799 /* exchange both proj's so the second one can be omitted */
800 const ir_node *t = proj_true;
802 proj_true = proj_false;
805 pnc = get_negated_pnc(pnc, mode);
808 /* in case of unordered compare, check for parity */
809 if (pnc & pn_Cmp_Uo) {
810 be_emit_cstring(env, "\tjp ");
811 ia32_emit_cfop_target(env, proj_true);
812 be_emit_finish_line_gas(env, proj_true);
815 be_emit_cstring(env, "\tj");
816 // The bits set by floating point compares correspond to unsigned comparisons
817 if (mode_is_float(mode))
818 pnc |= ia32_pn_Cmp_Unsigned;
819 ia32_emit_cmp_suffix(env, pnc);
820 be_emit_char(env, ' ');
821 ia32_emit_cfop_target(env, proj_true);
822 be_emit_finish_line_gas(env, proj_true);
824 /* the second Proj might be a fallthrough */
825 if (get_cfop_target_block(proj_false) != next_block) {
826 be_emit_cstring(env, "\tjmp ");
827 ia32_emit_cfop_target(env, proj_false);
828 be_emit_finish_line_gas(env, proj_false);
830 be_emit_cstring(env, "\t/* fallthrough to ");
831 ia32_emit_cfop_target(env, proj_false);
832 be_emit_cstring(env, " */");
833 be_emit_finish_line_gas(env, proj_false);
838 * Emits code for conditional jump.
841 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
842 be_emit_cstring(env, "\tcmp");
843 ia32_emit_mode_suffix(env, node);
844 be_emit_char(env, ' ');
845 ia32_emit_binop(env, node);
846 be_emit_finish_line_gas(env, node);
848 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
852 * Emits code for conditional jump with two variables.
855 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
856 CondJmp_emitter(env, node);
860 * Emits code for conditional test and jump.
863 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
864 be_emit_cstring(env, "\ttest");
865 ia32_emit_mode_suffix(env, node);
866 be_emit_char(env, ' ');
868 ia32_emit_binop(env, node);
869 be_emit_finish_line_gas(env, node);
871 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
875 * Emits code for conditional test and jump with two variables.
878 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
879 TestJmp_emitter(env, node);
883 * Emits code for conditional SSE floating point jump with two variables.
886 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
887 be_emit_cstring(env, "\tucomi");
888 ia32_emit_xmm_mode_suffix(env, node);
889 be_emit_char(env, ' ');
890 ia32_emit_binop(env, node);
891 be_emit_finish_line_gas(env, node);
893 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
897 * Emits code for conditional x87 floating point jump with two variables.
900 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
901 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
902 const char *reg = x87_attr->x87[1]->name;
903 long pnc = get_ia32_pncode(node);
905 switch (get_ia32_irn_opcode(node)) {
906 case iro_ia32_fcomrJmp:
907 pnc = get_inversed_pnc(pnc);
908 reg = x87_attr->x87[0]->name;
909 case iro_ia32_fcomJmp:
911 be_emit_cstring(env, "\tfucom ");
913 case iro_ia32_fcomrpJmp:
914 pnc = get_inversed_pnc(pnc);
915 reg = x87_attr->x87[0]->name;
916 case iro_ia32_fcompJmp:
917 be_emit_cstring(env, "\tfucomp ");
919 case iro_ia32_fcomrppJmp:
920 pnc = get_inversed_pnc(pnc);
921 case iro_ia32_fcomppJmp:
922 be_emit_cstring(env, "\tfucompp ");
928 be_emit_char(env, '%');
929 be_emit_string(env, reg);
931 be_emit_finish_line_gas(env, node);
933 be_emit_cstring(env, "\tfnstsw %ax");
934 be_emit_finish_line_gas(env, node);
935 be_emit_cstring(env, "\tsahf");
936 be_emit_finish_line_gas(env, node);
938 finish_CondJmp(env, node, mode_E, pnc);
942 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
944 const arch_register_t *in1, *in2, *out;
945 long pnc = get_ia32_pncode(node);
947 out = arch_get_irn_register(env->arch_env, node);
949 /* we have to emit the cmp first, because the destination register */
950 /* could be one of the compare registers */
951 if (is_ia32_xCmpCMov(node)) {
952 be_emit_cstring(env, "\tucomis");
953 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
954 be_emit_char(env, ' ');
955 ia32_emit_source_register(env, node, 1);
956 be_emit_cstring(env, ", ");
957 ia32_emit_source_register(env, node, 0);
959 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 2));
960 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 3));
962 if (is_ia32_CmpCMov(node)) {
963 be_emit_cstring(env, "\tcmp ");
965 assert(is_ia32_TestCMov(node));
966 be_emit_cstring(env, "\ttest ");
968 ia32_emit_binop(env, node);
970 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 5));
971 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 6));
973 be_emit_finish_line_gas(env, node);
976 /* best case: default in == out -> do nothing */
977 } else if(in2 == &ia32_gp_regs[REG_GP_UKNWN]) {
978 /* also nothign to do for unknown regs */
979 } else if (out == in1) {
980 const arch_register_t *t;
981 /* true in == out -> need complement compare and exchange true and
986 pnc = get_negated_pnc(pnc, get_irn_mode(node));
988 /* out is different from both ins: need copy default -> out */
989 be_emit_cstring(env, "\tmovl ");
990 ia32_emit_register(env, in2);
991 be_emit_cstring(env, ", ");
992 ia32_emit_register(env, out);
993 be_emit_finish_line_gas(env, node);
996 be_emit_cstring(env, "\tcmov");
997 ia32_emit_cmp_suffix(env, pnc );
998 be_emit_cstring(env, "l ");
999 ia32_emit_register(env, in1);
1000 be_emit_cstring(env, ", ");
1001 ia32_emit_register(env, out);
1003 be_emit_finish_line_gas(env, node);
1007 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
1009 CMov_emitter(env, node);
1013 void emit_ia32_TestCMov(ia32_emit_env_t *env, const ir_node *node)
1015 CMov_emitter(env, node);
1019 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
1021 CMov_emitter(env, node);
1025 void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
1027 long pnc = get_ia32_pncode(node);
1028 const char *reg8bit;
1029 const arch_register_t *out;
1031 out = arch_get_irn_register(env->arch_env, node);
1032 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1034 if(is_ia32_xCmpSet(node)) {
1035 be_emit_cstring(env, "\tucomis");
1036 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1037 be_emit_char(env, ' ');
1038 ia32_emit_binop(env, node);
1040 if (is_ia32_CmpSet(node)) {
1041 be_emit_cstring(env, "\tcmp ");
1043 assert(is_ia32_TestSet(node));
1044 be_emit_cstring(env, "\ttest ");
1046 ia32_emit_binop(env, node);
1048 be_emit_finish_line_gas(env, node);
1050 /* use mov to clear target because it doesn't affect the eflags */
1051 be_emit_cstring(env, "\tmovl $0, %");
1052 be_emit_string(env, arch_register_get_name(out));
1053 be_emit_finish_line_gas(env, node);
1055 be_emit_cstring(env, "\tset");
1056 ia32_emit_cmp_suffix(env, pnc);
1057 be_emit_cstring(env, " %");
1058 be_emit_string(env, reg8bit);
1059 be_emit_finish_line_gas(env, node);
1063 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1064 Set_emitter(env, node);
1068 void emit_ia32_TestSet(ia32_emit_env_t *env, const ir_node *node) {
1069 Set_emitter(env, node);
1073 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1074 Set_emitter(env, node);
1078 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1080 long pnc = get_ia32_pncode(node);
1081 long unord = pnc & pn_Cmp_Uo;
1083 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1086 case pn_Cmp_Leg: /* odered */
1089 case pn_Cmp_Uo: /* unordered */
1093 case pn_Cmp_Eq: /* == */
1097 case pn_Cmp_Lt: /* < */
1101 case pn_Cmp_Le: /* <= */
1105 case pn_Cmp_Gt: /* > */
1109 case pn_Cmp_Ge: /* >= */
1113 case pn_Cmp_Lg: /* != */
1118 assert(sse_pnc >= 0 && "unsupported compare");
1120 if (unord && sse_pnc != 3) {
1122 We need a separate compare against unordered.
1123 Quick and Dirty solution:
1124 - get some memory on stack
1128 - and result and stored result
1131 be_emit_cstring(env, "\tsubl $8, %esp");
1132 be_emit_finish_line_gas(env, node);
1134 be_emit_cstring(env, "\tcmpsd $3, ");
1135 ia32_emit_binop(env, node);
1136 be_emit_finish_line_gas(env, node);
1138 be_emit_cstring(env, "\tmovsd ");
1139 ia32_emit_dest_register(env, node, 0);
1140 be_emit_cstring(env, ", (%esp)");
1141 be_emit_finish_line_gas(env, node);
1144 be_emit_cstring(env, "\tcmpsd ");
1145 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1146 ia32_emit_binop(env, node);
1147 be_emit_finish_line_gas(env, node);
1149 if (unord && sse_pnc != 3) {
1150 be_emit_cstring(env, "\tandpd (%esp), ");
1151 ia32_emit_dest_register(env, node, 0);
1152 be_emit_finish_line_gas(env, node);
1154 be_emit_cstring(env, "\taddl $8, %esp");
1155 be_emit_finish_line_gas(env, node);
1159 /*********************************************************
1162 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1163 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1164 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1165 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1168 *********************************************************/
1170 /* jump table entry (target and corresponding number) */
1171 typedef struct _branch_t {
1176 /* jump table for switch generation */
1177 typedef struct _jmp_tbl_t {
1178 ir_node *defProj; /**< default target */
1179 long min_value; /**< smallest switch case */
1180 long max_value; /**< largest switch case */
1181 long num_branches; /**< number of jumps */
1182 char *label; /**< label of the jump table */
1183 branch_t *branches; /**< jump array */
1187 * Compare two variables of type branch_t. Used to sort all switch cases
1190 int ia32_cmp_branch_t(const void *a, const void *b) {
1191 branch_t *b1 = (branch_t *)a;
1192 branch_t *b2 = (branch_t *)b;
1194 if (b1->value <= b2->value)
1201 * Emits code for a SwitchJmp (creates a jump table if
1202 * possible otherwise a cmp-jmp cascade). Port from
1206 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1207 unsigned long interval;
1212 const ir_edge_t *edge;
1214 /* fill the table structure */
1215 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1216 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1218 tbl.num_branches = get_irn_n_edges(node);
1219 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1220 tbl.min_value = INT_MAX;
1221 tbl.max_value = INT_MIN;
1224 /* go over all proj's and collect them */
1225 foreach_out_edge(node, edge) {
1226 proj = get_edge_src_irn(edge);
1227 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1229 pnc = get_Proj_proj(proj);
1231 /* create branch entry */
1232 tbl.branches[i].target = proj;
1233 tbl.branches[i].value = pnc;
1235 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1236 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1238 /* check for default proj */
1239 if (pnc == get_ia32_pncode(node)) {
1240 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1247 /* sort the branches by their number */
1248 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1250 /* two-complement's magic make this work without overflow */
1251 interval = tbl.max_value - tbl.min_value;
1253 /* emit the table */
1254 be_emit_cstring(env, "\tcmpl $");
1255 be_emit_irprintf(env->emit, "%u, ", interval);
1256 ia32_emit_source_register(env, node, 0);
1257 be_emit_finish_line_gas(env, node);
1259 be_emit_cstring(env, "\tja ");
1260 ia32_emit_cfop_target(env, tbl.defProj);
1261 be_emit_finish_line_gas(env, node);
1263 if (tbl.num_branches > 1) {
1265 be_emit_cstring(env, "\tjmp *");
1266 be_emit_string(env, tbl.label);
1267 be_emit_cstring(env, "(,");
1268 ia32_emit_source_register(env, node, 0);
1269 be_emit_cstring(env, ",4)");
1270 be_emit_finish_line_gas(env, node);
1272 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1273 be_emit_cstring(env, "\t.align 4\n");
1274 be_emit_write_line(env);
1276 be_emit_string(env, tbl.label);
1277 be_emit_cstring(env, ":\n");
1278 be_emit_write_line(env);
1280 be_emit_cstring(env, ".long ");
1281 ia32_emit_cfop_target(env, tbl.branches[0].target);
1282 be_emit_finish_line_gas(env, NULL);
1284 last_value = tbl.branches[0].value;
1285 for (i = 1; i < tbl.num_branches; ++i) {
1286 while (++last_value < tbl.branches[i].value) {
1287 be_emit_cstring(env, ".long ");
1288 ia32_emit_cfop_target(env, tbl.defProj);
1289 be_emit_finish_line_gas(env, NULL);
1291 be_emit_cstring(env, ".long ");
1292 ia32_emit_cfop_target(env, tbl.branches[i].target);
1293 be_emit_finish_line_gas(env, NULL);
1295 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1297 /* one jump is enough */
1298 be_emit_cstring(env, "\tjmp ");
1299 ia32_emit_cfop_target(env, tbl.branches[0].target);
1300 be_emit_finish_line_gas(env, node);
1310 * Emits code for a unconditional jump.
1313 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1314 ir_node *block, *next_block;
1316 /* for now, the code works for scheduled and non-schedules blocks */
1317 block = get_nodes_block(node);
1319 /* we have a block schedule */
1320 next_block = next_blk_sched(block);
1321 if (get_cfop_target_block(node) != next_block) {
1322 be_emit_cstring(env, "\tjmp ");
1323 ia32_emit_cfop_target(env, node);
1325 be_emit_cstring(env, "\t/* fallthrough to ");
1326 ia32_emit_cfop_target(env, node);
1327 be_emit_cstring(env, " */");
1329 be_emit_finish_line_gas(env, node);
1333 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
1335 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1337 be_emit_char(env, '$');
1338 if(attr->symconst != NULL) {
1339 ident *id = get_entity_ld_ident(attr->symconst);
1341 if(attr->attr.data.am_sc_sign)
1342 be_emit_char(env, '-');
1343 be_emit_ident(env, id);
1345 if(attr->symconst == NULL || attr->offset != 0) {
1346 if(attr->symconst != NULL)
1347 be_emit_char(env, '+');
1348 be_emit_irprintf(env->emit, "%d", attr->offset);
1353 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1356 const arch_register_t *reg;
1357 const char *reg_name;
1361 const ia32_attr_t *attr;
1368 /* parse modifiers */
1371 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1372 be_emit_char(env, '%');
1375 be_emit_char(env, '%');
1395 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1396 "'%c' for asm op\n", node, c);
1402 sscanf(s, "%d%n", &num, &p);
1404 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1412 attr = get_ia32_attr_const(node);
1413 n_outs = ARR_LEN(attr->slots);
1415 reg = get_out_reg(env, node, num);
1418 int in = num - n_outs;
1419 if(in >= get_irn_arity(node)) {
1420 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1421 "op (%+F)\n", num, node);
1424 pred = get_irn_n(node, in);
1425 /* might be an immediate value */
1426 if(is_ia32_Immediate(pred)) {
1427 emit_ia32_Immediate(env, pred);
1430 reg = get_in_reg(env, node, in);
1433 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1434 "(%+F)\n", num, node);
1439 be_emit_char(env, '%');
1442 reg_name = arch_register_get_name(reg);
1445 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1448 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
1451 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1454 panic("Invalid asm op modifier");
1456 be_emit_string(env, reg_name);
1462 * Emits code for an ASM pseudo op.
1465 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1467 const void *gen_attr = get_irn_generic_attr_const(node);
1468 const ia32_asm_attr_t *attr
1469 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1470 ident *asm_text = attr->asm_text;
1471 const char *s = get_id_str(asm_text);
1473 be_emit_cstring(env, "# Begin ASM \t");
1474 be_emit_finish_line_gas(env, node);
1477 be_emit_char(env, '\t');
1481 s = emit_asm_operand(env, node, s);
1484 be_emit_char(env, *s);
1489 be_emit_char(env, '\n');
1490 be_emit_write_line(env);
1492 be_emit_cstring(env, "# End ASM\n");
1493 be_emit_write_line(env);
1496 /**********************************
1499 * | | ___ _ __ _ _| |_) |
1500 * | | / _ \| '_ \| | | | _ <
1501 * | |___| (_) | |_) | |_| | |_) |
1502 * \_____\___/| .__/ \__, |____/
1505 **********************************/
1508 * Emit movsb/w instructions to make mov count divideable by 4
1511 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1512 be_emit_cstring(env, "\tcld");
1513 be_emit_finish_line_gas(env, NULL);
1517 be_emit_cstring(env, "\tmovsb");
1518 be_emit_finish_line_gas(env, NULL);
1521 be_emit_cstring(env, "\tmovsw");
1522 be_emit_finish_line_gas(env, NULL);
1525 be_emit_cstring(env, "\tmovsb");
1526 be_emit_finish_line_gas(env, NULL);
1527 be_emit_cstring(env, "\tmovsw");
1528 be_emit_finish_line_gas(env, NULL);
1534 * Emit rep movsd instruction for memcopy.
1537 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1538 tarval *tv = get_ia32_Immop_tarval(node);
1539 int rem = get_tarval_long(tv);
1541 emit_CopyB_prolog(env, rem);
1543 be_emit_cstring(env, "\trep movsd");
1544 be_emit_finish_line_gas(env, node);
1548 * Emits unrolled memcopy.
1551 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1552 tarval *tv = get_ia32_Immop_tarval(node);
1553 int size = get_tarval_long(tv);
1555 emit_CopyB_prolog(env, size & 0x3);
1559 be_emit_cstring(env, "\tmovsd");
1560 be_emit_finish_line_gas(env, NULL);
1566 /***************************
1570 * | | / _ \| '_ \ \ / /
1571 * | |___| (_) | | | \ V /
1572 * \_____\___/|_| |_|\_/
1574 ***************************/
1577 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1580 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1581 ir_mode *ls_mode = get_ia32_ls_mode(node);
1582 int ls_bits = get_mode_size_bits(ls_mode);
1584 be_emit_cstring(env, "\tcvt");
1586 if(is_ia32_Conv_I2FP(node)) {
1588 be_emit_cstring(env, "si2ss");
1590 be_emit_cstring(env, "si2sd");
1592 } else if(is_ia32_Conv_FP2I(node)) {
1594 be_emit_cstring(env, "ss2si");
1596 be_emit_cstring(env, "sd2si");
1599 assert(is_ia32_Conv_FP2FP(node));
1601 be_emit_cstring(env, "sd2ss");
1603 be_emit_cstring(env, "ss2sd");
1606 be_emit_char(env, ' ');
1608 switch(get_ia32_op_type(node)) {
1610 ia32_emit_source_register(env, node, 2);
1611 be_emit_cstring(env, ", ");
1612 ia32_emit_dest_register(env, node, 0);
1614 case ia32_AddrModeS:
1615 ia32_emit_dest_register(env, node, 0);
1616 be_emit_cstring(env, ", ");
1617 ia32_emit_am(env, node);
1620 assert(0 && "unsupported op type for Conv");
1622 be_emit_finish_line_gas(env, node);
1626 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1627 emit_ia32_Conv_with_FP(env, node);
1631 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1632 emit_ia32_Conv_with_FP(env, node);
1636 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1637 emit_ia32_Conv_with_FP(env, node);
1641 * Emits code for an Int conversion.
1644 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1645 const char *sign_suffix;
1646 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1647 int smaller_bits = get_mode_size_bits(smaller_mode);
1649 const arch_register_t *in_reg, *out_reg;
1651 assert(!mode_is_float(smaller_mode));
1652 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1654 signed_mode = mode_is_signed(smaller_mode);
1655 if(smaller_bits == 32) {
1656 // this should not happen as it's no convert
1660 sign_suffix = signed_mode ? "s" : "z";
1663 switch(get_ia32_op_type(node)) {
1665 in_reg = get_in_reg(env, node, 2);
1666 out_reg = get_out_reg(env, node, 0);
1668 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1669 out_reg == &ia32_gp_regs[REG_EAX] &&
1673 /* argument and result are both in EAX and */
1674 /* signedness is ok: -> use the smaller cwtl opcode */
1675 be_emit_cstring(env, "\tcwtl");
1677 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1679 be_emit_cstring(env, "\tmov");
1680 be_emit_string(env, sign_suffix);
1681 ia32_emit_mode_suffix_mode(env, smaller_mode);
1682 be_emit_cstring(env, "l %");
1683 be_emit_string(env, sreg);
1684 be_emit_cstring(env, ", ");
1685 ia32_emit_dest_register(env, node, 0);
1688 case ia32_AddrModeS: {
1689 be_emit_cstring(env, "\tmov");
1690 be_emit_string(env, sign_suffix);
1691 ia32_emit_mode_suffix_mode(env, smaller_mode);
1692 be_emit_cstring(env, "l %");
1693 ia32_emit_am(env, node);
1694 be_emit_cstring(env, ", ");
1695 ia32_emit_dest_register(env, node, 0);
1699 assert(0 && "unsupported op type for Conv");
1701 be_emit_finish_line_gas(env, node);
1705 * Emits code for an 8Bit Int conversion.
1707 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1708 emit_ia32_Conv_I2I(env, node);
1712 /*******************************************
1715 * | |__ ___ _ __ ___ __| | ___ ___
1716 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1717 * | |_) | __/ | | | (_) | (_| | __/\__ \
1718 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1720 *******************************************/
1723 * Emits a backend call
1726 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1727 ir_entity *ent = be_Call_get_entity(node);
1729 be_emit_cstring(env, "\tcall ");
1731 set_entity_backend_marked(ent, 1);
1732 be_emit_string(env, get_entity_ld_name(ent));
1734 be_emit_char(env, '*');
1735 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1737 be_emit_finish_line_gas(env, node);
1741 * Emits code to increase stack pointer.
1744 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1745 int offs = be_get_IncSP_offset(node);
1751 be_emit_cstring(env, "\tsubl $");
1752 be_emit_irprintf(env->emit, "%u, ", offs);
1753 ia32_emit_source_register(env, node, 0);
1755 be_emit_cstring(env, "\taddl $");
1756 be_emit_irprintf(env->emit, "%u, ", -offs);
1757 ia32_emit_source_register(env, node, 0);
1759 be_emit_finish_line_gas(env, node);
1763 * Emits code to set stack pointer.
1766 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1767 be_emit_cstring(env, "\tmovl ");
1768 ia32_emit_source_register(env, node, 2);
1769 be_emit_cstring(env, ", ");
1770 ia32_emit_dest_register(env, node, 0);
1771 be_emit_finish_line_gas(env, node);
1775 * Emits code for Copy/CopyKeep.
1778 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1780 const arch_env_t *arch_env = env->arch_env;
1781 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1782 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1788 if(is_unknown_reg(in))
1790 /* copies of vf nodes aren't real... */
1791 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1794 mode = get_irn_mode(node);
1795 if (mode == mode_E) {
1796 be_emit_cstring(env, "\tmovsd ");
1797 ia32_emit_register(env, in);
1798 be_emit_cstring(env, ", ");
1799 ia32_emit_register(env, out);
1801 be_emit_cstring(env, "\tmovl ");
1802 ia32_emit_register(env, in);
1803 be_emit_cstring(env, ", ");
1804 ia32_emit_register(env, out);
1806 be_emit_finish_line_gas(env, node);
1810 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1811 Copy_emitter(env, node, be_get_Copy_op(node));
1815 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1816 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1820 * Emits code for exchange.
1823 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1824 const arch_register_t *in1, *in2;
1825 const arch_register_class_t *cls1, *cls2;
1827 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1828 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1830 cls1 = arch_register_get_class(in1);
1831 cls2 = arch_register_get_class(in2);
1833 assert(cls1 == cls2 && "Register class mismatch at Perm");
1835 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1836 be_emit_cstring(env, "\txchg ");
1837 ia32_emit_source_register(env, node, 1);
1838 be_emit_cstring(env, ", ");
1839 ia32_emit_source_register(env, node, 0);
1840 be_emit_finish_line_gas(env, node);
1841 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1842 be_emit_cstring(env, "\txorpd ");
1843 ia32_emit_source_register(env, node, 1);
1844 be_emit_cstring(env, ", ");
1845 ia32_emit_source_register(env, node, 0);
1846 be_emit_finish_line_gas(env, NULL);
1848 be_emit_cstring(env, "\txorpd ");
1849 ia32_emit_source_register(env, node, 0);
1850 be_emit_cstring(env, ", ");
1851 ia32_emit_source_register(env, node, 1);
1852 be_emit_finish_line_gas(env, NULL);
1854 be_emit_cstring(env, "\txorpd ");
1855 ia32_emit_source_register(env, node, 1);
1856 be_emit_cstring(env, ", ");
1857 ia32_emit_source_register(env, node, 0);
1858 be_emit_finish_line_gas(env, node);
1859 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1861 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1867 * Emits code for Constant loading.
1870 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1871 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1873 if (imm_tp == ia32_ImmSymConst) {
1874 be_emit_cstring(env, "\tmovl ");
1875 ia32_emit_immediate(env, node);
1876 be_emit_cstring(env, ", ");
1877 ia32_emit_dest_register(env, node, 0);
1879 tarval *tv = get_ia32_Immop_tarval(node);
1880 assert(get_irn_mode(node) == mode_Iu);
1881 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1882 if (tarval_is_null(tv)) {
1883 if (env->isa->opt_arch == arch_pentium_4) {
1884 /* P4 prefers sub r, r, others xor r, r */
1885 be_emit_cstring(env, "\tsubl ");
1887 be_emit_cstring(env, "\txorl ");
1889 ia32_emit_dest_register(env, node, 0);
1890 be_emit_cstring(env, ", ");
1891 ia32_emit_dest_register(env, node, 0);
1893 be_emit_cstring(env, "\tmovl ");
1894 ia32_emit_immediate(env, node);
1895 be_emit_cstring(env, ", ");
1896 ia32_emit_dest_register(env, node, 0);
1899 be_emit_finish_line_gas(env, node);
1903 * Emits code to load the TLS base
1906 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1907 be_emit_cstring(env, "\tmovl %gs:0, ");
1908 ia32_emit_dest_register(env, node, 0);
1909 be_emit_finish_line_gas(env, node);
1913 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
1915 be_emit_cstring(env, "\tret");
1916 be_emit_finish_line_gas(env, node);
1920 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
1927 /***********************************************************************************
1930 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1931 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1932 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1933 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1935 ***********************************************************************************/
1938 * Enters the emitter functions for handled nodes into the generic
1939 * pointer of an opcode.
1942 void ia32_register_emitters(void) {
1944 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1945 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1946 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1947 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1948 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1949 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1951 /* first clear the generic function pointer for all ops */
1952 clear_irp_opcodes_generic_func();
1954 /* register all emitter functions defined in spec */
1955 ia32_register_spec_emitters();
1957 /* other ia32 emitter functions */
1962 IA32_EMIT(TestCMov);
1965 IA32_EMIT(SwitchJmp);
1968 IA32_EMIT(Conv_I2FP);
1969 IA32_EMIT(Conv_FP2I);
1970 IA32_EMIT(Conv_FP2FP);
1971 IA32_EMIT(Conv_I2I);
1972 IA32_EMIT(Conv_I2I8Bit);
1977 IA32_EMIT(xCmpCMov);
1978 IA32_EMIT(xCondJmp);
1979 IA32_EMIT2(fcomJmp, x87CondJmp);
1980 IA32_EMIT2(fcompJmp, x87CondJmp);
1981 IA32_EMIT2(fcomppJmp, x87CondJmp);
1982 IA32_EMIT2(fcomrJmp, x87CondJmp);
1983 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1984 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1986 /* benode emitter */
2012 static const char *last_name = NULL;
2013 static unsigned last_line = -1;
2014 static unsigned num = -1;
2017 * Emit the debug support for node node.
2020 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
2021 dbg_info *db = get_irn_dbg_info(node);
2023 const char *fname = be_retrieve_dbg_info(db, &lineno);
2025 if (! env->cg->birg->main_env->options->stabs_debug_support)
2029 if (last_name != fname) {
2031 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2034 if (last_line != lineno) {
2037 snprintf(name, sizeof(name), ".LM%u", ++num);
2039 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2040 be_emit_string(env, name);
2041 be_emit_cstring(env, ":\n");
2042 be_emit_write_line(env);
2047 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2050 * Emits code for a node.
2053 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2054 ir_op *op = get_irn_op(node);
2056 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2058 if (op->ops.generic) {
2059 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2060 ia32_emit_dbg(env, node);
2061 (*func) (env, node);
2063 emit_Nothing(env, node);
2064 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
2070 * Emits gas alignment directives
2073 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2074 be_emit_cstring(env, "\t.p2align ");
2075 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2076 be_emit_write_line(env);
2080 * Emits gas alignment directives for Functions depended on cpu architecture.
2083 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2085 unsigned maximum_skip;
2100 maximum_skip = (1 << align) - 1;
2101 ia32_emit_alignment(env, align, maximum_skip);
2105 * Emits gas alignment directives for Labels depended on cpu architecture.
2108 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2109 unsigned align; unsigned maximum_skip;
2124 maximum_skip = (1 << align) - 1;
2125 ia32_emit_alignment(env, align, maximum_skip);
2129 * Test wether a block should be aligned.
2130 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2131 * 16 bytes. However we should only do that if the alignment nops before the
2132 * label aren't executed more often than we have jumps to the label.
2135 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2136 static const double DELTA = .0001;
2137 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2139 double prev_freq = 0; /**< execfreq of the fallthrough block */
2140 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2141 cpu_support cpu = env->isa->opt_arch;
2144 if(exec_freq == NULL)
2146 if(cpu == arch_i386 || cpu == arch_i486)
2149 block_freq = get_block_execfreq(exec_freq, block);
2150 if(block_freq < DELTA)
2153 n_cfgpreds = get_Block_n_cfgpreds(block);
2154 for(i = 0; i < n_cfgpreds; ++i) {
2155 ir_node *pred = get_Block_cfgpred_block(block, i);
2156 double pred_freq = get_block_execfreq(exec_freq, pred);
2159 prev_freq += pred_freq;
2161 jmp_freq += pred_freq;
2165 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2168 jmp_freq /= prev_freq;
2172 case arch_athlon_64:
2174 return jmp_freq > 3;
2176 return jmp_freq > 2;
2181 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2186 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2189 n_cfgpreds = get_Block_n_cfgpreds(block);
2190 if (n_cfgpreds == 0) {
2192 } else if (n_cfgpreds == 1) {
2193 ir_node *pred = get_Block_cfgpred(block, 0);
2194 ir_node *pred_block = get_nodes_block(pred);
2196 /* we don't need labels for fallthrough blocks, however switch-jmps
2197 * are no fallthroughs */
2198 if(pred_block == prev &&
2199 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2208 if (should_align_block(env, block, prev)) {
2210 ia32_emit_align_label(env, env->isa->opt_arch);
2214 ia32_emit_block_name(env, block);
2215 be_emit_char(env, ':');
2217 be_emit_pad_comment(env);
2218 be_emit_cstring(env, " /* preds:");
2220 /* emit list of pred blocks in comment */
2221 arity = get_irn_arity(block);
2222 for (i = 0; i < arity; ++i) {
2223 ir_node *predblock = get_Block_cfgpred_block(block, i);
2224 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2227 be_emit_cstring(env, "\t/* ");
2228 ia32_emit_block_name(env, block);
2229 be_emit_cstring(env, ": ");
2231 if (exec_freq != NULL) {
2232 be_emit_irprintf(env->emit, " freq: %f",
2233 get_block_execfreq(exec_freq, block));
2235 be_emit_cstring(env, " */\n");
2236 be_emit_write_line(env);
2240 * Walks over the nodes in a block connected by scheduling edges
2241 * and emits code for each node.
2244 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2246 const ir_node *node;
2248 ia32_emit_block_header(env, block, last_block);
2250 /* emit the contents of the block */
2251 ia32_emit_dbg(env, block);
2252 sched_foreach(block, node) {
2253 ia32_emit_node(env, node);
2258 * Emits code for function start.
2261 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2262 ir_entity *irg_ent = get_irg_entity(irg);
2263 const char *irg_name = get_entity_ld_name(irg_ent);
2264 cpu_support cpu = env->isa->opt_arch;
2265 const be_irg_t *birg = env->cg->birg;
2267 be_emit_write_line(env);
2268 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2269 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2270 ia32_emit_align_func(env, cpu);
2271 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2272 be_emit_cstring(env, ".global ");
2273 be_emit_string(env, irg_name);
2274 be_emit_char(env, '\n');
2275 be_emit_write_line(env);
2277 ia32_emit_function_object(env, irg_name);
2278 be_emit_string(env, irg_name);
2279 be_emit_cstring(env, ":\n");
2280 be_emit_write_line(env);
2284 * Emits code for function end
2287 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2288 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2289 const be_irg_t *birg = env->cg->birg;
2291 ia32_emit_function_size(env, irg_name);
2292 be_dbg_method_end(birg->main_env->db_handle);
2293 be_emit_char(env, '\n');
2294 be_emit_write_line(env);
2299 * Sets labels for control flow nodes (jump target)
2302 void ia32_gen_labels(ir_node *block, void *data)
2305 int n = get_Block_n_cfgpreds(block);
2308 for (n--; n >= 0; n--) {
2309 pred = get_Block_cfgpred(block, n);
2310 set_irn_link(pred, block);
2315 * Emit an exception label if the current instruction can fail.
2317 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2318 if (get_ia32_exc_label(node)) {
2319 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2320 be_emit_write_line(env);
2325 * Main driver. Emits the code for one routine.
2327 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2328 ia32_emit_env_t env;
2330 ir_node *last_block = NULL;
2333 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2334 env.emit = &env.isa->emit;
2335 env.arch_env = cg->arch_env;
2338 ia32_register_emitters();
2340 ia32_emit_func_prolog(&env, irg);
2341 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2343 n = ARR_LEN(cg->blk_sched);
2344 for (i = 0; i < n;) {
2347 block = cg->blk_sched[i];
2349 next_bl = i < n ? cg->blk_sched[i] : NULL;
2351 /* set here the link. the emitter expects to find the next block here */
2352 set_irn_link(block, next_bl);
2353 ia32_gen_block(&env, block, last_block);
2357 ia32_emit_func_epilog(&env, irg);
2360 void ia32_init_emitter(void)
2362 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");