2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
76 static ir_label_t exc_label_id;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 static bool is_fallthrough(const ir_node *cfgpred)
90 pred = get_Proj_pred(cfgpred);
91 if(is_ia32_SwitchJmp(pred))
97 static bool block_needs_label(const ir_node *block)
99 bool need_label = true;
100 int n_cfgpreds = get_Block_n_cfgpreds(block);
102 if (n_cfgpreds == 0) {
104 } else if (n_cfgpreds == 1) {
105 ir_node *cfgpred = get_Block_cfgpred(block, 0);
106 ir_node *cfgpred_block = get_nodes_block(cfgpred);
108 if (get_prev_block_sched(block) == cfgpred_block
109 && is_fallthrough(cfgpred)) {
118 * Returns the register at in position pos.
120 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
123 const arch_register_t *reg = NULL;
125 assert(get_irn_arity(irn) > pos && "Invalid IN position");
127 /* The out register of the operator at position pos is the
128 in register we need. */
129 op = get_irn_n(irn, pos);
131 reg = arch_get_irn_register(arch_env, op);
133 assert(reg && "no in register found");
135 if(reg == &ia32_gp_regs[REG_GP_NOREG])
136 panic("trying to emit noreg for %+F input %d", irn, pos);
138 /* in case of unknown register: just return a valid register */
139 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
140 const arch_register_req_t *req;
142 /* ask for the requirements */
143 req = arch_get_register_req(arch_env, irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(arch_env, irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = get_ia32_out_reg(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(arch_env, proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
214 static void emit_8bit_register(const arch_register_t *reg)
216 const char *reg_name = arch_register_get_name(reg);
219 be_emit_char(reg_name[1]);
223 static void emit_16bit_register(const arch_register_t *reg)
225 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
228 be_emit_string(reg_name);
231 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
233 const char *reg_name;
236 int size = get_mode_size_bits(mode);
238 emit_8bit_register(reg);
240 } else if(size == 16) {
241 emit_16bit_register(reg);
244 assert(mode_is_float(mode) || size == 32);
248 reg_name = arch_register_get_name(reg);
251 be_emit_string(reg_name);
254 void ia32_emit_source_register(const ir_node *node, int pos)
256 const arch_register_t *reg = get_in_reg(node, pos);
258 emit_register(reg, NULL);
261 static void emit_ia32_Immediate(const ir_node *node);
263 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
265 const arch_register_t *reg;
266 ir_node *in = get_irn_n(node, pos);
267 if(is_ia32_Immediate(in)) {
268 emit_ia32_Immediate(in);
272 reg = get_in_reg(node, pos);
273 emit_8bit_register(reg);
276 void ia32_emit_dest_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_out_reg(node, pos);
280 emit_register(reg, NULL);
283 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
285 const arch_register_t *reg = get_out_reg(node, pos);
287 emit_register(reg, mode_Bu);
290 void ia32_emit_x87_register(const ir_node *node, int pos)
292 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
296 be_emit_string(attr->x87[pos]->name);
299 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
301 if(mode_is_float(mode)) {
302 switch(get_mode_size_bits(mode)) {
303 case 32: be_emit_char('s'); return;
304 case 64: be_emit_char('l'); return;
306 case 96: be_emit_char('t'); return;
309 assert(mode_is_int(mode) || mode_is_reference(mode));
310 switch(get_mode_size_bits(mode)) {
311 case 64: be_emit_cstring("ll"); return;
312 /* gas docu says q is the suffix but gcc, objdump and icc use
314 case 32: be_emit_char('l'); return;
315 case 16: be_emit_char('w'); return;
316 case 8: be_emit_char('b'); return;
319 panic("Can't output mode_suffix for %+F\n", mode);
322 void ia32_emit_mode_suffix(const ir_node *node)
324 ir_mode *mode = get_ia32_ls_mode(node);
328 ia32_emit_mode_suffix_mode(mode);
331 void ia32_emit_x87_mode_suffix(const ir_node *node)
333 /* we only need to emit the mode on address mode */
334 if(get_ia32_op_type(node) != ia32_Normal) {
335 ir_mode *mode = get_ia32_ls_mode(node);
336 assert(mode != NULL);
337 ia32_emit_mode_suffix_mode(mode);
341 static char get_xmm_mode_suffix(ir_mode *mode)
343 assert(mode_is_float(mode));
344 switch(get_mode_size_bits(mode)) {
355 void ia32_emit_xmm_mode_suffix(const ir_node *node)
357 ir_mode *mode = get_ia32_ls_mode(node);
358 assert(mode != NULL);
360 be_emit_char(get_xmm_mode_suffix(mode));
363 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
365 ir_mode *mode = get_ia32_ls_mode(node);
366 assert(mode != NULL);
367 be_emit_char(get_xmm_mode_suffix(mode));
370 void ia32_emit_extend_suffix(const ir_mode *mode)
372 if(get_mode_size_bits(mode) == 32)
374 if(mode_is_signed(mode)) {
381 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
383 ir_node *in = get_irn_n(node, pos);
384 if(is_ia32_Immediate(in)) {
385 emit_ia32_Immediate(in);
387 const ir_mode *mode = get_ia32_ls_mode(node);
388 const arch_register_t *reg = get_in_reg(node, pos);
389 emit_register(reg, mode);
394 * Emits registers and/or address mode of a binary operation.
396 void ia32_emit_binop(const ir_node *node) {
397 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
398 const ir_mode *mode = get_ia32_ls_mode(node);
399 const arch_register_t *reg_left;
401 switch(get_ia32_op_type(node)) {
403 reg_left = get_in_reg(node, n_ia32_binary_left);
404 if(is_ia32_Immediate(right_op)) {
405 emit_ia32_Immediate(right_op);
406 be_emit_cstring(", ");
407 emit_register(reg_left, mode);
410 const arch_register_t *reg_right
411 = get_in_reg(node, n_ia32_binary_right);
412 emit_register(reg_right, mode);
413 be_emit_cstring(", ");
414 emit_register(reg_left, mode);
418 if(is_ia32_Immediate(right_op)) {
419 emit_ia32_Immediate(right_op);
420 be_emit_cstring(", ");
423 reg_left = get_in_reg(node, n_ia32_binary_left);
425 be_emit_cstring(", ");
426 emit_register(reg_left, mode);
430 panic("DestMode can't be output by %%binop anymore");
433 assert(0 && "unsupported op type");
438 * Emits registers and/or address mode of a binary operation.
440 void ia32_emit_x87_binop(const ir_node *node) {
441 switch(get_ia32_op_type(node)) {
444 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
445 const arch_register_t *in1 = x87_attr->x87[0];
446 const arch_register_t *in2 = x87_attr->x87[1];
447 const arch_register_t *out = x87_attr->x87[2];
448 const arch_register_t *in;
450 in = out ? ((out == in2) ? in1 : in2) : in2;
451 out = out ? out : in1;
454 be_emit_string(arch_register_get_name(in));
455 be_emit_cstring(", %");
456 be_emit_string(arch_register_get_name(out));
464 assert(0 && "unsupported op type");
469 * Emits registers and/or address mode of a unary operation.
471 void ia32_emit_unop(const ir_node *node, int pos) {
474 switch(get_ia32_op_type(node)) {
476 op = get_irn_n(node, pos);
477 if (is_ia32_Immediate(op)) {
478 emit_ia32_Immediate(op);
480 ia32_emit_source_register(node, pos);
488 assert(0 && "unsupported op type");
492 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
496 set_entity_backend_marked(entity, 1);
497 id = get_entity_ld_ident(entity);
500 if (get_entity_owner(entity) == get_tls_type()) {
501 if (get_entity_visibility(entity) == visibility_external_allocated) {
502 be_emit_cstring("@INDNTPOFF");
504 be_emit_cstring("@NTPOFF");
508 if (!no_pic_adjust && do_pic) {
509 /* TODO: only do this when necessary */
511 be_emit_string(pic_base_label);
516 * Emits address mode.
518 void ia32_emit_am(const ir_node *node) {
519 ir_entity *ent = get_ia32_am_sc(node);
520 int offs = get_ia32_am_offs_int(node);
521 ir_node *base = get_irn_n(node, 0);
522 int has_base = !is_ia32_NoReg_GP(base);
523 ir_node *index = get_irn_n(node, 1);
524 int has_index = !is_ia32_NoReg_GP(index);
526 /* just to be sure... */
527 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
531 if (is_ia32_am_sc_sign(node))
533 ia32_emit_entity(ent, 0);
538 be_emit_irprintf("%+d", offs);
540 be_emit_irprintf("%d", offs);
544 if (has_base || has_index) {
549 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
550 emit_register(reg, NULL);
553 /* emit index + scale */
555 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
558 emit_register(reg, NULL);
560 scale = get_ia32_am_scale(node);
562 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
568 /* special case if nothing is set */
569 if(ent == NULL && offs == 0 && !has_base && !has_index) {
574 static void emit_ia32_IMul(const ir_node *node)
576 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
577 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
579 be_emit_cstring("\timul");
580 ia32_emit_mode_suffix(node);
583 ia32_emit_binop(node);
585 /* do we need the 3-address form? */
586 if(is_ia32_NoReg_GP(left) ||
587 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
588 be_emit_cstring(", ");
589 emit_register(out_reg, get_ia32_ls_mode(node));
591 be_emit_finish_line_gas(node);
594 /*************************************************
597 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
598 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
599 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
600 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
602 *************************************************/
605 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
608 * coding of conditions
610 struct cmp2conditon_t {
616 * positive conditions for signed compares
618 static const struct cmp2conditon_t cmp2condition_s[] = {
619 { NULL, pn_Cmp_False }, /* always false */
620 { "e", pn_Cmp_Eq }, /* == */
621 { "l", pn_Cmp_Lt }, /* < */
622 { "le", pn_Cmp_Le }, /* <= */
623 { "g", pn_Cmp_Gt }, /* > */
624 { "ge", pn_Cmp_Ge }, /* >= */
625 { "ne", pn_Cmp_Lg }, /* != */
626 { NULL, pn_Cmp_Leg}, /* always true */
630 * positive conditions for unsigned compares
632 static const struct cmp2conditon_t cmp2condition_u[] = {
633 { NULL, pn_Cmp_False }, /* always false */
634 { "e", pn_Cmp_Eq }, /* == */
635 { "b", pn_Cmp_Lt }, /* < */
636 { "be", pn_Cmp_Le }, /* <= */
637 { "a", pn_Cmp_Gt }, /* > */
638 { "ae", pn_Cmp_Ge }, /* >= */
639 { "ne", pn_Cmp_Lg }, /* != */
640 { NULL, pn_Cmp_Leg }, /* always true */
644 * walks up a tree of copies/perms/spills/reloads to find the original value
645 * that is moved around
647 static ir_node *find_original_value(ir_node *node)
649 inc_irg_visited(current_ir_graph);
651 mark_irn_visited(node);
652 if(be_is_Copy(node)) {
653 node = be_get_Copy_op(node);
654 } else if(be_is_CopyKeep(node)) {
655 node = be_get_CopyKeep_op(node);
656 } else if(is_Proj(node)) {
657 ir_node *pred = get_Proj_pred(node);
658 if(be_is_Perm(pred)) {
659 node = get_irn_n(pred, get_Proj_proj(node));
660 } else if(be_is_MemPerm(pred)) {
661 node = get_irn_n(pred, get_Proj_proj(node) + 1);
662 } else if(is_ia32_Load(pred)) {
663 node = get_irn_n(pred, n_ia32_Load_mem);
667 } else if(is_ia32_Store(node)) {
668 node = get_irn_n(node, n_ia32_Store_val);
669 } else if(is_Phi(node)) {
671 arity = get_irn_arity(node);
672 for(i = 0; i < arity; ++i) {
673 ir_node *in = get_irn_n(node, i);
686 static int determine_final_pnc(const ir_node *node, int flags_pos,
689 ir_node *flags = get_irn_n(node, flags_pos);
690 const ia32_attr_t *flags_attr;
691 flags = skip_Proj(flags);
693 if(is_ia32_Sahf(flags)) {
694 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
695 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
696 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
697 cmp = find_original_value(cmp);
698 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
699 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
702 flags_attr = get_ia32_attr_const(cmp);
703 if(flags_attr->data.ins_permuted)
704 pnc = get_mirrored_pnc(pnc);
705 pnc |= ia32_pn_Cmp_float;
706 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
707 || is_ia32_Fucompi(flags)) {
708 flags_attr = get_ia32_attr_const(flags);
710 if(flags_attr->data.ins_permuted)
711 pnc = get_mirrored_pnc(pnc);
712 pnc |= ia32_pn_Cmp_float;
715 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
716 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
718 flags_attr = get_ia32_attr_const(flags);
720 if(flags_attr->data.ins_permuted)
721 pnc = get_mirrored_pnc(pnc);
722 if(flags_attr->data.cmp_unsigned)
723 pnc |= ia32_pn_Cmp_unsigned;
729 static void ia32_emit_cmp_suffix(int pnc)
733 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
735 assert(cmp2condition_u[pnc].num == pnc);
736 str = cmp2condition_u[pnc].name;
739 assert(cmp2condition_s[pnc].num == pnc);
740 str = cmp2condition_s[pnc].name;
746 void ia32_emit_cmp_suffix_node(const ir_node *node,
749 const ia32_attr_t *attr = get_ia32_attr_const(node);
751 pn_Cmp pnc = get_ia32_condcode(node);
753 pnc = determine_final_pnc(node, flags_pos, pnc);
754 if(attr->data.ins_permuted) {
755 if(pnc & ia32_pn_Cmp_float) {
756 pnc = get_negated_pnc(pnc, mode_F);
758 pnc = get_negated_pnc(pnc, mode_Iu);
762 ia32_emit_cmp_suffix(pnc);
766 * Returns the target block for a control flow node.
768 static ir_node *get_cfop_target_block(const ir_node *irn) {
769 assert(get_irn_mode(irn) == mode_X);
770 return get_irn_link(irn);
774 * Emits a block label for the given block.
776 static void ia32_emit_block_name(const ir_node *block)
778 if (has_Block_label(block)) {
779 be_emit_string(be_gas_block_label_prefix());
780 be_emit_irprintf("%lu", get_Block_label(block));
782 be_emit_cstring(BLOCK_PREFIX);
783 be_emit_irprintf("%ld", get_irn_node_nr(block));
788 * Emits an exception label for a given node.
790 static void ia32_emit_exc_label(const ir_node *node)
792 be_emit_string(be_gas_insn_label_prefix());
793 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
797 * Emits the target label for a control flow node.
799 static void ia32_emit_cfop_target(const ir_node *node)
801 ir_node *block = get_cfop_target_block(node);
803 ia32_emit_block_name(block);
807 * Returns the Proj with projection number proj and NOT mode_M
809 static ir_node *get_proj(const ir_node *node, long proj) {
810 const ir_edge_t *edge;
813 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
815 foreach_out_edge(node, edge) {
816 src = get_edge_src_irn(edge);
818 assert(is_Proj(src) && "Proj expected");
819 if (get_irn_mode(src) == mode_M)
822 if (get_Proj_proj(src) == proj)
828 static bool can_be_fallthrough(const ir_node *node)
830 ir_node *target_block = get_cfop_target_block(node);
831 ir_node *block = get_nodes_block(node);
832 return get_prev_block_sched(target_block) == block;
836 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
838 static void emit_ia32_Jcc(const ir_node *node)
840 int need_parity_label = 0;
841 const ir_node *proj_true;
842 const ir_node *proj_false;
843 const ir_node *block;
844 const ir_node *next_block;
845 pn_Cmp pnc = get_ia32_condcode(node);
847 pnc = determine_final_pnc(node, 0, pnc);
850 proj_true = get_proj(node, pn_ia32_Jcc_true);
851 assert(proj_true && "Jcc without true Proj");
853 proj_false = get_proj(node, pn_ia32_Jcc_false);
854 assert(proj_false && "Jcc without false Proj");
856 block = get_nodes_block(node);
858 if (can_be_fallthrough(proj_true)) {
859 /* exchange both proj's so the second one can be omitted */
860 const ir_node *t = proj_true;
862 proj_true = proj_false;
864 if(pnc & ia32_pn_Cmp_float) {
865 pnc = get_negated_pnc(pnc, mode_F);
867 pnc = get_negated_pnc(pnc, mode_Iu);
871 if (pnc & ia32_pn_Cmp_float) {
872 /* Some floating point comparisons require a test of the parity flag,
873 * which indicates that the result is unordered */
876 be_emit_cstring("\tjp ");
877 ia32_emit_cfop_target(proj_true);
878 be_emit_finish_line_gas(proj_true);
883 be_emit_cstring("\tjnp ");
884 ia32_emit_cfop_target(proj_true);
885 be_emit_finish_line_gas(proj_true);
891 /* we need a local label if the false proj is a fallthrough
892 * as the falseblock might have no label emitted then */
893 if (get_cfop_target_block(proj_false) == next_block) {
894 need_parity_label = 1;
895 be_emit_cstring("\tjp 1f");
897 be_emit_cstring("\tjp ");
898 ia32_emit_cfop_target(proj_false);
900 be_emit_finish_line_gas(proj_false);
906 be_emit_cstring("\tjp ");
907 ia32_emit_cfop_target(proj_true);
908 be_emit_finish_line_gas(proj_true);
916 be_emit_cstring("\tj");
917 ia32_emit_cmp_suffix(pnc);
919 ia32_emit_cfop_target(proj_true);
920 be_emit_finish_line_gas(proj_true);
923 if(need_parity_label) {
924 be_emit_cstring("1:");
925 be_emit_write_line();
928 /* the second Proj might be a fallthrough */
929 if (get_cfop_target_block(proj_false) != next_block) {
930 be_emit_cstring("\tjmp ");
931 ia32_emit_cfop_target(proj_false);
932 be_emit_finish_line_gas(proj_false);
934 be_emit_cstring("\t/* fallthrough to ");
935 ia32_emit_cfop_target(proj_false);
936 be_emit_cstring(" */");
937 be_emit_finish_line_gas(proj_false);
941 static void emit_ia32_CMov(const ir_node *node)
943 const ia32_attr_t *attr = get_ia32_attr_const(node);
944 int ins_permuted = attr->data.ins_permuted;
945 const arch_register_t *out = arch_get_irn_register(arch_env, node);
946 pn_Cmp pnc = get_ia32_condcode(node);
947 const arch_register_t *in_true;
948 const arch_register_t *in_false;
950 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
952 in_true = arch_get_irn_register(arch_env,
953 get_irn_n(node, n_ia32_CMov_val_true));
954 in_false = arch_get_irn_register(arch_env,
955 get_irn_n(node, n_ia32_CMov_val_false));
957 /* should be same constraint fullfilled? */
958 if(out == in_false) {
959 /* yes -> nothing to do */
960 } else if(out == in_true) {
961 const arch_register_t *tmp;
963 assert(get_ia32_op_type(node) == ia32_Normal);
965 ins_permuted = !ins_permuted;
972 be_emit_cstring("\tmovl ");
973 emit_register(in_false, NULL);
974 be_emit_cstring(", ");
975 emit_register(out, NULL);
976 be_emit_finish_line_gas(node);
980 if(pnc & ia32_pn_Cmp_float) {
981 pnc = get_negated_pnc(pnc, mode_F);
983 pnc = get_negated_pnc(pnc, mode_Iu);
987 /* TODO: handling of Nans isn't correct yet */
989 be_emit_cstring("\tcmov");
990 ia32_emit_cmp_suffix(pnc);
992 if(get_ia32_op_type(node) == ia32_AddrModeS) {
995 emit_register(in_true, get_ia32_ls_mode(node));
997 be_emit_cstring(", ");
998 emit_register(out, get_ia32_ls_mode(node));
999 be_emit_finish_line_gas(node);
1002 /*********************************************************
1005 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1006 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1007 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1008 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1011 *********************************************************/
1013 /* jump table entry (target and corresponding number) */
1014 typedef struct _branch_t {
1019 /* jump table for switch generation */
1020 typedef struct _jmp_tbl_t {
1021 ir_node *defProj; /**< default target */
1022 long min_value; /**< smallest switch case */
1023 long max_value; /**< largest switch case */
1024 long num_branches; /**< number of jumps */
1025 char *label; /**< label of the jump table */
1026 branch_t *branches; /**< jump array */
1030 * Compare two variables of type branch_t. Used to sort all switch cases
1032 static int ia32_cmp_branch_t(const void *a, const void *b) {
1033 branch_t *b1 = (branch_t *)a;
1034 branch_t *b2 = (branch_t *)b;
1036 if (b1->value <= b2->value)
1043 * Emits code for a SwitchJmp (creates a jump table if
1044 * possible otherwise a cmp-jmp cascade). Port from
1047 static void emit_ia32_SwitchJmp(const ir_node *node)
1049 unsigned long interval;
1055 const ir_edge_t *edge;
1057 /* fill the table structure */
1058 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1059 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1061 tbl.num_branches = get_irn_n_edges(node) - 1;
1062 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1063 tbl.min_value = INT_MAX;
1064 tbl.max_value = INT_MIN;
1066 default_pn = get_ia32_condcode(node);
1068 /* go over all proj's and collect them */
1069 foreach_out_edge(node, edge) {
1070 proj = get_edge_src_irn(edge);
1071 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1073 pnc = get_Proj_proj(proj);
1075 /* check for default proj */
1076 if (pnc == default_pn) {
1077 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1080 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1081 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1083 /* create branch entry */
1084 tbl.branches[i].target = proj;
1085 tbl.branches[i].value = pnc;
1090 assert(i == tbl.num_branches);
1092 /* sort the branches by their number */
1093 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1095 /* two-complement's magic make this work without overflow */
1096 interval = tbl.max_value - tbl.min_value;
1098 /* emit the table */
1099 be_emit_cstring("\tcmpl $");
1100 be_emit_irprintf("%u, ", interval);
1101 ia32_emit_source_register(node, 0);
1102 be_emit_finish_line_gas(node);
1104 be_emit_cstring("\tja ");
1105 ia32_emit_cfop_target(tbl.defProj);
1106 be_emit_finish_line_gas(node);
1108 if (tbl.num_branches > 1) {
1110 be_emit_cstring("\tjmp *");
1111 be_emit_string(tbl.label);
1112 be_emit_cstring("(,");
1113 ia32_emit_source_register(node, 0);
1114 be_emit_cstring(",4)");
1115 be_emit_finish_line_gas(node);
1117 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1118 be_emit_cstring("\t.align 4\n");
1119 be_emit_write_line();
1121 be_emit_string(tbl.label);
1122 be_emit_cstring(":\n");
1123 be_emit_write_line();
1125 be_emit_cstring(".long ");
1126 ia32_emit_cfop_target(tbl.branches[0].target);
1127 be_emit_finish_line_gas(NULL);
1129 last_value = tbl.branches[0].value;
1130 for (i = 1; i < tbl.num_branches; ++i) {
1131 while (++last_value < tbl.branches[i].value) {
1132 be_emit_cstring(".long ");
1133 ia32_emit_cfop_target(tbl.defProj);
1134 be_emit_finish_line_gas(NULL);
1136 be_emit_cstring(".long ");
1137 ia32_emit_cfop_target(tbl.branches[i].target);
1138 be_emit_finish_line_gas(NULL);
1140 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1142 /* one jump is enough */
1143 be_emit_cstring("\tjmp ");
1144 ia32_emit_cfop_target(tbl.branches[0].target);
1145 be_emit_finish_line_gas(node);
1155 * Emits code for a unconditional jump.
1157 static void emit_Jmp(const ir_node *node)
1161 /* for now, the code works for scheduled and non-schedules blocks */
1162 block = get_nodes_block(node);
1164 /* we have a block schedule */
1165 if (can_be_fallthrough(node)) {
1166 be_emit_cstring("\t/* fallthrough to ");
1167 ia32_emit_cfop_target(node);
1168 be_emit_cstring(" */");
1170 be_emit_cstring("\tjmp ");
1171 ia32_emit_cfop_target(node);
1173 be_emit_finish_line_gas(node);
1176 static void emit_ia32_Immediate(const ir_node *node)
1178 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1181 if(attr->symconst != NULL) {
1184 ia32_emit_entity(attr->symconst, 0);
1186 if(attr->symconst == NULL || attr->offset != 0) {
1187 if(attr->symconst != NULL) {
1188 be_emit_irprintf("%+d", attr->offset);
1190 be_emit_irprintf("0x%X", attr->offset);
1196 * Emit an inline assembler operand.
1198 * @param node the ia32_ASM node
1199 * @param s points to the operand (a %c)
1201 * @return pointer to the first char in s NOT in the current operand
1203 static const char* emit_asm_operand(const ir_node *node, const char *s)
1205 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1206 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1208 const arch_register_t *reg;
1209 const ia32_asm_reg_t *asm_regs = attr->register_map;
1210 const ia32_asm_reg_t *asm_reg;
1211 const char *reg_name;
1220 /* parse modifiers */
1223 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1247 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1248 "'%c' for asm op\n", node, c);
1254 sscanf(s, "%d%n", &num, &p);
1256 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1263 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1264 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1265 "input/output (%+F)\n", node);
1268 asm_reg = & asm_regs[num];
1269 assert(asm_reg->valid);
1272 if(asm_reg->use_input == 0) {
1273 reg = get_out_reg(node, asm_reg->inout_pos);
1275 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1277 /* might be an immediate value */
1278 if(is_ia32_Immediate(pred)) {
1279 emit_ia32_Immediate(pred);
1282 reg = get_in_reg(node, asm_reg->inout_pos);
1285 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1286 "(%+F)\n", num, node);
1290 if(asm_reg->memory) {
1299 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1302 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1305 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1308 panic("Invalid asm op modifier");
1310 be_emit_string(reg_name);
1312 emit_register(reg, asm_reg->mode);
1315 if(asm_reg->memory) {
1323 * Emits code for an ASM pseudo op.
1325 static void emit_ia32_Asm(const ir_node *node)
1327 const void *gen_attr = get_irn_generic_attr_const(node);
1328 const ia32_asm_attr_t *attr
1329 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1330 ident *asm_text = attr->asm_text;
1331 const char *s = get_id_str(asm_text);
1333 be_emit_cstring("# Begin ASM \t");
1334 be_emit_finish_line_gas(node);
1341 s = emit_asm_operand(node, s);
1350 be_emit_write_line();
1352 be_emit_cstring("# End ASM\n");
1353 be_emit_write_line();
1356 /**********************************
1359 * | | ___ _ __ _ _| |_) |
1360 * | | / _ \| '_ \| | | | _ <
1361 * | |___| (_) | |_) | |_| | |_) |
1362 * \_____\___/| .__/ \__, |____/
1365 **********************************/
1368 * Emit movsb/w instructions to make mov count divideable by 4
1370 static void emit_CopyB_prolog(unsigned size) {
1371 be_emit_cstring("\tcld");
1372 be_emit_finish_line_gas(NULL);
1376 be_emit_cstring("\tmovsb");
1377 be_emit_finish_line_gas(NULL);
1380 be_emit_cstring("\tmovsw");
1381 be_emit_finish_line_gas(NULL);
1384 be_emit_cstring("\tmovsb");
1385 be_emit_finish_line_gas(NULL);
1386 be_emit_cstring("\tmovsw");
1387 be_emit_finish_line_gas(NULL);
1393 * Emit rep movsd instruction for memcopy.
1395 static void emit_ia32_CopyB(const ir_node *node)
1397 unsigned size = get_ia32_copyb_size(node);
1399 emit_CopyB_prolog(size);
1401 be_emit_cstring("\trep movsd");
1402 be_emit_finish_line_gas(node);
1406 * Emits unrolled memcopy.
1408 static void emit_ia32_CopyB_i(const ir_node *node)
1410 unsigned size = get_ia32_copyb_size(node);
1412 emit_CopyB_prolog(size & 0x3);
1416 be_emit_cstring("\tmovsd");
1417 be_emit_finish_line_gas(NULL);
1423 /***************************
1427 * | | / _ \| '_ \ \ / /
1428 * | |___| (_) | | | \ V /
1429 * \_____\___/|_| |_|\_/
1431 ***************************/
1434 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1436 static void emit_ia32_Conv_with_FP(const ir_node *node)
1438 ir_mode *ls_mode = get_ia32_ls_mode(node);
1439 int ls_bits = get_mode_size_bits(ls_mode);
1441 be_emit_cstring("\tcvt");
1443 if(is_ia32_Conv_I2FP(node)) {
1445 be_emit_cstring("si2ss");
1447 be_emit_cstring("si2sd");
1449 } else if(is_ia32_Conv_FP2I(node)) {
1451 be_emit_cstring("ss2si");
1453 be_emit_cstring("sd2si");
1456 assert(is_ia32_Conv_FP2FP(node));
1458 be_emit_cstring("sd2ss");
1460 be_emit_cstring("ss2sd");
1465 switch(get_ia32_op_type(node)) {
1467 ia32_emit_source_register(node, n_ia32_unary_op);
1469 case ia32_AddrModeS:
1473 assert(0 && "unsupported op type for Conv");
1475 be_emit_cstring(", ");
1476 ia32_emit_dest_register(node, 0);
1477 be_emit_finish_line_gas(node);
1480 static void emit_ia32_Conv_I2FP(const ir_node *node)
1482 emit_ia32_Conv_with_FP(node);
1485 static void emit_ia32_Conv_FP2I(const ir_node *node)
1487 emit_ia32_Conv_with_FP(node);
1490 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1492 emit_ia32_Conv_with_FP(node);
1496 * Emits code for an Int conversion.
1498 static void emit_ia32_Conv_I2I(const ir_node *node)
1500 const char *sign_suffix;
1501 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1502 int smaller_bits = get_mode_size_bits(smaller_mode);
1504 const arch_register_t *in_reg, *out_reg;
1506 assert(!mode_is_float(smaller_mode));
1507 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1509 signed_mode = mode_is_signed(smaller_mode);
1510 if(smaller_bits == 32) {
1511 // this should not happen as it's no convert
1515 sign_suffix = signed_mode ? "s" : "z";
1518 out_reg = get_out_reg(node, 0);
1520 switch(get_ia32_op_type(node)) {
1522 in_reg = get_in_reg(node, n_ia32_unary_op);
1524 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1525 out_reg == &ia32_gp_regs[REG_EAX] &&
1529 /* argument and result are both in EAX and */
1530 /* signedness is ok: -> use the smaller cwtl opcode */
1531 be_emit_cstring("\tcwtl");
1533 be_emit_cstring("\tmov");
1534 be_emit_string(sign_suffix);
1535 ia32_emit_mode_suffix_mode(smaller_mode);
1536 be_emit_cstring("l ");
1537 emit_register(in_reg, smaller_mode);
1538 be_emit_cstring(", ");
1539 emit_register(out_reg, NULL);
1542 case ia32_AddrModeS: {
1543 be_emit_cstring("\tmov");
1544 be_emit_string(sign_suffix);
1545 ia32_emit_mode_suffix_mode(smaller_mode);
1546 be_emit_cstring("l ");
1548 be_emit_cstring(", ");
1549 emit_register(out_reg, NULL);
1553 assert(0 && "unsupported op type for Conv");
1555 be_emit_finish_line_gas(node);
1559 /*******************************************
1562 * | |__ ___ _ __ ___ __| | ___ ___
1563 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1564 * | |_) | __/ | | | (_) | (_| | __/\__ \
1565 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1567 *******************************************/
1570 * Emits a backend call
1572 static void emit_be_Call(const ir_node *node)
1574 ir_entity *ent = be_Call_get_entity(node);
1576 be_emit_cstring("\tcall ");
1578 ia32_emit_entity(ent, 1);
1580 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1582 emit_register(reg, NULL);
1584 be_emit_finish_line_gas(node);
1588 * Emits code to increase stack pointer.
1590 static void emit_be_IncSP(const ir_node *node)
1592 int offs = be_get_IncSP_offset(node);
1593 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1599 be_emit_cstring("\tsubl $");
1600 be_emit_irprintf("%u, ", offs);
1601 emit_register(reg, NULL);
1603 be_emit_cstring("\taddl $");
1604 be_emit_irprintf("%u, ", -offs);
1605 emit_register(reg, NULL);
1607 be_emit_finish_line_gas(node);
1611 * Emits code for Copy/CopyKeep.
1613 static void Copy_emitter(const ir_node *node, const ir_node *op)
1615 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1616 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1622 if(is_unknown_reg(in))
1624 /* copies of vf nodes aren't real... */
1625 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1628 mode = get_irn_mode(node);
1629 if (mode == mode_E) {
1630 be_emit_cstring("\tmovsd ");
1631 emit_register(in, NULL);
1632 be_emit_cstring(", ");
1633 emit_register(out, NULL);
1635 be_emit_cstring("\tmovl ");
1636 emit_register(in, NULL);
1637 be_emit_cstring(", ");
1638 emit_register(out, NULL);
1640 be_emit_finish_line_gas(node);
1643 static void emit_be_Copy(const ir_node *node)
1645 Copy_emitter(node, be_get_Copy_op(node));
1648 static void emit_be_CopyKeep(const ir_node *node)
1650 Copy_emitter(node, be_get_CopyKeep_op(node));
1654 * Emits code for exchange.
1656 static void emit_be_Perm(const ir_node *node)
1658 const arch_register_t *in0, *in1;
1659 const arch_register_class_t *cls0, *cls1;
1661 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1662 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1664 cls0 = arch_register_get_class(in0);
1665 cls1 = arch_register_get_class(in1);
1667 assert(cls0 == cls1 && "Register class mismatch at Perm");
1669 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1670 be_emit_cstring("\txchg ");
1671 emit_register(in1, NULL);
1672 be_emit_cstring(", ");
1673 emit_register(in0, NULL);
1674 be_emit_finish_line_gas(node);
1675 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1676 be_emit_cstring("\txorpd ");
1677 emit_register(in1, NULL);
1678 be_emit_cstring(", ");
1679 emit_register(in0, NULL);
1680 be_emit_finish_line_gas(NULL);
1682 be_emit_cstring("\txorpd ");
1683 emit_register(in0, NULL);
1684 be_emit_cstring(", ");
1685 emit_register(in1, NULL);
1686 be_emit_finish_line_gas(NULL);
1688 be_emit_cstring("\txorpd ");
1689 emit_register(in1, NULL);
1690 be_emit_cstring(", ");
1691 emit_register(in0, NULL);
1692 be_emit_finish_line_gas(node);
1693 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1695 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1698 panic("unexpected register class in be_Perm (%+F)\n", node);
1703 * Emits code for Constant loading.
1705 static void emit_ia32_Const(const ir_node *node)
1707 be_emit_cstring("\tmovl ");
1708 emit_ia32_Immediate(node);
1709 be_emit_cstring(", ");
1710 ia32_emit_dest_register(node, 0);
1712 be_emit_finish_line_gas(node);
1716 * Emits code to load the TLS base
1718 static void emit_ia32_LdTls(const ir_node *node)
1720 be_emit_cstring("\tmovl %gs:0, ");
1721 ia32_emit_dest_register(node, 0);
1722 be_emit_finish_line_gas(node);
1725 /* helper function for emit_ia32_Minus64Bit */
1726 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1728 be_emit_cstring("\tmovl ");
1729 emit_register(src, NULL);
1730 be_emit_cstring(", ");
1731 emit_register(dst, NULL);
1732 be_emit_finish_line_gas(node);
1735 /* helper function for emit_ia32_Minus64Bit */
1736 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1738 be_emit_cstring("\tnegl ");
1739 emit_register(reg, NULL);
1740 be_emit_finish_line_gas(node);
1743 /* helper function for emit_ia32_Minus64Bit */
1744 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1746 be_emit_cstring("\tsbbl $0, ");
1747 emit_register(reg, NULL);
1748 be_emit_finish_line_gas(node);
1751 /* helper function for emit_ia32_Minus64Bit */
1752 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1754 be_emit_cstring("\tsbbl ");
1755 emit_register(src, NULL);
1756 be_emit_cstring(", ");
1757 emit_register(dst, NULL);
1758 be_emit_finish_line_gas(node);
1761 /* helper function for emit_ia32_Minus64Bit */
1762 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1764 be_emit_cstring("\txchgl ");
1765 emit_register(src, NULL);
1766 be_emit_cstring(", ");
1767 emit_register(dst, NULL);
1768 be_emit_finish_line_gas(node);
1771 /* helper function for emit_ia32_Minus64Bit */
1772 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1774 be_emit_cstring("\txorl ");
1775 emit_register(reg, NULL);
1776 be_emit_cstring(", ");
1777 emit_register(reg, NULL);
1778 be_emit_finish_line_gas(node);
1781 static void emit_ia32_Minus64Bit(const ir_node *node)
1783 const arch_register_t *in_lo = get_in_reg(node, 0);
1784 const arch_register_t *in_hi = get_in_reg(node, 1);
1785 const arch_register_t *out_lo = get_out_reg(node, 0);
1786 const arch_register_t *out_hi = get_out_reg(node, 1);
1788 if (out_lo == in_lo) {
1789 if (out_hi != in_hi) {
1790 /* a -> a, b -> d */
1793 /* a -> a, b -> b */
1796 } else if (out_lo == in_hi) {
1797 if (out_hi == in_lo) {
1798 /* a -> b, b -> a */
1799 emit_xchg(node, in_lo, in_hi);
1802 /* a -> b, b -> d */
1803 emit_mov(node, in_hi, out_hi);
1804 emit_mov(node, in_lo, out_lo);
1808 if (out_hi == in_lo) {
1809 /* a -> c, b -> a */
1810 emit_mov(node, in_lo, out_lo);
1812 } else if (out_hi == in_hi) {
1813 /* a -> c, b -> b */
1814 emit_mov(node, in_lo, out_lo);
1817 /* a -> c, b -> d */
1818 emit_mov(node, in_lo, out_lo);
1824 emit_neg( node, out_hi);
1825 emit_neg( node, out_lo);
1826 emit_sbb0(node, out_hi);
1830 emit_zero(node, out_hi);
1831 emit_neg( node, out_lo);
1832 emit_sbb( node, in_hi, out_hi);
1835 static void emit_ia32_GetEIP(const ir_node *node)
1837 be_emit_cstring("\tcall ");
1838 be_emit_string(pic_base_label);
1839 be_emit_finish_line_gas(node);
1841 be_emit_string(pic_base_label);
1842 be_emit_cstring(":\n");
1843 be_emit_write_line();
1845 be_emit_cstring("\tpopl ");
1846 ia32_emit_dest_register(node, 0);
1848 be_emit_write_line();
1851 static void emit_be_Return(const ir_node *node)
1854 be_emit_cstring("\tret");
1856 pop = be_Return_get_pop(node);
1858 be_emit_irprintf(" $%d", pop);
1859 } else if (be_Return_get_emit_pop(node)) {
1860 ir_node *block = get_nodes_block(node);
1861 if (block_needs_label(block)) {
1862 be_emit_cstring(" $0");
1865 be_emit_finish_line_gas(node);
1868 static void emit_Nothing(const ir_node *node)
1874 /***********************************************************************************
1877 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1878 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1879 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1880 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1882 ***********************************************************************************/
1885 * Enters the emitter functions for handled nodes into the generic
1886 * pointer of an opcode.
1888 static void ia32_register_emitters(void) {
1890 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1891 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1892 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1893 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1894 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1895 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1897 /* first clear the generic function pointer for all ops */
1898 clear_irp_opcodes_generic_func();
1900 /* register all emitter functions defined in spec */
1901 ia32_register_spec_emitters();
1903 /* other ia32 emitter functions */
1907 IA32_EMIT(SwitchJmp);
1910 IA32_EMIT(Conv_I2FP);
1911 IA32_EMIT(Conv_FP2I);
1912 IA32_EMIT(Conv_FP2FP);
1913 IA32_EMIT(Conv_I2I);
1914 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1917 IA32_EMIT(Minus64Bit);
1921 /* benode emitter */
1946 typedef void (*emit_func_ptr) (const ir_node *);
1949 * Emits code for a node.
1951 static void ia32_emit_node(ir_node *node)
1953 ir_op *op = get_irn_op(node);
1955 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1957 if (is_ia32_irn(node) && get_ia32_exc_label(node)) {
1958 /* emit the exception label of this instruction */
1959 ia32_assign_exc_label(node);
1961 if (op->ops.generic) {
1962 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1964 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1969 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1975 * Emits gas alignment directives
1977 static void ia32_emit_alignment(unsigned align, unsigned skip)
1979 be_emit_cstring("\t.p2align ");
1980 be_emit_irprintf("%u,,%u\n", align, skip);
1981 be_emit_write_line();
1985 * Emits gas alignment directives for Labels depended on cpu architecture.
1987 static void ia32_emit_align_label(void)
1989 unsigned align = ia32_cg_config.label_alignment;
1990 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1991 ia32_emit_alignment(align, maximum_skip);
1995 * Test whether a block should be aligned.
1996 * For cpus in the P4/Athlon class it is useful to align jump labels to
1997 * 16 bytes. However we should only do that if the alignment nops before the
1998 * label aren't executed more often than we have jumps to the label.
2000 static int should_align_block(const ir_node *block)
2002 static const double DELTA = .0001;
2003 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2004 ir_node *prev = get_prev_block_sched(block);
2006 double prev_freq = 0; /**< execfreq of the fallthrough block */
2007 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2010 if(exec_freq == NULL)
2012 if(ia32_cg_config.label_alignment_factor <= 0)
2015 block_freq = get_block_execfreq(exec_freq, block);
2016 if(block_freq < DELTA)
2019 n_cfgpreds = get_Block_n_cfgpreds(block);
2020 for(i = 0; i < n_cfgpreds; ++i) {
2021 ir_node *pred = get_Block_cfgpred_block(block, i);
2022 double pred_freq = get_block_execfreq(exec_freq, pred);
2025 prev_freq += pred_freq;
2027 jmp_freq += pred_freq;
2031 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2034 jmp_freq /= prev_freq;
2036 return jmp_freq > ia32_cg_config.label_alignment_factor;
2040 * Emit the block header for a block.
2042 * @param block the block
2043 * @param prev_block the previous block
2045 static void ia32_emit_block_header(ir_node *block)
2047 ir_graph *irg = current_ir_graph;
2049 bool need_label = block_needs_label(block);
2051 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2053 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2056 if (ia32_cg_config.label_alignment > 0) {
2057 /* align the current block if:
2058 * a) if should be aligned due to its execution frequency
2059 * b) there is no fall-through here
2061 if (should_align_block(block)) {
2062 ia32_emit_align_label();
2064 /* if the predecessor block has no fall-through,
2065 we can always align the label. */
2067 bool has_fallthrough = false;;
2069 for (i = n_cfgpreds - 1; i >= 0; --i) {
2070 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2071 if (can_be_fallthrough(cfg_pred)) {
2072 has_fallthrough = true;
2077 if (!has_fallthrough)
2078 ia32_emit_align_label();
2082 if (need_label || has_Block_label(block)) {
2083 ia32_emit_block_name(block);
2086 be_emit_pad_comment();
2087 be_emit_cstring(" /* ");
2089 be_emit_cstring("\t/* ");
2090 ia32_emit_block_name(block);
2091 be_emit_cstring(": ");
2094 be_emit_cstring("preds:");
2096 /* emit list of pred blocks in comment */
2097 arity = get_irn_arity(block);
2098 for (i = 0; i < arity; ++i) {
2099 ir_node *predblock = get_Block_cfgpred_block(block, i);
2100 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2102 if (exec_freq != NULL) {
2103 be_emit_irprintf(" freq: %f",
2104 get_block_execfreq(exec_freq, block));
2106 be_emit_cstring(" */\n");
2107 be_emit_write_line();
2111 * Walks over the nodes in a block connected by scheduling edges
2112 * and emits code for each node.
2114 static void ia32_gen_block(ir_node *block)
2118 ia32_emit_block_header(block);
2120 /* emit the contents of the block */
2121 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2122 sched_foreach(block, node) {
2123 ia32_emit_node(node);
2127 typedef struct exc_entry {
2128 ir_node *exc_instr; /** The instruction that can issue an exception. */
2129 ir_node *block; /** The block to call then. */
2134 * Sets labels for control flow nodes (jump target).
2135 * Links control predecessors to there destination blocks.
2137 static void ia32_gen_labels(ir_node *block, void *data)
2139 exc_entry **exc_list = data;
2143 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2144 pred = get_Block_cfgpred(block, n);
2145 set_irn_link(pred, block);
2147 pred = skip_Proj(pred);
2148 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2153 ARR_APP1(exc_entry, *exc_list, e);
2154 set_irn_link(pred, block);
2160 * Assign and emit an exception label if the current instruction can fail.
2162 void ia32_assign_exc_label(ir_node *node)
2164 if (get_ia32_exc_label(node)) {
2165 /* assign a new ID to the instruction */
2166 set_ia32_exc_label_id(node, ++exc_label_id);
2168 ia32_emit_exc_label(node);
2170 be_emit_pad_comment();
2171 be_emit_cstring("/* exception to Block ");
2172 ia32_emit_cfop_target(node);
2173 be_emit_cstring(" */\n");
2174 be_emit_write_line();
2179 * Compare two exception_entries.
2181 static int cmp_exc_entry(const void *a, const void *b) {
2182 const exc_entry *ea = a;
2183 const exc_entry *eb = b;
2185 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2191 * Main driver. Emits the code for one routine.
2193 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2195 ir_entity *entity = get_irg_entity(irg);
2196 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2200 isa = (const ia32_isa_t*) cg->arch_env;
2201 arch_env = cg->arch_env;
2202 do_pic = cg->birg->main_env->options->pic;
2204 ia32_register_emitters();
2206 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2208 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2209 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2211 /* we use links to point to target blocks */
2212 set_using_irn_link(irg);
2213 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2215 /* initialize next block links */
2216 n = ARR_LEN(cg->blk_sched);
2217 for (i = 0; i < n; ++i) {
2218 ir_node *block = cg->blk_sched[i];
2219 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2221 set_irn_link(block, prev);
2224 for (i = 0; i < n; ++i) {
2225 ir_node *block = cg->blk_sched[i];
2227 ia32_gen_block(block);
2230 be_gas_emit_function_epilog(entity);
2231 be_dbg_method_end();
2233 be_emit_write_line();
2235 clear_using_irn_link(irg);
2237 /* Sort the exception table using the exception label id's.
2238 Those are ascending with ascending addresses. */
2239 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2243 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2244 be_emit_cstring("\t.long ");
2245 ia32_emit_exc_label(exc_list[i].exc_instr);
2247 be_emit_cstring("\t.long ");
2248 ia32_emit_block_name(exc_list[i].block);
2252 DEL_ARR_F(exc_list);
2255 void ia32_init_emitter(void)
2257 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");