2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
76 static ir_label_t exc_label_id;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 static int is_fallthrough(const ir_node *cfgpred)
90 pred = get_Proj_pred(cfgpred);
91 if(is_ia32_SwitchJmp(pred))
97 static int block_needs_label(const ir_node *block)
100 int n_cfgpreds = get_Block_n_cfgpreds(block);
102 if (n_cfgpreds == 0) {
104 } else if (n_cfgpreds == 1) {
105 ir_node *cfgpred = get_Block_cfgpred(block, 0);
106 ir_node *cfgpred_block = get_nodes_block(cfgpred);
108 if (get_prev_block_sched(block) == cfgpred_block
109 && is_fallthrough(cfgpred)) {
118 * Returns the register at in position pos.
120 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
123 const arch_register_t *reg = NULL;
125 assert(get_irn_arity(irn) > pos && "Invalid IN position");
127 /* The out register of the operator at position pos is the
128 in register we need. */
129 op = get_irn_n(irn, pos);
131 reg = arch_get_irn_register(arch_env, op);
133 assert(reg && "no in register found");
135 if(reg == &ia32_gp_regs[REG_GP_NOREG])
136 panic("trying to emit noreg for %+F input %d", irn, pos);
138 /* in case of unknown register: just return a valid register */
139 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
140 const arch_register_req_t *req;
142 /* ask for the requirements */
143 req = arch_get_register_req(arch_env, irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(arch_env, irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = get_ia32_out_reg(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(arch_env, proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
214 static void emit_8bit_register(const arch_register_t *reg)
216 const char *reg_name = arch_register_get_name(reg);
219 be_emit_char(reg_name[1]);
223 static void emit_16bit_register(const arch_register_t *reg)
225 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
228 be_emit_string(reg_name);
231 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
233 const char *reg_name;
236 int size = get_mode_size_bits(mode);
238 emit_8bit_register(reg);
240 } else if(size == 16) {
241 emit_16bit_register(reg);
244 assert(mode_is_float(mode) || size == 32);
248 reg_name = arch_register_get_name(reg);
251 be_emit_string(reg_name);
254 void ia32_emit_source_register(const ir_node *node, int pos)
256 const arch_register_t *reg = get_in_reg(node, pos);
258 emit_register(reg, NULL);
261 static void emit_ia32_Immediate(const ir_node *node);
263 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
265 const arch_register_t *reg;
266 ir_node *in = get_irn_n(node, pos);
267 if(is_ia32_Immediate(in)) {
268 emit_ia32_Immediate(in);
272 reg = get_in_reg(node, pos);
273 emit_8bit_register(reg);
276 void ia32_emit_dest_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_out_reg(node, pos);
280 emit_register(reg, NULL);
283 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
285 const arch_register_t *reg = get_out_reg(node, pos);
287 emit_register(reg, mode_Bu);
290 void ia32_emit_x87_register(const ir_node *node, int pos)
292 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
296 be_emit_string(attr->x87[pos]->name);
299 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
301 if(mode_is_float(mode)) {
302 switch(get_mode_size_bits(mode)) {
303 case 32: be_emit_char('s'); return;
304 case 64: be_emit_char('l'); return;
306 case 96: be_emit_char('t'); return;
309 assert(mode_is_int(mode) || mode_is_reference(mode));
310 switch(get_mode_size_bits(mode)) {
311 case 64: be_emit_cstring("ll"); return;
312 /* gas docu says q is the suffix but gcc, objdump and icc use
314 case 32: be_emit_char('l'); return;
315 case 16: be_emit_char('w'); return;
316 case 8: be_emit_char('b'); return;
319 panic("Can't output mode_suffix for %+F\n", mode);
322 void ia32_emit_mode_suffix(const ir_node *node)
324 ir_mode *mode = get_ia32_ls_mode(node);
328 ia32_emit_mode_suffix_mode(mode);
331 void ia32_emit_x87_mode_suffix(const ir_node *node)
333 /* we only need to emit the mode on address mode */
334 if(get_ia32_op_type(node) != ia32_Normal) {
335 ir_mode *mode = get_ia32_ls_mode(node);
336 assert(mode != NULL);
337 ia32_emit_mode_suffix_mode(mode);
341 static char get_xmm_mode_suffix(ir_mode *mode)
343 assert(mode_is_float(mode));
344 switch(get_mode_size_bits(mode)) {
355 void ia32_emit_xmm_mode_suffix(const ir_node *node)
357 ir_mode *mode = get_ia32_ls_mode(node);
358 assert(mode != NULL);
360 be_emit_char(get_xmm_mode_suffix(mode));
363 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
365 ir_mode *mode = get_ia32_ls_mode(node);
366 assert(mode != NULL);
367 be_emit_char(get_xmm_mode_suffix(mode));
370 void ia32_emit_extend_suffix(const ir_mode *mode)
372 if(get_mode_size_bits(mode) == 32)
374 if(mode_is_signed(mode)) {
381 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
383 ir_node *in = get_irn_n(node, pos);
384 if(is_ia32_Immediate(in)) {
385 emit_ia32_Immediate(in);
387 const ir_mode *mode = get_ia32_ls_mode(node);
388 const arch_register_t *reg = get_in_reg(node, pos);
389 emit_register(reg, mode);
394 * Emits registers and/or address mode of a binary operation.
396 void ia32_emit_binop(const ir_node *node) {
397 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
398 const ir_mode *mode = get_ia32_ls_mode(node);
399 const arch_register_t *reg_left;
401 switch(get_ia32_op_type(node)) {
403 reg_left = get_in_reg(node, n_ia32_binary_left);
404 if(is_ia32_Immediate(right_op)) {
405 emit_ia32_Immediate(right_op);
406 be_emit_cstring(", ");
407 emit_register(reg_left, mode);
410 const arch_register_t *reg_right
411 = get_in_reg(node, n_ia32_binary_right);
412 emit_register(reg_right, mode);
413 be_emit_cstring(", ");
414 emit_register(reg_left, mode);
418 if(is_ia32_Immediate(right_op)) {
419 emit_ia32_Immediate(right_op);
420 be_emit_cstring(", ");
423 reg_left = get_in_reg(node, n_ia32_binary_left);
425 be_emit_cstring(", ");
426 emit_register(reg_left, mode);
430 panic("DestMode can't be output by %%binop anymore");
433 assert(0 && "unsupported op type");
438 * Emits registers and/or address mode of a binary operation.
440 void ia32_emit_x87_binop(const ir_node *node) {
441 switch(get_ia32_op_type(node)) {
444 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
445 const arch_register_t *in1 = x87_attr->x87[0];
446 const arch_register_t *in2 = x87_attr->x87[1];
447 const arch_register_t *out = x87_attr->x87[2];
448 const arch_register_t *in;
450 in = out ? ((out == in2) ? in1 : in2) : in2;
451 out = out ? out : in1;
454 be_emit_string(arch_register_get_name(in));
455 be_emit_cstring(", %");
456 be_emit_string(arch_register_get_name(out));
464 assert(0 && "unsupported op type");
469 * Emits registers and/or address mode of a unary operation.
471 void ia32_emit_unop(const ir_node *node, int pos) {
474 switch(get_ia32_op_type(node)) {
476 op = get_irn_n(node, pos);
477 if (is_ia32_Immediate(op)) {
478 emit_ia32_Immediate(op);
480 ia32_emit_source_register(node, pos);
488 assert(0 && "unsupported op type");
492 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
496 set_entity_backend_marked(entity, 1);
497 id = get_entity_ld_ident(entity);
500 if (get_entity_owner(entity) == get_tls_type()) {
501 if (get_entity_visibility(entity) == visibility_external_allocated) {
502 be_emit_cstring("@INDNTPOFF");
504 be_emit_cstring("@NTPOFF");
508 if (!no_pic_adjust && do_pic) {
509 /* TODO: only do this when necessary */
511 be_emit_string(pic_base_label);
516 * Emits address mode.
518 void ia32_emit_am(const ir_node *node) {
519 ir_entity *ent = get_ia32_am_sc(node);
520 int offs = get_ia32_am_offs_int(node);
521 ir_node *base = get_irn_n(node, 0);
522 int has_base = !is_ia32_NoReg_GP(base);
523 ir_node *index = get_irn_n(node, 1);
524 int has_index = !is_ia32_NoReg_GP(index);
526 /* just to be sure... */
527 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
531 if (is_ia32_am_sc_sign(node))
533 ia32_emit_entity(ent, 0);
538 be_emit_irprintf("%+d", offs);
540 be_emit_irprintf("%d", offs);
544 if (has_base || has_index) {
549 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
550 emit_register(reg, NULL);
553 /* emit index + scale */
555 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
558 emit_register(reg, NULL);
560 scale = get_ia32_am_scale(node);
562 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
568 /* special case if nothing is set */
569 if(ent == NULL && offs == 0 && !has_base && !has_index) {
574 static void emit_ia32_IMul(const ir_node *node)
576 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
577 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
579 be_emit_cstring("\timul");
580 ia32_emit_mode_suffix(node);
583 ia32_emit_binop(node);
585 /* do we need the 3-address form? */
586 if(is_ia32_NoReg_GP(left) ||
587 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
588 be_emit_cstring(", ");
589 emit_register(out_reg, get_ia32_ls_mode(node));
591 be_emit_finish_line_gas(node);
594 /*************************************************
597 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
598 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
599 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
600 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
602 *************************************************/
605 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
608 * coding of conditions
610 struct cmp2conditon_t {
616 * positive conditions for signed compares
618 static const struct cmp2conditon_t cmp2condition_s[] = {
619 { NULL, pn_Cmp_False }, /* always false */
620 { "e", pn_Cmp_Eq }, /* == */
621 { "l", pn_Cmp_Lt }, /* < */
622 { "le", pn_Cmp_Le }, /* <= */
623 { "g", pn_Cmp_Gt }, /* > */
624 { "ge", pn_Cmp_Ge }, /* >= */
625 { "ne", pn_Cmp_Lg }, /* != */
626 { NULL, pn_Cmp_Leg}, /* always true */
630 * positive conditions for unsigned compares
632 static const struct cmp2conditon_t cmp2condition_u[] = {
633 { NULL, pn_Cmp_False }, /* always false */
634 { "e", pn_Cmp_Eq }, /* == */
635 { "b", pn_Cmp_Lt }, /* < */
636 { "be", pn_Cmp_Le }, /* <= */
637 { "a", pn_Cmp_Gt }, /* > */
638 { "ae", pn_Cmp_Ge }, /* >= */
639 { "ne", pn_Cmp_Lg }, /* != */
640 { NULL, pn_Cmp_Leg }, /* always true */
644 * walks up a tree of copies/perms/spills/reloads to find the original value
645 * that is moved around
647 static ir_node *find_original_value(ir_node *node)
649 inc_irg_visited(current_ir_graph);
651 mark_irn_visited(node);
652 if(be_is_Copy(node)) {
653 node = be_get_Copy_op(node);
654 } else if(be_is_CopyKeep(node)) {
655 node = be_get_CopyKeep_op(node);
656 } else if(is_Proj(node)) {
657 ir_node *pred = get_Proj_pred(node);
658 if(be_is_Perm(pred)) {
659 node = get_irn_n(pred, get_Proj_proj(node));
660 } else if(be_is_MemPerm(pred)) {
661 node = get_irn_n(pred, get_Proj_proj(node) + 1);
662 } else if(is_ia32_Load(pred)) {
663 node = get_irn_n(pred, n_ia32_Load_mem);
667 } else if(is_ia32_Store(node)) {
668 node = get_irn_n(node, n_ia32_Store_val);
669 } else if(is_Phi(node)) {
671 arity = get_irn_arity(node);
672 for(i = 0; i < arity; ++i) {
673 ir_node *in = get_irn_n(node, i);
686 static int determine_final_pnc(const ir_node *node, int flags_pos,
689 ir_node *flags = get_irn_n(node, flags_pos);
690 const ia32_attr_t *flags_attr;
691 flags = skip_Proj(flags);
693 if(is_ia32_Sahf(flags)) {
694 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
695 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
696 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
697 cmp = find_original_value(cmp);
698 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
699 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
702 flags_attr = get_ia32_attr_const(cmp);
703 if(flags_attr->data.ins_permuted)
704 pnc = get_mirrored_pnc(pnc);
705 pnc |= ia32_pn_Cmp_float;
706 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
707 || is_ia32_Fucompi(flags)) {
708 flags_attr = get_ia32_attr_const(flags);
710 if(flags_attr->data.ins_permuted)
711 pnc = get_mirrored_pnc(pnc);
712 pnc |= ia32_pn_Cmp_float;
715 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
716 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
718 flags_attr = get_ia32_attr_const(flags);
720 if(flags_attr->data.ins_permuted)
721 pnc = get_mirrored_pnc(pnc);
722 if(flags_attr->data.cmp_unsigned)
723 pnc |= ia32_pn_Cmp_unsigned;
729 static void ia32_emit_cmp_suffix(int pnc)
733 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
735 assert(cmp2condition_u[pnc].num == pnc);
736 str = cmp2condition_u[pnc].name;
739 assert(cmp2condition_s[pnc].num == pnc);
740 str = cmp2condition_s[pnc].name;
746 void ia32_emit_cmp_suffix_node(const ir_node *node,
749 const ia32_attr_t *attr = get_ia32_attr_const(node);
751 pn_Cmp pnc = get_ia32_condcode(node);
753 pnc = determine_final_pnc(node, flags_pos, pnc);
754 if(attr->data.ins_permuted) {
755 if(pnc & ia32_pn_Cmp_float) {
756 pnc = get_negated_pnc(pnc, mode_F);
758 pnc = get_negated_pnc(pnc, mode_Iu);
762 ia32_emit_cmp_suffix(pnc);
766 * Returns the target block for a control flow node.
768 static ir_node *get_cfop_target_block(const ir_node *irn) {
769 assert(get_irn_mode(irn) == mode_X);
770 return get_irn_link(irn);
774 * Emits a block label for the given block.
776 static void ia32_emit_block_name(const ir_node *block)
778 if (has_Block_label(block)) {
779 be_emit_string(be_gas_block_label_prefix());
780 be_emit_irprintf("%lu", get_Block_label(block));
782 be_emit_cstring(BLOCK_PREFIX);
783 be_emit_irprintf("%ld", get_irn_node_nr(block));
788 * Emits an exception label for a given node.
790 static void ia32_emit_exc_label(const ir_node *node)
792 be_emit_string(be_gas_insn_label_prefix());
793 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
797 * Emits the target label for a control flow node.
799 static void ia32_emit_cfop_target(const ir_node *node)
801 ir_node *block = get_cfop_target_block(node);
803 ia32_emit_block_name(block);
807 * Returns the Proj with projection number proj and NOT mode_M
809 static ir_node *get_proj(const ir_node *node, long proj) {
810 const ir_edge_t *edge;
813 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
815 foreach_out_edge(node, edge) {
816 src = get_edge_src_irn(edge);
818 assert(is_Proj(src) && "Proj expected");
819 if (get_irn_mode(src) == mode_M)
822 if (get_Proj_proj(src) == proj)
828 static int can_be_fallthrough(const ir_node *node)
830 ir_node *target_block = get_cfop_target_block(node);
831 ir_node *block = get_nodes_block(node);
832 return get_prev_block_sched(target_block) == block;
836 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
838 static void emit_ia32_Jcc(const ir_node *node)
840 int need_parity_label = 0;
841 const ir_node *proj_true;
842 const ir_node *proj_false;
843 const ir_node *block;
844 pn_Cmp pnc = get_ia32_condcode(node);
846 pnc = determine_final_pnc(node, 0, pnc);
849 proj_true = get_proj(node, pn_ia32_Jcc_true);
850 assert(proj_true && "Jcc without true Proj");
852 proj_false = get_proj(node, pn_ia32_Jcc_false);
853 assert(proj_false && "Jcc without false Proj");
855 block = get_nodes_block(node);
857 if (can_be_fallthrough(proj_true)) {
858 /* exchange both proj's so the second one can be omitted */
859 const ir_node *t = proj_true;
861 proj_true = proj_false;
863 if(pnc & ia32_pn_Cmp_float) {
864 pnc = get_negated_pnc(pnc, mode_F);
866 pnc = get_negated_pnc(pnc, mode_Iu);
870 if (pnc & ia32_pn_Cmp_float) {
871 /* Some floating point comparisons require a test of the parity flag,
872 * which indicates that the result is unordered */
875 be_emit_cstring("\tjp ");
876 ia32_emit_cfop_target(proj_true);
877 be_emit_finish_line_gas(proj_true);
882 be_emit_cstring("\tjnp ");
883 ia32_emit_cfop_target(proj_true);
884 be_emit_finish_line_gas(proj_true);
890 /* we need a local label if the false proj is a fallthrough
891 * as the falseblock might have no label emitted then */
892 if (can_be_fallthrough(proj_false)) {
893 need_parity_label = 1;
894 be_emit_cstring("\tjp 1f");
896 be_emit_cstring("\tjp ");
897 ia32_emit_cfop_target(proj_false);
899 be_emit_finish_line_gas(proj_false);
905 be_emit_cstring("\tjp ");
906 ia32_emit_cfop_target(proj_true);
907 be_emit_finish_line_gas(proj_true);
915 be_emit_cstring("\tj");
916 ia32_emit_cmp_suffix(pnc);
918 ia32_emit_cfop_target(proj_true);
919 be_emit_finish_line_gas(proj_true);
922 if(need_parity_label) {
923 be_emit_cstring("1:");
924 be_emit_write_line();
927 /* the second Proj might be a fallthrough */
928 if (can_be_fallthrough(proj_false)) {
929 be_emit_cstring("\t/* fallthrough to ");
930 ia32_emit_cfop_target(proj_false);
931 be_emit_cstring(" */");
932 be_emit_finish_line_gas(proj_false);
934 be_emit_cstring("\tjmp ");
935 ia32_emit_cfop_target(proj_false);
936 be_emit_finish_line_gas(proj_false);
940 static void emit_ia32_CMov(const ir_node *node)
942 const ia32_attr_t *attr = get_ia32_attr_const(node);
943 int ins_permuted = attr->data.ins_permuted;
944 const arch_register_t *out = arch_get_irn_register(arch_env, node);
945 pn_Cmp pnc = get_ia32_condcode(node);
946 const arch_register_t *in_true;
947 const arch_register_t *in_false;
949 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
951 in_true = arch_get_irn_register(arch_env,
952 get_irn_n(node, n_ia32_CMov_val_true));
953 in_false = arch_get_irn_register(arch_env,
954 get_irn_n(node, n_ia32_CMov_val_false));
956 /* should be same constraint fullfilled? */
957 if(out == in_false) {
958 /* yes -> nothing to do */
959 } else if(out == in_true) {
960 const arch_register_t *tmp;
962 assert(get_ia32_op_type(node) == ia32_Normal);
964 ins_permuted = !ins_permuted;
971 be_emit_cstring("\tmovl ");
972 emit_register(in_false, NULL);
973 be_emit_cstring(", ");
974 emit_register(out, NULL);
975 be_emit_finish_line_gas(node);
979 if(pnc & ia32_pn_Cmp_float) {
980 pnc = get_negated_pnc(pnc, mode_F);
982 pnc = get_negated_pnc(pnc, mode_Iu);
986 /* TODO: handling of Nans isn't correct yet */
988 be_emit_cstring("\tcmov");
989 ia32_emit_cmp_suffix(pnc);
991 if(get_ia32_op_type(node) == ia32_AddrModeS) {
994 emit_register(in_true, get_ia32_ls_mode(node));
996 be_emit_cstring(", ");
997 emit_register(out, get_ia32_ls_mode(node));
998 be_emit_finish_line_gas(node);
1001 /*********************************************************
1004 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1005 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1006 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1007 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1010 *********************************************************/
1012 /* jump table entry (target and corresponding number) */
1013 typedef struct _branch_t {
1018 /* jump table for switch generation */
1019 typedef struct _jmp_tbl_t {
1020 ir_node *defProj; /**< default target */
1021 long min_value; /**< smallest switch case */
1022 long max_value; /**< largest switch case */
1023 long num_branches; /**< number of jumps */
1024 char *label; /**< label of the jump table */
1025 branch_t *branches; /**< jump array */
1029 * Compare two variables of type branch_t. Used to sort all switch cases
1031 static int ia32_cmp_branch_t(const void *a, const void *b) {
1032 branch_t *b1 = (branch_t *)a;
1033 branch_t *b2 = (branch_t *)b;
1035 if (b1->value <= b2->value)
1042 * Emits code for a SwitchJmp (creates a jump table if
1043 * possible otherwise a cmp-jmp cascade). Port from
1046 static void emit_ia32_SwitchJmp(const ir_node *node)
1048 unsigned long interval;
1054 const ir_edge_t *edge;
1056 /* fill the table structure */
1057 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1058 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1060 tbl.num_branches = get_irn_n_edges(node) - 1;
1061 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1062 tbl.min_value = INT_MAX;
1063 tbl.max_value = INT_MIN;
1065 default_pn = get_ia32_condcode(node);
1067 /* go over all proj's and collect them */
1068 foreach_out_edge(node, edge) {
1069 proj = get_edge_src_irn(edge);
1070 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1072 pnc = get_Proj_proj(proj);
1074 /* check for default proj */
1075 if (pnc == default_pn) {
1076 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1079 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1080 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1082 /* create branch entry */
1083 tbl.branches[i].target = proj;
1084 tbl.branches[i].value = pnc;
1089 assert(i == tbl.num_branches);
1091 /* sort the branches by their number */
1092 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1094 /* two-complement's magic make this work without overflow */
1095 interval = tbl.max_value - tbl.min_value;
1097 /* emit the table */
1098 be_emit_cstring("\tcmpl $");
1099 be_emit_irprintf("%u, ", interval);
1100 ia32_emit_source_register(node, 0);
1101 be_emit_finish_line_gas(node);
1103 be_emit_cstring("\tja ");
1104 ia32_emit_cfop_target(tbl.defProj);
1105 be_emit_finish_line_gas(node);
1107 if (tbl.num_branches > 1) {
1109 be_emit_cstring("\tjmp *");
1110 be_emit_string(tbl.label);
1111 be_emit_cstring("(,");
1112 ia32_emit_source_register(node, 0);
1113 be_emit_cstring(",4)");
1114 be_emit_finish_line_gas(node);
1116 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1117 be_emit_cstring("\t.align 4\n");
1118 be_emit_write_line();
1120 be_emit_string(tbl.label);
1121 be_emit_cstring(":\n");
1122 be_emit_write_line();
1124 be_emit_cstring(".long ");
1125 ia32_emit_cfop_target(tbl.branches[0].target);
1126 be_emit_finish_line_gas(NULL);
1128 last_value = tbl.branches[0].value;
1129 for (i = 1; i < tbl.num_branches; ++i) {
1130 while (++last_value < tbl.branches[i].value) {
1131 be_emit_cstring(".long ");
1132 ia32_emit_cfop_target(tbl.defProj);
1133 be_emit_finish_line_gas(NULL);
1135 be_emit_cstring(".long ");
1136 ia32_emit_cfop_target(tbl.branches[i].target);
1137 be_emit_finish_line_gas(NULL);
1139 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1141 /* one jump is enough */
1142 be_emit_cstring("\tjmp ");
1143 ia32_emit_cfop_target(tbl.branches[0].target);
1144 be_emit_finish_line_gas(node);
1154 * Emits code for a unconditional jump.
1156 static void emit_Jmp(const ir_node *node)
1160 /* for now, the code works for scheduled and non-schedules blocks */
1161 block = get_nodes_block(node);
1163 /* we have a block schedule */
1164 if (can_be_fallthrough(node)) {
1165 be_emit_cstring("\t/* fallthrough to ");
1166 ia32_emit_cfop_target(node);
1167 be_emit_cstring(" */");
1169 be_emit_cstring("\tjmp ");
1170 ia32_emit_cfop_target(node);
1172 be_emit_finish_line_gas(node);
1175 static void emit_ia32_Immediate(const ir_node *node)
1177 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1180 if(attr->symconst != NULL) {
1183 ia32_emit_entity(attr->symconst, 0);
1185 if(attr->symconst == NULL || attr->offset != 0) {
1186 if(attr->symconst != NULL) {
1187 be_emit_irprintf("%+d", attr->offset);
1189 be_emit_irprintf("0x%X", attr->offset);
1195 * Emit an inline assembler operand.
1197 * @param node the ia32_ASM node
1198 * @param s points to the operand (a %c)
1200 * @return pointer to the first char in s NOT in the current operand
1202 static const char* emit_asm_operand(const ir_node *node, const char *s)
1204 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1205 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1207 const arch_register_t *reg;
1208 const ia32_asm_reg_t *asm_regs = attr->register_map;
1209 const ia32_asm_reg_t *asm_reg;
1210 const char *reg_name;
1219 /* parse modifiers */
1222 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1246 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1247 "'%c' for asm op\n", node, c);
1253 sscanf(s, "%d%n", &num, &p);
1255 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1262 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1263 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1264 "input/output (%+F)\n", node);
1267 asm_reg = & asm_regs[num];
1268 assert(asm_reg->valid);
1271 if(asm_reg->use_input == 0) {
1272 reg = get_out_reg(node, asm_reg->inout_pos);
1274 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1276 /* might be an immediate value */
1277 if(is_ia32_Immediate(pred)) {
1278 emit_ia32_Immediate(pred);
1281 reg = get_in_reg(node, asm_reg->inout_pos);
1284 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1285 "(%+F)\n", num, node);
1289 if(asm_reg->memory) {
1298 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1301 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1304 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1307 panic("Invalid asm op modifier");
1309 be_emit_string(reg_name);
1311 emit_register(reg, asm_reg->mode);
1314 if(asm_reg->memory) {
1322 * Emits code for an ASM pseudo op.
1324 static void emit_ia32_Asm(const ir_node *node)
1326 const void *gen_attr = get_irn_generic_attr_const(node);
1327 const ia32_asm_attr_t *attr
1328 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1329 ident *asm_text = attr->asm_text;
1330 const char *s = get_id_str(asm_text);
1332 be_emit_cstring("# Begin ASM \t");
1333 be_emit_finish_line_gas(node);
1340 s = emit_asm_operand(node, s);
1349 be_emit_write_line();
1351 be_emit_cstring("# End ASM\n");
1352 be_emit_write_line();
1355 /**********************************
1358 * | | ___ _ __ _ _| |_) |
1359 * | | / _ \| '_ \| | | | _ <
1360 * | |___| (_) | |_) | |_| | |_) |
1361 * \_____\___/| .__/ \__, |____/
1364 **********************************/
1367 * Emit movsb/w instructions to make mov count divideable by 4
1369 static void emit_CopyB_prolog(unsigned size) {
1370 be_emit_cstring("\tcld");
1371 be_emit_finish_line_gas(NULL);
1375 be_emit_cstring("\tmovsb");
1376 be_emit_finish_line_gas(NULL);
1379 be_emit_cstring("\tmovsw");
1380 be_emit_finish_line_gas(NULL);
1383 be_emit_cstring("\tmovsb");
1384 be_emit_finish_line_gas(NULL);
1385 be_emit_cstring("\tmovsw");
1386 be_emit_finish_line_gas(NULL);
1392 * Emit rep movsd instruction for memcopy.
1394 static void emit_ia32_CopyB(const ir_node *node)
1396 unsigned size = get_ia32_copyb_size(node);
1398 emit_CopyB_prolog(size);
1400 be_emit_cstring("\trep movsd");
1401 be_emit_finish_line_gas(node);
1405 * Emits unrolled memcopy.
1407 static void emit_ia32_CopyB_i(const ir_node *node)
1409 unsigned size = get_ia32_copyb_size(node);
1411 emit_CopyB_prolog(size & 0x3);
1415 be_emit_cstring("\tmovsd");
1416 be_emit_finish_line_gas(NULL);
1422 /***************************
1426 * | | / _ \| '_ \ \ / /
1427 * | |___| (_) | | | \ V /
1428 * \_____\___/|_| |_|\_/
1430 ***************************/
1433 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1435 static void emit_ia32_Conv_with_FP(const ir_node *node)
1437 ir_mode *ls_mode = get_ia32_ls_mode(node);
1438 int ls_bits = get_mode_size_bits(ls_mode);
1440 be_emit_cstring("\tcvt");
1442 if(is_ia32_Conv_I2FP(node)) {
1444 be_emit_cstring("si2ss");
1446 be_emit_cstring("si2sd");
1448 } else if(is_ia32_Conv_FP2I(node)) {
1450 be_emit_cstring("ss2si");
1452 be_emit_cstring("sd2si");
1455 assert(is_ia32_Conv_FP2FP(node));
1457 be_emit_cstring("sd2ss");
1459 be_emit_cstring("ss2sd");
1464 switch(get_ia32_op_type(node)) {
1466 ia32_emit_source_register(node, n_ia32_unary_op);
1468 case ia32_AddrModeS:
1472 assert(0 && "unsupported op type for Conv");
1474 be_emit_cstring(", ");
1475 ia32_emit_dest_register(node, 0);
1476 be_emit_finish_line_gas(node);
1479 static void emit_ia32_Conv_I2FP(const ir_node *node)
1481 emit_ia32_Conv_with_FP(node);
1484 static void emit_ia32_Conv_FP2I(const ir_node *node)
1486 emit_ia32_Conv_with_FP(node);
1489 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1491 emit_ia32_Conv_with_FP(node);
1495 * Emits code for an Int conversion.
1497 static void emit_ia32_Conv_I2I(const ir_node *node)
1499 const char *sign_suffix;
1500 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1501 int smaller_bits = get_mode_size_bits(smaller_mode);
1503 const arch_register_t *in_reg, *out_reg;
1505 assert(!mode_is_float(smaller_mode));
1506 assert(smaller_bits == 8 || smaller_bits == 16);
1508 signed_mode = mode_is_signed(smaller_mode);
1509 sign_suffix = signed_mode ? "s" : "z";
1511 out_reg = get_out_reg(node, 0);
1513 switch(get_ia32_op_type(node)) {
1515 in_reg = get_in_reg(node, n_ia32_unary_op);
1517 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1518 out_reg == &ia32_gp_regs[REG_EAX] &&
1522 /* argument and result are both in EAX and */
1523 /* signedness is ok: -> use the smaller cwtl opcode */
1524 be_emit_cstring("\tcwtl");
1526 be_emit_cstring("\tmov");
1527 be_emit_string(sign_suffix);
1528 ia32_emit_mode_suffix_mode(smaller_mode);
1529 be_emit_cstring("l ");
1530 emit_register(in_reg, smaller_mode);
1531 be_emit_cstring(", ");
1532 emit_register(out_reg, NULL);
1535 case ia32_AddrModeS: {
1536 be_emit_cstring("\tmov");
1537 be_emit_string(sign_suffix);
1538 ia32_emit_mode_suffix_mode(smaller_mode);
1539 be_emit_cstring("l ");
1541 be_emit_cstring(", ");
1542 emit_register(out_reg, NULL);
1546 panic("unsupported op type for Conv");
1548 be_emit_finish_line_gas(node);
1552 /*******************************************
1555 * | |__ ___ _ __ ___ __| | ___ ___
1556 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1557 * | |_) | __/ | | | (_) | (_| | __/\__ \
1558 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1560 *******************************************/
1563 * Emits a backend call
1565 static void emit_be_Call(const ir_node *node)
1567 ir_entity *ent = be_Call_get_entity(node);
1569 be_emit_cstring("\tcall ");
1571 ia32_emit_entity(ent, 1);
1573 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1575 emit_register(reg, NULL);
1577 be_emit_finish_line_gas(node);
1581 * Emits code to increase stack pointer.
1583 static void emit_be_IncSP(const ir_node *node)
1585 int offs = be_get_IncSP_offset(node);
1586 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1592 be_emit_cstring("\tsubl $");
1593 be_emit_irprintf("%u, ", offs);
1594 emit_register(reg, NULL);
1596 be_emit_cstring("\taddl $");
1597 be_emit_irprintf("%u, ", -offs);
1598 emit_register(reg, NULL);
1600 be_emit_finish_line_gas(node);
1604 * Emits code for Copy/CopyKeep.
1606 static void Copy_emitter(const ir_node *node, const ir_node *op)
1608 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1609 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1615 if(is_unknown_reg(in))
1617 /* copies of vf nodes aren't real... */
1618 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1621 mode = get_irn_mode(node);
1622 if (mode == mode_E) {
1623 be_emit_cstring("\tmovsd ");
1624 emit_register(in, NULL);
1625 be_emit_cstring(", ");
1626 emit_register(out, NULL);
1628 be_emit_cstring("\tmovl ");
1629 emit_register(in, NULL);
1630 be_emit_cstring(", ");
1631 emit_register(out, NULL);
1633 be_emit_finish_line_gas(node);
1636 static void emit_be_Copy(const ir_node *node)
1638 Copy_emitter(node, be_get_Copy_op(node));
1641 static void emit_be_CopyKeep(const ir_node *node)
1643 Copy_emitter(node, be_get_CopyKeep_op(node));
1647 * Emits code for exchange.
1649 static void emit_be_Perm(const ir_node *node)
1651 const arch_register_t *in0, *in1;
1652 const arch_register_class_t *cls0, *cls1;
1654 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1655 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1657 cls0 = arch_register_get_class(in0);
1658 cls1 = arch_register_get_class(in1);
1660 assert(cls0 == cls1 && "Register class mismatch at Perm");
1662 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1663 be_emit_cstring("\txchg ");
1664 emit_register(in1, NULL);
1665 be_emit_cstring(", ");
1666 emit_register(in0, NULL);
1667 be_emit_finish_line_gas(node);
1668 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1669 be_emit_cstring("\txorpd ");
1670 emit_register(in1, NULL);
1671 be_emit_cstring(", ");
1672 emit_register(in0, NULL);
1673 be_emit_finish_line_gas(NULL);
1675 be_emit_cstring("\txorpd ");
1676 emit_register(in0, NULL);
1677 be_emit_cstring(", ");
1678 emit_register(in1, NULL);
1679 be_emit_finish_line_gas(NULL);
1681 be_emit_cstring("\txorpd ");
1682 emit_register(in1, NULL);
1683 be_emit_cstring(", ");
1684 emit_register(in0, NULL);
1685 be_emit_finish_line_gas(node);
1686 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1688 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1691 panic("unexpected register class in be_Perm (%+F)\n", node);
1696 * Emits code for Constant loading.
1698 static void emit_ia32_Const(const ir_node *node)
1700 be_emit_cstring("\tmovl ");
1701 emit_ia32_Immediate(node);
1702 be_emit_cstring(", ");
1703 ia32_emit_dest_register(node, 0);
1705 be_emit_finish_line_gas(node);
1709 * Emits code to load the TLS base
1711 static void emit_ia32_LdTls(const ir_node *node)
1713 be_emit_cstring("\tmovl %gs:0, ");
1714 ia32_emit_dest_register(node, 0);
1715 be_emit_finish_line_gas(node);
1718 /* helper function for emit_ia32_Minus64Bit */
1719 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1721 be_emit_cstring("\tmovl ");
1722 emit_register(src, NULL);
1723 be_emit_cstring(", ");
1724 emit_register(dst, NULL);
1725 be_emit_finish_line_gas(node);
1728 /* helper function for emit_ia32_Minus64Bit */
1729 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1731 be_emit_cstring("\tnegl ");
1732 emit_register(reg, NULL);
1733 be_emit_finish_line_gas(node);
1736 /* helper function for emit_ia32_Minus64Bit */
1737 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1739 be_emit_cstring("\tsbbl $0, ");
1740 emit_register(reg, NULL);
1741 be_emit_finish_line_gas(node);
1744 /* helper function for emit_ia32_Minus64Bit */
1745 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1747 be_emit_cstring("\tsbbl ");
1748 emit_register(src, NULL);
1749 be_emit_cstring(", ");
1750 emit_register(dst, NULL);
1751 be_emit_finish_line_gas(node);
1754 /* helper function for emit_ia32_Minus64Bit */
1755 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1757 be_emit_cstring("\txchgl ");
1758 emit_register(src, NULL);
1759 be_emit_cstring(", ");
1760 emit_register(dst, NULL);
1761 be_emit_finish_line_gas(node);
1764 /* helper function for emit_ia32_Minus64Bit */
1765 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1767 be_emit_cstring("\txorl ");
1768 emit_register(reg, NULL);
1769 be_emit_cstring(", ");
1770 emit_register(reg, NULL);
1771 be_emit_finish_line_gas(node);
1774 static void emit_ia32_Minus64Bit(const ir_node *node)
1776 const arch_register_t *in_lo = get_in_reg(node, 0);
1777 const arch_register_t *in_hi = get_in_reg(node, 1);
1778 const arch_register_t *out_lo = get_out_reg(node, 0);
1779 const arch_register_t *out_hi = get_out_reg(node, 1);
1781 if (out_lo == in_lo) {
1782 if (out_hi != in_hi) {
1783 /* a -> a, b -> d */
1786 /* a -> a, b -> b */
1789 } else if (out_lo == in_hi) {
1790 if (out_hi == in_lo) {
1791 /* a -> b, b -> a */
1792 emit_xchg(node, in_lo, in_hi);
1795 /* a -> b, b -> d */
1796 emit_mov(node, in_hi, out_hi);
1797 emit_mov(node, in_lo, out_lo);
1801 if (out_hi == in_lo) {
1802 /* a -> c, b -> a */
1803 emit_mov(node, in_lo, out_lo);
1805 } else if (out_hi == in_hi) {
1806 /* a -> c, b -> b */
1807 emit_mov(node, in_lo, out_lo);
1810 /* a -> c, b -> d */
1811 emit_mov(node, in_lo, out_lo);
1817 emit_neg( node, out_hi);
1818 emit_neg( node, out_lo);
1819 emit_sbb0(node, out_hi);
1823 emit_zero(node, out_hi);
1824 emit_neg( node, out_lo);
1825 emit_sbb( node, in_hi, out_hi);
1828 static void emit_ia32_GetEIP(const ir_node *node)
1830 be_emit_cstring("\tcall ");
1831 be_emit_string(pic_base_label);
1832 be_emit_finish_line_gas(node);
1834 be_emit_string(pic_base_label);
1835 be_emit_cstring(":\n");
1836 be_emit_write_line();
1838 be_emit_cstring("\tpopl ");
1839 ia32_emit_dest_register(node, 0);
1841 be_emit_write_line();
1844 static void emit_be_Return(const ir_node *node)
1847 be_emit_cstring("\tret");
1849 pop = be_Return_get_pop(node);
1851 be_emit_irprintf(" $%d", pop);
1852 } else if (be_Return_get_emit_pop(node)) {
1853 ir_node *block = get_nodes_block(node);
1854 if (block_needs_label(block)) {
1855 be_emit_cstring(" $0");
1858 be_emit_finish_line_gas(node);
1861 static void emit_Nothing(const ir_node *node)
1867 /***********************************************************************************
1870 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1871 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1872 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1873 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1875 ***********************************************************************************/
1878 * Enters the emitter functions for handled nodes into the generic
1879 * pointer of an opcode.
1881 static void ia32_register_emitters(void) {
1883 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1884 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1885 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1886 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1887 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1888 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1890 /* first clear the generic function pointer for all ops */
1891 clear_irp_opcodes_generic_func();
1893 /* register all emitter functions defined in spec */
1894 ia32_register_spec_emitters();
1896 /* other ia32 emitter functions */
1900 IA32_EMIT(SwitchJmp);
1903 IA32_EMIT(Conv_I2FP);
1904 IA32_EMIT(Conv_FP2I);
1905 IA32_EMIT(Conv_FP2FP);
1906 IA32_EMIT(Conv_I2I);
1907 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1910 IA32_EMIT(Minus64Bit);
1914 /* benode emitter */
1939 typedef void (*emit_func_ptr) (const ir_node *);
1942 * Emits code for a node.
1944 static void ia32_emit_node(ir_node *node)
1946 ir_op *op = get_irn_op(node);
1948 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1950 if (is_ia32_irn(node) && get_ia32_exc_label(node)) {
1951 /* emit the exception label of this instruction */
1952 ia32_assign_exc_label(node);
1954 if (op->ops.generic) {
1955 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1957 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1962 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1968 * Emits gas alignment directives
1970 static void ia32_emit_alignment(unsigned align, unsigned skip)
1972 be_emit_cstring("\t.p2align ");
1973 be_emit_irprintf("%u,,%u\n", align, skip);
1974 be_emit_write_line();
1978 * Emits gas alignment directives for Labels depended on cpu architecture.
1980 static void ia32_emit_align_label(void)
1982 unsigned align = ia32_cg_config.label_alignment;
1983 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1984 ia32_emit_alignment(align, maximum_skip);
1988 * Test whether a block should be aligned.
1989 * For cpus in the P4/Athlon class it is useful to align jump labels to
1990 * 16 bytes. However we should only do that if the alignment nops before the
1991 * label aren't executed more often than we have jumps to the label.
1993 static int should_align_block(const ir_node *block)
1995 static const double DELTA = .0001;
1996 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1997 ir_node *prev = get_prev_block_sched(block);
1999 double prev_freq = 0; /**< execfreq of the fallthrough block */
2000 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2003 if(exec_freq == NULL)
2005 if(ia32_cg_config.label_alignment_factor <= 0)
2008 block_freq = get_block_execfreq(exec_freq, block);
2009 if(block_freq < DELTA)
2012 n_cfgpreds = get_Block_n_cfgpreds(block);
2013 for(i = 0; i < n_cfgpreds; ++i) {
2014 const ir_node *pred = get_Block_cfgpred_block(block, i);
2015 double pred_freq = get_block_execfreq(exec_freq, pred);
2018 prev_freq += pred_freq;
2020 jmp_freq += pred_freq;
2024 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2027 jmp_freq /= prev_freq;
2029 return jmp_freq > ia32_cg_config.label_alignment_factor;
2033 * Emit the block header for a block.
2035 * @param block the block
2036 * @param prev_block the previous block
2038 static void ia32_emit_block_header(ir_node *block)
2040 ir_graph *irg = current_ir_graph;
2041 int need_label = block_needs_label(block);
2043 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2045 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2048 if (ia32_cg_config.label_alignment > 0) {
2049 /* align the current block if:
2050 * a) if should be aligned due to its execution frequency
2051 * b) there is no fall-through here
2053 if (should_align_block(block)) {
2054 ia32_emit_align_label();
2056 /* if the predecessor block has no fall-through,
2057 we can always align the label. */
2059 int has_fallthrough = 0;
2061 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2062 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2063 if (can_be_fallthrough(cfg_pred)) {
2064 has_fallthrough = 1;
2069 if (!has_fallthrough)
2070 ia32_emit_align_label();
2074 if (need_label || has_Block_label(block)) {
2075 ia32_emit_block_name(block);
2078 be_emit_pad_comment();
2079 be_emit_cstring(" /* ");
2081 be_emit_cstring("\t/* ");
2082 ia32_emit_block_name(block);
2083 be_emit_cstring(": ");
2086 be_emit_cstring("preds:");
2088 /* emit list of pred blocks in comment */
2089 arity = get_irn_arity(block);
2090 for (i = 0; i < arity; ++i) {
2091 ir_node *predblock = get_Block_cfgpred_block(block, i);
2092 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2094 if (exec_freq != NULL) {
2095 be_emit_irprintf(" freq: %f",
2096 get_block_execfreq(exec_freq, block));
2098 be_emit_cstring(" */\n");
2099 be_emit_write_line();
2103 * Walks over the nodes in a block connected by scheduling edges
2104 * and emits code for each node.
2106 static void ia32_gen_block(ir_node *block)
2110 ia32_emit_block_header(block);
2112 /* emit the contents of the block */
2113 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2114 sched_foreach(block, node) {
2115 ia32_emit_node(node);
2119 typedef struct exc_entry {
2120 ir_node *exc_instr; /** The instruction that can issue an exception. */
2121 ir_node *block; /** The block to call then. */
2126 * Sets labels for control flow nodes (jump target).
2127 * Links control predecessors to there destination blocks.
2129 static void ia32_gen_labels(ir_node *block, void *data)
2131 exc_entry **exc_list = data;
2135 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2136 pred = get_Block_cfgpred(block, n);
2137 set_irn_link(pred, block);
2139 pred = skip_Proj(pred);
2140 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2145 ARR_APP1(exc_entry, *exc_list, e);
2146 set_irn_link(pred, block);
2152 * Assign and emit an exception label if the current instruction can fail.
2154 void ia32_assign_exc_label(ir_node *node)
2156 if (get_ia32_exc_label(node)) {
2157 /* assign a new ID to the instruction */
2158 set_ia32_exc_label_id(node, ++exc_label_id);
2160 ia32_emit_exc_label(node);
2162 be_emit_pad_comment();
2163 be_emit_cstring("/* exception to Block ");
2164 ia32_emit_cfop_target(node);
2165 be_emit_cstring(" */\n");
2166 be_emit_write_line();
2171 * Compare two exception_entries.
2173 static int cmp_exc_entry(const void *a, const void *b) {
2174 const exc_entry *ea = a;
2175 const exc_entry *eb = b;
2177 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2183 * Main driver. Emits the code for one routine.
2185 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2187 ir_entity *entity = get_irg_entity(irg);
2188 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2192 isa = (const ia32_isa_t*) cg->arch_env;
2193 arch_env = cg->arch_env;
2194 do_pic = cg->birg->main_env->options->pic;
2196 ia32_register_emitters();
2198 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2200 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2201 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2203 /* we use links to point to target blocks */
2204 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2205 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2207 /* initialize next block links */
2208 n = ARR_LEN(cg->blk_sched);
2209 for (i = 0; i < n; ++i) {
2210 ir_node *block = cg->blk_sched[i];
2211 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2213 set_irn_link(block, prev);
2216 for (i = 0; i < n; ++i) {
2217 ir_node *block = cg->blk_sched[i];
2219 ia32_gen_block(block);
2222 be_gas_emit_function_epilog(entity);
2223 be_dbg_method_end();
2225 be_emit_write_line();
2227 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2229 /* Sort the exception table using the exception label id's.
2230 Those are ascending with ascending addresses. */
2231 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2235 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2236 be_emit_cstring("\t.long ");
2237 ia32_emit_exc_label(exc_list[i].exc_instr);
2239 be_emit_cstring("\t.long ");
2240 ia32_emit_block_name(exc_list[i].block);
2244 DEL_ARR_F(exc_list);
2247 void ia32_init_emitter(void)
2249 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");