2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
157 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
160 be_emit_char(reg->name[1]); /* get the basic name of the register */
165 * Emit the name of the 8bit high register
167 static void emit_8bit_register_high(const arch_register_t *reg)
169 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
170 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
173 be_emit_char(reg->name[1]); /* get the basic name of the register */
177 static void emit_16bit_register(const arch_register_t *reg)
180 be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
184 * emit a register, possible shortened by a mode
186 * @param reg the register
187 * @param mode the mode of the register or NULL for full register
189 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
192 int size = get_mode_size_bits(mode);
194 case 8: emit_8bit_register(reg); return;
195 case 16: emit_16bit_register(reg); return;
197 assert(mode_is_float(mode) || size == 32);
201 be_emit_string(reg->name);
204 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
206 be_gas_emit_entity(entity);
208 if (get_entity_owner(entity) == get_tls_type()) {
209 if (!entity_has_definition(entity)) {
210 be_emit_cstring("@INDNTPOFF");
212 be_emit_cstring("@NTPOFF");
216 if (do_pic && !no_pic_adjust) {
218 be_emit_string(pic_base_label);
222 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
224 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
226 if (attr->symconst != NULL) {
229 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
231 if (attr->symconst == NULL || attr->offset != 0) {
232 if (attr->symconst != NULL) {
233 be_emit_irprintf("%+d", attr->offset);
235 be_emit_irprintf("0x%X", attr->offset);
240 static void emit_ia32_Immediate(const ir_node *node)
243 emit_ia32_Immediate_no_prefix(node);
246 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
248 assert(mode_is_int(mode) || mode_is_reference(mode));
249 switch (get_mode_size_bits(mode)) {
250 case 8: be_emit_char('b'); return;
251 case 16: be_emit_char('w'); return;
252 case 32: be_emit_char('l'); return;
253 /* gas docu says q is the suffix but gcc, objdump and icc use ll
255 case 64: be_emit_cstring("ll"); return;
257 panic("Can't output mode_suffix for %+F", mode);
260 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
264 /* we only need to emit the mode on address mode */
265 if (get_ia32_op_type(node) == ia32_Normal)
268 mode = get_ia32_ls_mode(node);
269 assert(mode != NULL);
271 if (mode_is_float(mode)) {
272 switch (get_mode_size_bits(mode)) {
273 case 32: be_emit_char('s'); return;
274 case 64: be_emit_char('l'); return;
275 /* long doubles have different sizes due to alignment on different
279 case 128: be_emit_char('t'); return;
282 assert(mode_is_int(mode) || mode_is_reference(mode));
283 switch (get_mode_size_bits(mode)) {
284 case 16: be_emit_char('s'); return;
285 case 32: be_emit_char('l'); return;
286 /* gas docu says q is the suffix but gcc, objdump and icc use ll
288 case 64: be_emit_cstring("ll"); return;
291 panic("Can't output mode_suffix for %+F", mode);
294 static char get_xmm_mode_suffix(ir_mode *mode)
296 assert(mode_is_float(mode));
297 switch (get_mode_size_bits(mode)) {
300 default: panic("Invalid XMM mode");
304 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
306 ir_mode *mode = get_ia32_ls_mode(node);
307 assert(mode != NULL);
308 be_emit_char(get_xmm_mode_suffix(mode));
312 * Returns the target block for a control flow node.
314 static ir_node *get_cfop_target_block(const ir_node *irn)
316 assert(get_irn_mode(irn) == mode_X);
317 return (ir_node*)get_irn_link(irn);
321 * Emits the target label for a control flow node.
323 static void ia32_emit_cfop_target(const ir_node *node)
325 ir_node *block = get_cfop_target_block(node);
326 be_gas_emit_block_name(block);
330 * Emit the suffix for a compare instruction.
332 static void ia32_emit_condition_code(ia32_condition_code_t cc)
335 case ia32_cc_overflow: be_emit_cstring("o"); return;
336 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
337 case ia32_cc_float_below:
338 case ia32_cc_float_unordered_below:
339 case ia32_cc_below: be_emit_cstring("b"); return;
340 case ia32_cc_float_above_equal:
341 case ia32_cc_float_unordered_above_equal:
342 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
343 case ia32_cc_float_equal:
344 case ia32_cc_equal: be_emit_cstring("e"); return;
345 case ia32_cc_float_not_equal:
346 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
347 case ia32_cc_float_below_equal:
348 case ia32_cc_float_unordered_below_equal:
349 case ia32_cc_below_equal: be_emit_cstring("be"); return;
350 case ia32_cc_float_above:
351 case ia32_cc_float_unordered_above:
352 case ia32_cc_above: be_emit_cstring("a"); return;
353 case ia32_cc_sign: be_emit_cstring("s"); return;
354 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
355 case ia32_cc_parity: be_emit_cstring("p"); return;
356 case ia32_cc_not_parity: be_emit_cstring("np"); return;
357 case ia32_cc_less: be_emit_cstring("l"); return;
358 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
359 case ia32_cc_less_equal: be_emit_cstring("le"); return;
360 case ia32_cc_greater: be_emit_cstring("g"); return;
361 case ia32_cc_float_parity_cases:
362 case ia32_cc_additional_float_cases:
365 panic("Invalid ia32 condition code");
368 typedef enum ia32_emit_mod_t {
370 EMIT_RESPECT_LS = 1U << 0,
371 EMIT_ALTERNATE_AM = 1U << 1,
373 EMIT_HIGH_REG = 1U << 3,
374 EMIT_LOW_REG = 1U << 4,
375 EMIT_16BIT_REG = 1U << 5
377 ENUM_BITSET(ia32_emit_mod_t)
380 * Emits address mode.
382 static void ia32_emit_am(ir_node const *const node)
384 ir_entity *ent = get_ia32_am_sc(node);
385 int offs = get_ia32_am_offs_int(node);
386 ir_node *base = get_irn_n(node, n_ia32_base);
387 int has_base = !is_ia32_NoReg_GP(base);
388 ir_node *idx = get_irn_n(node, n_ia32_index);
389 int has_index = !is_ia32_NoReg_GP(idx);
391 /* just to be sure... */
392 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
394 if (get_ia32_am_tls_segment(node))
395 be_emit_cstring("%gs:");
399 const ia32_attr_t *attr = get_ia32_attr_const(node);
400 if (is_ia32_am_sc_sign(node))
402 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
405 /* also handle special case if nothing is set */
406 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
408 be_emit_irprintf("%+d", offs);
410 be_emit_irprintf("%d", offs);
414 if (has_base || has_index) {
419 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
420 emit_register(reg, NULL);
423 /* emit index + scale */
425 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
428 emit_register(reg, NULL);
430 scale = get_ia32_am_scale(node);
432 be_emit_irprintf(",%d", 1 << scale);
439 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
441 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
448 const char *start = fmt;
449 ia32_emit_mod_t mod = EMIT_NONE;
451 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
454 be_emit_string_len(start, fmt - start);
459 be_emit_write_line();
473 case '*': mod |= EMIT_ALTERNATE_AM; break;
474 case '#': mod |= EMIT_RESPECT_LS; break;
475 case 'l': mod |= EMIT_LONG; break;
476 case '>': mod |= EMIT_HIGH_REG; break;
477 case '<': mod |= EMIT_LOW_REG; break;
478 case '^': mod |= EMIT_16BIT_REG; break;
487 arch_register_t const *reg;
497 if (get_ia32_op_type(node) == ia32_Normal) {
498 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
499 char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
500 be_emit_irprintf(fmt, attr->reg->name);
508 if (mod & EMIT_ALTERNATE_AM)
514 reg = va_arg(ap, const arch_register_t*);
515 if (get_ia32_op_type(node) == ia32_Normal) {
522 if (get_ia32_op_type(node) == ia32_Normal) {
529 default: goto unknown;
535 imm = get_irn_n(node, n_ia32_binary_right);
536 if (is_ia32_Immediate(imm)) {
537 emit_ia32_Immediate(imm);
538 be_emit_cstring(", ");
539 if (get_ia32_op_type(node) == ia32_Normal) {
540 goto destination_operand;
545 if (get_ia32_op_type(node) == ia32_Normal) {
546 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
547 emit_register(reg, get_ia32_ls_mode(node));
551 be_emit_cstring(", ");
553 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
554 emit_register(reg, get_ia32_ls_mode(node));
559 if (*fmt < '0' || '9' < *fmt)
561 reg = arch_get_irn_register_out(node, *fmt++ - '0');
566 ia32_emit_x87_mode_suffix(node);
567 } else if (*fmt == 'P') {
568 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
571 } else if (*fmt == 'R') {
572 /* NOTE: Work around a gas quirk for non-commutative operations if the
573 * destination register is not %st0. In this case r/non-r is swapped.
574 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
575 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
576 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
577 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
578 * In fact this corresponds to the encoding of the instruction:
579 * - The r suffix selects whether %st0 is on the left (no r) or on the
580 * right (r) side of the executed operation.
581 * - The placement of %st0 selects whether the result is written to
582 * %st0 (right) or the other register (left).
583 * This means that it is sufficient to test whether the operands are
584 * permuted. In particular it is not necessary to consider wether the
585 * result is to be placed into the explicit register operand. */
586 if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
588 } else if (*fmt == 'X') {
589 ia32_emit_xmm_mode_suffix(node);
590 } else if (*fmt == '0') {
592 be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
602 if (!(mod & EMIT_ALTERNATE_AM))
604 emit_ia32_Immediate_no_prefix(imm);
608 ia32_emit_cfop_target(node);
612 ir_mode *mode = get_ia32_ls_mode(node);
615 if (mod & EMIT_RESPECT_LS) {
616 if (get_mode_size_bits(mode) == 32)
618 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
620 ia32_emit_mode_suffix_mode(mode);
625 ia32_condition_code_t cc;
628 cc = (ia32_condition_code_t)va_arg(ap, int);
629 } else if ('0' <= *fmt && *fmt <= '9') {
630 cc = get_ia32_condcode(node);
631 cc = determine_final_cc(node, *fmt - '0', cc);
636 ia32_emit_condition_code(cc);
641 reg = va_arg(ap, const arch_register_t*);
643 if (mod & EMIT_ALTERNATE_AM)
645 if (mod & EMIT_HIGH_REG) {
646 emit_8bit_register_high(reg);
647 } else if (mod & EMIT_LOW_REG) {
648 emit_8bit_register(reg);
649 } else if (mod & EMIT_16BIT_REG) {
650 emit_16bit_register(reg);
652 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
660 if (*fmt < '0' || '9' < *fmt)
664 imm = get_irn_n(node, pos);
665 if (is_ia32_Immediate(imm)) {
668 reg = arch_get_irn_register_in(node, pos);
674 const char *str = va_arg(ap, const char*);
680 if (mod & EMIT_LONG) {
681 unsigned long num = va_arg(ap, unsigned long);
682 be_emit_irprintf("%lu", num);
684 unsigned num = va_arg(ap, unsigned);
685 be_emit_irprintf("%u", num);
690 if (mod & EMIT_LONG) {
691 long num = va_arg(ap, long);
692 be_emit_irprintf("%ld", num);
694 int num = va_arg(ap, int);
695 be_emit_irprintf("%d", num);
701 panic("unknown format conversion");
705 be_emit_finish_line_gas(node);
709 static void emit_ia32_IMul(const ir_node *node)
711 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
712 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
714 /* do we need the 3-address form? */
715 if (is_ia32_NoReg_GP(left) ||
716 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
717 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
719 ia32_emitf(node, "imul%M %#AS4, %#S3");
724 * walks up a tree of copies/perms/spills/reloads to find the original value
725 * that is moved around
727 static ir_node *find_original_value(ir_node *node)
729 if (irn_visited(node))
732 mark_irn_visited(node);
733 if (be_is_Copy(node)) {
734 return find_original_value(be_get_Copy_op(node));
735 } else if (be_is_CopyKeep(node)) {
736 return find_original_value(be_get_CopyKeep_op(node));
737 } else if (is_Proj(node)) {
738 ir_node *pred = get_Proj_pred(node);
739 if (be_is_Perm(pred)) {
740 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
741 } else if (be_is_MemPerm(pred)) {
742 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
743 } else if (is_ia32_Load(pred)) {
744 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
745 } else if (is_ia32_Store(pred)) {
746 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
750 } else if (is_Phi(node)) {
752 arity = get_irn_arity(node);
753 for (i = 0; i < arity; ++i) {
754 ir_node *in = get_irn_n(node, i);
755 ir_node *res = find_original_value(in);
766 static ia32_condition_code_t determine_final_cc(const ir_node *node,
767 int flags_pos, ia32_condition_code_t cc)
769 ir_node *flags = get_irn_n(node, flags_pos);
770 const ia32_attr_t *flags_attr;
771 flags = skip_Proj(flags);
773 if (is_ia32_Sahf(flags)) {
774 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
775 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
776 inc_irg_visited(current_ir_graph);
777 cmp = find_original_value(cmp);
779 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
782 flags_attr = get_ia32_attr_const(cmp);
784 flags_attr = get_ia32_attr_const(flags);
787 if (flags_attr->data.ins_permuted)
788 cc = ia32_invert_condition_code(cc);
793 * Emits an exception label for a given node.
795 static void ia32_emit_exc_label(const ir_node *node)
797 be_emit_string(be_gas_insn_label_prefix());
798 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
801 static int can_be_fallthrough(const ir_node *node)
803 ir_node *target_block = get_cfop_target_block(node);
804 ir_node *block = get_nodes_block(node);
805 return get_prev_block_sched(target_block) == block;
809 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
811 static void emit_ia32_Jcc(const ir_node *node)
813 int need_parity_label = 0;
814 ia32_condition_code_t cc = get_ia32_condcode(node);
816 cc = determine_final_cc(node, 0, cc);
819 ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
820 assert(proj_true && "Jcc without true Proj");
822 ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
823 assert(proj_false && "Jcc without false Proj");
825 if (can_be_fallthrough(proj_true)) {
826 /* exchange both proj's so the second one can be omitted */
827 const ir_node *t = proj_true;
829 proj_true = proj_false;
831 cc = ia32_negate_condition_code(cc);
834 if (cc & ia32_cc_float_parity_cases) {
835 /* Some floating point comparisons require a test of the parity flag,
836 * which indicates that the result is unordered */
837 if (cc & ia32_cc_negated) {
838 ia32_emitf(proj_true, "jp %L");
840 /* we need a local label if the false proj is a fallthrough
841 * as the falseblock might have no label emitted then */
842 if (can_be_fallthrough(proj_false)) {
843 need_parity_label = 1;
844 ia32_emitf(proj_false, "jp 1f");
846 ia32_emitf(proj_false, "jp %L");
850 ia32_emitf(proj_true, "j%PX %L", (int)cc);
851 if (need_parity_label) {
852 be_emit_cstring("1:\n");
853 be_emit_write_line();
856 /* the second Proj might be a fallthrough */
857 if (can_be_fallthrough(proj_false)) {
858 if (be_options.verbose_asm)
859 ia32_emitf(proj_false, "/* fallthrough to %L */");
861 ia32_emitf(proj_false, "jmp %L");
866 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
869 static void emit_ia32_Setcc(const ir_node *node)
871 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
873 ia32_condition_code_t cc = get_ia32_condcode(node);
874 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
875 if (cc & ia32_cc_float_parity_cases) {
876 if (cc & ia32_cc_negated) {
877 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
878 ia32_emitf(node, "setp %>R", dreg);
879 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
881 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
882 ia32_emitf(node, "setnp %>R", dreg);
883 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
886 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
890 static void emit_ia32_CMovcc(const ir_node *node)
892 const ia32_attr_t *attr = get_ia32_attr_const(node);
893 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
894 ia32_condition_code_t cc = get_ia32_condcode(node);
895 const arch_register_t *in_true;
896 const arch_register_t *in_false;
898 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
899 /* although you can't set ins_permuted in the constructor it might still
900 * be set by memory operand folding
901 * Permuting inputs of a cmov means the condition is negated!
903 if (attr->data.ins_permuted)
904 cc = ia32_negate_condition_code(cc);
906 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
907 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
909 /* should be same constraint fullfilled? */
910 if (out == in_false) {
911 /* yes -> nothing to do */
912 } else if (out == in_true) {
913 const arch_register_t *tmp;
915 assert(get_ia32_op_type(node) == ia32_Normal);
917 cc = ia32_negate_condition_code(cc);
924 ia32_emitf(node, "movl %R, %R", in_false, out);
927 if (cc & ia32_cc_float_parity_cases) {
928 panic("CMov with floatingpoint compare/parity not supported yet");
931 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
935 * Emits code for a SwitchJmp
937 static void emit_ia32_SwitchJmp(const ir_node *node)
939 ir_entity *jump_table = get_ia32_am_sc(node);
940 const ir_switch_table *table = get_ia32_switch_table(node);
942 ia32_emitf(node, "jmp %*AM");
943 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
947 * Emits code for a unconditional jump.
949 static void emit_ia32_Jmp(const ir_node *node)
951 /* we have a block schedule */
952 if (can_be_fallthrough(node)) {
953 if (be_options.verbose_asm)
954 ia32_emitf(node, "/* fallthrough to %L */");
956 ia32_emitf(node, "jmp %L");
961 * Emit an inline assembler operand.
963 * @param node the ia32_ASM node
964 * @param s points to the operand (a %c)
966 * @return pointer to the first char in s NOT in the current operand
968 static const char* emit_asm_operand(const ir_node *node, const char *s)
970 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
971 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
973 const arch_register_t *reg;
974 const ia32_asm_reg_t *asm_regs = attr->register_map;
975 const ia32_asm_reg_t *asm_reg;
984 /* parse modifiers */
987 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1013 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1020 if (sscanf(s, "%d%n", &num, &p) != 1) {
1021 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1028 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1030 "Error: Custom assembler references invalid input/output (%+F)\n",
1034 asm_reg = & asm_regs[num];
1035 assert(asm_reg->valid);
1038 if (asm_reg->use_input == 0) {
1039 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1041 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1043 /* might be an immediate value */
1044 if (is_ia32_Immediate(pred)) {
1045 emit_ia32_Immediate(pred);
1048 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1052 "Warning: no register assigned for %d asm op (%+F)\n",
1057 if (asm_reg->memory) {
1062 if (modifier != 0) {
1065 emit_8bit_register(reg);
1068 emit_8bit_register_high(reg);
1071 emit_16bit_register(reg);
1074 panic("Invalid asm op modifier");
1077 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1080 if (asm_reg->memory) {
1088 * Emits code for an ASM pseudo op.
1090 static void emit_ia32_Asm(const ir_node *node)
1092 const void *gen_attr = get_irn_generic_attr_const(node);
1093 const ia32_asm_attr_t *attr
1094 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1095 ident *asm_text = attr->asm_text;
1096 const char *s = get_id_str(asm_text);
1098 be_emit_cstring("#APP\n");
1099 be_emit_write_line();
1106 s = emit_asm_operand(node, s);
1112 be_emit_cstring("\n#NO_APP\n");
1113 be_emit_write_line();
1118 * Emit movsb/w instructions to make mov count divideable by 4
1120 static void emit_CopyB_prolog(unsigned size)
1123 ia32_emitf(NULL, "movsb");
1125 ia32_emitf(NULL, "movsw");
1129 * Emit rep movsd instruction for memcopy.
1131 static void emit_ia32_CopyB(const ir_node *node)
1133 unsigned size = get_ia32_copyb_size(node);
1135 emit_CopyB_prolog(size);
1136 ia32_emitf(node, "rep movsd");
1140 * Emits unrolled memcopy.
1142 static void emit_ia32_CopyB_i(const ir_node *node)
1144 unsigned size = get_ia32_copyb_size(node);
1146 emit_CopyB_prolog(size);
1150 ia32_emitf(NULL, "movsd");
1156 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1158 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1161 ir_mode *ls_mode = get_ia32_ls_mode(node);
1162 int ls_bits = get_mode_size_bits(ls_mode);
1163 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1165 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1168 static void emit_ia32_Conv_I2FP(const ir_node *node)
1170 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1173 static void emit_ia32_Conv_FP2I(const ir_node *node)
1175 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1178 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1180 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1184 * Emits code to increase stack pointer.
1186 static void emit_be_IncSP(const ir_node *node)
1188 int offs = be_get_IncSP_offset(node);
1194 ia32_emitf(node, "subl $%u, %D0", offs);
1196 ia32_emitf(node, "addl $%u, %D0", -offs);
1201 * Emits code for Copy/CopyKeep.
1203 static void Copy_emitter(const ir_node *node, const ir_node *op)
1205 const arch_register_t *in = arch_get_irn_register(op);
1206 const arch_register_t *out = arch_get_irn_register(node);
1211 /* copies of fp nodes aren't real... */
1212 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
1215 ia32_emitf(node, "movl %R, %R", in, out);
1218 static void emit_be_Copy(const ir_node *node)
1220 Copy_emitter(node, be_get_Copy_op(node));
1223 static void emit_be_CopyKeep(const ir_node *node)
1225 Copy_emitter(node, be_get_CopyKeep_op(node));
1229 * Emits code for exchange.
1231 static void emit_be_Perm(const ir_node *node)
1233 const arch_register_t *in0, *in1;
1235 in0 = arch_get_irn_register(get_irn_n(node, 0));
1236 in1 = arch_get_irn_register(get_irn_n(node, 1));
1238 arch_register_class_t const *const cls0 = in0->reg_class;
1239 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
1241 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1242 ia32_emitf(node, "xchg %R, %R", in1, in0);
1243 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1244 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1245 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1246 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1247 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
1250 panic("unexpected register class in be_Perm (%+F)", node);
1254 /* helper function for emit_ia32_Minus64Bit */
1255 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1257 ia32_emitf(node, "movl %R, %R", src, dst);
1260 /* helper function for emit_ia32_Minus64Bit */
1261 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1263 ia32_emitf(node, "negl %R", reg);
1266 /* helper function for emit_ia32_Minus64Bit */
1267 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1269 ia32_emitf(node, "sbbl $0, %R", reg);
1272 /* helper function for emit_ia32_Minus64Bit */
1273 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1275 ia32_emitf(node, "sbbl %R, %R", src, dst);
1278 /* helper function for emit_ia32_Minus64Bit */
1279 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1281 ia32_emitf(node, "xchgl %R, %R", src, dst);
1284 /* helper function for emit_ia32_Minus64Bit */
1285 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1287 ia32_emitf(node, "xorl %R, %R", reg, reg);
1290 static void emit_ia32_Minus64Bit(const ir_node *node)
1292 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1293 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1294 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1295 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1297 if (out_lo == in_lo) {
1298 if (out_hi != in_hi) {
1299 /* a -> a, b -> d */
1302 /* a -> a, b -> b */
1305 } else if (out_lo == in_hi) {
1306 if (out_hi == in_lo) {
1307 /* a -> b, b -> a */
1308 emit_xchg(node, in_lo, in_hi);
1311 /* a -> b, b -> d */
1312 emit_mov(node, in_hi, out_hi);
1313 emit_mov(node, in_lo, out_lo);
1317 if (out_hi == in_lo) {
1318 /* a -> c, b -> a */
1319 emit_mov(node, in_lo, out_lo);
1321 } else if (out_hi == in_hi) {
1322 /* a -> c, b -> b */
1323 emit_mov(node, in_lo, out_lo);
1326 /* a -> c, b -> d */
1327 emit_mov(node, in_lo, out_lo);
1333 emit_neg( node, out_hi);
1334 emit_neg( node, out_lo);
1335 emit_sbb0(node, out_hi);
1339 emit_zero(node, out_hi);
1340 emit_neg( node, out_lo);
1341 emit_sbb( node, in_hi, out_hi);
1344 static void emit_ia32_GetEIP(const ir_node *node)
1346 ia32_emitf(node, "call %s", pic_base_label);
1347 be_emit_irprintf("%s:\n", pic_base_label);
1348 be_emit_write_line();
1349 ia32_emitf(node, "popl %D0");
1352 static void emit_ia32_ClimbFrame(const ir_node *node)
1354 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1356 ia32_emitf(node, "movl %S0, %D0");
1357 ia32_emitf(node, "movl $%u, %S1", attr->count);
1358 be_gas_emit_block_name(node);
1359 be_emit_cstring(":\n");
1360 be_emit_write_line();
1361 ia32_emitf(node, "movl (%D0), %D0");
1362 ia32_emitf(node, "dec %S1");
1363 be_emit_cstring("\tjnz ");
1364 be_gas_emit_block_name(node);
1365 be_emit_finish_line_gas(node);
1368 static void emit_be_Return(const ir_node *node)
1370 unsigned pop = be_Return_get_pop(node);
1372 if (pop > 0 || be_Return_get_emit_pop(node)) {
1373 ia32_emitf(node, "ret $%u", pop);
1375 ia32_emitf(node, "ret");
1379 static void emit_Nothing(const ir_node *node)
1386 * Enters the emitter functions for handled nodes into the generic
1387 * pointer of an opcode.
1389 static void ia32_register_emitters(void)
1391 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1392 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1393 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1394 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1395 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1397 /* first clear the generic function pointer for all ops */
1398 ir_clear_opcodes_generic_func();
1400 /* register all emitter functions defined in spec */
1401 ia32_register_spec_emitters();
1403 /* other ia32 emitter functions */
1406 IA32_EMIT(Conv_FP2FP);
1407 IA32_EMIT(Conv_FP2I);
1408 IA32_EMIT(Conv_I2FP);
1415 IA32_EMIT(Minus64Bit);
1416 IA32_EMIT(SwitchJmp);
1417 IA32_EMIT(ClimbFrame);
1420 /* benode emitter */
1439 typedef void (*emit_func_ptr) (const ir_node *);
1442 * Assign and emit an exception label if the current instruction can fail.
1444 static void ia32_assign_exc_label(ir_node *node)
1446 /* assign a new ID to the instruction */
1447 set_ia32_exc_label_id(node, ++exc_label_id);
1449 ia32_emit_exc_label(node);
1451 be_emit_pad_comment();
1452 be_emit_cstring("/* exception to Block ");
1453 ia32_emit_cfop_target(node);
1454 be_emit_cstring(" */\n");
1455 be_emit_write_line();
1459 * Emits code for a node.
1461 static void ia32_emit_node(ir_node *node)
1463 ir_op *op = get_irn_op(node);
1465 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1467 if (is_ia32_irn(node)) {
1468 if (get_ia32_exc_label(node)) {
1469 /* emit the exception label of this instruction */
1470 ia32_assign_exc_label(node);
1472 if (mark_spill_reload) {
1473 if (is_ia32_is_spill(node)) {
1474 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1476 if (is_ia32_is_reload(node)) {
1477 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1479 if (is_ia32_is_remat(node)) {
1480 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1484 if (op->ops.generic) {
1485 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1487 be_dwarf_location(get_irn_dbg_info(node));
1492 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, get_irn_irg(node));
1497 int sp_change = arch_get_sp_bias(node);
1498 if (sp_change != 0) {
1499 assert(sp_change != SP_BIAS_RESET);
1500 callframe_offset += sp_change;
1501 be_dwarf_callframe_offset(callframe_offset);
1507 * Emits gas alignment directives
1509 static void ia32_emit_alignment(unsigned align, unsigned skip)
1511 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1515 * Emits gas alignment directives for Labels depended on cpu architecture.
1517 static void ia32_emit_align_label(void)
1519 unsigned align = ia32_cg_config.label_alignment;
1520 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1521 ia32_emit_alignment(align, maximum_skip);
1525 * Test whether a block should be aligned.
1526 * For cpus in the P4/Athlon class it is useful to align jump labels to
1527 * 16 bytes. However we should only do that if the alignment nops before the
1528 * label aren't executed more often than we have jumps to the label.
1530 static int should_align_block(const ir_node *block)
1532 static const double DELTA = .0001;
1533 ir_node *prev = get_prev_block_sched(block);
1534 double prev_freq = 0; /**< execfreq of the fallthrough block */
1535 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1539 if (ia32_cg_config.label_alignment_factor <= 0)
1542 block_freq = get_block_execfreq(block);
1543 if (block_freq < DELTA)
1546 n_cfgpreds = get_Block_n_cfgpreds(block);
1547 for (i = 0; i < n_cfgpreds; ++i) {
1548 const ir_node *pred = get_Block_cfgpred_block(block, i);
1549 double pred_freq = get_block_execfreq(pred);
1552 prev_freq += pred_freq;
1554 jmp_freq += pred_freq;
1558 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1561 jmp_freq /= prev_freq;
1563 return jmp_freq > ia32_cg_config.label_alignment_factor;
1567 * Emit the block header for a block.
1569 * @param block the block
1570 * @param prev_block the previous block
1572 static void ia32_emit_block_header(ir_node *block)
1574 ir_graph *const irg = get_Block_irg(block);
1575 if (block == get_irg_end_block(irg))
1578 if (ia32_cg_config.label_alignment > 0) {
1579 /* align the current block if:
1580 * a) if should be aligned due to its execution frequency
1581 * b) there is no fall-through here
1583 if (should_align_block(block)) {
1584 ia32_emit_align_label();
1586 /* if the predecessor block has no fall-through,
1587 we can always align the label. */
1589 int has_fallthrough = 0;
1591 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1592 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1593 if (can_be_fallthrough(cfg_pred)) {
1594 has_fallthrough = 1;
1599 if (!has_fallthrough)
1600 ia32_emit_align_label();
1604 int const need_label = block_needs_label(block);
1605 be_gas_begin_block(block, need_label);
1609 * Walks over the nodes in a block connected by scheduling edges
1610 * and emits code for each node.
1612 static void ia32_gen_block(ir_node *block)
1614 ia32_emit_block_header(block);
1617 ir_graph *irg = get_irn_irg(block);
1618 callframe_offset = 4; /* 4 bytes for the return address */
1619 /* ESP guessing, TODO perform a real ESP simulation */
1620 if (block != get_irg_start_block(irg)) {
1621 callframe_offset += frame_type_size;
1623 be_dwarf_callframe_offset(callframe_offset);
1626 /* emit the contents of the block */
1627 be_dwarf_location(get_irn_dbg_info(block));
1628 sched_foreach(block, node) {
1629 ia32_emit_node(node);
1633 typedef struct exc_entry {
1634 ir_node *exc_instr; /** The instruction that can issue an exception. */
1635 ir_node *block; /** The block to call then. */
1640 * Sets labels for control flow nodes (jump target).
1641 * Links control predecessors to there destination blocks.
1643 static void ia32_gen_labels(ir_node *block, void *data)
1645 exc_entry **exc_list = (exc_entry**)data;
1649 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1650 pred = get_Block_cfgpred(block, n);
1651 set_irn_link(pred, block);
1653 pred = skip_Proj(pred);
1654 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1659 ARR_APP1(exc_entry, *exc_list, e);
1660 set_irn_link(pred, block);
1666 * Compare two exception_entries.
1668 static int cmp_exc_entry(const void *a, const void *b)
1670 const exc_entry *ea = (const exc_entry*)a;
1671 const exc_entry *eb = (const exc_entry*)b;
1673 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1678 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1680 ir_entity *entity = get_irg_entity(irg);
1681 ir_type *type = get_entity_type(entity);
1682 size_t n_params = get_method_n_params(type);
1683 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1684 ir_type *arg_type = layout->arg_type;
1685 size_t n_members = get_compound_n_members(arg_type);
1686 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1689 for (i = 0; i < n_members; ++i) {
1690 ir_entity *member = get_compound_member(arg_type, i);
1692 if (!is_parameter_entity(member))
1694 param = get_entity_parameter_number(member);
1695 if (param == IR_VA_START_PARAMETER_NUMBER)
1697 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1698 infos[param].reg = NULL;
1699 infos[param].entity = member;
1706 * Main driver. Emits the code for one routine.
1708 void ia32_gen_routine(ir_graph *irg)
1710 ir_entity *entity = get_irg_entity(irg);
1711 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1712 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1713 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1714 ir_node **blk_sched = irg_data->blk_sched;
1715 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1716 parameter_dbg_info_t *infos;
1719 isa = (ia32_isa_t*) arch_env;
1720 do_pic = be_options.pic;
1722 be_gas_elf_type_char = '@';
1724 ia32_register_emitters();
1726 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1728 infos = construct_parameter_infos(irg);
1729 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1733 sp_relative = layout->sp_relative;
1734 if (layout->sp_relative) {
1735 ir_type *frame_type = get_irg_frame_type(irg);
1736 frame_type_size = get_type_size_bytes(frame_type);
1737 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1739 /* well not entirely correct here, we should emit this after the
1740 * "movl esp, ebp" */
1741 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1742 /* TODO: do not hardcode the following */
1743 be_dwarf_callframe_offset(8);
1744 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1747 /* we use links to point to target blocks */
1748 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1749 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1751 /* initialize next block links */
1752 n = ARR_LEN(blk_sched);
1753 for (i = 0; i < n; ++i) {
1754 ir_node *block = blk_sched[i];
1755 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1757 set_irn_link(block, prev);
1760 for (i = 0; i < n; ++i) {
1761 ir_node *block = blk_sched[i];
1763 ia32_gen_block(block);
1766 be_gas_emit_function_epilog(entity);
1768 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1770 /* Sort the exception table using the exception label id's.
1771 Those are ascending with ascending addresses. */
1772 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1776 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1777 be_emit_cstring("\t.long ");
1778 ia32_emit_exc_label(exc_list[e].exc_instr);
1780 be_emit_cstring("\t.long ");
1781 be_gas_emit_block_name(exc_list[e].block);
1785 DEL_ARR_F(exc_list);
1788 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1789 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1793 /* ==== Experimental binary emitter ==== */
1795 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1796 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1797 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1799 static void build_reg_map(void)
1801 reg_gp_map[REG_GP_EAX] = 0x0;
1802 reg_gp_map[REG_GP_ECX] = 0x1;
1803 reg_gp_map[REG_GP_EDX] = 0x2;
1804 reg_gp_map[REG_GP_EBX] = 0x3;
1805 reg_gp_map[REG_GP_ESP] = 0x4;
1806 reg_gp_map[REG_GP_EBP] = 0x5;
1807 reg_gp_map[REG_GP_ESI] = 0x6;
1808 reg_gp_map[REG_GP_EDI] = 0x7;
1811 /** Returns the encoding for a pnc field. */
1812 static unsigned char pnc2cc(ia32_condition_code_t cc)
1817 /** Sign extension bit values for binops */
1819 UNSIGNED_IMM = 0, /**< unsigned immediate */
1820 SIGNEXT_IMM = 2, /**< sign extended immediate */
1823 /** The mod encoding of the ModR/M */
1825 MOD_IND = 0x00, /**< [reg1] */
1826 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1827 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1828 MOD_REG = 0xC0 /**< reg1 */
1831 /** create R/M encoding for ModR/M */
1832 #define ENC_RM(x) (x)
1833 /** create REG encoding for ModR/M */
1834 #define ENC_REG(x) ((x) << 3)
1836 /** create encoding for a SIB byte */
1837 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1839 /* Node: The following routines are supposed to append bytes, words, dwords
1840 to the output stream.
1841 Currently the implementation is stupid in that it still creates output
1842 for an "assembler" in the form of .byte, .long
1843 We will change this when enough infrastructure is there to create complete
1844 machine code in memory/object files */
1846 static void bemit8(const unsigned char byte)
1848 be_emit_irprintf("\t.byte 0x%x\n", byte);
1849 be_emit_write_line();
1852 static void bemit16(const unsigned short u16)
1854 be_emit_irprintf("\t.word 0x%x\n", u16);
1855 be_emit_write_line();
1858 static void bemit32(const unsigned u32)
1860 be_emit_irprintf("\t.long 0x%x\n", u32);
1861 be_emit_write_line();
1865 * Emit address of an entity. If @p is_relative is true then a relative
1866 * offset from behind the address to the entity is created.
1868 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1871 if (entity == NULL) {
1876 /* the final version should remember the position in the bytestream
1877 and patch it with the correct address at linktime... */
1878 be_emit_cstring("\t.long ");
1881 be_gas_emit_entity(entity);
1883 if (get_entity_owner(entity) == get_tls_type()) {
1884 if (!entity_has_definition(entity)) {
1885 be_emit_cstring("@INDNTPOFF");
1887 be_emit_cstring("@NTPOFF");
1892 be_emit_cstring("-.");
1897 be_emit_irprintf("%+d", offset);
1900 be_emit_write_line();
1903 static void bemit_jmp_destination(const ir_node *dest_block)
1905 be_emit_cstring("\t.long ");
1906 be_gas_emit_block_name(dest_block);
1907 be_emit_cstring(" - . - 4\n");
1908 be_emit_write_line();
1911 /* end emit routines, all emitters following here should only use the functions
1914 typedef enum reg_modifier {
1919 /** Create a ModR/M byte for src1,src2 registers */
1920 static void bemit_modrr(const arch_register_t *src1,
1921 const arch_register_t *src2)
1923 unsigned char modrm = MOD_REG;
1924 modrm |= ENC_RM(reg_gp_map[src1->index]);
1925 modrm |= ENC_REG(reg_gp_map[src2->index]);
1929 /** Create a ModR/M8 byte for src1,src2 registers */
1930 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1931 reg_modifier_t high_part2, const arch_register_t *src2)
1933 unsigned char modrm = MOD_REG;
1934 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1935 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1939 /** Create a ModR/M byte for one register and extension */
1940 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1942 unsigned char modrm = MOD_REG;
1944 modrm |= ENC_RM(reg_gp_map[reg->index]);
1945 modrm |= ENC_REG(ext);
1949 /** Create a ModR/M8 byte for one register */
1950 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1952 unsigned char modrm = MOD_REG;
1953 assert(reg_gp_map[reg->index] < 4);
1954 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1960 * Calculate the size of an signed immediate in bytes.
1962 * @param offset an offset
1964 static unsigned get_signed_imm_size(int offset)
1966 if (-128 <= offset && offset < 128) {
1968 } else if (-32768 <= offset && offset < 32768) {
1976 * Emit an address mode.
1978 * @param reg content of the reg field: either a register index or an opcode extension
1979 * @param node the node
1981 static void bemit_mod_am(unsigned reg, const ir_node *node)
1983 ir_entity *ent = get_ia32_am_sc(node);
1984 int offs = get_ia32_am_offs_int(node);
1985 ir_node *base = get_irn_n(node, n_ia32_base);
1986 int has_base = !is_ia32_NoReg_GP(base);
1987 ir_node *idx = get_irn_n(node, n_ia32_index);
1988 int has_index = !is_ia32_NoReg_GP(idx);
1991 unsigned emitoffs = 0;
1992 bool emitsib = false;
1995 /* set the mod part depending on displacement */
1997 modrm |= MOD_IND_WORD_OFS;
1999 } else if (offs == 0) {
2002 } else if (-128 <= offs && offs < 128) {
2003 modrm |= MOD_IND_BYTE_OFS;
2006 modrm |= MOD_IND_WORD_OFS;
2011 const arch_register_t *base_reg = arch_get_irn_register(base);
2012 base_enc = reg_gp_map[base_reg->index];
2014 /* Use the EBP encoding + MOD_IND if NO base register. There is
2015 * always a 32bit offset present in this case. */
2021 /* Determine if we need a SIB byte. */
2023 const arch_register_t *reg_index = arch_get_irn_register(idx);
2024 int scale = get_ia32_am_scale(node);
2026 /* R/M set to ESP means SIB in 32bit mode. */
2027 modrm |= ENC_RM(0x04);
2028 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2030 } else if (base_enc == 0x04) {
2031 /* for the above reason we are forced to emit a SIB when base is ESP.
2032 * Only the base is used, index must be ESP too, which means no index.
2034 modrm |= ENC_RM(0x04);
2035 sib = ENC_SIB(0, 0x04, 0x04);
2038 modrm |= ENC_RM(base_enc);
2041 /* We are forced to emit an 8bit offset as EBP base without offset is a
2042 * special case for SIB without base register. */
2043 if (base_enc == 0x05 && emitoffs == 0) {
2044 modrm |= MOD_IND_BYTE_OFS;
2048 modrm |= ENC_REG(reg);
2054 /* emit displacement */
2055 if (emitoffs == 8) {
2056 bemit8((unsigned) offs);
2057 } else if (emitoffs == 32) {
2058 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2063 * Emit a binop with a immediate operand.
2065 * @param node the node to emit
2066 * @param opcode_eax the opcode for the op eax, imm variant
2067 * @param opcode the opcode for the reg, imm variant
2068 * @param ruval the opcode extension for opcode
2070 static void bemit_binop_with_imm(
2071 const ir_node *node,
2072 unsigned char opcode_ax,
2073 unsigned char opcode, unsigned char ruval)
2075 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2076 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2077 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2080 /* Some instructions (test) have no short form with 32bit value + 8bit
2082 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2085 /* check for sign extension */
2086 size = get_signed_imm_size(attr->offset);
2091 bemit8(opcode | SIGNEXT_IMM);
2092 /* cmp has this special mode */
2093 if (get_ia32_op_type(node) == ia32_Normal) {
2094 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2095 bemit_modru(reg, ruval);
2097 bemit_mod_am(ruval, node);
2099 bemit8((unsigned char)attr->offset);
2103 if (get_ia32_op_type(node) == ia32_Normal) {
2104 /* check for eax variant: this variant is shorter for 32bit immediates only */
2105 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2106 if (reg->index == REG_GP_EAX) {
2110 bemit_modru(reg, ruval);
2114 bemit_mod_am(ruval, node);
2116 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2119 panic("invalid imm size?!?");
2125 static void bemit_binop_2(const ir_node *node, unsigned code)
2127 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2129 if (get_ia32_op_type(node) == ia32_Normal) {
2130 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2131 bemit_modrr(op2, out);
2133 bemit_mod_am(reg_gp_map[out->index], node);
2140 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2142 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2143 if (is_ia32_Immediate(right)) {
2144 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2146 bemit_binop_2(node, opcodes[0]);
2153 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2156 if (get_ia32_op_type(node) == ia32_Normal) {
2157 const arch_register_t *in = arch_get_irn_register_in(node, input);
2158 bemit_modru(in, ext);
2160 bemit_mod_am(ext, node);
2164 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2166 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2167 bemit_unop(node, code, reg_gp_map[out->index], input);
2170 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2172 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2175 bemit8(size == 8 ? code : code + 1);
2176 bemit_mod_am(ext, node);
2179 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2182 bemit_unop_reg(node, code, input);
2185 static void bemit_immediate(const ir_node *node, bool relative)
2187 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2188 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2191 static void bemit_copy(const ir_node *copy)
2193 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2194 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2198 /* copies of fp nodes aren't real... */
2199 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
2202 assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
2204 bemit_modrr(in, out);
2207 static void bemit_perm(const ir_node *node)
2209 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2210 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2211 const arch_register_class_t *cls0 = in0->reg_class;
2213 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
2215 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2216 if (in0->index == REG_GP_EAX) {
2217 bemit8(0x90 + reg_gp_map[in1->index]);
2218 } else if (in1->index == REG_GP_EAX) {
2219 bemit8(0x90 + reg_gp_map[in0->index]);
2222 bemit_modrr(in0, in1);
2224 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2225 panic("unimplemented"); // TODO implement
2226 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2227 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2228 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2229 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
2232 panic("unexpected register class in be_Perm (%+F)", node);
2236 static void bemit_xor0(const ir_node *node)
2238 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2240 bemit_modrr(out, out);
2243 static void bemit_mov_const(const ir_node *node)
2245 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2246 bemit8(0xB8 + reg_gp_map[out->index]);
2247 bemit_immediate(node, false);
2251 * Creates a function for a Binop with 3 possible encodings.
2253 #define BINOP(op, op0, op1, op2, op2_ext) \
2254 static void bemit_ ## op(const ir_node *node) { \
2255 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2256 bemit_binop(node, op ## _codes); \
2259 /* insn def eax,imm imm */
2260 BINOP(add, 0x03, 0x05, 0x81, 0)
2261 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2262 BINOP(adc, 0x13, 0x15, 0x81, 2)
2263 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2264 BINOP(and, 0x23, 0x25, 0x81, 4)
2265 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2266 BINOP(xor, 0x33, 0x35, 0x81, 6)
2267 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2269 #define BINOPMEM(op, ext) \
2270 static void bemit_##op(const ir_node *node) \
2273 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2276 val = get_irn_n(node, n_ia32_unary_op); \
2277 if (is_ia32_Immediate(val)) { \
2278 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2279 int offset = attr->offset; \
2280 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2282 bemit_mod_am(ext, node); \
2286 bemit_mod_am(ext, node); \
2290 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2294 bemit8(ext << 3 | 1); \
2295 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2299 static void bemit_##op##8bit(const ir_node *node) \
2301 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2302 if (is_ia32_Immediate(val)) { \
2304 bemit_mod_am(ext, node); \
2305 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2308 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2320 * Creates a function for an Unop with code /ext encoding.
2322 #define UNOP(op, code, ext, input) \
2323 static void bemit_ ## op(const ir_node *node) { \
2324 bemit_unop(node, code, ext, input); \
2327 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2328 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2329 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2330 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2331 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2332 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2334 /* TODO: am support for IJmp */
2335 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2337 #define SHIFT(op, ext) \
2338 static void bemit_##op(const ir_node *node) \
2340 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2341 ir_node *count = get_irn_n(node, 1); \
2342 if (is_ia32_Immediate(count)) { \
2343 int offset = get_ia32_immediate_attr_const(count)->offset; \
2344 if (offset == 1) { \
2346 bemit_modru(out, ext); \
2349 bemit_modru(out, ext); \
2354 bemit_modru(out, ext); \
2358 static void bemit_##op##mem(const ir_node *node) \
2361 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2364 count = get_irn_n(node, 1); \
2365 if (is_ia32_Immediate(count)) { \
2366 int offset = get_ia32_immediate_attr_const(count)->offset; \
2367 if (offset == 1) { \
2368 bemit8(size == 8 ? 0xD0 : 0xD1); \
2369 bemit_mod_am(ext, node); \
2371 bemit8(size == 8 ? 0xC0 : 0xC1); \
2372 bemit_mod_am(ext, node); \
2376 bemit8(size == 8 ? 0xD2 : 0xD3); \
2377 bemit_mod_am(ext, node); \
2387 static void bemit_shld(const ir_node *node)
2389 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2390 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2391 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2393 if (is_ia32_Immediate(count)) {
2395 bemit_modrr(out, in);
2396 bemit8(get_ia32_immediate_attr_const(count)->offset);
2399 bemit_modrr(out, in);
2403 static void bemit_shrd(const ir_node *node)
2405 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2406 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2407 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2409 if (is_ia32_Immediate(count)) {
2411 bemit_modrr(out, in);
2412 bemit8(get_ia32_immediate_attr_const(count)->offset);
2415 bemit_modrr(out, in);
2419 static void bemit_sbb0(ir_node const *const node)
2421 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2422 unsigned char const reg = reg_gp_map[out->index];
2424 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2428 * binary emitter for setcc.
2430 static void bemit_setcc(const ir_node *node)
2432 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2434 ia32_condition_code_t cc = get_ia32_condcode(node);
2435 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2436 if (cc & ia32_cc_float_parity_cases) {
2437 if (cc & ia32_cc_negated) {
2440 bemit8(0x90 | pnc2cc(cc));
2441 bemit_modrm8(REG_LOW, dreg);
2446 bemit_modrm8(REG_HIGH, dreg);
2448 /* orb %>dreg, %<dreg */
2450 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2454 bemit8(0x90 | pnc2cc(cc));
2455 bemit_modrm8(REG_LOW, dreg);
2460 bemit_modrm8(REG_HIGH, dreg);
2462 /* andb %>dreg, %<dreg */
2464 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2469 bemit8(0x90 | pnc2cc(cc));
2470 bemit_modrm8(REG_LOW, dreg);
2474 static void bemit_bsf(ir_node const *const node)
2476 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2479 static void bemit_bsr(ir_node const *const node)
2481 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2484 static void bemit_bswap(ir_node const *const node)
2487 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2490 static void bemit_bt(ir_node const *const node)
2493 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2494 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2495 if (is_ia32_Immediate(right)) {
2496 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2497 int const offset = attr->offset;
2498 assert(!attr->symconst);
2499 assert(get_signed_imm_size(offset) == 1);
2501 bemit_modru(lreg, 4);
2505 bemit_modrr(lreg, arch_get_irn_register(right));
2509 static void bemit_cmovcc(const ir_node *node)
2511 const ia32_attr_t *attr = get_ia32_attr_const(node);
2512 int ins_permuted = attr->data.ins_permuted;
2513 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2514 ia32_condition_code_t cc = get_ia32_condcode(node);
2515 const arch_register_t *in_true;
2516 const arch_register_t *in_false;
2518 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2520 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2521 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2523 /* should be same constraint fullfilled? */
2524 if (out == in_false) {
2525 /* yes -> nothing to do */
2526 } else if (out == in_true) {
2527 assert(get_ia32_op_type(node) == ia32_Normal);
2528 ins_permuted = !ins_permuted;
2532 bemit8(0x8B); // mov %in_false, %out
2533 bemit_modrr(in_false, out);
2537 cc = ia32_negate_condition_code(cc);
2539 if (cc & ia32_cc_float_parity_cases)
2540 panic("cmov can't handle parity float cases");
2543 bemit8(0x40 | pnc2cc(cc));
2544 if (get_ia32_op_type(node) == ia32_Normal) {
2545 bemit_modrr(in_true, out);
2547 bemit_mod_am(reg_gp_map[out->index], node);
2551 static void bemit_cmp(const ir_node *node)
2553 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2559 right = get_irn_n(node, n_ia32_binary_right);
2560 if (is_ia32_Immediate(right)) {
2561 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2562 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2563 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2566 if (attr->symconst != NULL) {
2569 /* check for sign extension */
2570 size = get_signed_imm_size(attr->offset);
2575 bemit8(0x81 | SIGNEXT_IMM);
2576 /* cmp has this special mode */
2577 if (get_ia32_op_type(node) == ia32_Normal) {
2578 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2579 bemit_modru(reg, 7);
2581 bemit_mod_am(7, node);
2583 bemit8((unsigned char)attr->offset);
2587 /* check for eax variant: this variant is shorter for 32bit immediates only */
2588 if (get_ia32_op_type(node) == ia32_Normal) {
2589 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2590 if (reg->index == REG_GP_EAX) {
2594 bemit_modru(reg, 7);
2598 bemit_mod_am(7, node);
2600 if (ls_size == 16) {
2601 bemit16(attr->offset);
2603 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2607 panic("invalid imm size?!?");
2609 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2611 if (get_ia32_op_type(node) == ia32_Normal) {
2612 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2613 bemit_modrr(op2, out);
2615 bemit_mod_am(reg_gp_map[out->index], node);
2620 static void bemit_cmp8bit(const ir_node *node)
2622 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2623 if (is_ia32_Immediate(right)) {
2624 if (get_ia32_op_type(node) == ia32_Normal) {
2625 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2626 if (out->index == REG_GP_EAX) {
2630 bemit_modru(out, 7);
2634 bemit_mod_am(7, node);
2636 bemit8(get_ia32_immediate_attr_const(right)->offset);
2638 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2640 if (get_ia32_op_type(node) == ia32_Normal) {
2641 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2642 bemit_modrr(out, in);
2644 bemit_mod_am(reg_gp_map[out->index], node);
2649 static void bemit_test8bit(const ir_node *node)
2651 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2652 if (is_ia32_Immediate(right)) {
2653 if (get_ia32_op_type(node) == ia32_Normal) {
2654 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2655 if (out->index == REG_GP_EAX) {
2659 bemit_modru(out, 0);
2663 bemit_mod_am(0, node);
2665 bemit8(get_ia32_immediate_attr_const(right)->offset);
2667 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2669 if (get_ia32_op_type(node) == ia32_Normal) {
2670 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2671 bemit_modrr(out, in);
2673 bemit_mod_am(reg_gp_map[out->index], node);
2678 static void bemit_imul(const ir_node *node)
2680 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2681 /* Do we need the immediate form? */
2682 if (is_ia32_Immediate(right)) {
2683 int imm = get_ia32_immediate_attr_const(right)->offset;
2684 if (get_signed_imm_size(imm) == 1) {
2685 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2688 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2692 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2696 static void bemit_dec(const ir_node *node)
2698 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2699 bemit8(0x48 + reg_gp_map[out->index]);
2702 static void bemit_inc(const ir_node *node)
2704 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2705 bemit8(0x40 + reg_gp_map[out->index]);
2708 #define UNOPMEM(op, code, ext) \
2709 static void bemit_##op(const ir_node *node) \
2711 bemit_unop_mem(node, code, ext); \
2714 UNOPMEM(notmem, 0xF6, 2)
2715 UNOPMEM(negmem, 0xF6, 3)
2716 UNOPMEM(incmem, 0xFE, 0)
2717 UNOPMEM(decmem, 0xFE, 1)
2719 static void bemit_ldtls(const ir_node *node)
2721 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2723 bemit8(0x65); // gs:
2724 if (out->index == REG_GP_EAX) {
2725 bemit8(0xA1); // movl 0, %eax
2727 bemit8(0x8B); // movl 0, %reg
2728 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2736 static void bemit_lea(const ir_node *node)
2738 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2740 bemit_mod_am(reg_gp_map[out->index], node);
2743 /* helper function for bemit_minus64bit */
2744 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2746 bemit8(0x8B); // movl %src, %dst
2747 bemit_modrr(src, dst);
2750 /* helper function for bemit_minus64bit */
2751 static void bemit_helper_neg(const arch_register_t *reg)
2753 bemit8(0xF7); // negl %reg
2754 bemit_modru(reg, 3);
2757 /* helper function for bemit_minus64bit */
2758 static void bemit_helper_sbb0(const arch_register_t *reg)
2760 bemit8(0x83); // sbbl $0, %reg
2761 bemit_modru(reg, 3);
2765 /* helper function for bemit_minus64bit */
2766 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2768 bemit8(0x1B); // sbbl %src, %dst
2769 bemit_modrr(src, dst);
2772 /* helper function for bemit_minus64bit */
2773 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2775 if (src->index == REG_GP_EAX) {
2776 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2777 } else if (dst->index == REG_GP_EAX) {
2778 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2780 bemit8(0x87); // xchgl %src, %dst
2781 bemit_modrr(src, dst);
2785 /* helper function for bemit_minus64bit */
2786 static void bemit_helper_zero(const arch_register_t *reg)
2788 bemit8(0x33); // xorl %reg, %reg
2789 bemit_modrr(reg, reg);
2792 static void bemit_minus64bit(const ir_node *node)
2794 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2795 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2796 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2797 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2799 if (out_lo == in_lo) {
2800 if (out_hi != in_hi) {
2801 /* a -> a, b -> d */
2804 /* a -> a, b -> b */
2807 } else if (out_lo == in_hi) {
2808 if (out_hi == in_lo) {
2809 /* a -> b, b -> a */
2810 bemit_helper_xchg(in_lo, in_hi);
2813 /* a -> b, b -> d */
2814 bemit_helper_mov(in_hi, out_hi);
2815 bemit_helper_mov(in_lo, out_lo);
2819 if (out_hi == in_lo) {
2820 /* a -> c, b -> a */
2821 bemit_helper_mov(in_lo, out_lo);
2823 } else if (out_hi == in_hi) {
2824 /* a -> c, b -> b */
2825 bemit_helper_mov(in_lo, out_lo);
2828 /* a -> c, b -> d */
2829 bemit_helper_mov(in_lo, out_lo);
2835 bemit_helper_neg( out_hi);
2836 bemit_helper_neg( out_lo);
2837 bemit_helper_sbb0(out_hi);
2841 bemit_helper_zero(out_hi);
2842 bemit_helper_neg( out_lo);
2843 bemit_helper_sbb( in_hi, out_hi);
2847 * Emit a single opcode.
2849 #define EMIT_SINGLEOP(op, code) \
2850 static void bemit_ ## op(const ir_node *node) { \
2855 //EMIT_SINGLEOP(daa, 0x27)
2856 //EMIT_SINGLEOP(das, 0x2F)
2857 //EMIT_SINGLEOP(aaa, 0x37)
2858 //EMIT_SINGLEOP(aas, 0x3F)
2859 //EMIT_SINGLEOP(nop, 0x90)
2860 EMIT_SINGLEOP(cwtl, 0x98)
2861 EMIT_SINGLEOP(cltd, 0x99)
2862 //EMIT_SINGLEOP(fwait, 0x9B)
2863 EMIT_SINGLEOP(sahf, 0x9E)
2864 //EMIT_SINGLEOP(popf, 0x9D)
2865 EMIT_SINGLEOP(leave, 0xC9)
2866 EMIT_SINGLEOP(int3, 0xCC)
2867 //EMIT_SINGLEOP(iret, 0xCF)
2868 //EMIT_SINGLEOP(xlat, 0xD7)
2869 //EMIT_SINGLEOP(lock, 0xF0)
2870 EMIT_SINGLEOP(rep, 0xF3)
2871 //EMIT_SINGLEOP(halt, 0xF4)
2872 EMIT_SINGLEOP(cmc, 0xF5)
2873 EMIT_SINGLEOP(stc, 0xF9)
2874 //EMIT_SINGLEOP(cli, 0xFA)
2875 //EMIT_SINGLEOP(sti, 0xFB)
2876 //EMIT_SINGLEOP(std, 0xFD)
2879 * Emits a MOV out, [MEM].
2881 static void bemit_load(const ir_node *node)
2883 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2885 if (out->index == REG_GP_EAX) {
2886 ir_node *base = get_irn_n(node, n_ia32_base);
2887 int has_base = !is_ia32_NoReg_GP(base);
2888 ir_node *idx = get_irn_n(node, n_ia32_index);
2889 int has_index = !is_ia32_NoReg_GP(idx);
2890 if (!has_base && !has_index) {
2891 ir_entity *ent = get_ia32_am_sc(node);
2892 int offs = get_ia32_am_offs_int(node);
2893 /* load from constant address to EAX can be encoded
2896 bemit_entity(ent, 0, offs, false);
2901 bemit_mod_am(reg_gp_map[out->index], node);
2905 * Emits a MOV [mem], in.
2907 static void bemit_store(const ir_node *node)
2909 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2910 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2912 if (is_ia32_Immediate(value)) {
2915 bemit_mod_am(0, node);
2916 bemit8(get_ia32_immediate_attr_const(value)->offset);
2917 } else if (size == 16) {
2920 bemit_mod_am(0, node);
2921 bemit16(get_ia32_immediate_attr_const(value)->offset);
2924 bemit_mod_am(0, node);
2925 bemit_immediate(value, false);
2928 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2930 if (in->index == REG_GP_EAX) {
2931 ir_node *base = get_irn_n(node, n_ia32_base);
2932 int has_base = !is_ia32_NoReg_GP(base);
2933 ir_node *idx = get_irn_n(node, n_ia32_index);
2934 int has_index = !is_ia32_NoReg_GP(idx);
2935 if (!has_base && !has_index) {
2936 ir_entity *ent = get_ia32_am_sc(node);
2937 int offs = get_ia32_am_offs_int(node);
2938 /* store to constant address from EAX can be encoded as
2939 * 0xA2/0xA3 [offset]*/
2947 bemit_entity(ent, 0, offs, false);
2959 bemit_mod_am(reg_gp_map[in->index], node);
2963 static void bemit_conv_i2i(const ir_node *node)
2968 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
2969 unsigned opcode = 0xB6;
2970 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
2971 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
2972 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
2975 static void bemit_popcnt(ir_node const *const node)
2978 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
2984 static void bemit_push(const ir_node *node)
2986 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
2988 if (is_ia32_Immediate(value)) {
2989 const ia32_immediate_attr_t *attr
2990 = get_ia32_immediate_attr_const(value);
2991 unsigned size = get_signed_imm_size(attr->offset);
2997 bemit8((unsigned char)attr->offset);
3002 bemit_immediate(value, false);
3005 } else if (is_ia32_NoReg_GP(value)) {
3007 bemit_mod_am(6, node);
3009 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3010 bemit8(0x50 + reg_gp_map[reg->index]);
3017 static void bemit_pop(const ir_node *node)
3019 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3020 bemit8(0x58 + reg_gp_map[reg->index]);
3023 static void bemit_popmem(const ir_node *node)
3026 bemit_mod_am(0, node);
3029 static void bemit_call(const ir_node *node)
3031 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3033 if (is_ia32_Immediate(proc)) {
3035 bemit_immediate(proc, true);
3037 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3041 static void bemit_jmp(const ir_node *dest_block)
3044 bemit_jmp_destination(dest_block);
3047 static void bemit_jump(const ir_node *node)
3049 if (can_be_fallthrough(node))
3052 bemit_jmp(get_cfop_target_block(node));
3055 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3057 unsigned char cc = pnc2cc(pnc);
3060 bemit_jmp_destination(dest_block);
3063 static void bemit_jp(bool odd, const ir_node *dest_block)
3067 bemit_jmp_destination(dest_block);
3070 static void bemit_ia32_jcc(const ir_node *node)
3072 ia32_condition_code_t cc = get_ia32_condcode(node);
3073 const ir_node *dest_true;
3074 const ir_node *dest_false;
3076 cc = determine_final_cc(node, 0, cc);
3078 /* get both Projs */
3079 ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
3080 assert(proj_true && "Jcc without true Proj");
3082 ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
3083 assert(proj_false && "Jcc without false Proj");
3085 if (can_be_fallthrough(proj_true)) {
3086 /* exchange both proj's so the second one can be omitted */
3087 const ir_node *t = proj_true;
3089 proj_true = proj_false;
3091 cc = ia32_negate_condition_code(cc);
3094 dest_true = get_cfop_target_block(proj_true);
3095 dest_false = get_cfop_target_block(proj_false);
3097 if (cc & ia32_cc_float_parity_cases) {
3098 /* Some floating point comparisons require a test of the parity flag,
3099 * which indicates that the result is unordered */
3100 if (cc & ia32_cc_negated) {
3101 bemit_jp(false, dest_true);
3103 /* we need a local label if the false proj is a fallthrough
3104 * as the falseblock might have no label emitted then */
3105 if (can_be_fallthrough(proj_false)) {
3107 bemit8(0x06); // jp + 6
3109 bemit_jp(false, dest_false);
3113 bemit_jcc(cc, dest_true);
3115 /* the second Proj might be a fallthrough */
3116 if (can_be_fallthrough(proj_false)) {
3117 /* it's a fallthrough */
3119 bemit_jmp(dest_false);
3123 static void bemit_switchjmp(const ir_node *node)
3125 ir_entity *jump_table = get_ia32_am_sc(node);
3126 const ir_switch_table *table = get_ia32_switch_table(node);
3128 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3129 bemit_mod_am(0x05, node);
3131 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3137 static void bemit_return(const ir_node *node)
3139 unsigned pop = be_Return_get_pop(node);
3140 if (pop > 0 || be_Return_get_emit_pop(node)) {
3142 assert(pop <= 0xffff);
3149 static void bemit_subsp(const ir_node *node)
3151 const arch_register_t *out;
3154 /* mov %esp, %out */
3156 out = arch_get_irn_register_out(node, 1);
3157 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3160 static void bemit_incsp(const ir_node *node)
3163 const arch_register_t *reg;
3167 offs = be_get_IncSP_offset(node);
3178 size = get_signed_imm_size(offs);
3179 bemit8(size == 1 ? 0x83 : 0x81);
3181 reg = arch_get_irn_register_out(node, 0);
3182 bemit_modru(reg, ext);
3191 static void bemit_copybi(const ir_node *node)
3193 unsigned size = get_ia32_copyb_size(node);
3195 bemit8(0xA4); // movsb
3198 bemit8(0xA5); // movsw
3202 bemit8(0xA5); // movsl
3206 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3208 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3209 unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
3210 if (get_ia32_op_type(node) == ia32_Normal) {
3211 assert(!attr->pop || attr->res_in_reg);
3213 unsigned char op0 = 0xD8;
3214 if (attr->res_in_reg) op0 |= 0x04;
3215 if (attr->pop) op0 |= 0x02;
3218 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
3223 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3224 bemit8(size == 32 ? 0xD8 : 0xDC);
3225 bemit_mod_am(op, node);
3229 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3232 bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
3235 static void bemit_fabs(const ir_node *node)
3243 static void bemit_fadd(const ir_node *node)
3245 bemit_fbinop(node, 0, 0);
3248 static void bemit_fchs(const ir_node *node)
3256 static void bemit_fdiv(const ir_node *node)
3258 bemit_fbinop(node, 6, 7);
3261 static void bemit_ffreep(ir_node const *const node)
3263 bemit_fop_reg(node, 0xDF, 0xC0);
3266 static void bemit_fild(const ir_node *node)
3268 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3270 bemit8(0xDF); // filds
3271 bemit_mod_am(0, node);
3275 bemit8(0xDB); // fildl
3276 bemit_mod_am(0, node);
3280 bemit8(0xDF); // fildll
3281 bemit_mod_am(5, node);
3285 panic("invalid mode size");
3289 static void bemit_fist(const ir_node *node)
3292 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3294 case 16: bemit8(0xDF); op = 2; break; // fist[p]s
3295 case 32: bemit8(0xDB); op = 2; break; // fist[p]l
3296 case 64: bemit8(0xDF); op = 6; break; // fistpll
3297 default: panic("invalid mode size");
3299 if (get_ia32_x87_attr_const(node)->pop)
3301 // There is only a pop variant for 64 bit integer store.
3302 assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
3303 bemit_mod_am(op, node);
3306 static void bemit_fisttp(ir_node const *const node)
3308 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3309 case 16: bemit8(0xDF); break; // fisttps
3310 case 32: bemit8(0xDB); break; // fisttpl
3311 case 64: bemit8(0xDD); break; // fisttpll
3312 default: panic("Invalid mode size");
3314 bemit_mod_am(1, node);
3317 static void bemit_fld(const ir_node *node)
3319 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3321 bemit8(0xD9); // flds
3322 bemit_mod_am(0, node);
3326 bemit8(0xDD); // fldl
3327 bemit_mod_am(0, node);
3332 bemit8(0xDB); // fldt
3333 bemit_mod_am(5, node);
3337 panic("invalid mode size");
3341 static void bemit_fld1(const ir_node *node)
3345 bemit8(0xE8); // fld1
3348 static void bemit_fldcw(const ir_node *node)
3350 bemit8(0xD9); // fldcw
3351 bemit_mod_am(5, node);
3354 static void bemit_fldz(const ir_node *node)
3358 bemit8(0xEE); // fldz
3361 static void bemit_fmul(const ir_node *node)
3363 bemit_fbinop(node, 1, 1);
3366 static void bemit_fpop(const ir_node *node)
3368 bemit_fop_reg(node, 0xDD, 0xD8);
3371 static void bemit_fpush(const ir_node *node)
3373 bemit_fop_reg(node, 0xD9, 0xC0);
3376 static void bemit_fpushcopy(const ir_node *node)
3378 bemit_fop_reg(node, 0xD9, 0xC0);
3381 static void bemit_fst(const ir_node *node)
3384 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3386 case 32: bemit8(0xD9); op = 2; break; // fst[p]s
3387 case 64: bemit8(0xDD); op = 2; break; // fst[p]l
3389 case 96: bemit8(0xDB); op = 6; break; // fstpt
3390 default: panic("invalid mode size");
3392 if (get_ia32_x87_attr_const(node)->pop)
3394 // There is only a pop variant for long double store.
3395 assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
3396 bemit_mod_am(op, node);
3399 static void bemit_fsub(const ir_node *node)
3401 bemit_fbinop(node, 4, 5);
3404 static void bemit_fnstcw(const ir_node *node)
3406 bemit8(0xD9); // fnstcw
3407 bemit_mod_am(7, node);
3410 static void bemit_fnstsw(void)
3412 bemit8(0xDF); // fnstsw %ax
3416 static void bemit_ftstfnstsw(const ir_node *node)
3420 bemit8(0xD9); // ftst
3425 static void bemit_fucomi(const ir_node *node)
3427 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3428 bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
3429 bemit8(0xE8 + attr->reg->index);
3432 static void bemit_fucomfnstsw(const ir_node *node)
3434 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3435 bemit8(0xDD); // fucom[p]
3436 bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
3440 static void bemit_fucomppfnstsw(const ir_node *node)
3444 bemit8(0xDA); // fucompp
3449 static void bemit_fxch(const ir_node *node)
3451 bemit_fop_reg(node, 0xD9, 0xC8);
3455 * The type of a emitter function.
3457 typedef void (*emit_func) (const ir_node *);
3460 * Set a node emitter. Make it a bit more type safe.
3462 static void register_emitter(ir_op *op, emit_func func)
3464 op->ops.generic = (op_func) func;
3467 static void ia32_register_binary_emitters(void)
3469 /* first clear the generic function pointer for all ops */
3470 ir_clear_opcodes_generic_func();
3472 /* benode emitter */
3473 register_emitter(op_be_Copy, bemit_copy);
3474 register_emitter(op_be_CopyKeep, bemit_copy);
3475 register_emitter(op_be_IncSP, bemit_incsp);
3476 register_emitter(op_be_Perm, bemit_perm);
3477 register_emitter(op_be_Return, bemit_return);
3478 register_emitter(op_ia32_Adc, bemit_adc);
3479 register_emitter(op_ia32_Add, bemit_add);
3480 register_emitter(op_ia32_AddMem, bemit_addmem);
3481 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3482 register_emitter(op_ia32_And, bemit_and);
3483 register_emitter(op_ia32_AndMem, bemit_andmem);
3484 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3485 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3486 register_emitter(op_ia32_Breakpoint, bemit_int3);
3487 register_emitter(op_ia32_Bsf, bemit_bsf);
3488 register_emitter(op_ia32_Bsr, bemit_bsr);
3489 register_emitter(op_ia32_Bswap, bemit_bswap);
3490 register_emitter(op_ia32_Bt, bemit_bt);
3491 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3492 register_emitter(op_ia32_Call, bemit_call);
3493 register_emitter(op_ia32_Cltd, bemit_cltd);
3494 register_emitter(op_ia32_Cmc, bemit_cmc);
3495 register_emitter(op_ia32_Cmp, bemit_cmp);
3496 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3497 register_emitter(op_ia32_Const, bemit_mov_const);
3498 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3499 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3500 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3501 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3502 register_emitter(op_ia32_Dec, bemit_dec);
3503 register_emitter(op_ia32_DecMem, bemit_decmem);
3504 register_emitter(op_ia32_Div, bemit_div);
3505 register_emitter(op_ia32_FldCW, bemit_fldcw);
3506 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3507 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3508 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3509 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3510 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3511 register_emitter(op_ia32_IDiv, bemit_idiv);
3512 register_emitter(op_ia32_IJmp, bemit_ijmp);
3513 register_emitter(op_ia32_IMul, bemit_imul);
3514 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3515 register_emitter(op_ia32_Inc, bemit_inc);
3516 register_emitter(op_ia32_IncMem, bemit_incmem);
3517 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3518 register_emitter(op_ia32_Jmp, bemit_jump);
3519 register_emitter(op_ia32_LdTls, bemit_ldtls);
3520 register_emitter(op_ia32_Lea, bemit_lea);
3521 register_emitter(op_ia32_Leave, bemit_leave);
3522 register_emitter(op_ia32_Load, bemit_load);
3523 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3524 register_emitter(op_ia32_Mul, bemit_mul);
3525 register_emitter(op_ia32_Neg, bemit_neg);
3526 register_emitter(op_ia32_NegMem, bemit_negmem);
3527 register_emitter(op_ia32_Not, bemit_not);
3528 register_emitter(op_ia32_NotMem, bemit_notmem);
3529 register_emitter(op_ia32_Or, bemit_or);
3530 register_emitter(op_ia32_OrMem, bemit_ormem);
3531 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3532 register_emitter(op_ia32_Pop, bemit_pop);
3533 register_emitter(op_ia32_PopEbp, bemit_pop);
3534 register_emitter(op_ia32_PopMem, bemit_popmem);
3535 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3536 register_emitter(op_ia32_Push, bemit_push);
3537 register_emitter(op_ia32_RepPrefix, bemit_rep);
3538 register_emitter(op_ia32_Rol, bemit_rol);
3539 register_emitter(op_ia32_RolMem, bemit_rolmem);
3540 register_emitter(op_ia32_Ror, bemit_ror);
3541 register_emitter(op_ia32_RorMem, bemit_rormem);
3542 register_emitter(op_ia32_Sahf, bemit_sahf);
3543 register_emitter(op_ia32_Sar, bemit_sar);
3544 register_emitter(op_ia32_SarMem, bemit_sarmem);
3545 register_emitter(op_ia32_Sbb, bemit_sbb);
3546 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3547 register_emitter(op_ia32_Setcc, bemit_setcc);
3548 register_emitter(op_ia32_Shl, bemit_shl);
3549 register_emitter(op_ia32_ShlD, bemit_shld);
3550 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3551 register_emitter(op_ia32_Shr, bemit_shr);
3552 register_emitter(op_ia32_ShrD, bemit_shrd);
3553 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3554 register_emitter(op_ia32_Stc, bemit_stc);
3555 register_emitter(op_ia32_Store, bemit_store);
3556 register_emitter(op_ia32_Store8Bit, bemit_store);
3557 register_emitter(op_ia32_Sub, bemit_sub);
3558 register_emitter(op_ia32_SubMem, bemit_submem);
3559 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3560 register_emitter(op_ia32_SubSP, bemit_subsp);
3561 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3562 register_emitter(op_ia32_Test, bemit_test);
3563 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3564 register_emitter(op_ia32_Xor, bemit_xor);
3565 register_emitter(op_ia32_Xor0, bemit_xor0);
3566 register_emitter(op_ia32_XorMem, bemit_xormem);
3567 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3568 register_emitter(op_ia32_fabs, bemit_fabs);
3569 register_emitter(op_ia32_fadd, bemit_fadd);
3570 register_emitter(op_ia32_fchs, bemit_fchs);
3571 register_emitter(op_ia32_fdiv, bemit_fdiv);
3572 register_emitter(op_ia32_ffreep, bemit_ffreep);
3573 register_emitter(op_ia32_fild, bemit_fild);
3574 register_emitter(op_ia32_fist, bemit_fist);
3575 register_emitter(op_ia32_fisttp, bemit_fisttp);
3576 register_emitter(op_ia32_fld, bemit_fld);
3577 register_emitter(op_ia32_fld1, bemit_fld1);
3578 register_emitter(op_ia32_fldz, bemit_fldz);
3579 register_emitter(op_ia32_fmul, bemit_fmul);
3580 register_emitter(op_ia32_fpop, bemit_fpop);
3581 register_emitter(op_ia32_fpush, bemit_fpush);
3582 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3583 register_emitter(op_ia32_fst, bemit_fst);
3584 register_emitter(op_ia32_fsub, bemit_fsub);
3585 register_emitter(op_ia32_fxch, bemit_fxch);
3587 /* ignore the following nodes */
3588 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3589 register_emitter(op_ia32_Unknown, emit_Nothing);
3590 register_emitter(op_be_Keep, emit_Nothing);
3591 register_emitter(op_be_Start, emit_Nothing);
3592 register_emitter(op_Phi, emit_Nothing);
3593 register_emitter(op_Start, emit_Nothing);
3596 static void gen_binary_block(ir_node *block)
3598 ia32_emit_block_header(block);
3600 /* emit the contents of the block */
3601 sched_foreach(block, node) {
3602 ia32_emit_node(node);
3606 void ia32_gen_binary_routine(ir_graph *irg)
3608 ir_entity *entity = get_irg_entity(irg);
3609 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3610 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3611 ir_node **blk_sched = irg_data->blk_sched;
3613 parameter_dbg_info_t *infos;
3615 isa = (ia32_isa_t*) arch_env;
3617 ia32_register_binary_emitters();
3619 infos = construct_parameter_infos(irg);
3620 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3624 /* we use links to point to target blocks */
3625 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3626 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3628 /* initialize next block links */
3629 n = ARR_LEN(blk_sched);
3630 for (i = 0; i < n; ++i) {
3631 ir_node *block = blk_sched[i];
3632 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3634 set_irn_link(block, prev);
3637 for (i = 0; i < n; ++i) {
3638 ir_node *block = blk_sched[i];
3639 gen_binary_block(block);
3642 be_gas_emit_function_epilog(entity);
3644 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3648 void ia32_init_emitter(void)
3650 lc_opt_entry_t *be_grp;
3651 lc_opt_entry_t *ia32_grp;
3653 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3654 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3656 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3660 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");