2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 /* in case of a joker register: just return a valid register */
90 if (arch_register_type_is(reg, joker)) {
91 const arch_register_req_t *req;
93 /* ask for the requirements */
94 req = arch_get_register_req(arch_env, irn, pos);
96 if (arch_register_req_is(req, limited)) {
97 /* in case of limited requirements: get the first allowed register */
98 unsigned idx = rbitset_next(req->limited, 0, 1);
99 reg = arch_register_for_index(req->cls, idx);
101 /* otherwise get first register in class */
102 reg = arch_register_for_index(req->cls, 0);
110 * Returns the register at out position pos.
113 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
116 const arch_env_t *arch_env = env->arch_env;
118 const arch_register_t *reg = NULL;
120 /* 1st case: irn is not of mode_T, so it has only */
121 /* one OUT register -> good */
122 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
123 /* Proj with the corresponding projnum for the register */
125 if (get_irn_mode(irn) != mode_T) {
126 reg = arch_get_irn_register(arch_env, irn);
127 } else if (is_ia32_irn(irn)) {
128 reg = get_ia32_out_reg(irn, pos);
130 const ir_edge_t *edge;
132 foreach_out_edge(irn, edge) {
133 proj = get_edge_src_irn(edge);
134 assert(is_Proj(proj) && "non-Proj from mode_T node");
135 if (get_Proj_proj(proj) == pos) {
136 reg = arch_get_irn_register(arch_env, proj);
142 assert(reg && "no out register found");
147 * Determine the gnu assembler suffix that indicates a mode
150 char get_mode_suffix(const ir_mode *mode) {
151 if(mode_is_float(mode)) {
152 switch(get_mode_size_bits(mode)) {
162 assert(mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode));
163 switch(get_mode_size_bits(mode)) {
174 panic("Can't output mode_suffix for %+F\n", mode);
178 int produces_result(const ir_node *node) {
179 return !(is_ia32_St(node) ||
180 is_ia32_CondJmp(node) ||
181 is_ia32_xCondJmp(node) ||
182 is_ia32_CmpSet(node) ||
183 is_ia32_xCmpSet(node) ||
184 is_ia32_SwitchJmp(node));
188 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
189 const arch_register_t *reg) {
190 switch(get_mode_size_bits(mode)) {
192 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
194 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
196 return (char *)arch_register_get_name(reg);
201 * Add a number to a prefix. This number will not be used a second time.
204 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
205 static unsigned long id = 0;
206 snprintf(buf, buflen, "%s%lu", prefix, ++id);
210 /*************************************************************
212 * (_) | | / _| | | | |
213 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
214 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
215 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
216 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
219 *************************************************************/
221 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
222 // be_emit_env_t* so we cheat a bit...
223 #define be_emit_char(env,c) be_emit_char(env->emit,c)
224 #define be_emit_string(env,s) be_emit_string(env->emit,s)
225 #undef be_emit_cstring
226 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
227 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
228 #define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
229 #define be_emit_write_line(env) be_emit_write_line(env->emit)
230 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
231 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
233 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
235 const arch_register_t *reg = get_in_reg(env, node, pos);
236 const char *reg_name = arch_register_get_name(reg);
238 assert(pos < get_irn_arity(node));
240 be_emit_char(env, '%');
241 be_emit_string(env, reg_name);
244 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
245 const arch_register_t *reg = get_out_reg(env, node, pos);
246 const char *reg_name = arch_register_get_name(reg);
248 be_emit_char(env, '%');
249 be_emit_string(env, reg_name);
252 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
254 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
257 be_emit_char(env, '%');
258 be_emit_string(env, attr->x87[pos]->name);
261 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
267 be_emit_char(env, '$');
269 switch(get_ia32_immop_type(node)) {
271 tv = get_ia32_Immop_tarval(node);
272 be_emit_tarval(env, tv);
274 case ia32_ImmSymConst:
275 ent = get_ia32_Immop_symconst(node);
276 set_entity_backend_marked(ent, 1);
277 id = get_entity_ld_ident(ent);
278 be_emit_ident(env, id);
285 be_emit_string(env, "BAD");
290 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
292 be_emit_char(env, get_mode_suffix(mode));
295 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
297 ir_mode *mode = get_ia32_ls_mode(node);
301 ia32_emit_mode_suffix_mode(env, mode);
304 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
306 ir_mode *mode = get_ia32_ls_mode(node);
308 ia32_emit_mode_suffix_mode(env, mode);
312 char get_xmm_mode_suffix(ir_mode *mode)
314 assert(mode_is_float(mode));
315 switch(get_mode_size_bits(mode)) {
326 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
328 ir_mode *mode = get_ia32_ls_mode(node);
329 assert(mode != NULL);
330 be_emit_char(env, 's');
331 be_emit_char(env, get_xmm_mode_suffix(mode));
334 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
336 ir_mode *mode = get_ia32_ls_mode(node);
337 assert(mode != NULL);
338 be_emit_char(env, get_xmm_mode_suffix(mode));
341 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
343 if(get_mode_size_bits(mode) == 32)
345 if(mode_is_signed(mode)) {
346 be_emit_char(env, 's');
348 be_emit_char(env, 'z');
353 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
355 switch (be_gas_flavour) {
356 case GAS_FLAVOUR_NORMAL:
357 be_emit_cstring(env, "\t.type\t");
358 be_emit_string(env, name);
359 be_emit_cstring(env, ", @function\n");
360 be_emit_write_line(env);
362 case GAS_FLAVOUR_MINGW:
363 be_emit_cstring(env, "\t.def\t");
364 be_emit_string(env, name);
365 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
366 be_emit_write_line(env);
374 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
376 switch (be_gas_flavour) {
377 case GAS_FLAVOUR_NORMAL:
378 be_emit_cstring(env, "\t.size\t");
379 be_emit_string(env, name);
380 be_emit_cstring(env, ", .-");
381 be_emit_string(env, name);
382 be_emit_char(env, '\n');
383 be_emit_write_line(env);
392 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node);
395 * Emits registers and/or address mode of a binary operation.
397 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
399 const ir_node *right_op;
401 switch(get_ia32_op_type(node)) {
403 right_op = get_irn_n(node, 3);
404 if(is_ia32_Immediate(right_op)) {
405 emit_ia32_Immediate(env, right_op);
406 be_emit_cstring(env, ", ");
407 ia32_emit_source_register(env, node, 2);
409 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
410 ia32_emit_immediate(env, node);
411 be_emit_cstring(env, ", ");
412 ia32_emit_source_register(env, node, 2);
414 const arch_register_t *in1 = get_in_reg(env, node, 2);
415 const arch_register_t *in2 = get_in_reg(env, node, 3);
416 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
417 const arch_register_t *in;
420 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
421 out = out ? out : in1;
422 in_name = arch_register_get_name(in);
424 if (is_ia32_emit_cl(node)) {
425 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
429 be_emit_char(env, '%');
430 be_emit_string(env, in_name);
431 be_emit_cstring(env, ", %");
432 be_emit_string(env, arch_register_get_name(out));
436 ia32_emit_am(env, node);
437 be_emit_cstring(env, ", ");
438 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
439 assert(!produces_result(node) && "Source AM with Const must not produce result");
440 ia32_emit_immediate(env, node);
441 } else if (produces_result(node)) {
442 ia32_emit_dest_register(env, node, 0);
444 ia32_emit_source_register(env, node, 2);
448 right_pos = get_irn_arity(node) == 5 ? 3 : 2;
449 right_op = get_irn_n(node, right_pos);
450 if(is_ia32_Immediate(right_op)) {
451 emit_ia32_Immediate(env, right_op);
452 be_emit_cstring(env, ", ");
453 ia32_emit_am(env, node);
455 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
456 ia32_emit_immediate(env, node);
457 be_emit_cstring(env, ", ");
458 ia32_emit_am(env, node);
460 const arch_register_t *in1 = get_in_reg(env, node, right_pos);
461 ir_mode *mode = get_ia32_ls_mode(node);
464 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
466 if (is_ia32_emit_cl(node)) {
467 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
471 be_emit_char(env, '%');
472 be_emit_string(env, in_name);
473 be_emit_cstring(env, ", ");
474 ia32_emit_am(env, node);
478 assert(0 && "unsupported op type");
483 * Emits registers and/or address mode of a binary operation.
485 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
486 switch(get_ia32_op_type(node)) {
488 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
489 // should not happen...
492 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
493 const arch_register_t *in1 = x87_attr->x87[0];
494 const arch_register_t *in2 = x87_attr->x87[1];
495 const arch_register_t *out = x87_attr->x87[2];
496 const arch_register_t *in;
498 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
499 out = out ? out : in1;
501 be_emit_char(env, '%');
502 be_emit_string(env, arch_register_get_name(in));
503 be_emit_cstring(env, ", %");
504 be_emit_string(env, arch_register_get_name(out));
509 ia32_emit_am(env, node);
512 assert(0 && "unsupported op type");
516 void ia32_emit_am_or_dest_register(ia32_emit_env_t *env, const ir_node *node,
518 if(get_ia32_op_type(node) == ia32_Normal) {
519 ia32_emit_dest_register(env, node, pos);
521 assert(get_ia32_op_type(node) == ia32_AddrModeD);
522 ia32_emit_am(env, node);
527 * Emits registers and/or address mode of a unary operation.
529 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node, int pos) {
532 switch(get_ia32_op_type(node)) {
534 op = get_irn_n(node, pos);
535 if (is_ia32_Immediate(op)) {
536 emit_ia32_Immediate(env, op);
537 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
538 ia32_emit_immediate(env, node);
540 ia32_emit_source_register(env, node, pos);
545 ia32_emit_am(env, node);
548 assert(0 && "unsupported op type");
553 * Emits address mode.
555 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
556 ir_entity *ent = get_ia32_am_sc(node);
557 int offs = get_ia32_am_offs_int(node);
558 ir_node *base = get_irn_n(node, 0);
559 int has_base = !is_ia32_NoReg_GP(base);
560 ir_node *index = get_irn_n(node, 1);
561 int has_index = !is_ia32_NoReg_GP(index);
563 /* just to be sure... */
564 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
570 set_entity_backend_marked(ent, 1);
571 id = get_entity_ld_ident(ent);
572 if (is_ia32_am_sc_sign(node))
573 be_emit_char(env, '-');
574 be_emit_ident(env, id);
576 if(get_entity_owner(ent) == get_tls_type()) {
577 if (get_entity_visibility(ent) == visibility_external_allocated) {
578 be_emit_cstring(env, "@INDNTPOFF");
580 be_emit_cstring(env, "@NTPOFF");
587 be_emit_irprintf(env->emit, "%+d", offs);
589 be_emit_irprintf(env->emit, "%d", offs);
593 if (has_base || has_index) {
594 be_emit_char(env, '(');
598 ia32_emit_source_register(env, node, 0);
601 /* emit index + scale */
604 be_emit_char(env, ',');
605 ia32_emit_source_register(env, node, 1);
607 scale = get_ia32_am_scale(node);
609 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
612 be_emit_char(env, ')');
616 /*************************************************
619 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
620 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
621 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
622 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
624 *************************************************/
627 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
630 * coding of conditions
632 struct cmp2conditon_t {
638 * positive conditions for signed compares
641 const struct cmp2conditon_t cmp2condition_s[] = {
642 { NULL, pn_Cmp_False }, /* always false */
643 { "e", pn_Cmp_Eq }, /* == */
644 { "l", pn_Cmp_Lt }, /* < */
645 { "le", pn_Cmp_Le }, /* <= */
646 { "g", pn_Cmp_Gt }, /* > */
647 { "ge", pn_Cmp_Ge }, /* >= */
648 { "ne", pn_Cmp_Lg }, /* != */
649 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
650 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
651 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
652 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
653 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
654 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
655 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
656 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
657 { NULL, pn_Cmp_True }, /* always true */
661 * positive conditions for unsigned compares
664 const struct cmp2conditon_t cmp2condition_u[] = {
665 { NULL, pn_Cmp_False }, /* always false */
666 { "e", pn_Cmp_Eq }, /* == */
667 { "b", pn_Cmp_Lt }, /* < */
668 { "be", pn_Cmp_Le }, /* <= */
669 { "a", pn_Cmp_Gt }, /* > */
670 { "ae", pn_Cmp_Ge }, /* >= */
671 { "ne", pn_Cmp_Lg }, /* != */
672 { NULL, pn_Cmp_True }, /* always true */
676 * returns the condition code
679 const char *get_cmp_suffix(pn_Cmp cmp_code)
681 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
682 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
684 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
685 return cmp2condition_u[cmp_code & 7].name;
687 return cmp2condition_s[cmp_code & 15].name;
691 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
693 be_emit_string(env, get_cmp_suffix(pnc));
698 * Returns the target block for a control flow node.
701 ir_node *get_cfop_target_block(const ir_node *irn) {
702 return get_irn_link(irn);
706 * Emits a block label for the given block.
709 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
711 be_emit_cstring(env, BLOCK_PREFIX);
712 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
716 * Emits the target label for a control flow node.
719 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
720 ir_node *block = get_cfop_target_block(node);
722 ia32_emit_block_name(env, block);
725 /** Return the next block in Block schedule */
726 static ir_node *next_blk_sched(const ir_node *block) {
727 return get_irn_link(block);
731 * Returns the Proj with projection number proj and NOT mode_M
734 ir_node *get_proj(const ir_node *node, long proj) {
735 const ir_edge_t *edge;
738 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
740 foreach_out_edge(node, edge) {
741 src = get_edge_src_irn(edge);
743 assert(is_Proj(src) && "Proj expected");
744 if (get_irn_mode(src) == mode_M)
747 if (get_Proj_proj(src) == proj)
754 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
757 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
759 const ir_node *proj_true;
760 const ir_node *proj_false;
761 const ir_node *block;
762 const ir_node *next_block;
765 /* get both Proj's */
766 proj_true = get_proj(node, pn_Cond_true);
767 assert(proj_true && "CondJmp without true Proj");
769 proj_false = get_proj(node, pn_Cond_false);
770 assert(proj_false && "CondJmp without false Proj");
772 /* for now, the code works for scheduled and non-schedules blocks */
773 block = get_nodes_block(node);
775 /* we have a block schedule */
776 next_block = next_blk_sched(block);
778 if (get_cfop_target_block(proj_true) == next_block) {
779 /* exchange both proj's so the second one can be omitted */
780 const ir_node *t = proj_true;
782 proj_true = proj_false;
785 pnc = get_negated_pnc(pnc, mode);
788 /* in case of unordered compare, check for parity */
789 if (pnc & pn_Cmp_Uo) {
790 be_emit_cstring(env, "\tjp ");
791 ia32_emit_cfop_target(env, proj_true);
792 be_emit_finish_line_gas(env, proj_true);
795 be_emit_cstring(env, "\tj");
796 ia32_emit_cmp_suffix(env, pnc);
797 be_emit_char(env, ' ');
798 ia32_emit_cfop_target(env, proj_true);
799 be_emit_finish_line_gas(env, proj_true);
801 /* the second Proj might be a fallthrough */
802 if (get_cfop_target_block(proj_false) != next_block) {
803 be_emit_cstring(env, "\tjmp ");
804 ia32_emit_cfop_target(env, proj_false);
805 be_emit_finish_line_gas(env, proj_false);
807 be_emit_cstring(env, "\t/* fallthrough to ");
808 ia32_emit_cfop_target(env, proj_false);
809 be_emit_cstring(env, " */");
810 be_emit_finish_line_gas(env, proj_false);
815 * Emits code for conditional jump.
818 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
819 be_emit_cstring(env, "\tcmp ");
820 ia32_emit_binop(env, node);
821 be_emit_finish_line_gas(env, node);
823 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
827 * Emits code for conditional jump with two variables.
830 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
831 CondJmp_emitter(env, node);
835 * Emits code for conditional test and jump.
838 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
839 be_emit_cstring(env, "\ttest ");
840 ia32_emit_binop(env, node);
841 be_emit_finish_line_gas(env, node);
843 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
847 * Emits code for conditional test and jump with two variables.
850 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
851 TestJmp_emitter(env, node);
855 void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
856 be_emit_cstring(env, "/* omitted redundant test */");
857 be_emit_finish_line_gas(env, node);
859 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
863 void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
864 be_emit_cstring(env, "/* omitted redundant test/cmp */");
865 be_emit_finish_line_gas(env, node);
867 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
871 * Emits code for conditional SSE floating point jump with two variables.
874 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
875 be_emit_cstring(env, "\tucomi");
876 ia32_emit_xmm_mode_suffix(env, node);
877 be_emit_char(env, ' ');
878 ia32_emit_binop(env, node);
879 be_emit_finish_line_gas(env, node);
881 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
885 * Emits code for conditional x87 floating point jump with two variables.
888 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
889 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
890 const char *reg = x87_attr->x87[1]->name;
891 long pnc = get_ia32_pncode(node);
893 switch (get_ia32_irn_opcode(node)) {
894 case iro_ia32_fcomrJmp:
895 pnc = get_inversed_pnc(pnc);
896 reg = x87_attr->x87[0]->name;
897 case iro_ia32_fcomJmp:
899 be_emit_cstring(env, "\tfucom ");
901 case iro_ia32_fcomrpJmp:
902 pnc = get_inversed_pnc(pnc);
903 reg = x87_attr->x87[0]->name;
904 case iro_ia32_fcompJmp:
905 be_emit_cstring(env, "\tfucomp ");
907 case iro_ia32_fcomrppJmp:
908 pnc = get_inversed_pnc(pnc);
909 case iro_ia32_fcomppJmp:
910 be_emit_cstring(env, "\tfucompp ");
916 be_emit_char(env, '%');
917 be_emit_string(env, reg);
919 be_emit_finish_line_gas(env, node);
921 be_emit_cstring(env, "\tfnstsw %ax");
922 be_emit_finish_line_gas(env, node);
923 be_emit_cstring(env, "\tsahf");
924 be_emit_finish_line_gas(env, node);
926 finish_CondJmp(env, node, mode_E, pnc);
930 void emit_register_or_immediate(ia32_emit_env_t *env, const ir_node *node,
933 ir_node *op = get_irn_n(node, pos);
934 if(is_ia32_Immediate(op)) {
935 emit_ia32_Immediate(env, op);
937 ia32_emit_source_register(env, node, pos);
942 int is_ia32_Immediate_0(const ir_node *node)
944 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
946 return attr->offset == 0 && attr->symconst == NULL;
950 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
952 long pnc = get_ia32_pncode(node);
953 const arch_register_t *in1, *in2, *out;
955 out = arch_get_irn_register(env->arch_env, node);
956 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 2));
957 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 3));
959 /* we have to emit the cmp first, because the destination register */
960 /* could be one of the compare registers */
961 if (is_ia32_CmpCMov(node)) {
962 long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
963 ir_node *cmp_right = get_irn_n(node, 1);
965 if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
966 && is_ia32_Immediate(cmp_right)
967 && is_ia32_Immediate_0(cmp_right)) {
968 be_emit_cstring(env, "\ttest ");
969 ia32_emit_source_register(env, node, 0);
970 be_emit_cstring(env, ", ");
971 ia32_emit_source_register(env, node, 0);
973 be_emit_cstring(env, "\tcmp ");
974 emit_register_or_immediate(env, node, 1);
975 be_emit_cstring(env, ", ");
976 ia32_emit_source_register(env, node, 0);
978 } else if (is_ia32_xCmpCMov(node)) {
979 be_emit_cstring(env, "\tucomis");
980 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
981 be_emit_char(env, ' ');
982 ia32_emit_source_register(env, node, 1);
983 be_emit_cstring(env, ", ");
984 ia32_emit_source_register(env, node, 0);
986 assert(0 && "unsupported CMov");
988 be_emit_finish_line_gas(env, node);
990 if (REGS_ARE_EQUAL(out, in2)) {
991 /* best case: default in == out -> do nothing */
992 } else if (REGS_ARE_EQUAL(out, in1)) {
993 ir_node *n = (ir_node*) node;
994 /* true in == out -> need complement compare and exchange true and default in */
995 ir_node *t = get_irn_n(n, 2);
996 set_irn_n(n, 2, get_irn_n(n, 3));
999 pnc = get_negated_pnc(pnc, get_irn_mode(node));
1001 /* out is different from in: need copy default -> out */
1002 be_emit_cstring(env, "\tmovl ");
1003 ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_false);
1004 be_emit_cstring(env, ", ");
1005 ia32_emit_dest_register(env, node, 0);
1006 be_emit_finish_line_gas(env, node);
1009 be_emit_cstring(env, "\tcmov");
1010 ia32_emit_cmp_suffix(env, pnc);
1011 be_emit_cstring(env, "l ");
1012 ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_true);
1013 be_emit_cstring(env, ", ");
1014 ia32_emit_dest_register(env, node, 0);
1015 be_emit_finish_line_gas(env, node);
1019 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
1021 CMov_emitter(env, node);
1025 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
1027 CMov_emitter(env, node);
1031 void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
1033 long pnc = get_ia32_pncode(node);
1034 const char *reg8bit;
1035 const arch_register_t *out;
1037 out = arch_get_irn_register(env->arch_env, node);
1038 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1040 if (is_ia32_CmpSet(node)) {
1041 long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
1042 ir_node *cmp_right = get_irn_n(node, n_ia32_CmpSet_cmp_right);
1044 if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
1045 && is_ia32_Immediate(cmp_right)
1046 && is_ia32_Immediate_0(cmp_right)) {
1047 be_emit_cstring(env, "\ttest ");
1048 ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
1049 be_emit_cstring(env, ", ");
1050 ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
1052 be_emit_cstring(env, "\tcmp ");
1053 ia32_emit_binop(env, node);
1055 } else if (is_ia32_xCmpSet(node)) {
1056 be_emit_cstring(env, "\tucomis");
1057 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1058 be_emit_char(env, ' ');
1059 ia32_emit_binop(env, node);
1061 assert(0 && "unsupported Set");
1063 be_emit_finish_line_gas(env, node);
1065 /* use mov to clear target because it doesn't affect the eflags */
1066 be_emit_cstring(env, "\tmovl $0, %");
1067 be_emit_string(env, arch_register_get_name(out));
1068 be_emit_finish_line_gas(env, node);
1070 be_emit_cstring(env, "\tset");
1071 ia32_emit_cmp_suffix(env, pnc);
1072 be_emit_cstring(env, " %");
1073 be_emit_string(env, reg8bit);
1074 be_emit_finish_line_gas(env, node);
1078 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1079 Set_emitter(env, node);
1083 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1084 Set_emitter(env, node);
1088 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1090 long pnc = get_ia32_pncode(node);
1091 long unord = pnc & pn_Cmp_Uo;
1093 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1096 case pn_Cmp_Leg: /* odered */
1099 case pn_Cmp_Uo: /* unordered */
1103 case pn_Cmp_Eq: /* == */
1107 case pn_Cmp_Lt: /* < */
1111 case pn_Cmp_Le: /* <= */
1115 case pn_Cmp_Gt: /* > */
1119 case pn_Cmp_Ge: /* >= */
1123 case pn_Cmp_Lg: /* != */
1128 assert(sse_pnc >= 0 && "unsupported compare");
1130 if (unord && sse_pnc != 3) {
1132 We need a separate compare against unordered.
1133 Quick and Dirty solution:
1134 - get some memory on stack
1138 - and result and stored result
1141 be_emit_cstring(env, "\tsubl $8, %esp");
1142 be_emit_finish_line_gas(env, node);
1144 be_emit_cstring(env, "\tcmpsd $3, ");
1145 ia32_emit_binop(env, node);
1146 be_emit_finish_line_gas(env, node);
1148 be_emit_cstring(env, "\tmovsd ");
1149 ia32_emit_dest_register(env, node, 0);
1150 be_emit_cstring(env, ", (%esp)");
1151 be_emit_finish_line_gas(env, node);
1154 be_emit_cstring(env, "\tcmpsd ");
1155 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1156 ia32_emit_binop(env, node);
1157 be_emit_finish_line_gas(env, node);
1159 if (unord && sse_pnc != 3) {
1160 be_emit_cstring(env, "\tandpd (%esp), ");
1161 ia32_emit_dest_register(env, node, 0);
1162 be_emit_finish_line_gas(env, node);
1164 be_emit_cstring(env, "\taddl $8, %esp");
1165 be_emit_finish_line_gas(env, node);
1169 /*********************************************************
1172 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1173 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1174 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1175 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1178 *********************************************************/
1180 /* jump table entry (target and corresponding number) */
1181 typedef struct _branch_t {
1186 /* jump table for switch generation */
1187 typedef struct _jmp_tbl_t {
1188 ir_node *defProj; /**< default target */
1189 long min_value; /**< smallest switch case */
1190 long max_value; /**< largest switch case */
1191 long num_branches; /**< number of jumps */
1192 char *label; /**< label of the jump table */
1193 branch_t *branches; /**< jump array */
1197 * Compare two variables of type branch_t. Used to sort all switch cases
1200 int ia32_cmp_branch_t(const void *a, const void *b) {
1201 branch_t *b1 = (branch_t *)a;
1202 branch_t *b2 = (branch_t *)b;
1204 if (b1->value <= b2->value)
1211 * Emits code for a SwitchJmp (creates a jump table if
1212 * possible otherwise a cmp-jmp cascade). Port from
1216 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1217 unsigned long interval;
1222 const ir_edge_t *edge;
1224 /* fill the table structure */
1225 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1226 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1228 tbl.num_branches = get_irn_n_edges(node);
1229 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1230 tbl.min_value = INT_MAX;
1231 tbl.max_value = INT_MIN;
1234 /* go over all proj's and collect them */
1235 foreach_out_edge(node, edge) {
1236 proj = get_edge_src_irn(edge);
1237 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1239 pnc = get_Proj_proj(proj);
1241 /* create branch entry */
1242 tbl.branches[i].target = proj;
1243 tbl.branches[i].value = pnc;
1245 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1246 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1248 /* check for default proj */
1249 if (pnc == get_ia32_pncode(node)) {
1250 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1257 /* sort the branches by their number */
1258 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1260 /* two-complement's magic make this work without overflow */
1261 interval = tbl.max_value - tbl.min_value;
1263 /* emit the table */
1264 be_emit_cstring(env, "\tcmpl $");
1265 be_emit_irprintf(env->emit, "%u, ", interval);
1266 ia32_emit_source_register(env, node, 0);
1267 be_emit_finish_line_gas(env, node);
1269 be_emit_cstring(env, "\tja ");
1270 ia32_emit_cfop_target(env, tbl.defProj);
1271 be_emit_finish_line_gas(env, node);
1273 if (tbl.num_branches > 1) {
1275 be_emit_cstring(env, "\tjmp *");
1276 be_emit_string(env, tbl.label);
1277 be_emit_cstring(env, "(,");
1278 ia32_emit_source_register(env, node, 0);
1279 be_emit_cstring(env, ",4)");
1280 be_emit_finish_line_gas(env, node);
1282 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1283 be_emit_cstring(env, "\t.align 4\n");
1284 be_emit_write_line(env);
1286 be_emit_string(env, tbl.label);
1287 be_emit_cstring(env, ":\n");
1288 be_emit_write_line(env);
1290 be_emit_cstring(env, ".long ");
1291 ia32_emit_cfop_target(env, tbl.branches[0].target);
1292 be_emit_finish_line_gas(env, NULL);
1294 last_value = tbl.branches[0].value;
1295 for (i = 1; i < tbl.num_branches; ++i) {
1296 while (++last_value < tbl.branches[i].value) {
1297 be_emit_cstring(env, ".long ");
1298 ia32_emit_cfop_target(env, tbl.defProj);
1299 be_emit_finish_line_gas(env, NULL);
1301 be_emit_cstring(env, ".long ");
1302 ia32_emit_cfop_target(env, tbl.branches[i].target);
1303 be_emit_finish_line_gas(env, NULL);
1305 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1307 /* one jump is enough */
1308 be_emit_cstring(env, "\tjmp ");
1309 ia32_emit_cfop_target(env, tbl.branches[0].target);
1310 be_emit_finish_line_gas(env, node);
1320 * Emits code for a unconditional jump.
1323 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1324 ir_node *block, *next_block;
1326 /* for now, the code works for scheduled and non-schedules blocks */
1327 block = get_nodes_block(node);
1329 /* we have a block schedule */
1330 next_block = next_blk_sched(block);
1331 if (get_cfop_target_block(node) != next_block) {
1332 be_emit_cstring(env, "\tjmp ");
1333 ia32_emit_cfop_target(env, node);
1335 be_emit_cstring(env, "\t/* fallthrough to ");
1336 ia32_emit_cfop_target(env, node);
1337 be_emit_cstring(env, " */");
1339 be_emit_finish_line_gas(env, node);
1343 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
1345 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1347 be_emit_char(env, '$');
1348 if(attr->symconst != NULL) {
1349 ident *id = get_entity_ld_ident(attr->symconst);
1351 if(attr->attr.data.am_sc_sign)
1352 be_emit_char(env, '-');
1353 be_emit_ident(env, id);
1355 if(attr->symconst == NULL || attr->offset != 0) {
1356 if(attr->symconst != NULL)
1357 be_emit_char(env, '+');
1358 be_emit_irprintf(env->emit, "%d", attr->offset);
1363 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1366 const arch_register_t *reg;
1367 const char *reg_name;
1371 const ia32_attr_t *attr;
1378 /* parse modifiers */
1381 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1382 be_emit_char(env, '%');
1385 be_emit_char(env, '%');
1405 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1406 "'%c' for asm op\n", node, c);
1412 sscanf(s, "%d%n", &num, &p);
1414 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1422 attr = get_ia32_attr_const(node);
1423 n_outs = ARR_LEN(attr->slots);
1425 reg = get_out_reg(env, node, num);
1428 int in = num - n_outs;
1429 if(in >= get_irn_arity(node)) {
1430 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1431 "op (%+F)\n", num, node);
1434 pred = get_irn_n(node, in);
1435 /* might be an immediate value */
1436 if(is_ia32_Immediate(pred)) {
1437 emit_ia32_Immediate(env, pred);
1440 reg = get_in_reg(env, node, in);
1443 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1444 "(%+F)\n", num, node);
1449 be_emit_char(env, '%');
1452 reg_name = arch_register_get_name(reg);
1455 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1458 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
1461 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1464 panic("Invalid asm op modifier");
1466 be_emit_string(env, reg_name);
1472 * Emits code for an ASM pseudo op.
1475 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1477 const void *gen_attr = get_irn_generic_attr_const(node);
1478 const ia32_asm_attr_t *attr
1479 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1480 ident *asm_text = attr->asm_text;
1481 const char *s = get_id_str(asm_text);
1483 be_emit_cstring(env, "# Begin ASM \t");
1484 be_emit_finish_line_gas(env, node);
1487 be_emit_char(env, '\t');
1491 s = emit_asm_operand(env, node, s);
1494 be_emit_char(env, *s);
1499 be_emit_char(env, '\n');
1500 be_emit_write_line(env);
1502 be_emit_cstring(env, "# End ASM\n");
1503 be_emit_write_line(env);
1506 /**********************************
1509 * | | ___ _ __ _ _| |_) |
1510 * | | / _ \| '_ \| | | | _ <
1511 * | |___| (_) | |_) | |_| | |_) |
1512 * \_____\___/| .__/ \__, |____/
1515 **********************************/
1518 * Emit movsb/w instructions to make mov count divideable by 4
1521 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1522 be_emit_cstring(env, "\tcld");
1523 be_emit_finish_line_gas(env, NULL);
1527 be_emit_cstring(env, "\tmovsb");
1528 be_emit_finish_line_gas(env, NULL);
1531 be_emit_cstring(env, "\tmovsw");
1532 be_emit_finish_line_gas(env, NULL);
1535 be_emit_cstring(env, "\tmovsb");
1536 be_emit_finish_line_gas(env, NULL);
1537 be_emit_cstring(env, "\tmovsw");
1538 be_emit_finish_line_gas(env, NULL);
1544 * Emit rep movsd instruction for memcopy.
1547 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1548 tarval *tv = get_ia32_Immop_tarval(node);
1549 int rem = get_tarval_long(tv);
1551 emit_CopyB_prolog(env, rem);
1553 be_emit_cstring(env, "\trep movsd");
1554 be_emit_finish_line_gas(env, node);
1558 * Emits unrolled memcopy.
1561 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1562 tarval *tv = get_ia32_Immop_tarval(node);
1563 int size = get_tarval_long(tv);
1565 emit_CopyB_prolog(env, size & 0x3);
1569 be_emit_cstring(env, "\tmovsd");
1570 be_emit_finish_line_gas(env, NULL);
1576 /***************************
1580 * | | / _ \| '_ \ \ / /
1581 * | |___| (_) | | | \ V /
1582 * \_____\___/|_| |_|\_/
1584 ***************************/
1587 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1590 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1591 ir_mode *ls_mode = get_ia32_ls_mode(node);
1592 int ls_bits = get_mode_size_bits(ls_mode);
1594 be_emit_cstring(env, "\tcvt");
1596 if(is_ia32_Conv_I2FP(node)) {
1598 be_emit_cstring(env, "si2ss");
1600 be_emit_cstring(env, "si2sd");
1602 } else if(is_ia32_Conv_FP2I(node)) {
1604 be_emit_cstring(env, "ss2si");
1606 be_emit_cstring(env, "sd2si");
1609 assert(is_ia32_Conv_FP2FP(node));
1611 be_emit_cstring(env, "sd2ss");
1613 be_emit_cstring(env, "ss2sd");
1616 be_emit_char(env, ' ');
1618 switch(get_ia32_op_type(node)) {
1620 ia32_emit_source_register(env, node, 2);
1621 be_emit_cstring(env, ", ");
1622 ia32_emit_dest_register(env, node, 0);
1624 case ia32_AddrModeS:
1625 ia32_emit_dest_register(env, node, 0);
1626 be_emit_cstring(env, ", ");
1627 ia32_emit_am(env, node);
1630 assert(0 && "unsupported op type for Conv");
1632 be_emit_finish_line_gas(env, node);
1636 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1637 emit_ia32_Conv_with_FP(env, node);
1641 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1642 emit_ia32_Conv_with_FP(env, node);
1646 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1647 emit_ia32_Conv_with_FP(env, node);
1651 * Emits code for an Int conversion.
1654 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1655 const char *sign_suffix;
1656 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1657 int smaller_bits = get_mode_size_bits(smaller_mode);
1659 const arch_register_t *in_reg, *out_reg;
1661 assert(!mode_is_float(smaller_mode));
1662 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1664 signed_mode = mode_is_signed(smaller_mode);
1665 if(smaller_bits == 32) {
1666 // this should not happen as it's no convert
1670 sign_suffix = signed_mode ? "s" : "z";
1673 switch(get_ia32_op_type(node)) {
1675 in_reg = get_in_reg(env, node, 2);
1676 out_reg = get_out_reg(env, node, 0);
1678 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1679 REGS_ARE_EQUAL(out_reg, in_reg) &&
1683 /* argument and result are both in EAX and */
1684 /* signedness is ok: -> use the smaller cwtl opcode */
1685 be_emit_cstring(env, "\tcwtl");
1687 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1689 be_emit_cstring(env, "\tmov");
1690 be_emit_string(env, sign_suffix);
1691 ia32_emit_mode_suffix_mode(env, smaller_mode);
1692 be_emit_cstring(env, "l %");
1693 be_emit_string(env, sreg);
1694 be_emit_cstring(env, ", ");
1695 ia32_emit_dest_register(env, node, 0);
1698 case ia32_AddrModeS: {
1699 be_emit_cstring(env, "\tmov");
1700 be_emit_string(env, sign_suffix);
1701 ia32_emit_mode_suffix_mode(env, smaller_mode);
1702 be_emit_cstring(env, "l %");
1703 ia32_emit_am(env, node);
1704 be_emit_cstring(env, ", ");
1705 ia32_emit_dest_register(env, node, 0);
1709 assert(0 && "unsupported op type for Conv");
1711 be_emit_finish_line_gas(env, node);
1715 * Emits code for an 8Bit Int conversion.
1717 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1718 emit_ia32_Conv_I2I(env, node);
1722 /*******************************************
1725 * | |__ ___ _ __ ___ __| | ___ ___
1726 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1727 * | |_) | __/ | | | (_) | (_| | __/\__ \
1728 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1730 *******************************************/
1733 * Emits a backend call
1736 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1737 ir_entity *ent = be_Call_get_entity(node);
1739 be_emit_cstring(env, "\tcall ");
1741 set_entity_backend_marked(ent, 1);
1742 be_emit_string(env, get_entity_ld_name(ent));
1744 be_emit_char(env, '*');
1745 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1747 be_emit_finish_line_gas(env, node);
1751 * Emits code to increase stack pointer.
1754 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1755 int offs = be_get_IncSP_offset(node);
1761 be_emit_cstring(env, "\tsubl $");
1762 be_emit_irprintf(env->emit, "%u, ", offs);
1763 ia32_emit_source_register(env, node, 0);
1765 be_emit_cstring(env, "\taddl $");
1766 be_emit_irprintf(env->emit, "%u, ", -offs);
1767 ia32_emit_source_register(env, node, 0);
1769 be_emit_finish_line_gas(env, node);
1773 * Emits code to set stack pointer.
1776 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1777 be_emit_cstring(env, "\tmovl ");
1778 ia32_emit_source_register(env, node, 2);
1779 be_emit_cstring(env, ", ");
1780 ia32_emit_dest_register(env, node, 0);
1781 be_emit_finish_line_gas(env, node);
1785 * Emits code for Copy/CopyKeep.
1788 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1790 const arch_env_t *aenv = env->arch_env;
1793 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1794 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1797 mode = get_irn_mode(node);
1798 if (mode == mode_E) {
1799 be_emit_cstring(env, "\tmovsd ");
1800 ia32_emit_source_register(env, node, 0);
1801 be_emit_cstring(env, ", ");
1802 ia32_emit_dest_register(env, node, 0);
1804 be_emit_cstring(env, "\tmovl ");
1805 ia32_emit_source_register(env, node, 0);
1806 be_emit_cstring(env, ", ");
1807 ia32_emit_dest_register(env, node, 0);
1809 be_emit_finish_line_gas(env, node);
1813 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1814 Copy_emitter(env, node, be_get_Copy_op(node));
1818 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1819 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1823 * Emits code for exchange.
1826 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1827 const arch_register_t *in1, *in2;
1828 const arch_register_class_t *cls1, *cls2;
1830 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1831 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1833 cls1 = arch_register_get_class(in1);
1834 cls2 = arch_register_get_class(in2);
1836 assert(cls1 == cls2 && "Register class mismatch at Perm");
1838 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1839 be_emit_cstring(env, "\txchg ");
1840 ia32_emit_source_register(env, node, 1);
1841 be_emit_cstring(env, ", ");
1842 ia32_emit_source_register(env, node, 0);
1843 be_emit_finish_line_gas(env, node);
1844 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1845 be_emit_cstring(env, "\txorpd ");
1846 ia32_emit_source_register(env, node, 1);
1847 be_emit_cstring(env, ", ");
1848 ia32_emit_source_register(env, node, 0);
1849 be_emit_finish_line_gas(env, NULL);
1851 be_emit_cstring(env, "\txorpd ");
1852 ia32_emit_source_register(env, node, 0);
1853 be_emit_cstring(env, ", ");
1854 ia32_emit_source_register(env, node, 1);
1855 be_emit_finish_line_gas(env, NULL);
1857 be_emit_cstring(env, "\txorpd ");
1858 ia32_emit_source_register(env, node, 1);
1859 be_emit_cstring(env, ", ");
1860 ia32_emit_source_register(env, node, 0);
1861 be_emit_finish_line_gas(env, node);
1862 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1864 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1870 * Emits code for Constant loading.
1873 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1874 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1876 if (imm_tp == ia32_ImmSymConst) {
1877 be_emit_cstring(env, "\tmovl ");
1878 ia32_emit_immediate(env, node);
1879 be_emit_cstring(env, ", ");
1880 ia32_emit_dest_register(env, node, 0);
1882 tarval *tv = get_ia32_Immop_tarval(node);
1883 assert(get_irn_mode(node) == mode_Iu);
1884 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1885 if (tarval_is_null(tv)) {
1886 if (env->isa->opt_arch == arch_pentium_4) {
1887 /* P4 prefers sub r, r, others xor r, r */
1888 be_emit_cstring(env, "\tsubl ");
1890 be_emit_cstring(env, "\txorl ");
1892 ia32_emit_dest_register(env, node, 0);
1893 be_emit_cstring(env, ", ");
1894 ia32_emit_dest_register(env, node, 0);
1896 be_emit_cstring(env, "\tmovl ");
1897 ia32_emit_immediate(env, node);
1898 be_emit_cstring(env, ", ");
1899 ia32_emit_dest_register(env, node, 0);
1902 be_emit_finish_line_gas(env, node);
1906 * Emits code to load the TLS base
1909 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1910 be_emit_cstring(env, "\tmovl %gs:0, ");
1911 ia32_emit_dest_register(env, node, 0);
1912 be_emit_finish_line_gas(env, node);
1916 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
1918 be_emit_cstring(env, "\tret");
1919 be_emit_finish_line_gas(env, node);
1923 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
1930 /***********************************************************************************
1933 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1934 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1935 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1936 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1938 ***********************************************************************************/
1941 * Enters the emitter functions for handled nodes into the generic
1942 * pointer of an opcode.
1945 void ia32_register_emitters(void) {
1947 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1948 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1949 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1950 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1951 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1952 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1954 /* first clear the generic function pointer for all ops */
1955 clear_irp_opcodes_generic_func();
1957 /* register all emitter functions defined in spec */
1958 ia32_register_spec_emitters();
1960 /* other ia32 emitter functions */
1968 IA32_EMIT(SwitchJmp);
1971 IA32_EMIT(Conv_I2FP);
1972 IA32_EMIT(Conv_FP2I);
1973 IA32_EMIT(Conv_FP2FP);
1974 IA32_EMIT(Conv_I2I);
1975 IA32_EMIT(Conv_I2I8Bit);
1980 IA32_EMIT(xCmpCMov);
1981 IA32_EMIT(xCondJmp);
1982 IA32_EMIT2(fcomJmp, x87CondJmp);
1983 IA32_EMIT2(fcompJmp, x87CondJmp);
1984 IA32_EMIT2(fcomppJmp, x87CondJmp);
1985 IA32_EMIT2(fcomrJmp, x87CondJmp);
1986 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1987 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1989 /* benode emitter */
2015 static const char *last_name = NULL;
2016 static unsigned last_line = -1;
2017 static unsigned num = -1;
2020 * Emit the debug support for node node.
2023 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
2024 dbg_info *db = get_irn_dbg_info(node);
2026 const char *fname = be_retrieve_dbg_info(db, &lineno);
2028 if (! env->cg->birg->main_env->options->stabs_debug_support)
2032 if (last_name != fname) {
2034 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2037 if (last_line != lineno) {
2040 snprintf(name, sizeof(name), ".LM%u", ++num);
2042 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2043 be_emit_string(env, name);
2044 be_emit_cstring(env, ":\n");
2045 be_emit_write_line(env);
2050 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2053 * Emits code for a node.
2056 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2057 ir_op *op = get_irn_op(node);
2059 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2061 if (op->ops.generic) {
2062 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2063 ia32_emit_dbg(env, node);
2064 (*func) (env, node);
2066 emit_Nothing(env, node);
2067 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
2072 * Emits gas alignment directives
2075 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2076 be_emit_cstring(env, "\t.p2align ");
2077 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2078 be_emit_write_line(env);
2082 * Emits gas alignment directives for Functions depended on cpu architecture.
2085 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2087 unsigned maximum_skip;
2102 maximum_skip = (1 << align) - 1;
2103 ia32_emit_alignment(env, align, maximum_skip);
2107 * Emits gas alignment directives for Labels depended on cpu architecture.
2110 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2111 unsigned align; unsigned maximum_skip;
2126 maximum_skip = (1 << align) - 1;
2127 ia32_emit_alignment(env, align, maximum_skip);
2131 * Test wether a block should be aligned.
2132 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2133 * 16 bytes. However we should only do that if the alignment nops before the
2134 * label aren't executed more often than we have jumps to the label.
2137 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2138 static const double DELTA = .0001;
2139 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2141 double prev_freq = 0; /**< execfreq of the fallthrough block */
2142 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2143 cpu_support cpu = env->isa->opt_arch;
2146 if(exec_freq == NULL)
2148 if(cpu == arch_i386 || cpu == arch_i486)
2151 block_freq = get_block_execfreq(exec_freq, block);
2152 if(block_freq < DELTA)
2155 n_cfgpreds = get_Block_n_cfgpreds(block);
2156 for(i = 0; i < n_cfgpreds; ++i) {
2157 ir_node *pred = get_Block_cfgpred_block(block, i);
2158 double pred_freq = get_block_execfreq(exec_freq, pred);
2161 prev_freq += pred_freq;
2163 jmp_freq += pred_freq;
2167 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2170 jmp_freq /= prev_freq;
2174 case arch_athlon_64:
2176 return jmp_freq > 3;
2178 return jmp_freq > 2;
2183 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2188 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2191 n_cfgpreds = get_Block_n_cfgpreds(block);
2192 if (n_cfgpreds == 0) {
2194 } else if (n_cfgpreds == 1) {
2195 ir_node *pred = get_Block_cfgpred(block, 0);
2196 ir_node *pred_block = get_nodes_block(pred);
2198 /* we don't need labels for fallthrough blocks, however switch-jmps
2199 * are no fallthroughs */
2200 if(pred_block == prev &&
2201 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2210 if (should_align_block(env, block, prev)) {
2212 ia32_emit_align_label(env, env->isa->opt_arch);
2216 ia32_emit_block_name(env, block);
2217 be_emit_char(env, ':');
2219 be_emit_pad_comment(env);
2220 be_emit_cstring(env, " /* preds:");
2222 /* emit list of pred blocks in comment */
2223 arity = get_irn_arity(block);
2224 for (i = 0; i < arity; ++i) {
2225 ir_node *predblock = get_Block_cfgpred_block(block, i);
2226 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2229 be_emit_cstring(env, "\t/* ");
2230 ia32_emit_block_name(env, block);
2231 be_emit_cstring(env, ": ");
2233 if (exec_freq != NULL) {
2234 be_emit_irprintf(env->emit, " freq: %f",
2235 get_block_execfreq(exec_freq, block));
2237 be_emit_cstring(env, " */\n");
2238 be_emit_write_line(env);
2242 * Walks over the nodes in a block connected by scheduling edges
2243 * and emits code for each node.
2246 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2248 const ir_node *node;
2250 ia32_emit_block_header(env, block, last_block);
2252 /* emit the contents of the block */
2253 ia32_emit_dbg(env, block);
2254 sched_foreach(block, node) {
2255 ia32_emit_node(env, node);
2260 * Emits code for function start.
2263 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2264 ir_entity *irg_ent = get_irg_entity(irg);
2265 const char *irg_name = get_entity_ld_name(irg_ent);
2266 cpu_support cpu = env->isa->opt_arch;
2267 const be_irg_t *birg = env->cg->birg;
2269 be_emit_write_line(env);
2270 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2271 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2272 ia32_emit_align_func(env, cpu);
2273 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2274 be_emit_cstring(env, ".global ");
2275 be_emit_string(env, irg_name);
2276 be_emit_char(env, '\n');
2277 be_emit_write_line(env);
2279 ia32_emit_function_object(env, irg_name);
2280 be_emit_string(env, irg_name);
2281 be_emit_cstring(env, ":\n");
2282 be_emit_write_line(env);
2286 * Emits code for function end
2289 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2290 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2291 const be_irg_t *birg = env->cg->birg;
2293 ia32_emit_function_size(env, irg_name);
2294 be_dbg_method_end(birg->main_env->db_handle);
2295 be_emit_char(env, '\n');
2296 be_emit_write_line(env);
2301 * Sets labels for control flow nodes (jump target)
2304 void ia32_gen_labels(ir_node *block, void *data)
2307 int n = get_Block_n_cfgpreds(block);
2310 for (n--; n >= 0; n--) {
2311 pred = get_Block_cfgpred(block, n);
2312 set_irn_link(pred, block);
2317 * Emit an exception label if the current instruction can fail.
2319 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2320 if (get_ia32_exc_label(node)) {
2321 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2322 be_emit_write_line(env);
2327 * Main driver. Emits the code for one routine.
2329 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2330 ia32_emit_env_t env;
2332 ir_node *last_block = NULL;
2335 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2336 env.emit = &env.isa->emit;
2337 env.arch_env = cg->arch_env;
2340 ia32_register_emitters();
2342 ia32_emit_func_prolog(&env, irg);
2343 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2345 n = ARR_LEN(cg->blk_sched);
2346 for (i = 0; i < n;) {
2349 block = cg->blk_sched[i];
2351 next_bl = i < n ? cg->blk_sched[i] : NULL;
2353 /* set here the link. the emitter expects to find the next block here */
2354 set_irn_link(block, next_bl);
2355 ia32_gen_block(&env, block, last_block);
2359 ia32_emit_func_epilog(&env, irg);
2362 void ia32_init_emitter(void)
2364 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");