2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
43 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../benode.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
73 static char pic_base_label[128];
74 static ir_label_t exc_label_id;
75 static int mark_spill_reload = 0;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 /** Checks if the current block is a fall-through target. */
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
99 * returns non-zero if the given block needs a label
100 * because of being a jump-target (and not a fall-through)
102 static int block_needs_label(const ir_node *block)
105 int n_cfgpreds = get_Block_n_cfgpreds(block);
107 if (has_Block_entity(block))
110 if (n_cfgpreds == 0) {
112 } else if (n_cfgpreds == 1) {
113 ir_node *cfgpred = get_Block_cfgpred(block, 0);
114 ir_node *cfgpred_block = get_nodes_block(cfgpred);
116 if (get_prev_block_sched(block) == cfgpred_block
117 && is_fallthrough(cfgpred)) {
126 * Returns the register at in position pos.
128 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
131 const arch_register_t *reg = NULL;
133 assert(get_irn_arity(irn) > pos && "Invalid IN position");
135 /* The out register of the operator at position pos is the
136 in register we need. */
137 op = get_irn_n(irn, pos);
139 reg = arch_get_irn_register(op);
141 assert(reg && "no in register found");
143 if (reg == &ia32_gp_regs[REG_GP_NOREG])
144 panic("trying to emit noreg for %+F input %d", irn, pos);
146 /* in case of unknown register: just return a valid register */
147 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
148 const arch_register_req_t *req = arch_get_register_req(irn, pos);
150 if (arch_register_req_is(req, limited)) {
151 /* in case of limited requirements: get the first allowed register */
152 unsigned idx = rbitset_next(req->limited, 0, 1);
153 reg = arch_register_for_index(req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%lu", prefix, ++id);
208 /*************************************************************
210 * (_) | | / _| | | | |
211 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
212 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
213 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
214 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
217 *************************************************************/
220 * Emit the name of the 8bit low register
222 static void emit_8bit_register(const arch_register_t *reg)
224 const char *reg_name = arch_register_get_name(reg);
227 be_emit_char(reg_name[1]);
232 * Emit the name of the 8bit high register
234 static void emit_8bit_register_high(const arch_register_t *reg)
236 const char *reg_name = arch_register_get_name(reg);
239 be_emit_char(reg_name[1]);
243 static void emit_16bit_register(const arch_register_t *reg)
245 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
248 be_emit_string(reg_name);
252 * emit a register, possible shortened by a mode
254 * @param reg the register
255 * @param mode the mode of the register or NULL for full register
257 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
259 const char *reg_name;
262 int size = get_mode_size_bits(mode);
264 case 8: emit_8bit_register(reg); return;
265 case 16: emit_16bit_register(reg); return;
267 assert(mode_is_float(mode) || size == 32);
270 reg_name = arch_register_get_name(reg);
273 be_emit_string(reg_name);
276 void ia32_emit_source_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_in_reg(node, pos);
280 emit_register(reg, NULL);
283 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
285 set_entity_backend_marked(entity, 1);
286 be_gas_emit_entity(entity);
288 if (get_entity_owner(entity) == get_tls_type()) {
289 if (get_entity_visibility(entity) == visibility_external_allocated) {
290 be_emit_cstring("@INDNTPOFF");
292 be_emit_cstring("@NTPOFF");
296 if (do_pic && !no_pic_adjust) {
298 be_emit_string(pic_base_label);
302 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
304 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
306 if (attr->symconst != NULL) {
309 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
311 if (attr->symconst == NULL || attr->offset != 0) {
312 if (attr->symconst != NULL) {
313 be_emit_irprintf("%+d", attr->offset);
315 be_emit_irprintf("0x%X", attr->offset);
320 static void emit_ia32_Immediate(const ir_node *node)
323 emit_ia32_Immediate_no_prefix(node);
326 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
328 const arch_register_t *reg;
329 const ir_node *in = get_irn_n(node, pos);
330 if (is_ia32_Immediate(in)) {
331 emit_ia32_Immediate(in);
335 reg = get_in_reg(node, pos);
336 emit_8bit_register(reg);
339 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_in_reg(node, pos);
342 emit_8bit_register_high(reg);
345 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
347 const arch_register_t *reg;
348 const ir_node *in = get_irn_n(node, pos);
349 if (is_ia32_Immediate(in)) {
350 emit_ia32_Immediate(in);
354 reg = get_in_reg(node, pos);
355 emit_16bit_register(reg);
358 void ia32_emit_dest_register(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, NULL);
365 void ia32_emit_dest_register_size(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, get_ia32_ls_mode(node));
372 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
374 const arch_register_t *reg = get_out_reg(node, pos);
376 emit_register(reg, mode_Bu);
379 void ia32_emit_x87_register(const ir_node *node, int pos)
381 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
385 be_emit_string(attr->x87[pos]->name);
388 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
390 assert(mode_is_int(mode) || mode_is_reference(mode));
391 switch (get_mode_size_bits(mode)) {
392 case 8: be_emit_char('b'); return;
393 case 16: be_emit_char('w'); return;
394 case 32: be_emit_char('l'); return;
395 /* gas docu says q is the suffix but gcc, objdump and icc use ll
397 case 64: be_emit_cstring("ll"); return;
399 panic("Can't output mode_suffix for %+F", mode);
402 void ia32_emit_mode_suffix(const ir_node *node)
404 ir_mode *mode = get_ia32_ls_mode(node);
408 ia32_emit_mode_suffix_mode(mode);
411 void ia32_emit_x87_mode_suffix(const ir_node *node)
415 /* we only need to emit the mode on address mode */
416 if (get_ia32_op_type(node) == ia32_Normal)
419 mode = get_ia32_ls_mode(node);
420 assert(mode != NULL);
422 if (mode_is_float(mode)) {
423 switch (get_mode_size_bits(mode)) {
424 case 32: be_emit_char('s'); return;
425 case 64: be_emit_char('l'); return;
427 case 96: be_emit_char('t'); return;
430 assert(mode_is_int(mode));
431 switch (get_mode_size_bits(mode)) {
432 case 16: be_emit_char('s'); return;
433 case 32: be_emit_char('l'); return;
434 /* gas docu says q is the suffix but gcc, objdump and icc use ll
436 case 64: be_emit_cstring("ll"); return;
439 panic("Can't output mode_suffix for %+F", mode);
442 static char get_xmm_mode_suffix(ir_mode *mode)
444 assert(mode_is_float(mode));
445 switch(get_mode_size_bits(mode)) {
448 default: panic("Invalid XMM mode");
452 void ia32_emit_xmm_mode_suffix(const ir_node *node)
454 ir_mode *mode = get_ia32_ls_mode(node);
455 assert(mode != NULL);
457 be_emit_char(get_xmm_mode_suffix(mode));
460 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
462 ir_mode *mode = get_ia32_ls_mode(node);
463 assert(mode != NULL);
464 be_emit_char(get_xmm_mode_suffix(mode));
467 void ia32_emit_extend_suffix(const ir_node *node)
469 ir_mode *mode = get_ia32_ls_mode(node);
470 if (get_mode_size_bits(mode) == 32)
472 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
473 ia32_emit_mode_suffix_mode(mode);
476 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
478 ir_node *in = get_irn_n(node, pos);
479 if (is_ia32_Immediate(in)) {
480 emit_ia32_Immediate(in);
482 const ir_mode *mode = get_ia32_ls_mode(node);
483 const arch_register_t *reg = get_in_reg(node, pos);
484 emit_register(reg, mode);
489 * Returns the target block for a control flow node.
491 static ir_node *get_cfop_target_block(const ir_node *irn)
493 assert(get_irn_mode(irn) == mode_X);
494 return get_irn_link(irn);
498 * Emits a block label for the given block.
500 static void ia32_emit_block_name(const ir_node *block)
502 if (has_Block_entity(block)) {
503 ir_entity *entity = get_Block_entity(block);
504 be_gas_emit_entity(entity);
506 be_emit_cstring(BLOCK_PREFIX);
507 be_emit_irprintf("%ld", get_irn_node_nr(block));
512 * Emits the target label for a control flow node.
514 static void ia32_emit_cfop_target(const ir_node *node)
516 ir_node *block = get_cfop_target_block(node);
517 ia32_emit_block_name(block);
521 * positive conditions for signed compares
523 static const char *const cmp2condition_s[] = {
524 NULL, /* always false */
531 NULL /* always true */
535 * positive conditions for unsigned compares
537 static const char *const cmp2condition_u[] = {
538 NULL, /* always false */
545 NULL /* always true */
549 * Emit the suffix for a compare instruction.
551 static void ia32_emit_cmp_suffix(int pnc)
555 if (pnc == ia32_pn_Cmp_parity) {
560 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
561 str = cmp2condition_u[pnc & 7];
563 str = cmp2condition_s[pnc & 7];
569 typedef enum ia32_emit_mod_t {
570 EMIT_RESPECT_LS = 1U << 0,
571 EMIT_ALTERNATE_AM = 1U << 1,
573 EMIT_HIGH_REG = 1U << 3,
574 EMIT_LOW_REG = 1U << 4
578 * Emits address mode.
580 void ia32_emit_am(const ir_node *node)
582 ir_entity *ent = get_ia32_am_sc(node);
583 int offs = get_ia32_am_offs_int(node);
584 ir_node *base = get_irn_n(node, n_ia32_base);
585 int has_base = !is_ia32_NoReg_GP(base);
586 ir_node *index = get_irn_n(node, n_ia32_index);
587 int has_index = !is_ia32_NoReg_GP(index);
589 /* just to be sure... */
590 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
594 const ia32_attr_t *attr = get_ia32_attr_const(node);
595 if (is_ia32_am_sc_sign(node))
597 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
600 /* also handle special case if nothing is set */
601 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
603 be_emit_irprintf("%+d", offs);
605 be_emit_irprintf("%d", offs);
609 if (has_base || has_index) {
614 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
615 emit_register(reg, NULL);
618 /* emit index + scale */
620 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
623 emit_register(reg, NULL);
625 scale = get_ia32_am_scale(node);
627 be_emit_irprintf(",%d", 1 << scale);
635 * fmt parameter output
636 * ---- ---------------------- ---------------------------------------------
638 * %AM <node> address mode of the node
639 * %AR const arch_register_t* address mode of the node or register
640 * %ASx <node> address mode of the node or source register x
641 * %Dx <node> destination register x
642 * %I <node> immediate of the node
643 * %L <node> control flow target of the node
644 * %M <node> mode suffix of the node
645 * %P int condition code
646 * %R const arch_register_t* register
647 * %Sx <node> source register x
648 * %s const char* string
649 * %u unsigned int unsigned int
650 * %d signed int signed int
653 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
654 * * modifier does not prefix immediates with $, but AM with *
655 * l modifier for %lu and %ld
656 * > modifier to output high 8bit register (ah, bh)
657 * < modifier to output low 8bit register (al, bl)
659 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
665 const char *start = fmt;
666 ia32_emit_mod_t mod = 0;
668 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
671 be_emit_string_len(start, fmt - start);
675 be_emit_finish_line_gas(node);
688 case '*': mod |= EMIT_ALTERNATE_AM; break;
689 case '#': mod |= EMIT_RESPECT_LS; break;
690 case 'l': mod |= EMIT_LONG; break;
691 case '>': mod |= EMIT_HIGH_REG; break;
692 case '<': mod |= EMIT_LOW_REG; break;
708 if (mod & EMIT_ALTERNATE_AM)
715 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
716 if (mod & EMIT_ALTERNATE_AM)
718 if (get_ia32_op_type(node) == ia32_AddrModeS) {
721 emit_register(reg, NULL);
727 if (get_ia32_op_type(node) == ia32_AddrModeS) {
728 if (mod & EMIT_ALTERNATE_AM)
733 assert(get_ia32_op_type(node) == ia32_Normal);
738 default: goto unknown;
745 const arch_register_t *reg;
747 if (*fmt < '0' || '9' <= *fmt)
751 reg = get_out_reg(node, pos);
752 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
757 if (!(mod & EMIT_ALTERNATE_AM))
759 emit_ia32_Immediate_no_prefix(node);
763 ia32_emit_cfop_target(node);
767 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
772 int pnc = va_arg(ap, int);
773 ia32_emit_cmp_suffix(pnc);
778 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
779 if (mod & EMIT_HIGH_REG) {
780 emit_8bit_register_high(reg);
781 } else if (mod & EMIT_LOW_REG) {
782 emit_8bit_register(reg);
784 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
794 if (*fmt < '0' || '9' <= *fmt)
798 in = get_irn_n(node, pos);
799 if (is_ia32_Immediate(in)) {
800 if (!(mod & EMIT_ALTERNATE_AM))
802 emit_ia32_Immediate_no_prefix(in);
804 const arch_register_t *reg;
806 if (mod & EMIT_ALTERNATE_AM)
808 reg = get_in_reg(node, pos);
809 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
815 const char *str = va_arg(ap, const char*);
821 if (mod & EMIT_LONG) {
822 unsigned long num = va_arg(ap, unsigned long);
823 be_emit_irprintf("%lu", num);
825 unsigned num = va_arg(ap, unsigned);
826 be_emit_irprintf("%u", num);
831 if (mod & EMIT_LONG) {
832 long num = va_arg(ap, long);
833 be_emit_irprintf("%ld", num);
835 int num = va_arg(ap, int);
836 be_emit_irprintf("%d", num);
842 panic("unknown format conversion in ia32_emitf()");
850 * Emits registers and/or address mode of a binary operation.
852 void ia32_emit_binop(const ir_node *node)
854 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
855 ia32_emitf(node, "%#S4, %#AS3");
857 ia32_emitf(node, "%#AS4, %#S3");
862 * Emits registers and/or address mode of a binary operation.
864 void ia32_emit_x87_binop(const ir_node *node)
866 switch(get_ia32_op_type(node)) {
869 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
870 const arch_register_t *in1 = x87_attr->x87[0];
871 const arch_register_t *in = x87_attr->x87[1];
872 const arch_register_t *out = x87_attr->x87[2];
876 } else if (out == in) {
881 be_emit_string(arch_register_get_name(in));
882 be_emit_cstring(", %");
883 be_emit_string(arch_register_get_name(out));
891 assert(0 && "unsupported op type");
896 * Emits registers and/or address mode of a unary operation.
898 void ia32_emit_unop(const ir_node *node, int pos)
902 ia32_emitf(node, fmt);
905 static void emit_ia32_IMul(const ir_node *node)
907 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
908 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
910 /* do we need the 3-address form? */
911 if (is_ia32_NoReg_GP(left) ||
912 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
913 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
915 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
920 * walks up a tree of copies/perms/spills/reloads to find the original value
921 * that is moved around
923 static ir_node *find_original_value(ir_node *node)
925 if (irn_visited(node))
928 mark_irn_visited(node);
929 if (be_is_Copy(node)) {
930 return find_original_value(be_get_Copy_op(node));
931 } else if (be_is_CopyKeep(node)) {
932 return find_original_value(be_get_CopyKeep_op(node));
933 } else if (is_Proj(node)) {
934 ir_node *pred = get_Proj_pred(node);
935 if (be_is_Perm(pred)) {
936 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
937 } else if (be_is_MemPerm(pred)) {
938 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
939 } else if (is_ia32_Load(pred)) {
940 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
944 } else if (is_ia32_Store(node)) {
945 return find_original_value(get_irn_n(node, n_ia32_Store_val));
946 } else if (is_Phi(node)) {
948 arity = get_irn_arity(node);
949 for (i = 0; i < arity; ++i) {
950 ir_node *in = get_irn_n(node, i);
951 ir_node *res = find_original_value(in);
962 static int determine_final_pnc(const ir_node *node, int flags_pos,
965 ir_node *flags = get_irn_n(node, flags_pos);
966 const ia32_attr_t *flags_attr;
967 flags = skip_Proj(flags);
969 if (is_ia32_Sahf(flags)) {
970 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
971 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
972 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
973 inc_irg_visited(current_ir_graph);
974 cmp = find_original_value(cmp);
976 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
977 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
980 flags_attr = get_ia32_attr_const(cmp);
981 if (flags_attr->data.ins_permuted)
982 pnc = get_mirrored_pnc(pnc);
983 pnc |= ia32_pn_Cmp_float;
984 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
985 || is_ia32_Fucompi(flags)) {
986 flags_attr = get_ia32_attr_const(flags);
988 if (flags_attr->data.ins_permuted)
989 pnc = get_mirrored_pnc(pnc);
990 pnc |= ia32_pn_Cmp_float;
992 flags_attr = get_ia32_attr_const(flags);
994 if (flags_attr->data.ins_permuted)
995 pnc = get_mirrored_pnc(pnc);
996 if (flags_attr->data.cmp_unsigned)
997 pnc |= ia32_pn_Cmp_unsigned;
1003 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
1005 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
1006 return get_negated_pnc(pnc, mode);
1009 void ia32_emit_cmp_suffix_node(const ir_node *node,
1012 const ia32_attr_t *attr = get_ia32_attr_const(node);
1014 pn_Cmp pnc = get_ia32_condcode(node);
1016 pnc = determine_final_pnc(node, flags_pos, pnc);
1017 if (attr->data.ins_permuted)
1018 pnc = ia32_get_negated_pnc(pnc);
1020 ia32_emit_cmp_suffix(pnc);
1024 * Emits an exception label for a given node.
1026 static void ia32_emit_exc_label(const ir_node *node)
1028 be_emit_string(be_gas_insn_label_prefix());
1029 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1033 * Returns the Proj with projection number proj and NOT mode_M
1035 static ir_node *get_proj(const ir_node *node, long proj)
1037 const ir_edge_t *edge;
1040 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1042 foreach_out_edge(node, edge) {
1043 src = get_edge_src_irn(edge);
1045 assert(is_Proj(src) && "Proj expected");
1046 if (get_irn_mode(src) == mode_M)
1049 if (get_Proj_proj(src) == proj)
1055 static int can_be_fallthrough(const ir_node *node)
1057 ir_node *target_block = get_cfop_target_block(node);
1058 ir_node *block = get_nodes_block(node);
1059 return get_prev_block_sched(target_block) == block;
1063 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1065 static void emit_ia32_Jcc(const ir_node *node)
1067 int need_parity_label = 0;
1068 const ir_node *proj_true;
1069 const ir_node *proj_false;
1070 const ir_node *block;
1071 pn_Cmp pnc = get_ia32_condcode(node);
1073 pnc = determine_final_pnc(node, 0, pnc);
1075 /* get both Projs */
1076 proj_true = get_proj(node, pn_ia32_Jcc_true);
1077 assert(proj_true && "Jcc without true Proj");
1079 proj_false = get_proj(node, pn_ia32_Jcc_false);
1080 assert(proj_false && "Jcc without false Proj");
1082 block = get_nodes_block(node);
1084 if (can_be_fallthrough(proj_true)) {
1085 /* exchange both proj's so the second one can be omitted */
1086 const ir_node *t = proj_true;
1088 proj_true = proj_false;
1090 pnc = ia32_get_negated_pnc(pnc);
1093 if (pnc & ia32_pn_Cmp_float) {
1094 /* Some floating point comparisons require a test of the parity flag,
1095 * which indicates that the result is unordered */
1096 switch (pnc & 0x0f) {
1098 ia32_emitf(proj_true, "\tjp %L\n");
1103 ia32_emitf(proj_true, "\tjnp %L\n");
1109 /* we need a local label if the false proj is a fallthrough
1110 * as the falseblock might have no label emitted then */
1111 if (can_be_fallthrough(proj_false)) {
1112 need_parity_label = 1;
1113 ia32_emitf(proj_false, "\tjp 1f\n");
1115 ia32_emitf(proj_false, "\tjp %L\n");
1122 ia32_emitf(proj_true, "\tjp %L\n");
1130 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1133 if (need_parity_label) {
1134 ia32_emitf(NULL, "1:\n");
1137 /* the second Proj might be a fallthrough */
1138 if (can_be_fallthrough(proj_false)) {
1139 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1141 ia32_emitf(proj_false, "\tjmp %L\n");
1146 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1149 static void emit_ia32_Setcc(const ir_node *node)
1151 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1153 pn_Cmp pnc = get_ia32_condcode(node);
1154 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1155 if (pnc & ia32_pn_Cmp_float) {
1156 switch (pnc & 0x0f) {
1158 ia32_emitf(node, "\tsetp %#R\n", dreg);
1162 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1168 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1169 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1170 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1176 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1177 ia32_emitf(node, "\tsetp %>R\n", dreg);
1178 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1185 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1188 static void emit_ia32_CMovcc(const ir_node *node)
1190 const ia32_attr_t *attr = get_ia32_attr_const(node);
1191 int ins_permuted = attr->data.ins_permuted;
1192 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1193 pn_Cmp pnc = get_ia32_condcode(node);
1194 const arch_register_t *in_true;
1195 const arch_register_t *in_false;
1197 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1199 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1200 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1202 /* should be same constraint fullfilled? */
1203 if (out == in_false) {
1204 /* yes -> nothing to do */
1205 } else if (out == in_true) {
1206 const arch_register_t *tmp;
1208 assert(get_ia32_op_type(node) == ia32_Normal);
1210 ins_permuted = !ins_permuted;
1217 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1221 pnc = ia32_get_negated_pnc(pnc);
1223 /* TODO: handling of Nans isn't correct yet */
1225 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1228 /*********************************************************
1231 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1232 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1233 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1234 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1237 *********************************************************/
1239 /* jump table entry (target and corresponding number) */
1240 typedef struct _branch_t {
1245 /* jump table for switch generation */
1246 typedef struct _jmp_tbl_t {
1247 ir_node *defProj; /**< default target */
1248 long min_value; /**< smallest switch case */
1249 long max_value; /**< largest switch case */
1250 long num_branches; /**< number of jumps */
1251 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1252 branch_t *branches; /**< jump array */
1256 * Compare two variables of type branch_t. Used to sort all switch cases
1258 static int ia32_cmp_branch_t(const void *a, const void *b)
1260 branch_t *b1 = (branch_t *)a;
1261 branch_t *b2 = (branch_t *)b;
1263 if (b1->value <= b2->value)
1269 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1275 const ir_edge_t *edge;
1277 /* fill the table structure */
1278 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, ".TBL_");
1279 tbl->defProj = NULL;
1280 tbl->num_branches = get_irn_n_edges(node) - 1;
1281 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1282 tbl->min_value = LONG_MAX;
1283 tbl->max_value = LONG_MIN;
1285 default_pn = get_ia32_condcode(node);
1287 /* go over all proj's and collect them */
1288 foreach_out_edge(node, edge) {
1289 proj = get_edge_src_irn(edge);
1290 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1292 pnc = get_Proj_proj(proj);
1294 /* check for default proj */
1295 if (pnc == default_pn) {
1296 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1297 tbl->defProj = proj;
1299 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1300 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1302 /* create branch entry */
1303 tbl->branches[i].target = proj;
1304 tbl->branches[i].value = pnc;
1309 assert(i == tbl->num_branches);
1311 /* sort the branches by their number */
1312 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1316 * Emits code for a SwitchJmp (creates a jump table if
1317 * possible otherwise a cmp-jmp cascade). Port from
1320 static void emit_ia32_SwitchJmp(const ir_node *node)
1322 unsigned long interval;
1326 /* fill the table structure */
1327 generate_jump_table(&tbl, node);
1329 /* two-complement's magic make this work without overflow */
1330 interval = tbl.max_value - tbl.min_value;
1332 /* emit the table */
1333 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1334 ia32_emitf(tbl.defProj, "\tja %L\n");
1336 if (tbl.num_branches > 1) {
1338 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1340 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1341 ia32_emitf(NULL, "\t.align 4\n");
1342 ia32_emitf(NULL, "%s:\n", tbl.label);
1344 last_value = tbl.branches[0].value;
1345 for (i = 0; i != tbl.num_branches; ++i) {
1346 while (last_value != tbl.branches[i].value) {
1347 ia32_emitf(tbl.defProj, ".long %L\n");
1350 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1353 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1355 /* one jump is enough */
1356 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1363 * Emits code for a unconditional jump.
1365 static void emit_ia32_Jmp(const ir_node *node)
1369 /* for now, the code works for scheduled and non-schedules blocks */
1370 block = get_nodes_block(node);
1372 /* we have a block schedule */
1373 if (can_be_fallthrough(node)) {
1374 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1376 ia32_emitf(node, "\tjmp %L\n");
1381 * Emit an inline assembler operand.
1383 * @param node the ia32_ASM node
1384 * @param s points to the operand (a %c)
1386 * @return pointer to the first char in s NOT in the current operand
1388 static const char* emit_asm_operand(const ir_node *node, const char *s)
1390 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1391 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1393 const arch_register_t *reg;
1394 const ia32_asm_reg_t *asm_regs = attr->register_map;
1395 const ia32_asm_reg_t *asm_reg;
1396 const char *reg_name;
1405 /* parse modifiers */
1408 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1433 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1440 sscanf(s, "%d%n", &num, &p);
1442 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1449 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1451 "Error: Custom assembler references invalid input/output (%+F)\n",
1455 asm_reg = & asm_regs[num];
1456 assert(asm_reg->valid);
1459 if (asm_reg->use_input == 0) {
1460 reg = get_out_reg(node, asm_reg->inout_pos);
1462 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1464 /* might be an immediate value */
1465 if (is_ia32_Immediate(pred)) {
1466 emit_ia32_Immediate(pred);
1469 reg = get_in_reg(node, asm_reg->inout_pos);
1473 "Warning: no register assigned for %d asm op (%+F)\n",
1478 if (asm_reg->memory) {
1483 if (modifier != 0) {
1487 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1490 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1493 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1496 panic("Invalid asm op modifier");
1498 be_emit_string(reg_name);
1500 emit_register(reg, asm_reg->mode);
1503 if (asm_reg->memory) {
1511 * Emits code for an ASM pseudo op.
1513 static void emit_ia32_Asm(const ir_node *node)
1515 const void *gen_attr = get_irn_generic_attr_const(node);
1516 const ia32_asm_attr_t *attr
1517 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1518 ident *asm_text = attr->asm_text;
1519 const char *s = get_id_str(asm_text);
1521 ia32_emitf(node, "#APP\t\n");
1528 s = emit_asm_operand(node, s);
1534 ia32_emitf(NULL, "\n#NO_APP\n");
1537 /**********************************
1540 * | | ___ _ __ _ _| |_) |
1541 * | | / _ \| '_ \| | | | _ <
1542 * | |___| (_) | |_) | |_| | |_) |
1543 * \_____\___/| .__/ \__, |____/
1546 **********************************/
1549 * Emit movsb/w instructions to make mov count divideable by 4
1551 static void emit_CopyB_prolog(unsigned size)
1554 ia32_emitf(NULL, "\tmovsb\n");
1556 ia32_emitf(NULL, "\tmovsw\n");
1560 * Emit rep movsd instruction for memcopy.
1562 static void emit_ia32_CopyB(const ir_node *node)
1564 unsigned size = get_ia32_copyb_size(node);
1566 emit_CopyB_prolog(size);
1567 ia32_emitf(node, "\trep movsd\n");
1571 * Emits unrolled memcopy.
1573 static void emit_ia32_CopyB_i(const ir_node *node)
1575 unsigned size = get_ia32_copyb_size(node);
1577 emit_CopyB_prolog(size);
1581 ia32_emitf(NULL, "\tmovsd\n");
1587 /***************************
1591 * | | / _ \| '_ \ \ / /
1592 * | |___| (_) | | | \ V /
1593 * \_____\___/|_| |_|\_/
1595 ***************************/
1598 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1600 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1603 ir_mode *ls_mode = get_ia32_ls_mode(node);
1604 int ls_bits = get_mode_size_bits(ls_mode);
1605 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1607 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1610 static void emit_ia32_Conv_I2FP(const ir_node *node)
1612 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1615 static void emit_ia32_Conv_FP2I(const ir_node *node)
1617 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1620 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1622 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1626 * Emits code for an Int conversion.
1628 static void emit_ia32_Conv_I2I(const ir_node *node)
1630 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1631 int signed_mode = mode_is_signed(smaller_mode);
1632 const char *sign_suffix;
1634 assert(!mode_is_float(smaller_mode));
1636 sign_suffix = signed_mode ? "s" : "z";
1637 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1643 static void emit_ia32_Call(const ir_node *node)
1645 /* Special case: Call must not have its immediates prefixed by $, instead
1646 * address mode is prefixed by *. */
1647 ia32_emitf(node, "\tcall %*AS3\n");
1651 /*******************************************
1654 * | |__ ___ _ __ ___ __| | ___ ___
1655 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1656 * | |_) | __/ | | | (_) | (_| | __/\__ \
1657 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1659 *******************************************/
1662 * Emits code to increase stack pointer.
1664 static void emit_be_IncSP(const ir_node *node)
1666 int offs = be_get_IncSP_offset(node);
1672 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1674 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1678 static inline bool is_unknown_reg(const arch_register_t *reg)
1680 if(reg == &ia32_gp_regs[REG_GP_UKNWN]
1681 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1682 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1689 * Emits code for Copy/CopyKeep.
1691 static void Copy_emitter(const ir_node *node, const ir_node *op)
1693 const arch_register_t *in = arch_get_irn_register(op);
1694 const arch_register_t *out = arch_get_irn_register(node);
1699 if (is_unknown_reg(in))
1701 /* copies of vf nodes aren't real... */
1702 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1705 if (get_irn_mode(node) == mode_E) {
1706 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1708 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1712 static void emit_be_Copy(const ir_node *node)
1714 Copy_emitter(node, be_get_Copy_op(node));
1717 static void emit_be_CopyKeep(const ir_node *node)
1719 Copy_emitter(node, be_get_CopyKeep_op(node));
1723 * Emits code for exchange.
1725 static void emit_be_Perm(const ir_node *node)
1727 const arch_register_t *in0, *in1;
1728 const arch_register_class_t *cls0, *cls1;
1730 in0 = arch_get_irn_register(get_irn_n(node, 0));
1731 in1 = arch_get_irn_register(get_irn_n(node, 1));
1733 cls0 = arch_register_get_class(in0);
1734 cls1 = arch_register_get_class(in1);
1736 assert(cls0 == cls1 && "Register class mismatch at Perm");
1738 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1739 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1740 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1741 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1742 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1743 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1744 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1746 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1749 panic("unexpected register class in be_Perm (%+F)", node);
1754 * Emits code for Constant loading.
1756 static void emit_ia32_Const(const ir_node *node)
1758 ia32_emitf(node, "\tmovl %I, %D0\n");
1762 * Emits code to load the TLS base
1764 static void emit_ia32_LdTls(const ir_node *node)
1766 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1769 /* helper function for emit_ia32_Minus64Bit */
1770 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1772 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1775 /* helper function for emit_ia32_Minus64Bit */
1776 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1778 ia32_emitf(node, "\tnegl %R\n", reg);
1781 /* helper function for emit_ia32_Minus64Bit */
1782 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1784 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1787 /* helper function for emit_ia32_Minus64Bit */
1788 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1790 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1793 /* helper function for emit_ia32_Minus64Bit */
1794 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1796 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1799 /* helper function for emit_ia32_Minus64Bit */
1800 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1802 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1805 static void emit_ia32_Minus64Bit(const ir_node *node)
1807 const arch_register_t *in_lo = get_in_reg(node, 0);
1808 const arch_register_t *in_hi = get_in_reg(node, 1);
1809 const arch_register_t *out_lo = get_out_reg(node, 0);
1810 const arch_register_t *out_hi = get_out_reg(node, 1);
1812 if (out_lo == in_lo) {
1813 if (out_hi != in_hi) {
1814 /* a -> a, b -> d */
1817 /* a -> a, b -> b */
1820 } else if (out_lo == in_hi) {
1821 if (out_hi == in_lo) {
1822 /* a -> b, b -> a */
1823 emit_xchg(node, in_lo, in_hi);
1826 /* a -> b, b -> d */
1827 emit_mov(node, in_hi, out_hi);
1828 emit_mov(node, in_lo, out_lo);
1832 if (out_hi == in_lo) {
1833 /* a -> c, b -> a */
1834 emit_mov(node, in_lo, out_lo);
1836 } else if (out_hi == in_hi) {
1837 /* a -> c, b -> b */
1838 emit_mov(node, in_lo, out_lo);
1841 /* a -> c, b -> d */
1842 emit_mov(node, in_lo, out_lo);
1848 emit_neg( node, out_hi);
1849 emit_neg( node, out_lo);
1850 emit_sbb0(node, out_hi);
1854 emit_zero(node, out_hi);
1855 emit_neg( node, out_lo);
1856 emit_sbb( node, in_hi, out_hi);
1859 static void emit_ia32_GetEIP(const ir_node *node)
1861 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1862 ia32_emitf(NULL, "%s:\n", pic_base_label);
1863 ia32_emitf(node, "\tpopl %D0\n");
1866 static void emit_ia32_ClimbFrame(const ir_node *node)
1868 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1870 ia32_emitf(node, "\tmovl %S0, %D0\n");
1871 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1872 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1873 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1874 ia32_emitf(node, "\tdec %S1\n");
1875 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1878 static void emit_be_Return(const ir_node *node)
1880 unsigned pop = be_Return_get_pop(node);
1882 if (pop > 0 || be_Return_get_emit_pop(node)) {
1883 ia32_emitf(node, "\tret $%u\n", pop);
1885 ia32_emitf(node, "\tret\n");
1889 static void emit_Nothing(const ir_node *node)
1895 /***********************************************************************************
1898 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1899 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1900 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1901 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1903 ***********************************************************************************/
1906 * Enters the emitter functions for handled nodes into the generic
1907 * pointer of an opcode.
1909 static void ia32_register_emitters(void)
1911 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1912 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1913 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1914 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1915 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1916 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1918 /* first clear the generic function pointer for all ops */
1919 clear_irp_opcodes_generic_func();
1921 /* register all emitter functions defined in spec */
1922 ia32_register_spec_emitters();
1924 /* other ia32 emitter functions */
1925 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1930 IA32_EMIT(Conv_FP2FP);
1931 IA32_EMIT(Conv_FP2I);
1932 IA32_EMIT(Conv_I2FP);
1933 IA32_EMIT(Conv_I2I);
1941 IA32_EMIT(Minus64Bit);
1942 IA32_EMIT(SwitchJmp);
1943 IA32_EMIT(ClimbFrame);
1946 /* benode emitter */
1967 typedef void (*emit_func_ptr) (const ir_node *);
1970 * Assign and emit an exception label if the current instruction can fail.
1972 static void ia32_assign_exc_label(ir_node *node)
1974 /* assign a new ID to the instruction */
1975 set_ia32_exc_label_id(node, ++exc_label_id);
1977 ia32_emit_exc_label(node);
1979 be_emit_pad_comment();
1980 be_emit_cstring("/* exception to Block ");
1981 ia32_emit_cfop_target(node);
1982 be_emit_cstring(" */\n");
1983 be_emit_write_line();
1987 * Emits code for a node.
1989 static void ia32_emit_node(ir_node *node)
1991 ir_op *op = get_irn_op(node);
1993 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1995 if (is_ia32_irn(node)) {
1996 if (get_ia32_exc_label(node)) {
1997 /* emit the exception label of this instruction */
1998 ia32_assign_exc_label(node);
2000 if (mark_spill_reload) {
2001 if (is_ia32_is_spill(node)) {
2002 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
2004 if (is_ia32_is_reload(node)) {
2005 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
2007 if (is_ia32_is_remat(node)) {
2008 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
2012 if (op->ops.generic) {
2013 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2015 be_dbg_set_dbg_info(get_irn_dbg_info(node));
2020 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
2026 * Emits gas alignment directives
2028 static void ia32_emit_alignment(unsigned align, unsigned skip)
2030 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
2034 * Emits gas alignment directives for Labels depended on cpu architecture.
2036 static void ia32_emit_align_label(void)
2038 unsigned align = ia32_cg_config.label_alignment;
2039 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
2040 ia32_emit_alignment(align, maximum_skip);
2044 * Test whether a block should be aligned.
2045 * For cpus in the P4/Athlon class it is useful to align jump labels to
2046 * 16 bytes. However we should only do that if the alignment nops before the
2047 * label aren't executed more often than we have jumps to the label.
2049 static int should_align_block(const ir_node *block)
2051 static const double DELTA = .0001;
2052 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2053 ir_node *prev = get_prev_block_sched(block);
2055 double prev_freq = 0; /**< execfreq of the fallthrough block */
2056 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2059 if (exec_freq == NULL)
2061 if (ia32_cg_config.label_alignment_factor <= 0)
2064 block_freq = get_block_execfreq(exec_freq, block);
2065 if (block_freq < DELTA)
2068 n_cfgpreds = get_Block_n_cfgpreds(block);
2069 for(i = 0; i < n_cfgpreds; ++i) {
2070 const ir_node *pred = get_Block_cfgpred_block(block, i);
2071 double pred_freq = get_block_execfreq(exec_freq, pred);
2074 prev_freq += pred_freq;
2076 jmp_freq += pred_freq;
2080 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2083 jmp_freq /= prev_freq;
2085 return jmp_freq > ia32_cg_config.label_alignment_factor;
2089 * Emit the block header for a block.
2091 * @param block the block
2092 * @param prev_block the previous block
2094 static void ia32_emit_block_header(ir_node *block)
2096 ir_graph *irg = current_ir_graph;
2097 int need_label = block_needs_label(block);
2099 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2101 if (block == get_irg_end_block(irg))
2104 if (ia32_cg_config.label_alignment > 0) {
2105 /* align the current block if:
2106 * a) if should be aligned due to its execution frequency
2107 * b) there is no fall-through here
2109 if (should_align_block(block)) {
2110 ia32_emit_align_label();
2112 /* if the predecessor block has no fall-through,
2113 we can always align the label. */
2115 int has_fallthrough = 0;
2117 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2118 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2119 if (can_be_fallthrough(cfg_pred)) {
2120 has_fallthrough = 1;
2125 if (!has_fallthrough)
2126 ia32_emit_align_label();
2131 ia32_emit_block_name(block);
2134 be_emit_pad_comment();
2135 be_emit_cstring(" /* ");
2137 be_emit_cstring("\t/* ");
2138 ia32_emit_block_name(block);
2139 be_emit_cstring(": ");
2142 be_emit_cstring("preds:");
2144 /* emit list of pred blocks in comment */
2145 arity = get_irn_arity(block);
2147 be_emit_cstring(" none");
2149 for (i = 0; i < arity; ++i) {
2150 ir_node *predblock = get_Block_cfgpred_block(block, i);
2151 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2154 if (exec_freq != NULL) {
2155 be_emit_irprintf(", freq: %f",
2156 get_block_execfreq(exec_freq, block));
2158 be_emit_cstring(" */\n");
2159 be_emit_write_line();
2163 * Walks over the nodes in a block connected by scheduling edges
2164 * and emits code for each node.
2166 static void ia32_gen_block(ir_node *block)
2170 ia32_emit_block_header(block);
2172 /* emit the contents of the block */
2173 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2174 sched_foreach(block, node) {
2175 ia32_emit_node(node);
2179 typedef struct exc_entry {
2180 ir_node *exc_instr; /** The instruction that can issue an exception. */
2181 ir_node *block; /** The block to call then. */
2186 * Sets labels for control flow nodes (jump target).
2187 * Links control predecessors to there destination blocks.
2189 static void ia32_gen_labels(ir_node *block, void *data)
2191 exc_entry **exc_list = data;
2195 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2196 pred = get_Block_cfgpred(block, n);
2197 set_irn_link(pred, block);
2199 pred = skip_Proj(pred);
2200 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2205 ARR_APP1(exc_entry, *exc_list, e);
2206 set_irn_link(pred, block);
2212 * Compare two exception_entries.
2214 static int cmp_exc_entry(const void *a, const void *b)
2216 const exc_entry *ea = a;
2217 const exc_entry *eb = b;
2219 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2225 * Main driver. Emits the code for one routine.
2227 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2229 ir_entity *entity = get_irg_entity(irg);
2230 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2235 do_pic = cg->birg->main_env->options->pic;
2237 ia32_register_emitters();
2239 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2241 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2242 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2244 /* we use links to point to target blocks */
2245 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2246 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2248 /* initialize next block links */
2249 n = ARR_LEN(cg->blk_sched);
2250 for (i = 0; i < n; ++i) {
2251 ir_node *block = cg->blk_sched[i];
2252 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2254 set_irn_link(block, prev);
2257 for (i = 0; i < n; ++i) {
2258 ir_node *block = cg->blk_sched[i];
2260 ia32_gen_block(block);
2263 be_gas_emit_function_epilog(entity);
2264 be_dbg_method_end();
2266 be_emit_write_line();
2268 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2270 /* Sort the exception table using the exception label id's.
2271 Those are ascending with ascending addresses. */
2272 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2276 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2277 be_emit_cstring("\t.long ");
2278 ia32_emit_exc_label(exc_list[i].exc_instr);
2280 be_emit_cstring("\t.long ");
2281 ia32_emit_block_name(exc_list[i].block);
2285 DEL_ARR_F(exc_list);
2288 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2289 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2293 /* ==== Experimental binary emitter ==== */
2295 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2296 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2297 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2298 static unsigned char pnc_map_signed[8];
2299 static unsigned char pnc_map_unsigned[8];
2301 static void build_reg_map(void)
2303 reg_gp_map[REG_EAX] = 0x0;
2304 reg_gp_map[REG_ECX] = 0x1;
2305 reg_gp_map[REG_EDX] = 0x2;
2306 reg_gp_map[REG_EBX] = 0x3;
2307 reg_gp_map[REG_ESP] = 0x4;
2308 reg_gp_map[REG_EBP] = 0x5;
2309 reg_gp_map[REG_ESI] = 0x6;
2310 reg_gp_map[REG_EDI] = 0x7;
2312 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2313 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2314 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2315 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2316 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2317 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2319 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2320 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2321 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2322 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2323 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2324 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2327 /** Returns the encoding for a pnc field. */
2328 static unsigned char pnc2cc(int pnc)
2331 if (pnc == ia32_pn_Cmp_parity) {
2333 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2334 cc = pnc_map_unsigned[pnc & 0x07];
2336 cc = pnc_map_signed[pnc & 0x07];
2342 /** Sign extension bit values for binops */
2344 UNSIGNED_IMM = 0, /**< unsigned immediate */
2345 SIGNEXT_IMM = 2, /**< sign extended immediate */
2348 /** The mod encoding of the ModR/M */
2350 MOD_IND = 0x00, /**< [reg1] */
2351 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2352 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2353 MOD_REG = 0xC0 /**< reg1 */
2356 /** create R/M encoding for ModR/M */
2357 #define ENC_RM(x) (x)
2358 /** create REG encoding for ModR/M */
2359 #define ENC_REG(x) ((x) << 3)
2361 /** create encoding for a SIB byte */
2362 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2364 /* Node: The following routines are supposed to append bytes, words, dwords
2365 to the output stream.
2366 Currently the implementation is stupid in that it still creates output
2367 for an "assembler" in the form of .byte, .long
2368 We will change this when enough infrastructure is there to create complete
2369 machine code in memory/object files */
2371 static void bemit8(const unsigned char byte)
2373 be_emit_irprintf("\t.byte 0x%x\n", byte);
2374 be_emit_write_line();
2377 static void bemit16(const unsigned short u16)
2379 be_emit_irprintf("\t.word 0x%x\n", u16);
2380 be_emit_write_line();
2383 static void bemit32(const unsigned u32)
2385 be_emit_irprintf("\t.long 0x%x\n", u32);
2386 be_emit_write_line();
2390 * Emit address of an entity. If @p is_relative is true then a relative
2391 * offset from behind the address to the entity is created.
2393 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2396 if (entity == NULL) {
2401 /* the final version should remember the position in the bytestream
2402 and patch it with the correct address at linktime... */
2403 be_emit_cstring("\t.long ");
2406 set_entity_backend_marked(entity, 1);
2407 be_gas_emit_entity(entity);
2409 if (get_entity_owner(entity) == get_tls_type()) {
2410 if (get_entity_visibility(entity) == visibility_external_allocated) {
2411 be_emit_cstring("@INDNTPOFF");
2413 be_emit_cstring("@NTPOFF");
2418 be_emit_cstring("-.");
2423 be_emit_irprintf("%+d", offset);
2426 be_emit_write_line();
2429 static void bemit_jmp_destination(const ir_node *dest_block)
2431 be_emit_cstring("\t.long ");
2432 ia32_emit_block_name(dest_block);
2433 be_emit_cstring(" - . - 4\n");
2434 be_emit_write_line();
2437 /* end emit routines, all emitters following here should only use the functions
2440 typedef enum reg_modifier {
2445 /** Create a ModR/M byte for src1,src2 registers */
2446 static void bemit_modrr(const arch_register_t *src1,
2447 const arch_register_t *src2)
2449 unsigned char modrm = MOD_REG;
2450 modrm |= ENC_RM(reg_gp_map[src1->index]);
2451 modrm |= ENC_REG(reg_gp_map[src2->index]);
2455 /** Create a ModR/M8 byte for src1,src2 registers */
2456 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2457 reg_modifier_t high_part2, const arch_register_t *src2)
2459 unsigned char modrm = MOD_REG;
2460 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2461 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2465 /** Create a ModR/M byte for one register and extension */
2466 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2468 unsigned char modrm = MOD_REG;
2470 modrm |= ENC_RM(reg_gp_map[reg->index]);
2471 modrm |= ENC_REG(ext);
2475 /** Create a ModR/M8 byte for one register */
2476 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2478 unsigned char modrm = MOD_REG;
2479 assert(reg_gp_map[reg->index] < 4);
2480 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2486 * Calculate the size of an signed immediate in bytes.
2488 * @param offset an offset
2490 static unsigned get_signed_imm_size(int offset)
2492 if (-128 <= offset && offset < 128) {
2494 } else if (-32768 <= offset && offset < 32768) {
2502 * Emit an address mode.
2504 * @param reg content of the reg field: either a register index or an opcode extension
2505 * @param node the node
2507 static void bemit_mod_am(unsigned reg, const ir_node *node)
2509 ir_entity *ent = get_ia32_am_sc(node);
2510 int offs = get_ia32_am_offs_int(node);
2511 ir_node *base = get_irn_n(node, n_ia32_base);
2512 int has_base = !is_ia32_NoReg_GP(base);
2513 ir_node *index = get_irn_n(node, n_ia32_index);
2514 int has_index = !is_ia32_NoReg_GP(index);
2517 unsigned emitoffs = 0;
2518 bool emitsib = false;
2521 /* set the mod part depending on displacement */
2523 modrm |= MOD_IND_WORD_OFS;
2525 } else if (offs == 0) {
2528 } else if (-128 <= offs && offs < 128) {
2529 modrm |= MOD_IND_BYTE_OFS;
2532 modrm |= MOD_IND_WORD_OFS;
2537 const arch_register_t *base_reg = arch_get_irn_register(base);
2538 base_enc = reg_gp_map[base_reg->index];
2540 /* Use the EBP encoding + MOD_IND if NO base register. There is
2541 * always a 32bit offset present in this case. */
2547 /* Determine if we need a SIB byte. */
2549 const arch_register_t *reg_index = arch_get_irn_register(index);
2550 int scale = get_ia32_am_scale(node);
2552 /* R/M set to ESP means SIB in 32bit mode. */
2553 modrm |= ENC_RM(0x04);
2554 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2556 } else if (base_enc == 0x04) {
2557 /* for the above reason we are forced to emit a SIB when base is ESP.
2558 * Only the base is used, index must be ESP too, which means no index.
2560 modrm |= ENC_RM(0x04);
2561 sib = ENC_SIB(0, 0x04, 0x04);
2564 modrm |= ENC_RM(base_enc);
2567 /* We are forced to emit an 8bit offset as EBP base without offset is a
2568 * special case for SIB without base register. */
2569 if (base_enc == 0x05 && emitoffs == 0) {
2570 modrm |= MOD_IND_BYTE_OFS;
2574 modrm |= ENC_REG(reg);
2580 /* emit displacement */
2581 if (emitoffs == 8) {
2582 bemit8((unsigned) offs);
2583 } else if (emitoffs == 32) {
2584 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2589 * Emit a binop with a immediate operand.
2591 * @param node the node to emit
2592 * @param opcode_eax the opcode for the op eax, imm variant
2593 * @param opcode the opcode for the reg, imm variant
2594 * @param ruval the opcode extension for opcode
2596 static void bemit_binop_with_imm(
2597 const ir_node *node,
2598 unsigned char opcode_ax,
2599 unsigned char opcode, unsigned char ruval)
2601 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2602 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2603 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2606 /* Some instructions (test) have no short form with 32bit value + 8bit
2608 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2611 /* check for sign extension */
2612 size = get_signed_imm_size(attr->offset);
2617 bemit8(opcode | SIGNEXT_IMM);
2618 /* cmp has this special mode */
2619 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2620 bemit_mod_am(ruval, node);
2622 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2623 bemit_modru(reg, ruval);
2625 bemit8((unsigned char)attr->offset);
2629 /* check for eax variant: this variant is shorter for 32bit immediates only */
2630 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2632 bemit_mod_am(ruval, node);
2634 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2635 if (reg->index == REG_EAX) {
2639 bemit_modru(reg, ruval);
2642 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2645 panic("invalid imm size?!?");
2651 static void bemit_binop_2(const ir_node *node, unsigned code)
2653 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2655 if (get_ia32_op_type(node) == ia32_Normal) {
2656 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2657 bemit_modrr(op2, out);
2659 bemit_mod_am(reg_gp_map[out->index], node);
2666 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2668 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2669 if (is_ia32_Immediate(right)) {
2670 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2672 bemit_binop_2(node, opcodes[0]);
2679 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2682 if (get_ia32_op_type(node) == ia32_Normal) {
2683 const arch_register_t *in = get_in_reg(node, input);
2684 bemit_modru(in, ext);
2686 bemit_mod_am(ext, node);
2690 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2692 const arch_register_t *out = get_out_reg(node, 0);
2693 bemit_unop(node, code, reg_gp_map[out->index], input);
2696 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2698 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2701 bemit8(size == 8 ? code : code + 1);
2702 bemit_mod_am(ext, node);
2705 static void bemit_immediate(const ir_node *node, bool relative)
2707 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2708 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2711 static void bemit_copy(const ir_node *copy)
2713 const arch_register_t *in = get_in_reg(copy, 0);
2714 const arch_register_t *out = get_out_reg(copy, 0);
2716 if (in == out || is_unknown_reg(in))
2718 /* copies of vf nodes aren't real... */
2719 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2722 if (get_irn_mode(copy) == mode_E) {
2725 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2727 bemit_modrr(in, out);
2731 static void bemit_perm(const ir_node *node)
2733 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2734 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2735 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2737 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2739 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2740 if (in0->index == REG_EAX) {
2741 bemit8(0x90 + reg_gp_map[in1->index]);
2742 } else if (in1->index == REG_EAX) {
2743 bemit8(0x90 + reg_gp_map[in0->index]);
2746 bemit_modrr(in0, in1);
2748 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2749 panic("unimplemented"); // TODO implement
2750 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2751 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2752 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2753 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2755 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2758 panic("unexpected register class in be_Perm (%+F)", node);
2762 static void bemit_xor0(const ir_node *node)
2764 const arch_register_t *out = get_out_reg(node, 0);
2766 bemit_modrr(out, out);
2769 static void bemit_mov_const(const ir_node *node)
2771 const arch_register_t *out = get_out_reg(node, 0);
2772 bemit8(0xB8 + reg_gp_map[out->index]);
2773 bemit_immediate(node, false);
2777 * Creates a function for a Binop with 3 possible encodings.
2779 #define BINOP(op, op0, op1, op2, op2_ext) \
2780 static void bemit_ ## op(const ir_node *node) { \
2781 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2782 bemit_binop(node, op ## _codes); \
2785 /* insn def eax,imm imm */
2786 BINOP(add, 0x03, 0x05, 0x81, 0)
2787 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2788 BINOP(adc, 0x13, 0x15, 0x81, 2)
2789 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2790 BINOP(and, 0x23, 0x25, 0x81, 4)
2791 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2792 BINOP(xor, 0x33, 0x35, 0x81, 6)
2793 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2795 #define BINOPMEM(op, ext) \
2796 static void bemit_##op(const ir_node *node) \
2799 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2802 val = get_irn_n(node, n_ia32_unary_op); \
2803 if (is_ia32_Immediate(val)) { \
2804 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2805 int offset = attr->offset; \
2806 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2808 bemit_mod_am(ext, node); \
2812 bemit_mod_am(ext, node); \
2816 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2820 bemit8(ext << 3 | 1); \
2821 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2825 static void bemit_##op##8bit(const ir_node *node) \
2827 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2828 if (is_ia32_Immediate(val)) { \
2830 bemit_mod_am(ext, node); \
2831 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2834 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2846 * Creates a function for an Unop with code /ext encoding.
2848 #define UNOP(op, code, ext, input) \
2849 static void bemit_ ## op(const ir_node *node) { \
2850 bemit_unop(node, code, ext, input); \
2853 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2854 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2855 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2856 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2857 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2858 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2860 /* TODO: am support for IJmp */
2861 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2863 #define SHIFT(op, ext) \
2864 static void bemit_##op(const ir_node *node) \
2866 const arch_register_t *out = get_out_reg(node, 0); \
2867 ir_node *count = get_irn_n(node, 1); \
2868 if (is_ia32_Immediate(count)) { \
2869 int offset = get_ia32_immediate_attr_const(count)->offset; \
2870 if (offset == 1) { \
2872 bemit_modru(out, ext); \
2875 bemit_modru(out, ext); \
2880 bemit_modru(out, ext); \
2884 static void bemit_##op##mem(const ir_node *node) \
2887 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2890 count = get_irn_n(node, 1); \
2891 if (is_ia32_Immediate(count)) { \
2892 int offset = get_ia32_immediate_attr_const(count)->offset; \
2893 if (offset == 1) { \
2894 bemit8(size == 8 ? 0xD0 : 0xD1); \
2895 bemit_mod_am(ext, node); \
2897 bemit8(size == 8 ? 0xC0 : 0xC1); \
2898 bemit_mod_am(ext, node); \
2902 bemit8(size == 8 ? 0xD2 : 0xD3); \
2903 bemit_mod_am(ext, node); \
2913 static void bemit_shld(const ir_node *node)
2915 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2916 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2917 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2919 if (is_ia32_Immediate(count)) {
2921 bemit_modrr(out, in);
2922 bemit8(get_ia32_immediate_attr_const(count)->offset);
2925 bemit_modrr(out, in);
2929 static void bemit_shrd(const ir_node *node)
2931 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2932 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2933 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2935 if (is_ia32_Immediate(count)) {
2937 bemit_modrr(out, in);
2938 bemit8(get_ia32_immediate_attr_const(count)->offset);
2941 bemit_modrr(out, in);
2946 * binary emitter for setcc.
2948 static void bemit_setcc(const ir_node *node)
2950 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2952 pn_Cmp pnc = get_ia32_condcode(node);
2953 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
2954 if (pnc & ia32_pn_Cmp_float) {
2955 switch (pnc & 0x0f) {
2960 bemit_modrm8(REG_LOW, dreg);
2967 bemit_modrm8(REG_LOW, dreg);
2975 bemit8(0x90 | pnc2cc(pnc));
2976 bemit_modrm8(REG_LOW, dreg);
2981 bemit_modrm8(REG_HIGH, dreg);
2983 /* andb %>dreg, %<dreg */
2985 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2993 bemit8(0x90 | pnc2cc(pnc));
2994 bemit_modrm8(REG_LOW, dreg);
2999 bemit_modrm8(REG_HIGH, dreg);
3001 /* orb %>dreg, %<dreg */
3003 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
3012 bemit8(0x90 | pnc2cc(pnc));
3013 bemit_modrm8(REG_LOW, dreg);
3016 static void bemit_cmovcc(const ir_node *node)
3018 const ia32_attr_t *attr = get_ia32_attr_const(node);
3019 int ins_permuted = attr->data.ins_permuted;
3020 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
3021 pn_Cmp pnc = get_ia32_condcode(node);
3022 const arch_register_t *in_true;
3023 const arch_register_t *in_false;
3025 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
3027 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
3028 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
3030 /* should be same constraint fullfilled? */
3031 if (out == in_false) {
3032 /* yes -> nothing to do */
3033 } else if (out == in_true) {
3034 assert(get_ia32_op_type(node) == ia32_Normal);
3035 ins_permuted = !ins_permuted;
3039 bemit8(0x8B); // mov %in_false, %out
3040 bemit_modrr(in_false, out);
3044 pnc = ia32_get_negated_pnc(pnc);
3046 /* TODO: handling of Nans isn't correct yet */
3049 bemit8(0x40 | pnc2cc(pnc));
3050 if (get_ia32_op_type(node) == ia32_Normal) {
3051 bemit_modrr(in_true, out);
3053 bemit_mod_am(reg_gp_map[out->index], node);
3057 static void bemit_cmp(const ir_node *node)
3059 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
3065 right = get_irn_n(node, n_ia32_binary_right);
3066 if (is_ia32_Immediate(right)) {
3067 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
3068 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
3069 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
3072 if (attr->symconst != NULL) {
3075 /* check for sign extension */
3076 size = get_signed_imm_size(attr->offset);
3081 bemit8(0x81 | SIGNEXT_IMM);
3082 /* cmp has this special mode */
3083 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3084 bemit_mod_am(7, node);
3086 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3087 bemit_modru(reg, 7);
3089 bemit8((unsigned char)attr->offset);
3093 /* check for eax variant: this variant is shorter for 32bit immediates only */
3094 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3096 bemit_mod_am(7, node);
3098 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3099 if (reg->index == REG_EAX) {
3103 bemit_modru(reg, 7);
3106 if (ls_size == 16) {
3107 bemit16(attr->offset);
3109 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3113 panic("invalid imm size?!?");
3115 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3117 if (get_ia32_op_type(node) == ia32_Normal) {
3118 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3119 bemit_modrr(op2, out);
3121 bemit_mod_am(reg_gp_map[out->index], node);
3126 static void bemit_cmp8bit(const ir_node *node)
3128 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3129 if (is_ia32_Immediate(right)) {
3130 if (get_ia32_op_type(node) == ia32_Normal) {
3131 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3132 if (out->index == REG_EAX) {
3136 bemit_modru(out, 7);
3140 bemit_mod_am(7, node);
3142 bemit8(get_ia32_immediate_attr_const(right)->offset);
3144 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3146 if (get_ia32_op_type(node) == ia32_Normal) {
3147 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3148 bemit_modrr(out, in);
3150 bemit_mod_am(reg_gp_map[out->index], node);
3155 static void bemit_test8bit(const ir_node *node)
3157 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3158 if (is_ia32_Immediate(right)) {
3159 if (get_ia32_op_type(node) == ia32_Normal) {
3160 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3161 if (out->index == REG_EAX) {
3165 bemit_modru(out, 0);
3169 bemit_mod_am(0, node);
3171 bemit8(get_ia32_immediate_attr_const(right)->offset);
3173 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3175 if (get_ia32_op_type(node) == ia32_Normal) {
3176 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3177 bemit_modrr(out, in);
3179 bemit_mod_am(reg_gp_map[out->index], node);
3184 static void bemit_imul(const ir_node *node)
3186 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3187 /* Do we need the immediate form? */
3188 if (is_ia32_Immediate(right)) {
3189 int imm = get_ia32_immediate_attr_const(right)->offset;
3190 if (get_signed_imm_size(imm) == 1) {
3191 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3194 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3199 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3203 static void bemit_dec(const ir_node *node)
3205 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3206 bemit8(0x48 + reg_gp_map[out->index]);
3209 static void bemit_inc(const ir_node *node)
3211 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3212 bemit8(0x40 + reg_gp_map[out->index]);
3215 #define UNOPMEM(op, code, ext) \
3216 static void bemit_##op(const ir_node *node) \
3218 bemit_unop_mem(node, code, ext); \
3221 UNOPMEM(notmem, 0xF6, 2)
3222 UNOPMEM(negmem, 0xF6, 3)
3223 UNOPMEM(incmem, 0xFE, 0)
3224 UNOPMEM(decmem, 0xFE, 1)
3226 static void bemit_ldtls(const ir_node *node)
3228 const arch_register_t *out = get_out_reg(node, 0);
3230 bemit8(0x65); // gs:
3231 if (out->index == REG_EAX) {
3232 bemit8(0xA1); // movl 0, %eax
3234 bemit8(0x8B); // movl 0, %reg
3235 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3243 static void bemit_lea(const ir_node *node)
3245 const arch_register_t *out = get_out_reg(node, 0);
3247 bemit_mod_am(reg_gp_map[out->index], node);
3250 /* helper function for bemit_minus64bit */
3251 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3253 bemit8(0x8B); // movl %src, %dst
3254 bemit_modrr(src, dst);
3257 /* helper function for bemit_minus64bit */
3258 static void bemit_helper_neg(const arch_register_t *reg)
3260 bemit8(0xF7); // negl %reg
3261 bemit_modru(reg, 3);
3264 /* helper function for bemit_minus64bit */
3265 static void bemit_helper_sbb0(const arch_register_t *reg)
3267 bemit8(0x83); // sbbl $0, %reg
3268 bemit_modru(reg, 3);
3272 /* helper function for bemit_minus64bit */
3273 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3275 bemit8(0x1B); // sbbl %src, %dst
3276 bemit_modrr(src, dst);
3279 /* helper function for bemit_minus64bit */
3280 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3282 if (src->index == REG_EAX) {
3283 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3284 } else if (dst->index == REG_EAX) {
3285 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3287 bemit8(0x87); // xchgl %src, %dst
3288 bemit_modrr(src, dst);
3292 /* helper function for bemit_minus64bit */
3293 static void bemit_helper_zero(const arch_register_t *reg)
3295 bemit8(0x33); // xorl %reg, %reg
3296 bemit_modrr(reg, reg);
3299 static void bemit_minus64bit(const ir_node *node)
3301 const arch_register_t *in_lo = get_in_reg(node, 0);
3302 const arch_register_t *in_hi = get_in_reg(node, 1);
3303 const arch_register_t *out_lo = get_out_reg(node, 0);
3304 const arch_register_t *out_hi = get_out_reg(node, 1);
3306 if (out_lo == in_lo) {
3307 if (out_hi != in_hi) {
3308 /* a -> a, b -> d */
3311 /* a -> a, b -> b */
3314 } else if (out_lo == in_hi) {
3315 if (out_hi == in_lo) {
3316 /* a -> b, b -> a */
3317 bemit_helper_xchg(in_lo, in_hi);
3320 /* a -> b, b -> d */
3321 bemit_helper_mov(in_hi, out_hi);
3322 bemit_helper_mov(in_lo, out_lo);
3326 if (out_hi == in_lo) {
3327 /* a -> c, b -> a */
3328 bemit_helper_mov(in_lo, out_lo);
3330 } else if (out_hi == in_hi) {
3331 /* a -> c, b -> b */
3332 bemit_helper_mov(in_lo, out_lo);
3335 /* a -> c, b -> d */
3336 bemit_helper_mov(in_lo, out_lo);
3342 bemit_helper_neg( out_hi);
3343 bemit_helper_neg( out_lo);
3344 bemit_helper_sbb0(out_hi);
3348 bemit_helper_zero(out_hi);
3349 bemit_helper_neg( out_lo);
3350 bemit_helper_sbb( in_hi, out_hi);
3354 * Emit a single opcode.
3356 #define EMIT_SINGLEOP(op, code) \
3357 static void bemit_ ## op(const ir_node *node) { \
3362 //EMIT_SINGLEOP(daa, 0x27)
3363 //EMIT_SINGLEOP(das, 0x2F)
3364 //EMIT_SINGLEOP(aaa, 0x37)
3365 //EMIT_SINGLEOP(aas, 0x3F)
3366 //EMIT_SINGLEOP(nop, 0x90)
3367 EMIT_SINGLEOP(cwtl, 0x98)
3368 EMIT_SINGLEOP(cltd, 0x99)
3369 //EMIT_SINGLEOP(fwait, 0x9B)
3370 EMIT_SINGLEOP(sahf, 0x9E)
3371 //EMIT_SINGLEOP(popf, 0x9D)
3372 EMIT_SINGLEOP(leave, 0xC9)
3373 EMIT_SINGLEOP(int3, 0xCC)
3374 //EMIT_SINGLEOP(iret, 0xCF)
3375 //EMIT_SINGLEOP(xlat, 0xD7)
3376 //EMIT_SINGLEOP(lock, 0xF0)
3377 EMIT_SINGLEOP(rep, 0xF3)
3378 //EMIT_SINGLEOP(halt, 0xF4)
3379 EMIT_SINGLEOP(cmc, 0xF5)
3380 EMIT_SINGLEOP(stc, 0xF9)
3381 //EMIT_SINGLEOP(cli, 0xFA)
3382 //EMIT_SINGLEOP(sti, 0xFB)
3383 //EMIT_SINGLEOP(std, 0xFD)
3386 * Emits a MOV out, [MEM].
3388 static void bemit_load(const ir_node *node)
3390 const arch_register_t *out = get_out_reg(node, 0);
3392 if (out->index == REG_EAX) {
3393 ir_node *base = get_irn_n(node, n_ia32_base);
3394 int has_base = !is_ia32_NoReg_GP(base);
3395 ir_node *index = get_irn_n(node, n_ia32_index);
3396 int has_index = !is_ia32_NoReg_GP(index);
3397 if (!has_base && !has_index) {
3398 ir_entity *ent = get_ia32_am_sc(node);
3399 int offs = get_ia32_am_offs_int(node);
3400 /* load from constant address to EAX can be encoded
3403 bemit_entity(ent, 0, offs, false);
3408 bemit_mod_am(reg_gp_map[out->index], node);
3412 * Emits a MOV [mem], in.
3414 static void bemit_store(const ir_node *node)
3416 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3417 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3419 if (is_ia32_Immediate(value)) {
3422 bemit_mod_am(0, node);
3423 bemit8(get_ia32_immediate_attr_const(value)->offset);
3424 } else if (size == 16) {
3427 bemit_mod_am(0, node);
3428 bemit16(get_ia32_immediate_attr_const(value)->offset);
3431 bemit_mod_am(0, node);
3432 bemit_immediate(value, false);
3435 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3437 if (in->index == REG_EAX) {
3438 ir_node *base = get_irn_n(node, n_ia32_base);
3439 int has_base = !is_ia32_NoReg_GP(base);
3440 ir_node *index = get_irn_n(node, n_ia32_index);
3441 int has_index = !is_ia32_NoReg_GP(index);
3442 if (!has_base && !has_index) {
3443 ir_entity *ent = get_ia32_am_sc(node);
3444 int offs = get_ia32_am_offs_int(node);
3445 /* store to constant address from EAX can be encoded as
3446 * 0xA2/0xA3 [offset]*/
3454 bemit_entity(ent, 0, offs, false);
3466 bemit_mod_am(reg_gp_map[in->index], node);
3470 static void bemit_conv_i2i(const ir_node *node)
3472 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3481 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3482 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3483 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3489 static void bemit_push(const ir_node *node)
3491 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3493 if (is_ia32_Immediate(value)) {
3494 const ia32_immediate_attr_t *attr
3495 = get_ia32_immediate_attr_const(value);
3496 unsigned size = get_signed_imm_size(attr->offset);
3502 bemit8((unsigned char)attr->offset);
3507 bemit_immediate(value, false);
3510 } else if (is_ia32_NoReg_GP(value)) {
3512 bemit_mod_am(6, node);
3514 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3515 bemit8(0x50 + reg_gp_map[reg->index]);
3522 static void bemit_pop(const ir_node *node)
3524 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3525 bemit8(0x58 + reg_gp_map[reg->index]);
3528 static void bemit_popmem(const ir_node *node)
3531 bemit_mod_am(0, node);
3534 static void bemit_call(const ir_node *node)
3536 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3538 if (is_ia32_Immediate(proc)) {
3540 bemit_immediate(proc, true);
3542 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3546 static void bemit_jmp(const ir_node *dest_block)
3549 bemit_jmp_destination(dest_block);
3552 static void bemit_jump(const ir_node *node)
3554 if (can_be_fallthrough(node))
3557 bemit_jmp(get_cfop_target_block(node));
3560 static void bemit_jcc(int pnc, const ir_node *dest_block)
3562 unsigned char cc = pnc2cc(pnc);
3565 bemit_jmp_destination(dest_block);
3568 static void bemit_jp(bool odd, const ir_node *dest_block)
3572 bemit_jmp_destination(dest_block);
3575 static void bemit_ia32_jcc(const ir_node *node)
3577 int pnc = get_ia32_condcode(node);
3578 const ir_node *proj_true;
3579 const ir_node *proj_false;
3580 const ir_node *dest_true;
3581 const ir_node *dest_false;
3582 const ir_node *block;
3584 pnc = determine_final_pnc(node, 0, pnc);
3586 /* get both Projs */
3587 proj_true = get_proj(node, pn_ia32_Jcc_true);
3588 assert(proj_true && "Jcc without true Proj");
3590 proj_false = get_proj(node, pn_ia32_Jcc_false);
3591 assert(proj_false && "Jcc without false Proj");
3593 block = get_nodes_block(node);
3595 if (can_be_fallthrough(proj_true)) {
3596 /* exchange both proj's so the second one can be omitted */
3597 const ir_node *t = proj_true;
3599 proj_true = proj_false;
3601 pnc = ia32_get_negated_pnc(pnc);
3604 dest_true = get_cfop_target_block(proj_true);
3605 dest_false = get_cfop_target_block(proj_false);
3607 if (pnc & ia32_pn_Cmp_float) {
3608 /* Some floating point comparisons require a test of the parity flag,
3609 * which indicates that the result is unordered */
3612 bemit_jp(false, dest_true);
3617 bemit_jp(true, dest_true);
3623 /* we need a local label if the false proj is a fallthrough
3624 * as the falseblock might have no label emitted then */
3625 if (can_be_fallthrough(proj_false)) {
3627 bemit8(0x06); // jp + 6
3629 bemit_jp(false, dest_false);
3636 bemit_jp(false, dest_true);
3644 bemit_jcc(pnc, dest_true);
3647 /* the second Proj might be a fallthrough */
3648 if (can_be_fallthrough(proj_false)) {
3649 /* it's a fallthrough */
3651 bemit_jmp(dest_false);
3655 static void bemit_switchjmp(const ir_node *node)
3657 unsigned long interval;
3661 const arch_register_t *in;
3663 /* fill the table structure */
3664 generate_jump_table(&tbl, node);
3666 /* two-complement's magic make this work without overflow */
3667 interval = tbl.max_value - tbl.min_value;
3669 in = get_in_reg(node, 0);
3670 /* emit the table */
3671 if (get_signed_imm_size(interval) == 1) {
3672 bemit8(0x83); // cmpl $imm8, %in
3676 bemit8(0x81); // cmpl $imm32, %in
3680 bemit8(0x0F); // ja tbl.defProj
3682 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3684 if (tbl.num_branches > 1) {
3686 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3687 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3688 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3689 be_emit_irprintf("\t.long %s\n", tbl.label);
3691 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3692 be_emit_cstring(".align 4\n");
3693 be_emit_irprintf("%s:\n", tbl.label);
3695 last_value = tbl.branches[0].value;
3696 for (i = 0; i != tbl.num_branches; ++i) {
3697 while (last_value != tbl.branches[i].value) {
3698 ia32_emitf(tbl.defProj, ".long %L\n");
3701 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3704 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3706 /* one jump is enough */
3707 panic("switch only has one case");
3708 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3711 be_emit_write_line();
3719 static void bemit_return(const ir_node *node)
3721 unsigned pop = be_Return_get_pop(node);
3722 if (pop > 0 || be_Return_get_emit_pop(node)) {
3724 assert(pop <= 0xffff);
3731 static void bemit_subsp(const ir_node *node)
3733 const arch_register_t *out;
3736 /* mov %esp, %out */
3738 out = get_out_reg(node, 1);
3739 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3742 static void bemit_incsp(const ir_node *node)
3745 const arch_register_t *reg;
3749 offs = be_get_IncSP_offset(node);
3760 size = get_signed_imm_size(offs);
3761 bemit8(size == 1 ? 0x83 : 0x81);
3763 reg = get_out_reg(node, 0);
3764 bemit_modru(reg, ext);
3773 static void bemit_copybi(const ir_node *node)
3775 unsigned size = get_ia32_copyb_size(node);
3777 bemit8(0xA4); // movsb
3780 bemit8(0xA5); // movsw
3784 bemit8(0xA5); // movsl
3788 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3790 if (get_ia32_op_type(node) == ia32_Normal) {
3791 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3792 const arch_register_t *in1 = x87_attr->x87[0];
3793 const arch_register_t *in = x87_attr->x87[1];
3794 const arch_register_t *out = x87_attr->x87[2];
3798 } else if (out == in) {
3802 if (out->index == 0) {
3804 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3807 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3810 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3815 bemit_mod_am(code, node);
3819 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3821 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3822 const arch_register_t *out = x87_attr->x87[2];
3824 bemit8(code + out->index);
3827 static void bemit_fabs(const ir_node *node)
3835 static void bemit_fadd(const ir_node *node)
3837 bemit_fbinop(node, 0, 0);
3840 static void bemit_faddp(const ir_node *node)
3842 bemit_fbinopp(node, 0xC0);
3845 static void bemit_fchs(const ir_node *node)
3853 static void bemit_fdiv(const ir_node *node)
3855 bemit_fbinop(node, 6, 7);
3858 static void bemit_fdivp(const ir_node *node)
3860 bemit_fbinopp(node, 0xF8);
3863 static void bemit_fdivr(const ir_node *node)
3865 bemit_fbinop(node, 7, 6);
3868 static void bemit_fdivrp(const ir_node *node)
3870 bemit_fbinopp(node, 0xF0);
3873 static void bemit_fild(const ir_node *node)
3875 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3877 bemit8(0xDF); // filds
3878 bemit_mod_am(0, node);
3882 bemit8(0xDB); // fildl
3883 bemit_mod_am(0, node);
3887 bemit8(0xDF); // fildll
3888 bemit_mod_am(5, node);
3892 panic("invalid mode size");
3896 static void bemit_fist(const ir_node *node)
3898 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3900 bemit8(0xDF); // fists
3904 bemit8(0xDB); // fistl
3908 panic("invalid mode size");
3910 bemit_mod_am(2, node);
3913 static void bemit_fistp(const ir_node *node)
3915 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3917 bemit8(0xDF); // fistps
3918 bemit_mod_am(3, node);
3922 bemit8(0xDB); // fistpl
3923 bemit_mod_am(3, node);
3927 bemit8(0xDF); // fistpll
3928 bemit_mod_am(7, node);
3932 panic("invalid mode size");
3936 static void bemit_fld(const ir_node *node)
3938 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3940 bemit8(0xD9); // flds
3941 bemit_mod_am(0, node);
3945 bemit8(0xDD); // fldl
3946 bemit_mod_am(0, node);
3951 bemit8(0xDB); // fldt
3952 bemit_mod_am(5, node);
3956 panic("invalid mode size");
3960 static void bemit_fld1(const ir_node *node)
3964 bemit8(0xE8); // fld1
3967 static void bemit_fldcw(const ir_node *node)
3969 bemit8(0xD9); // fldcw
3970 bemit_mod_am(5, node);
3973 static void bemit_fldz(const ir_node *node)
3977 bemit8(0xEE); // fldz
3980 static void bemit_fmul(const ir_node *node)
3982 bemit_fbinop(node, 1, 1);
3985 static void bemit_fmulp(const ir_node *node)
3987 bemit_fbinopp(node, 0xC8);
3990 static void bemit_fpop(const ir_node *node)
3992 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3994 bemit8(0xD8 + attr->x87[0]->index);
3997 static void bemit_fpush(const ir_node *node)
3999 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4001 bemit8(0xC0 + attr->x87[0]->index);
4004 static void bemit_fpushcopy(const ir_node *node)
4006 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4008 bemit8(0xC0 + attr->x87[0]->index);
4011 static void bemit_fst(const ir_node *node)
4013 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4015 bemit8(0xD9); // fsts
4019 bemit8(0xDD); // fstl
4023 panic("invalid mode size");
4025 bemit_mod_am(2, node);
4028 static void bemit_fstp(const ir_node *node)
4030 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4032 bemit8(0xD9); // fstps
4033 bemit_mod_am(3, node);
4037 bemit8(0xDD); // fstpl
4038 bemit_mod_am(3, node);
4043 bemit8(0xDB); // fstpt
4044 bemit_mod_am(7, node);
4048 panic("invalid mode size");
4052 static void bemit_fsub(const ir_node *node)
4054 bemit_fbinop(node, 4, 5);
4057 static void bemit_fsubp(const ir_node *node)
4059 bemit_fbinopp(node, 0xE8);
4062 static void bemit_fsubr(const ir_node *node)
4064 bemit_fbinop(node, 5, 4);
4067 static void bemit_fsubrp(const ir_node *node)
4069 bemit_fbinopp(node, 0xE0);
4072 static void bemit_fnstcw(const ir_node *node)
4074 bemit8(0xD9); // fnstcw
4075 bemit_mod_am(7, node);
4078 static void bemit_fnstsw(void)
4080 bemit8(0xDF); // fnstsw %ax
4084 static void bemit_ftstfnstsw(const ir_node *node)
4088 bemit8(0xD9); // ftst
4093 static void bemit_fucomi(const ir_node *node)
4095 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4096 bemit8(0xDB); // fucomi
4097 bemit8(0xE8 + attr->x87[1]->index);
4100 static void bemit_fucomip(const ir_node *node)
4102 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4103 bemit8(0xDF); // fucomip
4104 bemit8(0xE8 + attr->x87[1]->index);
4107 static void bemit_fucomfnstsw(const ir_node *node)
4109 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4110 bemit8(0xDD); // fucom
4111 bemit8(0xE0 + attr->x87[1]->index);
4115 static void bemit_fucompfnstsw(const ir_node *node)
4117 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4118 bemit8(0xDD); // fucomp
4119 bemit8(0xE8 + attr->x87[1]->index);
4123 static void bemit_fucomppfnstsw(const ir_node *node)
4127 bemit8(0xDA); // fucompp
4132 static void bemit_fxch(const ir_node *node)
4134 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4136 bemit8(0xC8 + attr->x87[0]->index);
4140 * The type of a emitter function.
4142 typedef void (*emit_func) (const ir_node *);
4145 * Set a node emitter. Make it a bit more type safe.
4147 static void register_emitter(ir_op *op, emit_func func)
4149 op->ops.generic = (op_func) func;
4152 static void ia32_register_binary_emitters(void)
4154 /* first clear the generic function pointer for all ops */
4155 clear_irp_opcodes_generic_func();
4157 /* benode emitter */
4158 register_emitter(op_be_Copy, bemit_copy);
4159 register_emitter(op_be_CopyKeep, bemit_copy);
4160 register_emitter(op_be_IncSP, bemit_incsp);
4161 register_emitter(op_be_Perm, bemit_perm);
4162 register_emitter(op_be_Return, bemit_return);
4163 register_emitter(op_ia32_Adc, bemit_adc);
4164 register_emitter(op_ia32_Add, bemit_add);
4165 register_emitter(op_ia32_AddMem, bemit_addmem);
4166 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4167 register_emitter(op_ia32_And, bemit_and);
4168 register_emitter(op_ia32_AndMem, bemit_andmem);
4169 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4170 register_emitter(op_ia32_Breakpoint, bemit_int3);
4171 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4172 register_emitter(op_ia32_Call, bemit_call);
4173 register_emitter(op_ia32_Cltd, bemit_cltd);
4174 register_emitter(op_ia32_Cmc, bemit_cmc);
4175 register_emitter(op_ia32_Cmp, bemit_cmp);
4176 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4177 register_emitter(op_ia32_Const, bemit_mov_const);
4178 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4179 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4180 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4181 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4182 register_emitter(op_ia32_Dec, bemit_dec);
4183 register_emitter(op_ia32_DecMem, bemit_decmem);
4184 register_emitter(op_ia32_Div, bemit_div);
4185 register_emitter(op_ia32_FldCW, bemit_fldcw);
4186 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4187 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4188 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4189 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4190 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4191 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4192 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4193 register_emitter(op_ia32_IDiv, bemit_idiv);
4194 register_emitter(op_ia32_IJmp, bemit_ijmp);
4195 register_emitter(op_ia32_IMul, bemit_imul);
4196 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4197 register_emitter(op_ia32_Inc, bemit_inc);
4198 register_emitter(op_ia32_IncMem, bemit_incmem);
4199 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4200 register_emitter(op_ia32_Jmp, bemit_jump);
4201 register_emitter(op_ia32_LdTls, bemit_ldtls);
4202 register_emitter(op_ia32_Lea, bemit_lea);
4203 register_emitter(op_ia32_Leave, bemit_leave);
4204 register_emitter(op_ia32_Load, bemit_load);
4205 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4206 register_emitter(op_ia32_Mul, bemit_mul);
4207 register_emitter(op_ia32_Neg, bemit_neg);
4208 register_emitter(op_ia32_NegMem, bemit_negmem);
4209 register_emitter(op_ia32_Not, bemit_not);
4210 register_emitter(op_ia32_NotMem, bemit_notmem);
4211 register_emitter(op_ia32_Or, bemit_or);
4212 register_emitter(op_ia32_OrMem, bemit_ormem);
4213 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4214 register_emitter(op_ia32_Pop, bemit_pop);
4215 register_emitter(op_ia32_PopEbp, bemit_pop);
4216 register_emitter(op_ia32_PopMem, bemit_popmem);
4217 register_emitter(op_ia32_Push, bemit_push);
4218 register_emitter(op_ia32_RepPrefix, bemit_rep);
4219 register_emitter(op_ia32_Rol, bemit_rol);
4220 register_emitter(op_ia32_RolMem, bemit_rolmem);
4221 register_emitter(op_ia32_Ror, bemit_ror);
4222 register_emitter(op_ia32_RorMem, bemit_rormem);
4223 register_emitter(op_ia32_Sahf, bemit_sahf);
4224 register_emitter(op_ia32_Sar, bemit_sar);
4225 register_emitter(op_ia32_SarMem, bemit_sarmem);
4226 register_emitter(op_ia32_Sbb, bemit_sbb);
4227 register_emitter(op_ia32_Setcc, bemit_setcc);
4228 register_emitter(op_ia32_Shl, bemit_shl);
4229 register_emitter(op_ia32_ShlD, bemit_shld);
4230 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4231 register_emitter(op_ia32_Shr, bemit_shr);
4232 register_emitter(op_ia32_ShrD, bemit_shrd);
4233 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4234 register_emitter(op_ia32_Stc, bemit_stc);
4235 register_emitter(op_ia32_Store, bemit_store);
4236 register_emitter(op_ia32_Store8Bit, bemit_store);
4237 register_emitter(op_ia32_Sub, bemit_sub);
4238 register_emitter(op_ia32_SubMem, bemit_submem);
4239 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4240 register_emitter(op_ia32_SubSP, bemit_subsp);
4241 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4242 register_emitter(op_ia32_Test, bemit_test);
4243 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4244 register_emitter(op_ia32_Xor, bemit_xor);
4245 register_emitter(op_ia32_Xor0, bemit_xor0);
4246 register_emitter(op_ia32_XorMem, bemit_xormem);
4247 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4248 register_emitter(op_ia32_fabs, bemit_fabs);
4249 register_emitter(op_ia32_fadd, bemit_fadd);
4250 register_emitter(op_ia32_faddp, bemit_faddp);
4251 register_emitter(op_ia32_fchs, bemit_fchs);
4252 register_emitter(op_ia32_fdiv, bemit_fdiv);
4253 register_emitter(op_ia32_fdivp, bemit_fdivp);
4254 register_emitter(op_ia32_fdivr, bemit_fdivr);
4255 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4256 register_emitter(op_ia32_fild, bemit_fild);
4257 register_emitter(op_ia32_fist, bemit_fist);
4258 register_emitter(op_ia32_fistp, bemit_fistp);
4259 register_emitter(op_ia32_fld, bemit_fld);
4260 register_emitter(op_ia32_fld1, bemit_fld1);
4261 register_emitter(op_ia32_fldz, bemit_fldz);
4262 register_emitter(op_ia32_fmul, bemit_fmul);
4263 register_emitter(op_ia32_fmulp, bemit_fmulp);
4264 register_emitter(op_ia32_fpop, bemit_fpop);
4265 register_emitter(op_ia32_fpush, bemit_fpush);
4266 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4267 register_emitter(op_ia32_fst, bemit_fst);
4268 register_emitter(op_ia32_fstp, bemit_fstp);
4269 register_emitter(op_ia32_fsub, bemit_fsub);
4270 register_emitter(op_ia32_fsubp, bemit_fsubp);
4271 register_emitter(op_ia32_fsubr, bemit_fsubr);
4272 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4273 register_emitter(op_ia32_fxch, bemit_fxch);
4275 /* ignore the following nodes */
4276 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4277 register_emitter(op_be_Barrier, emit_Nothing);
4278 register_emitter(op_be_Keep, emit_Nothing);
4279 register_emitter(op_be_Start, emit_Nothing);
4280 register_emitter(op_Phi, emit_Nothing);
4281 register_emitter(op_Start, emit_Nothing);
4284 static void gen_binary_block(ir_node *block)
4288 ia32_emit_block_header(block);
4290 /* emit the contents of the block */
4291 sched_foreach(block, node) {
4292 ia32_emit_node(node);
4296 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
4298 ir_entity *entity = get_irg_entity(irg);
4304 ia32_register_binary_emitters();
4306 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4308 /* we use links to point to target blocks */
4309 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4310 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4312 /* initialize next block links */
4313 n = ARR_LEN(cg->blk_sched);
4314 for (i = 0; i < n; ++i) {
4315 ir_node *block = cg->blk_sched[i];
4316 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4318 set_irn_link(block, prev);
4321 for (i = 0; i < n; ++i) {
4322 ir_node *block = cg->blk_sched[i];
4323 gen_binary_block(block);
4326 be_gas_emit_function_epilog(entity);
4327 be_dbg_method_end();
4329 be_emit_write_line();
4331 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4337 void ia32_init_emitter(void)
4339 lc_opt_entry_t *be_grp;
4340 lc_opt_entry_t *ia32_grp;
4342 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4343 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4345 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4349 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");