2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
42 #include "raw_bitset.h"
45 #include "../besched_t.h"
46 #include "../benode_t.h"
48 #include "../be_dbgout.h"
49 #include "../beemitter.h"
50 #include "../begnuas.h"
51 #include "../beirg_t.h"
52 #include "../be_dbgout.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
72 static char pic_base_label[128];
73 static ir_label_t exc_label_id;
74 static int mark_spill_reload = 0;
76 /** Return the next block in Block schedule */
77 static ir_node *get_prev_block_sched(const ir_node *block)
79 return get_irn_link(block);
82 /** Checks if the current block is a fall-through target. */
83 static int is_fallthrough(const ir_node *cfgpred)
87 if (!is_Proj(cfgpred))
89 pred = get_Proj_pred(cfgpred);
90 if (is_ia32_SwitchJmp(pred))
97 * returns non-zero if the given block needs a label
98 * because of being a jump-target (and not a fall-through)
100 static int block_needs_label(const ir_node *block)
103 int n_cfgpreds = get_Block_n_cfgpreds(block);
105 if (n_cfgpreds == 0) {
107 } else if (n_cfgpreds == 1) {
108 ir_node *cfgpred = get_Block_cfgpred(block, 0);
109 ir_node *cfgpred_block = get_nodes_block(cfgpred);
111 if (get_prev_block_sched(block) == cfgpred_block
112 && is_fallthrough(cfgpred)) {
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
126 const arch_register_t *reg = NULL;
128 assert(get_irn_arity(irn) > pos && "Invalid IN position");
130 /* The out register of the operator at position pos is the
131 in register we need. */
132 op = get_irn_n(irn, pos);
134 reg = arch_get_irn_register(op);
136 assert(reg && "no in register found");
138 if (reg == &ia32_gp_regs[REG_GP_NOREG])
139 panic("trying to emit noreg for %+F input %d", irn, pos);
141 /* in case of unknown register: just return a valid register */
142 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
143 const arch_register_req_t *req = arch_get_register_req(irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = arch_irn_get_register(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
215 * Emit the name of the 8bit low register
217 static void emit_8bit_register(const arch_register_t *reg)
219 const char *reg_name = arch_register_get_name(reg);
222 be_emit_char(reg_name[1]);
227 * Emit the name of the 8bit high register
229 static void emit_8bit_register_high(const arch_register_t *reg)
231 const char *reg_name = arch_register_get_name(reg);
234 be_emit_char(reg_name[1]);
238 static void emit_16bit_register(const arch_register_t *reg)
240 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
243 be_emit_string(reg_name);
247 * emit a register, possible shortened by a mode
249 * @param reg the register
250 * @param mode the mode of the register or NULL for full register
252 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
254 const char *reg_name;
257 int size = get_mode_size_bits(mode);
259 case 8: emit_8bit_register(reg); return;
260 case 16: emit_16bit_register(reg); return;
262 assert(mode_is_float(mode) || size == 32);
265 reg_name = arch_register_get_name(reg);
268 be_emit_string(reg_name);
271 void ia32_emit_source_register(const ir_node *node, int pos)
273 const arch_register_t *reg = get_in_reg(node, pos);
275 emit_register(reg, NULL);
278 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
282 set_entity_backend_marked(entity, 1);
283 id = get_entity_ld_ident(entity);
286 if (get_entity_owner(entity) == get_tls_type()) {
287 if (get_entity_visibility(entity) == visibility_external_allocated) {
288 be_emit_cstring("@INDNTPOFF");
290 be_emit_cstring("@NTPOFF");
294 if (!no_pic_adjust && do_pic) {
295 /* TODO: only do this when necessary */
297 be_emit_string(pic_base_label);
301 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
303 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
305 if (attr->symconst != NULL) {
308 ia32_emit_entity(attr->symconst, 0);
310 if (attr->symconst == NULL || attr->offset != 0) {
311 if (attr->symconst != NULL) {
312 be_emit_irprintf("%+d", attr->offset);
314 be_emit_irprintf("0x%X", attr->offset);
319 static void emit_ia32_Immediate(const ir_node *node)
322 emit_ia32_Immediate_no_prefix(node);
325 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
327 const arch_register_t *reg;
328 const ir_node *in = get_irn_n(node, pos);
329 if (is_ia32_Immediate(in)) {
330 emit_ia32_Immediate(in);
334 reg = get_in_reg(node, pos);
335 emit_8bit_register(reg);
338 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
340 const arch_register_t *reg = get_in_reg(node, pos);
341 emit_8bit_register_high(reg);
344 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
346 const arch_register_t *reg;
347 const ir_node *in = get_irn_n(node, pos);
348 if (is_ia32_Immediate(in)) {
349 emit_ia32_Immediate(in);
353 reg = get_in_reg(node, pos);
354 emit_16bit_register(reg);
357 void ia32_emit_dest_register(const ir_node *node, int pos)
359 const arch_register_t *reg = get_out_reg(node, pos);
361 emit_register(reg, NULL);
364 void ia32_emit_dest_register_size(const ir_node *node, int pos)
366 const arch_register_t *reg = get_out_reg(node, pos);
368 emit_register(reg, get_ia32_ls_mode(node));
371 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
373 const arch_register_t *reg = get_out_reg(node, pos);
375 emit_register(reg, mode_Bu);
378 void ia32_emit_x87_register(const ir_node *node, int pos)
380 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
384 be_emit_string(attr->x87[pos]->name);
387 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
389 assert(mode_is_int(mode) || mode_is_reference(mode));
390 switch (get_mode_size_bits(mode)) {
391 case 8: be_emit_char('b'); return;
392 case 16: be_emit_char('w'); return;
393 case 32: be_emit_char('l'); return;
394 /* gas docu says q is the suffix but gcc, objdump and icc use ll
396 case 64: be_emit_cstring("ll"); return;
398 panic("Can't output mode_suffix for %+F", mode);
401 void ia32_emit_mode_suffix(const ir_node *node)
403 ir_mode *mode = get_ia32_ls_mode(node);
407 ia32_emit_mode_suffix_mode(mode);
410 void ia32_emit_x87_mode_suffix(const ir_node *node)
414 /* we only need to emit the mode on address mode */
415 if (get_ia32_op_type(node) == ia32_Normal)
418 mode = get_ia32_ls_mode(node);
419 assert(mode != NULL);
421 if (mode_is_float(mode)) {
422 switch (get_mode_size_bits(mode)) {
423 case 32: be_emit_char('s'); return;
424 case 64: be_emit_char('l'); return;
426 case 96: be_emit_char('t'); return;
429 assert(mode_is_int(mode));
430 switch (get_mode_size_bits(mode)) {
431 case 16: be_emit_char('s'); return;
432 case 32: be_emit_char('l'); return;
433 /* gas docu says q is the suffix but gcc, objdump and icc use ll
435 case 64: be_emit_cstring("ll"); return;
438 panic("Can't output mode_suffix for %+F", mode);
441 static char get_xmm_mode_suffix(ir_mode *mode)
443 assert(mode_is_float(mode));
444 switch(get_mode_size_bits(mode)) {
447 default: panic("Invalid XMM mode");
451 void ia32_emit_xmm_mode_suffix(const ir_node *node)
453 ir_mode *mode = get_ia32_ls_mode(node);
454 assert(mode != NULL);
456 be_emit_char(get_xmm_mode_suffix(mode));
459 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
461 ir_mode *mode = get_ia32_ls_mode(node);
462 assert(mode != NULL);
463 be_emit_char(get_xmm_mode_suffix(mode));
466 void ia32_emit_extend_suffix(const ir_node *node)
468 ir_mode *mode = get_ia32_ls_mode(node);
469 if (get_mode_size_bits(mode) == 32)
471 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
472 ia32_emit_mode_suffix_mode(mode);
475 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
477 ir_node *in = get_irn_n(node, pos);
478 if (is_ia32_Immediate(in)) {
479 emit_ia32_Immediate(in);
481 const ir_mode *mode = get_ia32_ls_mode(node);
482 const arch_register_t *reg = get_in_reg(node, pos);
483 emit_register(reg, mode);
488 * Returns the target block for a control flow node.
490 static ir_node *get_cfop_target_block(const ir_node *irn)
492 assert(get_irn_mode(irn) == mode_X);
493 return get_irn_link(irn);
497 * Emits a block label for the given block.
499 static void ia32_emit_block_name(const ir_node *block)
501 if (has_Block_label(block)) {
502 be_emit_string(be_gas_block_label_prefix());
503 be_emit_irprintf("%lu", get_Block_label(block));
505 be_emit_cstring(BLOCK_PREFIX);
506 be_emit_irprintf("%ld", get_irn_node_nr(block));
511 * Emits the target label for a control flow node.
513 static void ia32_emit_cfop_target(const ir_node *node)
515 ir_node *block = get_cfop_target_block(node);
516 ia32_emit_block_name(block);
520 * positive conditions for signed compares
522 static const char *const cmp2condition_s[] = {
523 NULL, /* always false */
530 NULL /* always true */
534 * positive conditions for unsigned compares
536 static const char *const cmp2condition_u[] = {
537 NULL, /* always false */
544 NULL /* always true */
547 static void ia32_emit_cmp_suffix(int pnc)
551 if (pnc == ia32_pn_Cmp_parity) {
555 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
556 str = cmp2condition_u[pnc & 7];
558 str = cmp2condition_s[pnc & 7];
564 typedef enum ia32_emit_mod_t {
565 EMIT_RESPECT_LS = 1U << 0,
566 EMIT_ALTERNATE_AM = 1U << 1,
571 * fmt parameter output
572 * ---- ---------------------- ---------------------------------------------
574 * %AM <node> address mode of the node
575 * %AR const arch_register_t* address mode of the node or register
576 * %ASx <node> address mode of the node or source register x
577 * %Dx <node> destination register x
578 * %I <node> immediate of the node
579 * %L <node> control flow target of the node
580 * %M <node> mode suffix of the node
581 * %P int condition code
582 * %R const arch_register_t* register
583 * %Sx <node> source register x
584 * %s const char* string
585 * %u unsigned int unsigned int
586 * %d signed int signed int
589 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
590 * * modifier does not prefix immediates with $, but AM with *
591 * l modifier for %lu and %ld
593 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
599 const char *start = fmt;
600 ia32_emit_mod_t mod = 0;
602 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
605 be_emit_string_len(start, fmt - start);
609 be_emit_finish_line_gas(node);
621 mod |= EMIT_ALTERNATE_AM;
626 mod |= EMIT_RESPECT_LS;
643 if (mod & EMIT_ALTERNATE_AM)
649 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
650 if (mod & EMIT_ALTERNATE_AM)
652 if (get_ia32_op_type(node) == ia32_AddrModeS) {
655 emit_register(reg, NULL);
661 if (get_ia32_op_type(node) == ia32_AddrModeS) {
662 if (mod & EMIT_ALTERNATE_AM)
667 assert(get_ia32_op_type(node) == ia32_Normal);
672 default: goto unknown;
679 const arch_register_t *reg;
681 if (*fmt < '0' || '9' <= *fmt)
685 reg = get_out_reg(node, pos);
686 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
691 if (!(mod & EMIT_ALTERNATE_AM))
693 emit_ia32_Immediate_no_prefix(node);
697 ia32_emit_cfop_target(node);
701 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
706 int pnc = va_arg(ap, int);
707 ia32_emit_cmp_suffix(pnc);
712 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
713 emit_register(reg, NULL);
722 if (*fmt < '0' || '9' <= *fmt)
726 in = get_irn_n(node, pos);
727 if (is_ia32_Immediate(in)) {
728 if (!(mod & EMIT_ALTERNATE_AM))
730 emit_ia32_Immediate_no_prefix(in);
732 const arch_register_t *reg;
734 if (mod & EMIT_ALTERNATE_AM)
736 reg = get_in_reg(node, pos);
737 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
743 const char *str = va_arg(ap, const char*);
749 if (mod & EMIT_LONG) {
750 unsigned long num = va_arg(ap, unsigned long);
751 be_emit_irprintf("%lu", num);
753 unsigned num = va_arg(ap, unsigned);
754 be_emit_irprintf("%u", num);
759 if (mod & EMIT_LONG) {
760 long num = va_arg(ap, long);
761 be_emit_irprintf("%ld", num);
763 int num = va_arg(ap, int);
764 be_emit_irprintf("%d", num);
770 panic("unknown format conversion in ia32_emitf()");
778 * Emits registers and/or address mode of a binary operation.
780 void ia32_emit_binop(const ir_node *node)
782 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
783 ia32_emitf(node, "%#S4, %#AS3");
785 ia32_emitf(node, "%#AS4, %#S3");
790 * Emits registers and/or address mode of a binary operation.
792 void ia32_emit_x87_binop(const ir_node *node)
794 switch(get_ia32_op_type(node)) {
797 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
798 const arch_register_t *in1 = x87_attr->x87[0];
799 const arch_register_t *in = x87_attr->x87[1];
800 const arch_register_t *out = x87_attr->x87[2];
804 } else if (out == in) {
809 be_emit_string(arch_register_get_name(in));
810 be_emit_cstring(", %");
811 be_emit_string(arch_register_get_name(out));
819 assert(0 && "unsupported op type");
824 * Emits registers and/or address mode of a unary operation.
826 void ia32_emit_unop(const ir_node *node, int pos)
830 ia32_emitf(node, fmt);
834 * Emits address mode.
836 void ia32_emit_am(const ir_node *node)
838 ir_entity *ent = get_ia32_am_sc(node);
839 int offs = get_ia32_am_offs_int(node);
840 ir_node *base = get_irn_n(node, n_ia32_base);
841 int has_base = !is_ia32_NoReg_GP(base);
842 ir_node *index = get_irn_n(node, n_ia32_index);
843 int has_index = !is_ia32_NoReg_GP(index);
845 /* just to be sure... */
846 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
850 if (is_ia32_am_sc_sign(node))
852 ia32_emit_entity(ent, 0);
855 /* also handle special case if nothing is set */
856 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
858 be_emit_irprintf("%+d", offs);
860 be_emit_irprintf("%d", offs);
864 if (has_base || has_index) {
869 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
870 emit_register(reg, NULL);
873 /* emit index + scale */
875 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
878 emit_register(reg, NULL);
880 scale = get_ia32_am_scale(node);
882 be_emit_irprintf(",%d", 1 << scale);
889 static void emit_ia32_IMul(const ir_node *node)
891 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
892 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
894 /* do we need the 3-address form? */
895 if (is_ia32_NoReg_GP(left) ||
896 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
897 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
899 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
904 * walks up a tree of copies/perms/spills/reloads to find the original value
905 * that is moved around
907 static ir_node *find_original_value(ir_node *node)
909 if (irn_visited(node))
912 mark_irn_visited(node);
913 if (be_is_Copy(node)) {
914 return find_original_value(be_get_Copy_op(node));
915 } else if (be_is_CopyKeep(node)) {
916 return find_original_value(be_get_CopyKeep_op(node));
917 } else if (is_Proj(node)) {
918 ir_node *pred = get_Proj_pred(node);
919 if (be_is_Perm(pred)) {
920 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
921 } else if (be_is_MemPerm(pred)) {
922 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
923 } else if (is_ia32_Load(pred)) {
924 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
928 } else if (is_ia32_Store(node)) {
929 return find_original_value(get_irn_n(node, n_ia32_Store_val));
930 } else if (is_Phi(node)) {
932 arity = get_irn_arity(node);
933 for (i = 0; i < arity; ++i) {
934 ir_node *in = get_irn_n(node, i);
935 ir_node *res = find_original_value(in);
946 static int determine_final_pnc(const ir_node *node, int flags_pos,
949 ir_node *flags = get_irn_n(node, flags_pos);
950 const ia32_attr_t *flags_attr;
951 flags = skip_Proj(flags);
953 if (is_ia32_Sahf(flags)) {
954 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
955 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
956 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
957 inc_irg_visited(current_ir_graph);
958 cmp = find_original_value(cmp);
960 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
961 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
964 flags_attr = get_ia32_attr_const(cmp);
965 if (flags_attr->data.ins_permuted)
966 pnc = get_mirrored_pnc(pnc);
967 pnc |= ia32_pn_Cmp_float;
968 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
969 || is_ia32_Fucompi(flags)) {
970 flags_attr = get_ia32_attr_const(flags);
972 if (flags_attr->data.ins_permuted)
973 pnc = get_mirrored_pnc(pnc);
974 pnc |= ia32_pn_Cmp_float;
976 flags_attr = get_ia32_attr_const(flags);
978 if (flags_attr->data.ins_permuted)
979 pnc = get_mirrored_pnc(pnc);
980 if (flags_attr->data.cmp_unsigned)
981 pnc |= ia32_pn_Cmp_unsigned;
987 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
989 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
990 return get_negated_pnc(pnc, mode);
993 void ia32_emit_cmp_suffix_node(const ir_node *node,
996 const ia32_attr_t *attr = get_ia32_attr_const(node);
998 pn_Cmp pnc = get_ia32_condcode(node);
1000 pnc = determine_final_pnc(node, flags_pos, pnc);
1001 if (attr->data.ins_permuted)
1002 pnc = ia32_get_negated_pnc(pnc);
1004 ia32_emit_cmp_suffix(pnc);
1008 * Emits an exception label for a given node.
1010 static void ia32_emit_exc_label(const ir_node *node)
1012 be_emit_string(be_gas_insn_label_prefix());
1013 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1017 * Returns the Proj with projection number proj and NOT mode_M
1019 static ir_node *get_proj(const ir_node *node, long proj)
1021 const ir_edge_t *edge;
1024 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1026 foreach_out_edge(node, edge) {
1027 src = get_edge_src_irn(edge);
1029 assert(is_Proj(src) && "Proj expected");
1030 if (get_irn_mode(src) == mode_M)
1033 if (get_Proj_proj(src) == proj)
1039 static int can_be_fallthrough(const ir_node *node)
1041 ir_node *target_block = get_cfop_target_block(node);
1042 ir_node *block = get_nodes_block(node);
1043 return get_prev_block_sched(target_block) == block;
1047 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1049 static void emit_ia32_Jcc(const ir_node *node)
1051 int need_parity_label = 0;
1052 const ir_node *proj_true;
1053 const ir_node *proj_false;
1054 const ir_node *block;
1055 pn_Cmp pnc = get_ia32_condcode(node);
1057 pnc = determine_final_pnc(node, 0, pnc);
1059 /* get both Projs */
1060 proj_true = get_proj(node, pn_ia32_Jcc_true);
1061 assert(proj_true && "Jcc without true Proj");
1063 proj_false = get_proj(node, pn_ia32_Jcc_false);
1064 assert(proj_false && "Jcc without false Proj");
1066 block = get_nodes_block(node);
1068 if (can_be_fallthrough(proj_true)) {
1069 /* exchange both proj's so the second one can be omitted */
1070 const ir_node *t = proj_true;
1072 proj_true = proj_false;
1074 pnc = ia32_get_negated_pnc(pnc);
1077 if (pnc & ia32_pn_Cmp_float) {
1078 /* Some floating point comparisons require a test of the parity flag,
1079 * which indicates that the result is unordered */
1082 ia32_emitf(proj_true, "\tjp %L\n");
1087 ia32_emitf(proj_true, "\tjnp %L\n");
1093 /* we need a local label if the false proj is a fallthrough
1094 * as the falseblock might have no label emitted then */
1095 if (can_be_fallthrough(proj_false)) {
1096 need_parity_label = 1;
1097 ia32_emitf(proj_false, "\tjp 1f\n");
1099 ia32_emitf(proj_false, "\tjp %L\n");
1106 ia32_emitf(proj_true, "\tjp %L\n");
1114 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1117 if (need_parity_label) {
1118 ia32_emitf(NULL, "1:\n");
1121 /* the second Proj might be a fallthrough */
1122 if (can_be_fallthrough(proj_false)) {
1123 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1125 ia32_emitf(proj_false, "\tjmp %L\n");
1129 static void emit_ia32_CMov(const ir_node *node)
1131 const ia32_attr_t *attr = get_ia32_attr_const(node);
1132 int ins_permuted = attr->data.ins_permuted;
1133 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1134 pn_Cmp pnc = get_ia32_condcode(node);
1135 const arch_register_t *in_true;
1136 const arch_register_t *in_false;
1138 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1140 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1141 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1143 /* should be same constraint fullfilled? */
1144 if (out == in_false) {
1145 /* yes -> nothing to do */
1146 } else if (out == in_true) {
1147 const arch_register_t *tmp;
1149 assert(get_ia32_op_type(node) == ia32_Normal);
1151 ins_permuted = !ins_permuted;
1158 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1162 pnc = ia32_get_negated_pnc(pnc);
1164 /* TODO: handling of Nans isn't correct yet */
1166 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1169 /*********************************************************
1172 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1173 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1174 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1175 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1178 *********************************************************/
1180 /* jump table entry (target and corresponding number) */
1181 typedef struct _branch_t {
1186 /* jump table for switch generation */
1187 typedef struct _jmp_tbl_t {
1188 ir_node *defProj; /**< default target */
1189 long min_value; /**< smallest switch case */
1190 long max_value; /**< largest switch case */
1191 long num_branches; /**< number of jumps */
1192 char *label; /**< label of the jump table */
1193 branch_t *branches; /**< jump array */
1197 * Compare two variables of type branch_t. Used to sort all switch cases
1199 static int ia32_cmp_branch_t(const void *a, const void *b)
1201 branch_t *b1 = (branch_t *)a;
1202 branch_t *b2 = (branch_t *)b;
1204 if (b1->value <= b2->value)
1211 * Emits code for a SwitchJmp (creates a jump table if
1212 * possible otherwise a cmp-jmp cascade). Port from
1215 static void emit_ia32_SwitchJmp(const ir_node *node)
1217 unsigned long interval;
1223 const ir_edge_t *edge;
1225 /* fill the table structure */
1226 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1227 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1229 tbl.num_branches = get_irn_n_edges(node) - 1;
1230 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1231 tbl.min_value = INT_MAX;
1232 tbl.max_value = INT_MIN;
1234 default_pn = get_ia32_condcode(node);
1236 /* go over all proj's and collect them */
1237 foreach_out_edge(node, edge) {
1238 proj = get_edge_src_irn(edge);
1239 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1241 pnc = get_Proj_proj(proj);
1243 /* check for default proj */
1244 if (pnc == default_pn) {
1245 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1248 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1249 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1251 /* create branch entry */
1252 tbl.branches[i].target = proj;
1253 tbl.branches[i].value = pnc;
1258 assert(i == tbl.num_branches);
1260 /* sort the branches by their number */
1261 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1263 /* two-complement's magic make this work without overflow */
1264 interval = tbl.max_value - tbl.min_value;
1266 /* emit the table */
1267 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1268 ia32_emitf(tbl.defProj, "\tja %L\n");
1270 if (tbl.num_branches > 1) {
1272 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1274 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1275 ia32_emitf(NULL, "\t.align 4\n");
1276 ia32_emitf(NULL, "%s:\n", tbl.label);
1278 last_value = tbl.branches[0].value;
1279 for (i = 0; i != tbl.num_branches; ++i) {
1280 while (last_value != tbl.branches[i].value) {
1281 ia32_emitf(tbl.defProj, ".long %L\n");
1284 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1287 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1289 /* one jump is enough */
1290 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1300 * Emits code for a unconditional jump.
1302 static void emit_Jmp(const ir_node *node)
1306 /* for now, the code works for scheduled and non-schedules blocks */
1307 block = get_nodes_block(node);
1309 /* we have a block schedule */
1310 if (can_be_fallthrough(node)) {
1311 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1313 ia32_emitf(node, "\tjmp %L\n");
1318 * Emit an inline assembler operand.
1320 * @param node the ia32_ASM node
1321 * @param s points to the operand (a %c)
1323 * @return pointer to the first char in s NOT in the current operand
1325 static const char* emit_asm_operand(const ir_node *node, const char *s)
1327 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1328 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1330 const arch_register_t *reg;
1331 const ia32_asm_reg_t *asm_regs = attr->register_map;
1332 const ia32_asm_reg_t *asm_reg;
1333 const char *reg_name;
1342 /* parse modifiers */
1345 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1370 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1377 sscanf(s, "%d%n", &num, &p);
1379 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1386 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1388 "Error: Custom assembler references invalid input/output (%+F)\n",
1392 asm_reg = & asm_regs[num];
1393 assert(asm_reg->valid);
1396 if (asm_reg->use_input == 0) {
1397 reg = get_out_reg(node, asm_reg->inout_pos);
1399 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1401 /* might be an immediate value */
1402 if (is_ia32_Immediate(pred)) {
1403 emit_ia32_Immediate(pred);
1406 reg = get_in_reg(node, asm_reg->inout_pos);
1410 "Warning: no register assigned for %d asm op (%+F)\n",
1415 if (asm_reg->memory) {
1420 if (modifier != 0) {
1424 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1427 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1430 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1433 panic("Invalid asm op modifier");
1435 be_emit_string(reg_name);
1437 emit_register(reg, asm_reg->mode);
1440 if (asm_reg->memory) {
1448 * Emits code for an ASM pseudo op.
1450 static void emit_ia32_Asm(const ir_node *node)
1452 const void *gen_attr = get_irn_generic_attr_const(node);
1453 const ia32_asm_attr_t *attr
1454 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1455 ident *asm_text = attr->asm_text;
1456 const char *s = get_id_str(asm_text);
1458 ia32_emitf(node, "#APP\t\n");
1465 s = emit_asm_operand(node, s);
1471 ia32_emitf(NULL, "\n#NO_APP\n");
1474 /**********************************
1477 * | | ___ _ __ _ _| |_) |
1478 * | | / _ \| '_ \| | | | _ <
1479 * | |___| (_) | |_) | |_| | |_) |
1480 * \_____\___/| .__/ \__, |____/
1483 **********************************/
1486 * Emit movsb/w instructions to make mov count divideable by 4
1488 static void emit_CopyB_prolog(unsigned size)
1491 ia32_emitf(NULL, "\tmovsb\n");
1493 ia32_emitf(NULL, "\tmovsw\n");
1497 * Emit rep movsd instruction for memcopy.
1499 static void emit_ia32_CopyB(const ir_node *node)
1501 unsigned size = get_ia32_copyb_size(node);
1503 emit_CopyB_prolog(size);
1504 ia32_emitf(node, "\trep movsd\n");
1508 * Emits unrolled memcopy.
1510 static void emit_ia32_CopyB_i(const ir_node *node)
1512 unsigned size = get_ia32_copyb_size(node);
1514 emit_CopyB_prolog(size);
1518 ia32_emitf(NULL, "\tmovsd\n");
1524 /***************************
1528 * | | / _ \| '_ \ \ / /
1529 * | |___| (_) | | | \ V /
1530 * \_____\___/|_| |_|\_/
1532 ***************************/
1535 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1537 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1540 ir_mode *ls_mode = get_ia32_ls_mode(node);
1541 int ls_bits = get_mode_size_bits(ls_mode);
1542 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1544 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1547 static void emit_ia32_Conv_I2FP(const ir_node *node)
1549 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1552 static void emit_ia32_Conv_FP2I(const ir_node *node)
1554 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1557 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1559 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1563 * Emits code for an Int conversion.
1565 static void emit_ia32_Conv_I2I(const ir_node *node)
1567 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1568 int signed_mode = mode_is_signed(smaller_mode);
1569 const char *sign_suffix;
1571 assert(!mode_is_float(smaller_mode));
1573 sign_suffix = signed_mode ? "s" : "z";
1574 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1580 static void emit_ia32_Call(const ir_node *node)
1582 /* Special case: Call must not have its immediates prefixed by $, instead
1583 * address mode is prefixed by *. */
1584 ia32_emitf(node, "\tcall %*AS3\n");
1588 /*******************************************
1591 * | |__ ___ _ __ ___ __| | ___ ___
1592 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1593 * | |_) | __/ | | | (_) | (_| | __/\__ \
1594 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1596 *******************************************/
1599 * Emits code to increase stack pointer.
1601 static void emit_be_IncSP(const ir_node *node)
1603 int offs = be_get_IncSP_offset(node);
1609 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1611 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1616 * Emits code for Copy/CopyKeep.
1618 static void Copy_emitter(const ir_node *node, const ir_node *op)
1620 const arch_register_t *in = arch_get_irn_register(op);
1621 const arch_register_t *out = arch_get_irn_register(node);
1626 if (is_unknown_reg(in))
1628 /* copies of vf nodes aren't real... */
1629 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1632 if (get_irn_mode(node) == mode_E) {
1633 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1635 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1639 static void emit_be_Copy(const ir_node *node)
1641 Copy_emitter(node, be_get_Copy_op(node));
1644 static void emit_be_CopyKeep(const ir_node *node)
1646 Copy_emitter(node, be_get_CopyKeep_op(node));
1650 * Emits code for exchange.
1652 static void emit_be_Perm(const ir_node *node)
1654 const arch_register_t *in0, *in1;
1655 const arch_register_class_t *cls0, *cls1;
1657 in0 = arch_get_irn_register(get_irn_n(node, 0));
1658 in1 = arch_get_irn_register(get_irn_n(node, 1));
1660 cls0 = arch_register_get_class(in0);
1661 cls1 = arch_register_get_class(in1);
1663 assert(cls0 == cls1 && "Register class mismatch at Perm");
1665 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1666 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1667 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1668 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1669 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1670 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1671 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1673 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1676 panic("unexpected register class in be_Perm (%+F)", node);
1681 * Emits code for Constant loading.
1683 static void emit_ia32_Const(const ir_node *node)
1685 ia32_emitf(node, "\tmovl %I, %D0\n");
1689 * Emits code to load the TLS base
1691 static void emit_ia32_LdTls(const ir_node *node)
1693 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1696 /* helper function for emit_ia32_Minus64Bit */
1697 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1699 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1702 /* helper function for emit_ia32_Minus64Bit */
1703 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1705 ia32_emitf(node, "\tnegl %R\n", reg);
1708 /* helper function for emit_ia32_Minus64Bit */
1709 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1711 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1714 /* helper function for emit_ia32_Minus64Bit */
1715 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1717 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1720 /* helper function for emit_ia32_Minus64Bit */
1721 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1723 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1726 /* helper function for emit_ia32_Minus64Bit */
1727 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1729 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1732 static void emit_ia32_Minus64Bit(const ir_node *node)
1734 const arch_register_t *in_lo = get_in_reg(node, 0);
1735 const arch_register_t *in_hi = get_in_reg(node, 1);
1736 const arch_register_t *out_lo = get_out_reg(node, 0);
1737 const arch_register_t *out_hi = get_out_reg(node, 1);
1739 if (out_lo == in_lo) {
1740 if (out_hi != in_hi) {
1741 /* a -> a, b -> d */
1744 /* a -> a, b -> b */
1747 } else if (out_lo == in_hi) {
1748 if (out_hi == in_lo) {
1749 /* a -> b, b -> a */
1750 emit_xchg(node, in_lo, in_hi);
1753 /* a -> b, b -> d */
1754 emit_mov(node, in_hi, out_hi);
1755 emit_mov(node, in_lo, out_lo);
1759 if (out_hi == in_lo) {
1760 /* a -> c, b -> a */
1761 emit_mov(node, in_lo, out_lo);
1763 } else if (out_hi == in_hi) {
1764 /* a -> c, b -> b */
1765 emit_mov(node, in_lo, out_lo);
1768 /* a -> c, b -> d */
1769 emit_mov(node, in_lo, out_lo);
1775 emit_neg( node, out_hi);
1776 emit_neg( node, out_lo);
1777 emit_sbb0(node, out_hi);
1781 emit_zero(node, out_hi);
1782 emit_neg( node, out_lo);
1783 emit_sbb( node, in_hi, out_hi);
1786 static void emit_ia32_GetEIP(const ir_node *node)
1788 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1789 ia32_emitf(NULL, "%s:\n", pic_base_label);
1790 ia32_emitf(node, "\tpopl %D0\n");
1793 static void emit_ia32_ClimbFrame(const ir_node *node)
1795 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1797 ia32_emitf(node, "\tmovl %S0, %D0\n");
1798 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1799 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1800 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1801 ia32_emitf(node, "\tdec %S1\n");
1802 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1805 static void emit_be_Return(const ir_node *node)
1807 unsigned pop = be_Return_get_pop(node);
1809 if (pop > 0 || be_Return_get_emit_pop(node)) {
1810 ia32_emitf(node, "\tret $%u\n", pop);
1812 ia32_emitf(node, "\tret\n");
1816 static void emit_Nothing(const ir_node *node)
1822 /***********************************************************************************
1825 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1826 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1827 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1828 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1830 ***********************************************************************************/
1833 * Enters the emitter functions for handled nodes into the generic
1834 * pointer of an opcode.
1836 static void ia32_register_emitters(void)
1838 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1839 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1840 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1841 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1842 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1843 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1845 /* first clear the generic function pointer for all ops */
1846 clear_irp_opcodes_generic_func();
1848 /* register all emitter functions defined in spec */
1849 ia32_register_spec_emitters();
1851 /* other ia32 emitter functions */
1852 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1857 IA32_EMIT(Conv_FP2FP);
1858 IA32_EMIT(Conv_FP2I);
1859 IA32_EMIT(Conv_I2FP);
1860 IA32_EMIT(Conv_I2I);
1867 IA32_EMIT(Minus64Bit);
1868 IA32_EMIT(SwitchJmp);
1869 IA32_EMIT(ClimbFrame);
1871 /* benode emitter */
1894 typedef void (*emit_func_ptr) (const ir_node *);
1897 * Assign and emit an exception label if the current instruction can fail.
1899 static void ia32_assign_exc_label(ir_node *node)
1901 /* assign a new ID to the instruction */
1902 set_ia32_exc_label_id(node, ++exc_label_id);
1904 ia32_emit_exc_label(node);
1906 be_emit_pad_comment();
1907 be_emit_cstring("/* exception to Block ");
1908 ia32_emit_cfop_target(node);
1909 be_emit_cstring(" */\n");
1910 be_emit_write_line();
1914 * Emits code for a node.
1916 static void ia32_emit_node(ir_node *node)
1918 ir_op *op = get_irn_op(node);
1920 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1922 if (is_ia32_irn(node)) {
1923 if (get_ia32_exc_label(node)) {
1924 /* emit the exception label of this instruction */
1925 ia32_assign_exc_label(node);
1927 if (mark_spill_reload) {
1928 if (is_ia32_is_spill(node)) {
1929 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1931 if (is_ia32_is_reload(node)) {
1932 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1934 if (is_ia32_is_remat(node)) {
1935 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1939 if (op->ops.generic) {
1940 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1942 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1947 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1953 * Emits gas alignment directives
1955 static void ia32_emit_alignment(unsigned align, unsigned skip)
1957 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1961 * Emits gas alignment directives for Labels depended on cpu architecture.
1963 static void ia32_emit_align_label(void)
1965 unsigned align = ia32_cg_config.label_alignment;
1966 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1967 ia32_emit_alignment(align, maximum_skip);
1971 * Test whether a block should be aligned.
1972 * For cpus in the P4/Athlon class it is useful to align jump labels to
1973 * 16 bytes. However we should only do that if the alignment nops before the
1974 * label aren't executed more often than we have jumps to the label.
1976 static int should_align_block(const ir_node *block)
1978 static const double DELTA = .0001;
1979 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1980 ir_node *prev = get_prev_block_sched(block);
1982 double prev_freq = 0; /**< execfreq of the fallthrough block */
1983 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1986 if (exec_freq == NULL)
1988 if (ia32_cg_config.label_alignment_factor <= 0)
1991 block_freq = get_block_execfreq(exec_freq, block);
1992 if (block_freq < DELTA)
1995 n_cfgpreds = get_Block_n_cfgpreds(block);
1996 for(i = 0; i < n_cfgpreds; ++i) {
1997 const ir_node *pred = get_Block_cfgpred_block(block, i);
1998 double pred_freq = get_block_execfreq(exec_freq, pred);
2001 prev_freq += pred_freq;
2003 jmp_freq += pred_freq;
2007 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2010 jmp_freq /= prev_freq;
2012 return jmp_freq > ia32_cg_config.label_alignment_factor;
2016 * Emit the block header for a block.
2018 * @param block the block
2019 * @param prev_block the previous block
2021 static void ia32_emit_block_header(ir_node *block)
2023 ir_graph *irg = current_ir_graph;
2024 int need_label = block_needs_label(block);
2026 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2028 if (block == get_irg_end_block(irg))
2031 if (ia32_cg_config.label_alignment > 0) {
2032 /* align the current block if:
2033 * a) if should be aligned due to its execution frequency
2034 * b) there is no fall-through here
2036 if (should_align_block(block)) {
2037 ia32_emit_align_label();
2039 /* if the predecessor block has no fall-through,
2040 we can always align the label. */
2042 int has_fallthrough = 0;
2044 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2045 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2046 if (can_be_fallthrough(cfg_pred)) {
2047 has_fallthrough = 1;
2052 if (!has_fallthrough)
2053 ia32_emit_align_label();
2057 if (need_label || has_Block_label(block)) {
2058 ia32_emit_block_name(block);
2061 be_emit_pad_comment();
2062 be_emit_cstring(" /* ");
2064 be_emit_cstring("\t/* ");
2065 ia32_emit_block_name(block);
2066 be_emit_cstring(": ");
2069 be_emit_cstring("preds:");
2071 /* emit list of pred blocks in comment */
2072 arity = get_irn_arity(block);
2074 be_emit_cstring(" none");
2076 for (i = 0; i < arity; ++i) {
2077 ir_node *predblock = get_Block_cfgpred_block(block, i);
2078 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2081 if (exec_freq != NULL) {
2082 be_emit_irprintf(", freq: %f",
2083 get_block_execfreq(exec_freq, block));
2085 be_emit_cstring(" */\n");
2086 be_emit_write_line();
2090 * Walks over the nodes in a block connected by scheduling edges
2091 * and emits code for each node.
2093 static void ia32_gen_block(ir_node *block)
2097 ia32_emit_block_header(block);
2099 /* emit the contents of the block */
2100 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2101 sched_foreach(block, node) {
2102 ia32_emit_node(node);
2106 typedef struct exc_entry {
2107 ir_node *exc_instr; /** The instruction that can issue an exception. */
2108 ir_node *block; /** The block to call then. */
2113 * Sets labels for control flow nodes (jump target).
2114 * Links control predecessors to there destination blocks.
2116 static void ia32_gen_labels(ir_node *block, void *data)
2118 exc_entry **exc_list = data;
2122 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2123 pred = get_Block_cfgpred(block, n);
2124 set_irn_link(pred, block);
2126 pred = skip_Proj(pred);
2127 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2132 ARR_APP1(exc_entry, *exc_list, e);
2133 set_irn_link(pred, block);
2139 * Compare two exception_entries.
2141 static int cmp_exc_entry(const void *a, const void *b)
2143 const exc_entry *ea = a;
2144 const exc_entry *eb = b;
2146 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2152 * Main driver. Emits the code for one routine.
2154 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2156 ir_entity *entity = get_irg_entity(irg);
2157 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2162 do_pic = cg->birg->main_env->options->pic;
2164 ia32_register_emitters();
2166 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2168 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2169 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2171 /* we use links to point to target blocks */
2172 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2173 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2175 /* initialize next block links */
2176 n = ARR_LEN(cg->blk_sched);
2177 for (i = 0; i < n; ++i) {
2178 ir_node *block = cg->blk_sched[i];
2179 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2181 set_irn_link(block, prev);
2184 for (i = 0; i < n; ++i) {
2185 ir_node *block = cg->blk_sched[i];
2187 ia32_gen_block(block);
2190 be_gas_emit_function_epilog(entity);
2191 be_dbg_method_end();
2193 be_emit_write_line();
2195 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2197 /* Sort the exception table using the exception label id's.
2198 Those are ascending with ascending addresses. */
2199 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2203 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2204 be_emit_cstring("\t.long ");
2205 ia32_emit_exc_label(exc_list[i].exc_instr);
2207 be_emit_cstring("\t.long ");
2208 ia32_emit_block_name(exc_list[i].block);
2212 DEL_ARR_F(exc_list);
2215 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2216 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2220 void ia32_init_emitter(void)
2222 lc_opt_entry_t *be_grp;
2223 lc_opt_entry_t *ia32_grp;
2225 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2226 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2228 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2230 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");