2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
76 static ir_label_t exc_label_id;
77 static int mark_spill_reload = 0;
79 /** Return the next block in Block schedule */
80 static ir_node *get_prev_block_sched(const ir_node *block)
82 return get_irn_link(block);
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
98 static int block_needs_label(const ir_node *block)
101 int n_cfgpreds = get_Block_n_cfgpreds(block);
103 if (n_cfgpreds == 0) {
105 } else if (n_cfgpreds == 1) {
106 ir_node *cfgpred = get_Block_cfgpred(block, 0);
107 ir_node *cfgpred_block = get_nodes_block(cfgpred);
109 if (get_prev_block_sched(block) == cfgpred_block
110 && is_fallthrough(cfgpred)) {
119 * Returns the register at in position pos.
121 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
124 const arch_register_t *reg = NULL;
126 assert(get_irn_arity(irn) > pos && "Invalid IN position");
128 /* The out register of the operator at position pos is the
129 in register we need. */
130 op = get_irn_n(irn, pos);
132 reg = arch_get_irn_register(arch_env, op);
134 assert(reg && "no in register found");
136 if (reg == &ia32_gp_regs[REG_GP_NOREG])
137 panic("trying to emit noreg for %+F input %d", irn, pos);
139 /* in case of unknown register: just return a valid register */
140 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
141 const arch_register_req_t *req;
143 /* ask for the requirements */
144 req = arch_get_register_req(arch_env, irn, pos);
146 if (arch_register_req_is(req, limited)) {
147 /* in case of limited requirements: get the first allowed register */
148 unsigned idx = rbitset_next(req->limited, 0, 1);
149 reg = arch_register_for_index(req->cls, idx);
151 /* otherwise get first register in class */
152 reg = arch_register_for_index(req->cls, 0);
160 * Returns the register at out position pos.
162 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
165 const arch_register_t *reg = NULL;
167 /* 1st case: irn is not of mode_T, so it has only */
168 /* one OUT register -> good */
169 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
170 /* Proj with the corresponding projnum for the register */
172 if (get_irn_mode(irn) != mode_T) {
174 reg = arch_get_irn_register(arch_env, irn);
175 } else if (is_ia32_irn(irn)) {
176 reg = get_ia32_out_reg(irn, pos);
178 const ir_edge_t *edge;
180 foreach_out_edge(irn, edge) {
181 proj = get_edge_src_irn(edge);
182 assert(is_Proj(proj) && "non-Proj from mode_T node");
183 if (get_Proj_proj(proj) == pos) {
184 reg = arch_get_irn_register(arch_env, proj);
190 assert(reg && "no out register found");
195 * Add a number to a prefix. This number will not be used a second time.
197 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
199 static unsigned long id = 0;
200 snprintf(buf, buflen, "%s%lu", prefix, ++id);
204 /*************************************************************
206 * (_) | | / _| | | | |
207 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
208 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
209 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
210 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
213 *************************************************************/
215 static void emit_8bit_register(const arch_register_t *reg)
217 const char *reg_name = arch_register_get_name(reg);
220 be_emit_char(reg_name[1]);
224 static void emit_16bit_register(const arch_register_t *reg)
226 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
229 be_emit_string(reg_name);
232 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
234 const char *reg_name;
237 int size = get_mode_size_bits(mode);
239 case 8: emit_8bit_register(reg); return;
240 case 16: emit_16bit_register(reg); return;
242 assert(mode_is_float(mode) || size == 32);
245 reg_name = arch_register_get_name(reg);
248 be_emit_string(reg_name);
251 void ia32_emit_source_register(const ir_node *node, int pos)
253 const arch_register_t *reg = get_in_reg(node, pos);
255 emit_register(reg, NULL);
258 static void emit_ia32_Immediate(const ir_node *node);
260 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
262 const arch_register_t *reg;
263 ir_node *in = get_irn_n(node, pos);
264 if (is_ia32_Immediate(in)) {
265 emit_ia32_Immediate(in);
269 reg = get_in_reg(node, pos);
270 emit_8bit_register(reg);
273 void ia32_emit_dest_register(const ir_node *node, int pos)
275 const arch_register_t *reg = get_out_reg(node, pos);
277 emit_register(reg, NULL);
280 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
282 const arch_register_t *reg = get_out_reg(node, pos);
284 emit_register(reg, mode_Bu);
287 void ia32_emit_x87_register(const ir_node *node, int pos)
289 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
293 be_emit_string(attr->x87[pos]->name);
296 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
298 assert(mode_is_int(mode) || mode_is_reference(mode));
299 switch (get_mode_size_bits(mode)) {
300 case 8: be_emit_char('b'); return;
301 case 16: be_emit_char('w'); return;
302 case 32: be_emit_char('l'); return;
303 /* gas docu says q is the suffix but gcc, objdump and icc use ll
305 case 64: be_emit_cstring("ll"); return;
307 panic("Can't output mode_suffix for %+F", mode);
310 void ia32_emit_mode_suffix(const ir_node *node)
312 ir_mode *mode = get_ia32_ls_mode(node);
316 ia32_emit_mode_suffix_mode(mode);
319 void ia32_emit_x87_mode_suffix(const ir_node *node)
323 /* we only need to emit the mode on address mode */
324 if (get_ia32_op_type(node) == ia32_Normal)
327 mode = get_ia32_ls_mode(node);
328 assert(mode != NULL);
330 if (mode_is_float(mode)) {
331 switch (get_mode_size_bits(mode)) {
332 case 32: be_emit_char('s'); return;
333 case 64: be_emit_char('l'); return;
335 case 96: be_emit_char('t'); return;
338 assert(mode_is_int(mode));
339 switch (get_mode_size_bits(mode)) {
340 case 16: be_emit_char('s'); return;
341 case 32: be_emit_char('l'); return;
342 /* gas docu says q is the suffix but gcc, objdump and icc use ll
344 case 64: be_emit_cstring("ll"); return;
347 panic("Can't output mode_suffix for %+F", mode);
350 static char get_xmm_mode_suffix(ir_mode *mode)
352 assert(mode_is_float(mode));
353 switch(get_mode_size_bits(mode)) {
356 default: panic("Invalid XMM mode");
360 void ia32_emit_xmm_mode_suffix(const ir_node *node)
362 ir_mode *mode = get_ia32_ls_mode(node);
363 assert(mode != NULL);
365 be_emit_char(get_xmm_mode_suffix(mode));
368 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
370 ir_mode *mode = get_ia32_ls_mode(node);
371 assert(mode != NULL);
372 be_emit_char(get_xmm_mode_suffix(mode));
375 void ia32_emit_extend_suffix(const ir_mode *mode)
377 if (get_mode_size_bits(mode) == 32)
379 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
382 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
384 ir_node *in = get_irn_n(node, pos);
385 if (is_ia32_Immediate(in)) {
386 emit_ia32_Immediate(in);
388 const ir_mode *mode = get_ia32_ls_mode(node);
389 const arch_register_t *reg = get_in_reg(node, pos);
390 emit_register(reg, mode);
395 * Emits registers and/or address mode of a binary operation.
397 void ia32_emit_binop(const ir_node *node)
399 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
400 const ir_mode *mode = get_ia32_ls_mode(node);
401 const arch_register_t *reg_left;
403 switch(get_ia32_op_type(node)) {
405 reg_left = get_in_reg(node, n_ia32_binary_left);
406 if (is_ia32_Immediate(right_op)) {
407 emit_ia32_Immediate(right_op);
408 be_emit_cstring(", ");
409 emit_register(reg_left, mode);
412 const arch_register_t *reg_right
413 = get_in_reg(node, n_ia32_binary_right);
414 emit_register(reg_right, mode);
415 be_emit_cstring(", ");
416 emit_register(reg_left, mode);
420 if (is_ia32_Immediate(right_op)) {
421 emit_ia32_Immediate(right_op);
422 be_emit_cstring(", ");
425 reg_left = get_in_reg(node, n_ia32_binary_left);
427 be_emit_cstring(", ");
428 emit_register(reg_left, mode);
432 panic("DestMode can't be output by %%binop anymore");
435 assert(0 && "unsupported op type");
440 * Emits registers and/or address mode of a binary operation.
442 void ia32_emit_x87_binop(const ir_node *node)
444 switch(get_ia32_op_type(node)) {
447 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
448 const arch_register_t *in1 = x87_attr->x87[0];
449 const arch_register_t *in = x87_attr->x87[1];
450 const arch_register_t *out = x87_attr->x87[2];
454 } else if (out == in) {
459 be_emit_string(arch_register_get_name(in));
460 be_emit_cstring(", %");
461 be_emit_string(arch_register_get_name(out));
469 assert(0 && "unsupported op type");
474 * Emits registers and/or address mode of a unary operation.
476 void ia32_emit_unop(const ir_node *node, int pos)
480 switch(get_ia32_op_type(node)) {
482 op = get_irn_n(node, pos);
483 if (is_ia32_Immediate(op)) {
484 emit_ia32_Immediate(op);
486 ia32_emit_source_register(node, pos);
494 assert(0 && "unsupported op type");
498 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
502 set_entity_backend_marked(entity, 1);
503 id = get_entity_ld_ident(entity);
506 if (get_entity_owner(entity) == get_tls_type()) {
507 if (get_entity_visibility(entity) == visibility_external_allocated) {
508 be_emit_cstring("@INDNTPOFF");
510 be_emit_cstring("@NTPOFF");
514 if (!no_pic_adjust && do_pic) {
515 /* TODO: only do this when necessary */
517 be_emit_string(pic_base_label);
522 * Emits address mode.
524 void ia32_emit_am(const ir_node *node)
526 ir_entity *ent = get_ia32_am_sc(node);
527 int offs = get_ia32_am_offs_int(node);
528 ir_node *base = get_irn_n(node, n_ia32_base);
529 int has_base = !is_ia32_NoReg_GP(base);
530 ir_node *index = get_irn_n(node, n_ia32_index);
531 int has_index = !is_ia32_NoReg_GP(index);
533 /* just to be sure... */
534 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
538 if (is_ia32_am_sc_sign(node))
540 ia32_emit_entity(ent, 0);
543 /* also handle special case if nothing is set */
544 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
546 be_emit_irprintf("%+d", offs);
548 be_emit_irprintf("%d", offs);
552 if (has_base || has_index) {
557 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
558 emit_register(reg, NULL);
561 /* emit index + scale */
563 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
566 emit_register(reg, NULL);
568 scale = get_ia32_am_scale(node);
570 be_emit_irprintf(",%d", 1 << scale);
577 static void emit_ia32_IMul(const ir_node *node)
579 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
580 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
582 be_emit_cstring("\timul");
583 ia32_emit_mode_suffix(node);
586 ia32_emit_binop(node);
588 /* do we need the 3-address form? */
589 if (is_ia32_NoReg_GP(left) ||
590 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
591 be_emit_cstring(", ");
592 emit_register(out_reg, get_ia32_ls_mode(node));
594 be_emit_finish_line_gas(node);
597 /*************************************************
600 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
601 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
602 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
603 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
605 *************************************************/
608 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
611 * coding of conditions
613 struct cmp2conditon_t {
619 * positive conditions for signed compares
621 static const struct cmp2conditon_t cmp2condition_s[] = {
622 { NULL, pn_Cmp_False }, /* always false */
623 { "e", pn_Cmp_Eq }, /* == */
624 { "l", pn_Cmp_Lt }, /* < */
625 { "le", pn_Cmp_Le }, /* <= */
626 { "g", pn_Cmp_Gt }, /* > */
627 { "ge", pn_Cmp_Ge }, /* >= */
628 { "ne", pn_Cmp_Lg }, /* != */
629 { NULL, pn_Cmp_Leg}, /* always true */
633 * positive conditions for unsigned compares
635 static const struct cmp2conditon_t cmp2condition_u[] = {
636 { NULL, pn_Cmp_False }, /* always false */
637 { "e", pn_Cmp_Eq }, /* == */
638 { "b", pn_Cmp_Lt }, /* < */
639 { "be", pn_Cmp_Le }, /* <= */
640 { "a", pn_Cmp_Gt }, /* > */
641 { "ae", pn_Cmp_Ge }, /* >= */
642 { "ne", pn_Cmp_Lg }, /* != */
643 { NULL, pn_Cmp_Leg }, /* always true */
647 * walks up a tree of copies/perms/spills/reloads to find the original value
648 * that is moved around
650 static ir_node *find_original_value(ir_node *node)
652 if (irn_visited(node))
655 mark_irn_visited(node);
656 if (be_is_Copy(node)) {
657 return find_original_value(be_get_Copy_op(node));
658 } else if (be_is_CopyKeep(node)) {
659 return find_original_value(be_get_CopyKeep_op(node));
660 } else if (is_Proj(node)) {
661 ir_node *pred = get_Proj_pred(node);
662 if (be_is_Perm(pred)) {
663 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
664 } else if (be_is_MemPerm(pred)) {
665 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
666 } else if (is_ia32_Load(pred)) {
667 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
671 } else if (is_ia32_Store(node)) {
672 return find_original_value(get_irn_n(node, n_ia32_Store_val));
673 } else if (is_Phi(node)) {
675 arity = get_irn_arity(node);
676 for (i = 0; i < arity; ++i) {
677 ir_node *in = get_irn_n(node, i);
678 ir_node *res = find_original_value(in);
689 static int determine_final_pnc(const ir_node *node, int flags_pos,
692 ir_node *flags = get_irn_n(node, flags_pos);
693 const ia32_attr_t *flags_attr;
694 flags = skip_Proj(flags);
696 if (is_ia32_Sahf(flags)) {
697 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
698 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
699 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
700 inc_irg_visited(current_ir_graph);
701 cmp = find_original_value(cmp);
703 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
704 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
707 flags_attr = get_ia32_attr_const(cmp);
708 if (flags_attr->data.ins_permuted)
709 pnc = get_mirrored_pnc(pnc);
710 pnc |= ia32_pn_Cmp_float;
711 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
712 || is_ia32_Fucompi(flags)) {
713 flags_attr = get_ia32_attr_const(flags);
715 if (flags_attr->data.ins_permuted)
716 pnc = get_mirrored_pnc(pnc);
717 pnc |= ia32_pn_Cmp_float;
719 flags_attr = get_ia32_attr_const(flags);
721 if (flags_attr->data.ins_permuted)
722 pnc = get_mirrored_pnc(pnc);
723 if (flags_attr->data.cmp_unsigned)
724 pnc |= ia32_pn_Cmp_unsigned;
730 static void ia32_emit_cmp_suffix(int pnc)
734 if ((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
736 assert(cmp2condition_u[pnc].num == pnc);
737 str = cmp2condition_u[pnc].name;
740 assert(cmp2condition_s[pnc].num == pnc);
741 str = cmp2condition_s[pnc].name;
747 void ia32_emit_cmp_suffix_node(const ir_node *node,
750 const ia32_attr_t *attr = get_ia32_attr_const(node);
752 pn_Cmp pnc = get_ia32_condcode(node);
754 pnc = determine_final_pnc(node, flags_pos, pnc);
755 if (attr->data.ins_permuted) {
756 if (pnc & ia32_pn_Cmp_float) {
757 pnc = get_negated_pnc(pnc, mode_F);
759 pnc = get_negated_pnc(pnc, mode_Iu);
763 ia32_emit_cmp_suffix(pnc);
767 * Returns the target block for a control flow node.
769 static ir_node *get_cfop_target_block(const ir_node *irn)
771 assert(get_irn_mode(irn) == mode_X);
772 return get_irn_link(irn);
776 * Emits a block label for the given block.
778 static void ia32_emit_block_name(const ir_node *block)
780 if (has_Block_label(block)) {
781 be_emit_string(be_gas_block_label_prefix());
782 be_emit_irprintf("%lu", get_Block_label(block));
784 be_emit_cstring(BLOCK_PREFIX);
785 be_emit_irprintf("%ld", get_irn_node_nr(block));
790 * Emits an exception label for a given node.
792 static void ia32_emit_exc_label(const ir_node *node)
794 be_emit_string(be_gas_insn_label_prefix());
795 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
799 * Emits the target label for a control flow node.
801 static void ia32_emit_cfop_target(const ir_node *node)
803 ir_node *block = get_cfop_target_block(node);
805 ia32_emit_block_name(block);
809 * Returns the Proj with projection number proj and NOT mode_M
811 static ir_node *get_proj(const ir_node *node, long proj)
813 const ir_edge_t *edge;
816 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
818 foreach_out_edge(node, edge) {
819 src = get_edge_src_irn(edge);
821 assert(is_Proj(src) && "Proj expected");
822 if (get_irn_mode(src) == mode_M)
825 if (get_Proj_proj(src) == proj)
831 static int can_be_fallthrough(const ir_node *node)
833 ir_node *target_block = get_cfop_target_block(node);
834 ir_node *block = get_nodes_block(node);
835 return get_prev_block_sched(target_block) == block;
839 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
841 static void emit_ia32_Jcc(const ir_node *node)
843 int need_parity_label = 0;
844 const ir_node *proj_true;
845 const ir_node *proj_false;
846 const ir_node *block;
847 pn_Cmp pnc = get_ia32_condcode(node);
849 pnc = determine_final_pnc(node, 0, pnc);
852 proj_true = get_proj(node, pn_ia32_Jcc_true);
853 assert(proj_true && "Jcc without true Proj");
855 proj_false = get_proj(node, pn_ia32_Jcc_false);
856 assert(proj_false && "Jcc without false Proj");
858 block = get_nodes_block(node);
860 if (can_be_fallthrough(proj_true)) {
861 /* exchange both proj's so the second one can be omitted */
862 const ir_node *t = proj_true;
864 proj_true = proj_false;
866 if (pnc & ia32_pn_Cmp_float) {
867 pnc = get_negated_pnc(pnc, mode_F);
869 pnc = get_negated_pnc(pnc, mode_Iu);
873 if (pnc & ia32_pn_Cmp_float) {
874 /* Some floating point comparisons require a test of the parity flag,
875 * which indicates that the result is unordered */
878 be_emit_cstring("\tjp ");
879 ia32_emit_cfop_target(proj_true);
880 be_emit_finish_line_gas(proj_true);
885 be_emit_cstring("\tjnp ");
886 ia32_emit_cfop_target(proj_true);
887 be_emit_finish_line_gas(proj_true);
893 /* we need a local label if the false proj is a fallthrough
894 * as the falseblock might have no label emitted then */
895 if (can_be_fallthrough(proj_false)) {
896 need_parity_label = 1;
897 be_emit_cstring("\tjp 1f");
899 be_emit_cstring("\tjp ");
900 ia32_emit_cfop_target(proj_false);
902 be_emit_finish_line_gas(proj_false);
908 be_emit_cstring("\tjp ");
909 ia32_emit_cfop_target(proj_true);
910 be_emit_finish_line_gas(proj_true);
918 be_emit_cstring("\tj");
919 ia32_emit_cmp_suffix(pnc);
921 ia32_emit_cfop_target(proj_true);
922 be_emit_finish_line_gas(proj_true);
925 if (need_parity_label) {
926 be_emit_cstring("1:");
927 be_emit_write_line();
930 /* the second Proj might be a fallthrough */
931 if (can_be_fallthrough(proj_false)) {
932 be_emit_cstring("\t/* fallthrough to ");
933 ia32_emit_cfop_target(proj_false);
934 be_emit_cstring(" */");
935 be_emit_finish_line_gas(proj_false);
937 be_emit_cstring("\tjmp ");
938 ia32_emit_cfop_target(proj_false);
939 be_emit_finish_line_gas(proj_false);
943 static void emit_ia32_CMov(const ir_node *node)
945 const ia32_attr_t *attr = get_ia32_attr_const(node);
946 int ins_permuted = attr->data.ins_permuted;
947 const arch_register_t *out = arch_get_irn_register(arch_env, node);
948 pn_Cmp pnc = get_ia32_condcode(node);
949 const arch_register_t *in_true;
950 const arch_register_t *in_false;
952 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
954 in_true = arch_get_irn_register(arch_env,
955 get_irn_n(node, n_ia32_CMov_val_true));
956 in_false = arch_get_irn_register(arch_env,
957 get_irn_n(node, n_ia32_CMov_val_false));
959 /* should be same constraint fullfilled? */
960 if (out == in_false) {
961 /* yes -> nothing to do */
962 } else if (out == in_true) {
963 const arch_register_t *tmp;
965 assert(get_ia32_op_type(node) == ia32_Normal);
967 ins_permuted = !ins_permuted;
974 be_emit_cstring("\tmovl ");
975 emit_register(in_false, NULL);
976 be_emit_cstring(", ");
977 emit_register(out, NULL);
978 be_emit_finish_line_gas(node);
982 if (pnc & ia32_pn_Cmp_float) {
983 pnc = get_negated_pnc(pnc, mode_F);
985 pnc = get_negated_pnc(pnc, mode_Iu);
989 /* TODO: handling of Nans isn't correct yet */
991 be_emit_cstring("\tcmov");
992 ia32_emit_cmp_suffix(pnc);
994 if (get_ia32_op_type(node) == ia32_AddrModeS) {
997 emit_register(in_true, get_ia32_ls_mode(node));
999 be_emit_cstring(", ");
1000 emit_register(out, get_ia32_ls_mode(node));
1001 be_emit_finish_line_gas(node);
1004 /*********************************************************
1007 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1008 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1009 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1010 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1013 *********************************************************/
1015 /* jump table entry (target and corresponding number) */
1016 typedef struct _branch_t {
1021 /* jump table for switch generation */
1022 typedef struct _jmp_tbl_t {
1023 ir_node *defProj; /**< default target */
1024 long min_value; /**< smallest switch case */
1025 long max_value; /**< largest switch case */
1026 long num_branches; /**< number of jumps */
1027 char *label; /**< label of the jump table */
1028 branch_t *branches; /**< jump array */
1032 * Compare two variables of type branch_t. Used to sort all switch cases
1034 static int ia32_cmp_branch_t(const void *a, const void *b)
1036 branch_t *b1 = (branch_t *)a;
1037 branch_t *b2 = (branch_t *)b;
1039 if (b1->value <= b2->value)
1046 * Emits code for a SwitchJmp (creates a jump table if
1047 * possible otherwise a cmp-jmp cascade). Port from
1050 static void emit_ia32_SwitchJmp(const ir_node *node)
1052 unsigned long interval;
1058 const ir_edge_t *edge;
1060 /* fill the table structure */
1061 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1062 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1064 tbl.num_branches = get_irn_n_edges(node) - 1;
1065 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1066 tbl.min_value = INT_MAX;
1067 tbl.max_value = INT_MIN;
1069 default_pn = get_ia32_condcode(node);
1071 /* go over all proj's and collect them */
1072 foreach_out_edge(node, edge) {
1073 proj = get_edge_src_irn(edge);
1074 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1076 pnc = get_Proj_proj(proj);
1078 /* check for default proj */
1079 if (pnc == default_pn) {
1080 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1083 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1084 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1086 /* create branch entry */
1087 tbl.branches[i].target = proj;
1088 tbl.branches[i].value = pnc;
1093 assert(i == tbl.num_branches);
1095 /* sort the branches by their number */
1096 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1098 /* two-complement's magic make this work without overflow */
1099 interval = tbl.max_value - tbl.min_value;
1101 /* emit the table */
1102 be_emit_cstring("\tcmpl $");
1103 be_emit_irprintf("%u, ", interval);
1104 ia32_emit_source_register(node, 0);
1105 be_emit_finish_line_gas(node);
1107 be_emit_cstring("\tja ");
1108 ia32_emit_cfop_target(tbl.defProj);
1109 be_emit_finish_line_gas(node);
1111 if (tbl.num_branches > 1) {
1113 be_emit_cstring("\tjmp *");
1114 be_emit_string(tbl.label);
1115 be_emit_cstring("(,");
1116 ia32_emit_source_register(node, 0);
1117 be_emit_cstring(",4)");
1118 be_emit_finish_line_gas(node);
1120 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1121 be_emit_cstring("\t.align 4\n");
1122 be_emit_write_line();
1124 be_emit_string(tbl.label);
1125 be_emit_cstring(":\n");
1126 be_emit_write_line();
1128 be_emit_cstring(".long ");
1129 ia32_emit_cfop_target(tbl.branches[0].target);
1130 be_emit_finish_line_gas(NULL);
1132 last_value = tbl.branches[0].value;
1133 for (i = 1; i < tbl.num_branches; ++i) {
1134 while (++last_value < tbl.branches[i].value) {
1135 be_emit_cstring(".long ");
1136 ia32_emit_cfop_target(tbl.defProj);
1137 be_emit_finish_line_gas(NULL);
1139 be_emit_cstring(".long ");
1140 ia32_emit_cfop_target(tbl.branches[i].target);
1141 be_emit_finish_line_gas(NULL);
1143 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1145 /* one jump is enough */
1146 be_emit_cstring("\tjmp ");
1147 ia32_emit_cfop_target(tbl.branches[0].target);
1148 be_emit_finish_line_gas(node);
1158 * Emits code for a unconditional jump.
1160 static void emit_Jmp(const ir_node *node)
1164 /* for now, the code works for scheduled and non-schedules blocks */
1165 block = get_nodes_block(node);
1167 /* we have a block schedule */
1168 if (can_be_fallthrough(node)) {
1169 be_emit_cstring("\t/* fallthrough to ");
1170 ia32_emit_cfop_target(node);
1171 be_emit_cstring(" */");
1173 be_emit_cstring("\tjmp ");
1174 ia32_emit_cfop_target(node);
1176 be_emit_finish_line_gas(node);
1179 static void emit_ia32_Immediate(const ir_node *node)
1181 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1184 if (attr->symconst != NULL) {
1187 ia32_emit_entity(attr->symconst, 0);
1189 if (attr->symconst == NULL || attr->offset != 0) {
1190 if (attr->symconst != NULL) {
1191 be_emit_irprintf("%+d", attr->offset);
1193 be_emit_irprintf("0x%X", attr->offset);
1199 * Emit an inline assembler operand.
1201 * @param node the ia32_ASM node
1202 * @param s points to the operand (a %c)
1204 * @return pointer to the first char in s NOT in the current operand
1206 static const char* emit_asm_operand(const ir_node *node, const char *s)
1208 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1209 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1211 const arch_register_t *reg;
1212 const ia32_asm_reg_t *asm_regs = attr->register_map;
1213 const ia32_asm_reg_t *asm_reg;
1214 const char *reg_name;
1223 /* parse modifiers */
1226 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1250 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1251 "'%c' for asm op\n", node, c);
1257 sscanf(s, "%d%n", &num, &p);
1259 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1266 if (num < 0 || num >= ARR_LEN(asm_regs)) {
1267 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1268 "input/output (%+F)\n", node);
1271 asm_reg = & asm_regs[num];
1272 assert(asm_reg->valid);
1275 if (asm_reg->use_input == 0) {
1276 reg = get_out_reg(node, asm_reg->inout_pos);
1278 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1280 /* might be an immediate value */
1281 if (is_ia32_Immediate(pred)) {
1282 emit_ia32_Immediate(pred);
1285 reg = get_in_reg(node, asm_reg->inout_pos);
1288 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1289 "(%+F)\n", num, node);
1293 if (asm_reg->memory) {
1298 if (modifier != 0) {
1302 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1305 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1308 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1311 panic("Invalid asm op modifier");
1313 be_emit_string(reg_name);
1315 emit_register(reg, asm_reg->mode);
1318 if (asm_reg->memory) {
1326 * Emits code for an ASM pseudo op.
1328 static void emit_ia32_Asm(const ir_node *node)
1330 const void *gen_attr = get_irn_generic_attr_const(node);
1331 const ia32_asm_attr_t *attr
1332 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1333 ident *asm_text = attr->asm_text;
1334 const char *s = get_id_str(asm_text);
1336 be_emit_cstring("#APP\t");
1337 be_emit_finish_line_gas(node);
1344 s = emit_asm_operand(node, s);
1351 be_emit_write_line();
1353 be_emit_cstring("#NO_APP\n");
1354 be_emit_write_line();
1357 /**********************************
1360 * | | ___ _ __ _ _| |_) |
1361 * | | / _ \| '_ \| | | | _ <
1362 * | |___| (_) | |_) | |_| | |_) |
1363 * \_____\___/| .__/ \__, |____/
1366 **********************************/
1369 * Emit movsb/w instructions to make mov count divideable by 4
1371 static void emit_CopyB_prolog(unsigned size)
1374 be_emit_cstring("\tmovsb");
1375 be_emit_finish_line_gas(NULL);
1378 be_emit_cstring("\tmovsw");
1379 be_emit_finish_line_gas(NULL);
1384 * Emit rep movsd instruction for memcopy.
1386 static void emit_ia32_CopyB(const ir_node *node)
1388 unsigned size = get_ia32_copyb_size(node);
1390 emit_CopyB_prolog(size);
1392 be_emit_cstring("\trep movsd");
1393 be_emit_finish_line_gas(node);
1397 * Emits unrolled memcopy.
1399 static void emit_ia32_CopyB_i(const ir_node *node)
1401 unsigned size = get_ia32_copyb_size(node);
1403 emit_CopyB_prolog(size);
1407 be_emit_cstring("\tmovsd");
1408 be_emit_finish_line_gas(NULL);
1414 /***************************
1418 * | | / _ \| '_ \ \ / /
1419 * | |___| (_) | | | \ V /
1420 * \_____\___/|_| |_|\_/
1422 ***************************/
1425 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1427 static void emit_ia32_Conv_with_FP(const ir_node *node)
1429 ir_mode *ls_mode = get_ia32_ls_mode(node);
1430 int ls_bits = get_mode_size_bits(ls_mode);
1432 be_emit_cstring("\tcvt");
1434 if (is_ia32_Conv_I2FP(node)) {
1435 if (ls_bits == 32) {
1436 be_emit_cstring("si2ss");
1438 be_emit_cstring("si2sd");
1440 } else if (is_ia32_Conv_FP2I(node)) {
1441 if (ls_bits == 32) {
1442 be_emit_cstring("ss2si");
1444 be_emit_cstring("sd2si");
1447 assert(is_ia32_Conv_FP2FP(node));
1448 if (ls_bits == 32) {
1449 be_emit_cstring("sd2ss");
1451 be_emit_cstring("ss2sd");
1456 switch(get_ia32_op_type(node)) {
1458 ia32_emit_source_register(node, n_ia32_unary_op);
1460 case ia32_AddrModeS:
1464 assert(0 && "unsupported op type for Conv");
1466 be_emit_cstring(", ");
1467 ia32_emit_dest_register(node, 0);
1468 be_emit_finish_line_gas(node);
1471 static void emit_ia32_Conv_I2FP(const ir_node *node)
1473 emit_ia32_Conv_with_FP(node);
1476 static void emit_ia32_Conv_FP2I(const ir_node *node)
1478 emit_ia32_Conv_with_FP(node);
1481 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1483 emit_ia32_Conv_with_FP(node);
1487 * Emits code for an Int conversion.
1489 static void emit_ia32_Conv_I2I(const ir_node *node)
1491 const char *sign_suffix;
1492 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1493 int smaller_bits = get_mode_size_bits(smaller_mode);
1495 const arch_register_t *in_reg, *out_reg;
1497 assert(!mode_is_float(smaller_mode));
1498 assert(smaller_bits == 8 || smaller_bits == 16);
1500 signed_mode = mode_is_signed(smaller_mode);
1501 sign_suffix = signed_mode ? "s" : "z";
1503 out_reg = get_out_reg(node, 0);
1505 switch(get_ia32_op_type(node)) {
1507 in_reg = get_in_reg(node, n_ia32_unary_op);
1509 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1510 out_reg == &ia32_gp_regs[REG_EAX] &&
1514 /* argument and result are both in EAX and */
1515 /* signedness is ok: -> use the smaller cwtl opcode */
1516 be_emit_cstring("\tcwtl");
1518 be_emit_cstring("\tmov");
1519 be_emit_string(sign_suffix);
1520 ia32_emit_mode_suffix_mode(smaller_mode);
1521 be_emit_cstring("l ");
1522 emit_register(in_reg, smaller_mode);
1523 be_emit_cstring(", ");
1524 emit_register(out_reg, NULL);
1527 case ia32_AddrModeS: {
1528 be_emit_cstring("\tmov");
1529 be_emit_string(sign_suffix);
1530 ia32_emit_mode_suffix_mode(smaller_mode);
1531 be_emit_cstring("l ");
1533 be_emit_cstring(", ");
1534 emit_register(out_reg, NULL);
1538 panic("unsupported op type for Conv");
1540 be_emit_finish_line_gas(node);
1544 /*******************************************
1547 * | |__ ___ _ __ ___ __| | ___ ___
1548 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1549 * | |_) | __/ | | | (_) | (_| | __/\__ \
1550 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1552 *******************************************/
1555 * Emits a backend call
1557 static void emit_be_Call(const ir_node *node)
1559 ir_entity *ent = be_Call_get_entity(node);
1561 be_emit_cstring("\tcall ");
1563 ia32_emit_entity(ent, 1);
1565 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1567 emit_register(reg, NULL);
1569 be_emit_finish_line_gas(node);
1573 * Emits code to increase stack pointer.
1575 static void emit_be_IncSP(const ir_node *node)
1577 int offs = be_get_IncSP_offset(node);
1578 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1584 be_emit_cstring("\tsubl $");
1585 be_emit_irprintf("%u, ", offs);
1586 emit_register(reg, NULL);
1588 be_emit_cstring("\taddl $");
1589 be_emit_irprintf("%u, ", -offs);
1590 emit_register(reg, NULL);
1592 be_emit_finish_line_gas(node);
1596 * Emits code for Copy/CopyKeep.
1598 static void Copy_emitter(const ir_node *node, const ir_node *op)
1600 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1601 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1607 if (is_unknown_reg(in))
1609 /* copies of vf nodes aren't real... */
1610 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1613 mode = get_irn_mode(node);
1614 if (mode == mode_E) {
1615 be_emit_cstring("\tmovsd ");
1616 emit_register(in, NULL);
1617 be_emit_cstring(", ");
1618 emit_register(out, NULL);
1620 be_emit_cstring("\tmovl ");
1621 emit_register(in, NULL);
1622 be_emit_cstring(", ");
1623 emit_register(out, NULL);
1625 be_emit_finish_line_gas(node);
1628 static void emit_be_Copy(const ir_node *node)
1630 Copy_emitter(node, be_get_Copy_op(node));
1633 static void emit_be_CopyKeep(const ir_node *node)
1635 Copy_emitter(node, be_get_CopyKeep_op(node));
1639 * Emits code for exchange.
1641 static void emit_be_Perm(const ir_node *node)
1643 const arch_register_t *in0, *in1;
1644 const arch_register_class_t *cls0, *cls1;
1646 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1647 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1649 cls0 = arch_register_get_class(in0);
1650 cls1 = arch_register_get_class(in1);
1652 assert(cls0 == cls1 && "Register class mismatch at Perm");
1654 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1655 be_emit_cstring("\txchg ");
1656 emit_register(in1, NULL);
1657 be_emit_cstring(", ");
1658 emit_register(in0, NULL);
1659 be_emit_finish_line_gas(node);
1660 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1661 be_emit_cstring("\txorpd ");
1662 emit_register(in1, NULL);
1663 be_emit_cstring(", ");
1664 emit_register(in0, NULL);
1665 be_emit_finish_line_gas(NULL);
1667 be_emit_cstring("\txorpd ");
1668 emit_register(in0, NULL);
1669 be_emit_cstring(", ");
1670 emit_register(in1, NULL);
1671 be_emit_finish_line_gas(NULL);
1673 be_emit_cstring("\txorpd ");
1674 emit_register(in1, NULL);
1675 be_emit_cstring(", ");
1676 emit_register(in0, NULL);
1677 be_emit_finish_line_gas(node);
1678 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1680 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1683 panic("unexpected register class in be_Perm (%+F)", node);
1688 * Emits code for Constant loading.
1690 static void emit_ia32_Const(const ir_node *node)
1692 be_emit_cstring("\tmovl ");
1693 emit_ia32_Immediate(node);
1694 be_emit_cstring(", ");
1695 ia32_emit_dest_register(node, 0);
1697 be_emit_finish_line_gas(node);
1701 * Emits code to load the TLS base
1703 static void emit_ia32_LdTls(const ir_node *node)
1705 be_emit_cstring("\tmovl %gs:0, ");
1706 ia32_emit_dest_register(node, 0);
1707 be_emit_finish_line_gas(node);
1710 /* helper function for emit_ia32_Minus64Bit */
1711 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1713 be_emit_cstring("\tmovl ");
1714 emit_register(src, NULL);
1715 be_emit_cstring(", ");
1716 emit_register(dst, NULL);
1717 be_emit_finish_line_gas(node);
1720 /* helper function for emit_ia32_Minus64Bit */
1721 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1723 be_emit_cstring("\tnegl ");
1724 emit_register(reg, NULL);
1725 be_emit_finish_line_gas(node);
1728 /* helper function for emit_ia32_Minus64Bit */
1729 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1731 be_emit_cstring("\tsbbl $0, ");
1732 emit_register(reg, NULL);
1733 be_emit_finish_line_gas(node);
1736 /* helper function for emit_ia32_Minus64Bit */
1737 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1739 be_emit_cstring("\tsbbl ");
1740 emit_register(src, NULL);
1741 be_emit_cstring(", ");
1742 emit_register(dst, NULL);
1743 be_emit_finish_line_gas(node);
1746 /* helper function for emit_ia32_Minus64Bit */
1747 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1749 be_emit_cstring("\txchgl ");
1750 emit_register(src, NULL);
1751 be_emit_cstring(", ");
1752 emit_register(dst, NULL);
1753 be_emit_finish_line_gas(node);
1756 /* helper function for emit_ia32_Minus64Bit */
1757 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1759 be_emit_cstring("\txorl ");
1760 emit_register(reg, NULL);
1761 be_emit_cstring(", ");
1762 emit_register(reg, NULL);
1763 be_emit_finish_line_gas(node);
1766 static void emit_ia32_Minus64Bit(const ir_node *node)
1768 const arch_register_t *in_lo = get_in_reg(node, 0);
1769 const arch_register_t *in_hi = get_in_reg(node, 1);
1770 const arch_register_t *out_lo = get_out_reg(node, 0);
1771 const arch_register_t *out_hi = get_out_reg(node, 1);
1773 if (out_lo == in_lo) {
1774 if (out_hi != in_hi) {
1775 /* a -> a, b -> d */
1778 /* a -> a, b -> b */
1781 } else if (out_lo == in_hi) {
1782 if (out_hi == in_lo) {
1783 /* a -> b, b -> a */
1784 emit_xchg(node, in_lo, in_hi);
1787 /* a -> b, b -> d */
1788 emit_mov(node, in_hi, out_hi);
1789 emit_mov(node, in_lo, out_lo);
1793 if (out_hi == in_lo) {
1794 /* a -> c, b -> a */
1795 emit_mov(node, in_lo, out_lo);
1797 } else if (out_hi == in_hi) {
1798 /* a -> c, b -> b */
1799 emit_mov(node, in_lo, out_lo);
1802 /* a -> c, b -> d */
1803 emit_mov(node, in_lo, out_lo);
1809 emit_neg( node, out_hi);
1810 emit_neg( node, out_lo);
1811 emit_sbb0(node, out_hi);
1815 emit_zero(node, out_hi);
1816 emit_neg( node, out_lo);
1817 emit_sbb( node, in_hi, out_hi);
1820 static void emit_ia32_GetEIP(const ir_node *node)
1822 be_emit_cstring("\tcall ");
1823 be_emit_string(pic_base_label);
1824 be_emit_finish_line_gas(node);
1826 be_emit_string(pic_base_label);
1827 be_emit_cstring(":\n");
1828 be_emit_write_line();
1830 be_emit_cstring("\tpopl ");
1831 ia32_emit_dest_register(node, 0);
1833 be_emit_write_line();
1836 static void emit_be_Return(const ir_node *node)
1839 be_emit_cstring("\tret");
1841 pop = be_Return_get_pop(node);
1842 if (pop > 0 || be_Return_get_emit_pop(node)) {
1843 be_emit_irprintf(" $%d", pop);
1845 be_emit_finish_line_gas(node);
1848 static void emit_Nothing(const ir_node *node)
1854 /***********************************************************************************
1857 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1858 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1859 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1860 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1862 ***********************************************************************************/
1865 * Enters the emitter functions for handled nodes into the generic
1866 * pointer of an opcode.
1868 static void ia32_register_emitters(void)
1870 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1871 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1872 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1873 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1874 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1875 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1877 /* first clear the generic function pointer for all ops */
1878 clear_irp_opcodes_generic_func();
1880 /* register all emitter functions defined in spec */
1881 ia32_register_spec_emitters();
1883 /* other ia32 emitter functions */
1887 IA32_EMIT(SwitchJmp);
1890 IA32_EMIT(Conv_I2FP);
1891 IA32_EMIT(Conv_FP2I);
1892 IA32_EMIT(Conv_FP2FP);
1893 IA32_EMIT(Conv_I2I);
1894 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1897 IA32_EMIT(Minus64Bit);
1901 /* benode emitter */
1926 typedef void (*emit_func_ptr) (const ir_node *);
1929 * Emits code for a node.
1931 static void ia32_emit_node(ir_node *node)
1933 ir_op *op = get_irn_op(node);
1935 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1937 if (is_ia32_irn(node)) {
1938 if (get_ia32_exc_label(node)) {
1939 /* emit the exception label of this instruction */
1940 ia32_assign_exc_label(node);
1942 if (mark_spill_reload) {
1943 if (is_ia32_is_spill(node)) {
1944 be_emit_cstring("\txchg %ebx, %ebx /* spill mark */\n");
1945 be_emit_write_line();
1947 if (is_ia32_is_reload(node)) {
1948 be_emit_cstring("\txchg %edx, %edx /* reload mark */\n");
1949 be_emit_write_line();
1951 if (is_ia32_is_remat(node)) {
1952 be_emit_cstring("\txchg %ecx, %ecx /* remat mark */\n");
1953 be_emit_write_line();
1957 if (op->ops.generic) {
1958 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1960 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1965 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1971 * Emits gas alignment directives
1973 static void ia32_emit_alignment(unsigned align, unsigned skip)
1975 be_emit_cstring("\t.p2align ");
1976 be_emit_irprintf("%u,,%u\n", align, skip);
1977 be_emit_write_line();
1981 * Emits gas alignment directives for Labels depended on cpu architecture.
1983 static void ia32_emit_align_label(void)
1985 unsigned align = ia32_cg_config.label_alignment;
1986 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1987 ia32_emit_alignment(align, maximum_skip);
1991 * Test whether a block should be aligned.
1992 * For cpus in the P4/Athlon class it is useful to align jump labels to
1993 * 16 bytes. However we should only do that if the alignment nops before the
1994 * label aren't executed more often than we have jumps to the label.
1996 static int should_align_block(const ir_node *block)
1998 static const double DELTA = .0001;
1999 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2000 ir_node *prev = get_prev_block_sched(block);
2002 double prev_freq = 0; /**< execfreq of the fallthrough block */
2003 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2006 if (exec_freq == NULL)
2008 if (ia32_cg_config.label_alignment_factor <= 0)
2011 block_freq = get_block_execfreq(exec_freq, block);
2012 if (block_freq < DELTA)
2015 n_cfgpreds = get_Block_n_cfgpreds(block);
2016 for(i = 0; i < n_cfgpreds; ++i) {
2017 const ir_node *pred = get_Block_cfgpred_block(block, i);
2018 double pred_freq = get_block_execfreq(exec_freq, pred);
2021 prev_freq += pred_freq;
2023 jmp_freq += pred_freq;
2027 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2030 jmp_freq /= prev_freq;
2032 return jmp_freq > ia32_cg_config.label_alignment_factor;
2036 * Emit the block header for a block.
2038 * @param block the block
2039 * @param prev_block the previous block
2041 static void ia32_emit_block_header(ir_node *block)
2043 ir_graph *irg = current_ir_graph;
2044 int need_label = block_needs_label(block);
2046 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2048 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2051 if (ia32_cg_config.label_alignment > 0) {
2052 /* align the current block if:
2053 * a) if should be aligned due to its execution frequency
2054 * b) there is no fall-through here
2056 if (should_align_block(block)) {
2057 ia32_emit_align_label();
2059 /* if the predecessor block has no fall-through,
2060 we can always align the label. */
2062 int has_fallthrough = 0;
2064 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2065 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2066 if (can_be_fallthrough(cfg_pred)) {
2067 has_fallthrough = 1;
2072 if (!has_fallthrough)
2073 ia32_emit_align_label();
2077 if (need_label || has_Block_label(block)) {
2078 ia32_emit_block_name(block);
2081 be_emit_pad_comment();
2082 be_emit_cstring(" /* ");
2084 be_emit_cstring("\t/* ");
2085 ia32_emit_block_name(block);
2086 be_emit_cstring(": ");
2089 be_emit_cstring("preds:");
2091 /* emit list of pred blocks in comment */
2092 arity = get_irn_arity(block);
2093 for (i = 0; i < arity; ++i) {
2094 ir_node *predblock = get_Block_cfgpred_block(block, i);
2095 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2097 if (exec_freq != NULL) {
2098 be_emit_irprintf(" freq: %f",
2099 get_block_execfreq(exec_freq, block));
2101 be_emit_cstring(" */\n");
2102 be_emit_write_line();
2106 * Walks over the nodes in a block connected by scheduling edges
2107 * and emits code for each node.
2109 static void ia32_gen_block(ir_node *block)
2113 ia32_emit_block_header(block);
2115 /* emit the contents of the block */
2116 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2117 sched_foreach(block, node) {
2118 ia32_emit_node(node);
2122 typedef struct exc_entry {
2123 ir_node *exc_instr; /** The instruction that can issue an exception. */
2124 ir_node *block; /** The block to call then. */
2129 * Sets labels for control flow nodes (jump target).
2130 * Links control predecessors to there destination blocks.
2132 static void ia32_gen_labels(ir_node *block, void *data)
2134 exc_entry **exc_list = data;
2138 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2139 pred = get_Block_cfgpred(block, n);
2140 set_irn_link(pred, block);
2142 pred = skip_Proj(pred);
2143 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2148 ARR_APP1(exc_entry, *exc_list, e);
2149 set_irn_link(pred, block);
2155 * Assign and emit an exception label if the current instruction can fail.
2157 void ia32_assign_exc_label(ir_node *node)
2159 if (get_ia32_exc_label(node)) {
2160 /* assign a new ID to the instruction */
2161 set_ia32_exc_label_id(node, ++exc_label_id);
2163 ia32_emit_exc_label(node);
2165 be_emit_pad_comment();
2166 be_emit_cstring("/* exception to Block ");
2167 ia32_emit_cfop_target(node);
2168 be_emit_cstring(" */\n");
2169 be_emit_write_line();
2174 * Compare two exception_entries.
2176 static int cmp_exc_entry(const void *a, const void *b)
2178 const exc_entry *ea = a;
2179 const exc_entry *eb = b;
2181 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2187 * Main driver. Emits the code for one routine.
2189 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2191 ir_entity *entity = get_irg_entity(irg);
2192 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2196 isa = (const ia32_isa_t*) cg->arch_env;
2197 arch_env = cg->arch_env;
2198 do_pic = cg->birg->main_env->options->pic;
2200 ia32_register_emitters();
2202 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2204 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2205 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2207 /* we use links to point to target blocks */
2208 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2209 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2211 /* initialize next block links */
2212 n = ARR_LEN(cg->blk_sched);
2213 for (i = 0; i < n; ++i) {
2214 ir_node *block = cg->blk_sched[i];
2215 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2217 set_irn_link(block, prev);
2220 for (i = 0; i < n; ++i) {
2221 ir_node *block = cg->blk_sched[i];
2223 ia32_gen_block(block);
2226 be_gas_emit_function_epilog(entity);
2227 be_dbg_method_end();
2229 be_emit_write_line();
2231 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2233 /* Sort the exception table using the exception label id's.
2234 Those are ascending with ascending addresses. */
2235 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2239 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2240 be_emit_cstring("\t.long ");
2241 ia32_emit_exc_label(exc_list[i].exc_instr);
2243 be_emit_cstring("\t.long ");
2244 ia32_emit_block_name(exc_list[i].block);
2248 DEL_ARR_F(exc_list);
2251 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2252 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2256 void ia32_init_emitter(void)
2258 lc_opt_entry_t *be_grp;
2259 lc_opt_entry_t *ia32_grp;
2261 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2262 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2264 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2266 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");