2 * This file implements the node emitter.
3 * @author Christian Wuerdig, Matthias Braun
21 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX ".L"
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
125 const arch_register_t *reg = NULL;
127 assert(get_irn_arity(irn) > pos && "Invalid IN position");
129 /* The out register of the operator at position pos is the
130 in register we need. */
131 op = get_irn_n(irn, pos);
133 reg = arch_get_irn_register(arch_env, op);
135 assert(reg && "no in register found");
137 /* in case of a joker register: just return a valid register */
138 if (arch_register_type_is(reg, joker)) {
139 arch_register_req_t req;
140 const arch_register_req_t *p_req;
142 /* ask for the requirements */
143 p_req = arch_get_register_req(arch_env, &req, irn, pos);
145 if (arch_register_req_is(p_req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
148 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
151 p_req->limited(p_req->limited_env, bs);
152 idx = bitset_next_set(bs, 0);
153 reg = arch_register_for_index(p_req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(p_req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
168 const arch_register_t *reg = NULL;
170 /* 1st case: irn is not of mode_T, so it has only */
171 /* one OUT register -> good */
172 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
173 /* Proj with the corresponding projnum for the register */
175 if (get_irn_mode(irn) != mode_T) {
176 reg = arch_get_irn_register(arch_env, irn);
177 } else if (is_ia32_irn(irn)) {
178 reg = get_ia32_out_reg(irn, pos);
180 const ir_edge_t *edge;
182 foreach_out_edge(irn, edge) {
183 proj = get_edge_src_irn(edge);
184 assert(is_Proj(proj) && "non-Proj from mode_T node");
185 if (get_Proj_proj(proj) == pos) {
186 reg = arch_get_irn_register(arch_env, proj);
192 assert(reg && "no out register found");
197 * Returns an ident for the given tarval tv.
199 static ident *get_ident_for_tv(tarval *tv) {
201 int len = tarval_snprintf(buf, sizeof(buf), tv);
203 return new_id_from_str(buf);
207 * Determine the gnu assembler suffix that indicates a mode
209 static char get_mode_suffix(const ir_mode *mode) {
210 if(mode_is_float(mode)) {
211 switch(get_mode_size_bits(mode)) {
220 assert(mode_is_int(mode) || mode_is_reference(mode));
221 switch(get_mode_size_bits(mode)) {
232 panic("Can't output mode_suffix for %+F\n", mode);
235 static int produces_result(const ir_node *node) {
236 return !(is_ia32_St(node) ||
237 is_ia32_Store8Bit(node) ||
238 is_ia32_CondJmp(node) ||
239 is_ia32_xCondJmp(node) ||
240 is_ia32_CmpSet(node) ||
241 is_ia32_xCmpSet(node) ||
242 is_ia32_SwitchJmp(node));
245 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
246 switch(get_mode_size_bits(mode)) {
248 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
250 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
252 return (char *)arch_register_get_name(reg);
258 * Determines the SSE suffix depending on the mode.
260 static int ia32_print_mode_suffix(lc_appendable_t *app,
261 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
263 ir_node *irn = arg->v_ptr;
264 ir_mode *mode = get_ia32_ls_mode(irn);
266 if (mode_is_float(mode)) {
267 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
269 if(get_mode_size_bits(mode) == 32)
272 if(mode_is_signed(mode))
273 lc_appendable_chadd(app, 's');
275 lc_appendable_chadd(app, 'z');
277 lc_appendable_chadd(app, get_mode_suffix(mode));
284 * Add a number to a prefix. This number will not be used a second time.
286 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
287 static unsigned long id = 0;
288 snprintf(buf, buflen, "%s%lu", prefix, ++id);
292 /*************************************************************
294 * (_) | | / _| | | | |
295 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
296 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
297 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
298 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
301 *************************************************************/
303 void ia32_emit_ident(ia32_emit_env_t *env, ident *id)
305 size_t len = get_id_strlen(id);
306 const char* str = get_id_str(id);
308 ia32_emit_string_len(env, str, len);
311 void ia32_emit_irprintf(ia32_emit_env_t *env, const char *fmt, ...)
317 ir_vsnprintf(buf, sizeof(buf), fmt, ap);
320 ia32_emit_string(env, buf);
323 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
325 const arch_register_t *reg = get_in_reg(node, pos);
326 const char *reg_name = arch_register_get_name(reg);
328 assert(pos < get_irn_arity(node));
330 ia32_emit_char(env, '%');
331 ia32_emit_string(env, reg_name);
334 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
335 const arch_register_t *reg = get_out_reg(node, pos);
336 const char *reg_name = arch_register_get_name(reg);
338 ia32_emit_char(env, '%');
339 ia32_emit_string(env, reg_name);
342 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
344 ia32_attr_t *attr = get_ia32_attr(node);
347 ia32_emit_char(env, '%');
348 ia32_emit_string(env, attr->x87[pos]->name);
351 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
356 switch(get_ia32_immop_type(node)) {
358 tv = get_ia32_Immop_tarval(node);
359 id = get_ident_for_tv(tv);
361 case ia32_ImmSymConst:
362 id = get_ia32_Immop_symconst(node);
366 ia32_emit_string(env, "BAD");
370 ia32_emit_ident(env, id);
373 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode)
375 ia32_emit_char(env, get_mode_suffix(mode));
378 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
380 ir_mode *mode = get_ia32_ls_mode(node);
382 ia32_emit_mode_suffix(env, mode);
385 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
387 ir_mode *mode = get_ia32_ls_mode(node);
388 ia32_emit_char(env, 's');
390 assert(mode_is_float(mode));
391 switch(get_mode_size_bits(mode)) {
393 ia32_emit_char(env, 's');
396 ia32_emit_char(env, 'd');
404 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
406 if(get_mode_size_bits(mode) == 32)
408 if(mode_is_signed(mode)) {
409 ia32_emit_char(env, 's');
411 ia32_emit_char(env, 'z');
416 * Emits registers and/or address mode of a binary operation.
418 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
419 switch(get_ia32_op_type(node)) {
421 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
422 ia32_emit_char(env, '$');
423 ia32_emit_immediate(env, node);
424 ia32_emit_cstring(env, ", ");
425 ia32_emit_source_register(env, node, 2);
427 const arch_register_t *in1 = get_in_reg(node, 2);
428 const arch_register_t *in2 = get_in_reg(node, 3);
429 const arch_register_t *out = produces_result(node) ? get_out_reg(node, 0) : NULL;
430 const arch_register_t *in;
433 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
434 out = out ? out : in1;
435 in_name = arch_register_get_name(in);
437 if (is_ia32_emit_cl(node)) {
438 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
442 ia32_emit_char(env, '%');
443 ia32_emit_string(env, in_name);
444 ia32_emit_cstring(env, ", %");
445 ia32_emit_string(env, arch_register_get_name(out));
449 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
450 assert(!produces_result(node) && "Source AM with Const must not produce result");
451 ia32_emit_am(env, node);
452 ia32_emit_cstring(env, ", $");
453 ia32_emit_immediate(env, node);
454 } else if (produces_result(node)) {
455 ia32_emit_am(env, node);
456 ia32_emit_cstring(env, ", ");
457 ia32_emit_dest_register(env, node, 0);
459 ia32_emit_am(env, node);
460 ia32_emit_cstring(env, ", ");
461 ia32_emit_source_register(env, node, 2);
465 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
466 ia32_emit_char(env, '$');
467 ia32_emit_immediate(env, node);
468 ia32_emit_cstring(env, ", ");
469 ia32_emit_am(env, node);
471 const arch_register_t *in1 = get_in_reg(node, get_irn_arity(node) == 5 ? 3 : 2);
472 ir_mode *mode = get_ia32_ls_mode(node);
475 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
477 if (is_ia32_emit_cl(node)) {
478 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
482 ia32_emit_char(env, '%');
483 ia32_emit_string(env, in_name);
484 ia32_emit_cstring(env, ", ");
485 ia32_emit_am(env, node);
489 assert(0 && "unsupported op type");
494 * Emits registers and/or address mode of a binary operation.
496 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
497 switch(get_ia32_op_type(node)) {
499 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
500 // should not happen...
503 ia32_attr_t *attr = get_ia32_attr(node);
504 const arch_register_t *in1 = attr->x87[0];
505 const arch_register_t *in2 = attr->x87[1];
506 const arch_register_t *out = attr->x87[2];
507 const arch_register_t *in;
509 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
510 out = out ? out : in1;
512 ia32_emit_char(env, '%');
513 ia32_emit_string(env, arch_register_get_name(in));
514 ia32_emit_cstring(env, ", %");
515 ia32_emit_string(env, arch_register_get_name(out));
520 ia32_emit_am(env, node);
523 assert(0 && "unsupported op type");
528 * Emits registers and/or address mode of a unary operation.
530 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node) {
531 switch(get_ia32_op_type(node)) {
533 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
534 ia32_emit_char(env, '$');
535 ia32_emit_immediate(env, node);
537 if (is_ia32_Mul(node) || is_ia32_IMul1OP(node)) {
538 ia32_emit_source_register(env, node, 3);
539 } else if(is_ia32_IDiv(node) || is_ia32_Div(node)) {
540 ia32_emit_source_register(env, node, 4);
541 } else if(is_ia32_Push(node)) {
542 ia32_emit_source_register(env, node, 2);
543 } else if(is_ia32_Pop(node)) {
544 ia32_emit_dest_register(env, node, 1);
546 ia32_emit_dest_register(env, node, 0);
552 ia32_emit_am(env, node);
555 assert(0 && "unsupported op type");
560 * Emits address mode.
562 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
563 ia32_am_flavour_t am_flav = get_ia32_am_flavour(node);
564 ident *id = get_ia32_am_sc(node);
565 int offs = get_ia32_am_offs_int(node);
567 /* just to be sure... */
568 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
572 if (is_ia32_am_sc_sign(node))
573 ia32_emit_char(env, '-');
574 ia32_emit_ident(env, id);
579 ia32_emit_irprintf(env, "%+d", offs);
581 ia32_emit_irprintf(env, "%d", offs);
585 if (am_flav & (ia32_B | ia32_I)) {
586 ia32_emit_char(env, '(');
589 if (am_flav & ia32_B) {
590 ia32_emit_source_register(env, node, 0);
593 /* emit index + scale */
594 if (am_flav & ia32_I) {
595 ia32_emit_char(env, ',');
596 ia32_emit_source_register(env, node, 1);
598 if (am_flav & ia32_S) {
599 ia32_emit_irprintf(env, ",%d", 1 << get_ia32_am_scale(node));
602 ia32_emit_char(env, ')');
608 * Formated print of commands and comments.
610 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
612 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
615 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
617 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
621 void ia32_write_line(ia32_emit_env_t *env)
623 char *finished_line = obstack_finish(env->obst);
625 fwrite(finished_line, env->linelength, 1, env->out);
627 obstack_free(env->obst, finished_line);
630 void ia32_pad_comment(ia32_emit_env_t *env)
632 while(env->linelength <= 30) {
633 ia32_emit_char(env, ' ');
635 ia32_emit_cstring(env, " ");
638 void ia32_emit_finish_line(ia32_emit_env_t *env, const ir_node *node)
641 const char *sourcefile;
645 ia32_emit_char(env, '\n');
646 ia32_write_line(env);
650 ia32_pad_comment(env);
651 ia32_emit_cstring(env, "/* ");
652 ia32_emit_irprintf(env, "%+F ", node);
654 dbg = get_irn_dbg_info(node);
655 sourcefile = be_retrieve_dbg_info(dbg, &lineno);
656 if(sourcefile != NULL) {
657 ia32_emit_string(env, sourcefile);
658 ia32_emit_irprintf(env, ":%u", lineno);
660 ia32_emit_cstring(env, " */\n");
661 ia32_write_line(env);
665 /*************************************************
668 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
669 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
670 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
671 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
673 *************************************************/
676 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
679 * coding of conditions
681 struct cmp2conditon_t {
687 * positive conditions for signed compares
689 static const struct cmp2conditon_t cmp2condition_s[] = {
690 { NULL, pn_Cmp_False }, /* always false */
691 { "e", pn_Cmp_Eq }, /* == */
692 { "l", pn_Cmp_Lt }, /* < */
693 { "le", pn_Cmp_Le }, /* <= */
694 { "g", pn_Cmp_Gt }, /* > */
695 { "ge", pn_Cmp_Ge }, /* >= */
696 { "ne", pn_Cmp_Lg }, /* != */
697 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
698 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
699 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
700 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
701 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
702 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
703 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
704 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
705 { NULL, pn_Cmp_True }, /* always true */
709 * positive conditions for unsigned compares
711 static const struct cmp2conditon_t cmp2condition_u[] = {
712 { NULL, pn_Cmp_False }, /* always false */
713 { "e", pn_Cmp_Eq }, /* == */
714 { "b", pn_Cmp_Lt }, /* < */
715 { "be", pn_Cmp_Le }, /* <= */
716 { "a", pn_Cmp_Gt }, /* > */
717 { "ae", pn_Cmp_Ge }, /* >= */
718 { "ne", pn_Cmp_Lg }, /* != */
719 { NULL, pn_Cmp_True }, /* always true */
723 * returns the condition code
725 static const char *get_cmp_suffix(int cmp_code)
727 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
728 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
730 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
731 return cmp2condition_u[cmp_code & 7].name;
733 return cmp2condition_s[cmp_code & 15].name;
737 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
739 ia32_emit_string(env, get_cmp_suffix(pnc));
744 * Returns the target block for a control flow node.
746 static ir_node *get_cfop_target_block(const ir_node *irn) {
747 return get_irn_link(irn);
751 * Returns the target label for a control flow node.
753 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
754 ir_node *block = get_cfop_target_block(node);
756 ia32_emit_cstring(env, BLOCK_PREFIX);
757 ia32_emit_irprintf(env, "%d", get_irn_node_nr(block));
760 /** Return the next block in Block schedule */
761 static ir_node *next_blk_sched(const ir_node *block) {
762 return get_irn_link(block);
766 * Returns the Proj with projection number proj and NOT mode_M
768 static ir_node *get_proj(const ir_node *node, long proj) {
769 const ir_edge_t *edge;
772 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
774 foreach_out_edge(node, edge) {
775 src = get_edge_src_irn(edge);
777 assert(is_Proj(src) && "Proj expected");
778 if (get_irn_mode(src) == mode_M)
781 if (get_Proj_proj(src) == proj)
788 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
790 static void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node,
791 ir_mode *mode, long pnc) {
792 const ir_node *proj_true;
793 const ir_node *proj_false;
794 const ir_node *block;
795 const ir_node *next_block;
798 /* get both Proj's */
799 proj_true = get_proj(node, pn_Cond_true);
800 assert(proj_true && "CondJmp without true Proj");
802 proj_false = get_proj(node, pn_Cond_false);
803 assert(proj_false && "CondJmp without false Proj");
805 /* for now, the code works for scheduled and non-schedules blocks */
806 block = get_nodes_block(node);
808 /* we have a block schedule */
809 next_block = next_blk_sched(block);
811 if (get_cfop_target_block(proj_true) == next_block) {
812 /* exchange both proj's so the second one can be omitted */
813 const ir_node *t = proj_true;
815 proj_true = proj_false;
818 pnc = get_negated_pnc(pnc, mode);
821 /* in case of unordered compare, check for parity */
822 if (pnc & pn_Cmp_Uo) {
823 ia32_emit_cstring(env, "\tjp ");
824 ia32_emit_cfop_target(env, proj_true);
825 ia32_emit_finish_line(env, proj_true);
828 ia32_emit_cstring(env, "\tj");
829 ia32_emit_cmp_suffix(env, pnc);
830 ia32_emit_char(env, ' ');
831 ia32_emit_cfop_target(env, proj_true);
832 ia32_emit_finish_line(env, proj_true);
834 /* the second Proj might be a fallthrough */
835 if (get_cfop_target_block(proj_false) != next_block) {
836 ia32_emit_cstring(env, "\tjmp ");
837 ia32_emit_cfop_target(env, proj_false);
838 ia32_emit_finish_line(env, proj_false);
840 ia32_emit_cstring(env, "\t/* fallthrough to");
841 ia32_emit_cfop_target(env, proj_false);
842 ia32_emit_cstring(env, " */");
843 ia32_emit_finish_line(env, proj_false);
848 * Emits code for conditional jump.
850 static void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
851 ia32_emit_cstring(env, "\tcmp ");
852 ia32_emit_binop(env, node);
853 ia32_emit_finish_line(env, node);
855 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
859 * Emits code for conditional jump with two variables.
861 static void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
862 CondJmp_emitter(env, node);
866 * Emits code for conditional test and jump.
868 static void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
869 if(is_ia32_ImmSymConst(node) || is_ia32_ImmConst(node)) {
870 ia32_emit_cstring(env, "\ttest $");
871 ia32_emit_immediate(env, node);
872 ia32_emit_cstring(env, ", ");
873 ia32_emit_source_register(env, node, 0);
874 ia32_emit_finish_line(env, node);
876 ia32_emit_cstring(env, "\ttest ");
877 ia32_emit_source_register(env, node, 1);
878 ia32_emit_cstring(env, ", ");
879 ia32_emit_source_register(env, node, 0);
880 ia32_emit_finish_line(env, node);
882 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
886 * Emits code for conditional test and jump with two variables.
888 static void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
889 TestJmp_emitter(env, node);
892 static void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
893 ia32_emit_cstring(env, "/* omitted redundant test */");
894 ia32_emit_finish_line(env, node);
896 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
899 static void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
900 ia32_emit_cstring(env, "/* omitted redundant test/cmp */");
901 ia32_emit_finish_line(env, node);
903 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
907 * Emits code for conditional SSE floating point jump with two variables.
909 static void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
910 ia32_emit_cstring(env, "\tucomis");
911 ia32_emit_mode_suffix(env, get_irn_mode(node));
912 ia32_emit_char(env, ' ');
913 ia32_emit_binop(env, node);
914 ia32_emit_finish_line(env, node);
916 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
920 * Emits code for conditional x87 floating point jump with two variables.
922 static void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
923 ia32_attr_t *attr = get_ia32_attr(node);
924 const char *reg = attr->x87[1]->name;
925 long pnc = get_ia32_pncode(node);
927 switch (get_ia32_irn_opcode(node)) {
928 case iro_ia32_fcomrJmp:
929 pnc = get_inversed_pnc(pnc);
930 case iro_ia32_fcomJmp:
932 ia32_emit_cstring(env, "\tfucom ");
934 case iro_ia32_fcomrpJmp:
935 pnc = get_inversed_pnc(pnc);
936 case iro_ia32_fcompJmp:
937 ia32_emit_cstring(env, "\tfucomp ");
939 case iro_ia32_fcomrppJmp:
940 pnc = get_inversed_pnc(pnc);
941 case iro_ia32_fcomppJmp:
942 ia32_emit_cstring(env, "\tfucompp ");
948 ia32_emit_char(env, '%');
949 ia32_emit_string(env, reg);
951 ia32_emit_finish_line(env, node);
953 ia32_emit_cstring(env, "\tfnstsw %ax");
954 ia32_emit_finish_line(env, node);
955 ia32_emit_cstring(env, "\tsahf");
956 ia32_emit_finish_line(env, node);
958 finish_CondJmp(env, node, mode_E, pnc);
961 static void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
962 long pnc = get_ia32_pncode(node);
963 int is_PsiCondCMov = is_ia32_PsiCondCMov(node);
964 int idx_left = 2 - is_PsiCondCMov;
965 int idx_right = 3 - is_PsiCondCMov;
966 const arch_register_t *in1, *in2, *out;
968 out = arch_get_irn_register(env->arch_env, node);
969 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_left));
970 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_right));
972 /* we have to emit the cmp first, because the destination register */
973 /* could be one of the compare registers */
974 if (is_ia32_CmpCMov(node)) {
975 ia32_emit_cstring(env, "\tcmp ");
976 ia32_emit_source_register(env, node, 1);
977 ia32_emit_cstring(env, ", ");
978 ia32_emit_source_register(env, node, 0);
979 } else if (is_ia32_xCmpCMov(node)) {
980 ia32_emit_cstring(env, "\tucomis");
981 ia32_emit_mode_suffix(env, get_irn_mode(node));
982 ia32_emit_char(env, ' ');
983 ia32_emit_source_register(env, node, 1);
984 ia32_emit_cstring(env, ", ");
985 ia32_emit_source_register(env, node, 0);
986 } else if (is_PsiCondCMov) {
987 /* omit compare because flags are already set by And/Or */
988 ia32_emit_cstring(env, "\ttest ");
989 ia32_emit_source_register(env, node, 0);
990 ia32_emit_cstring(env, ", ");
991 ia32_emit_source_register(env, node, 0);
993 assert(0 && "unsupported CMov");
995 ia32_emit_finish_line(env, node);
997 if (REGS_ARE_EQUAL(out, in2)) {
998 /* best case: default in == out -> do nothing */
999 } else if (REGS_ARE_EQUAL(out, in1)) {
1000 ir_node *n = (ir_node*) node;
1001 /* true in == out -> need complement compare and exchange true and default in */
1002 ir_node *t = get_irn_n(n, idx_left);
1003 set_irn_n(n, idx_left, get_irn_n(n, idx_right));
1004 set_irn_n(n, idx_right, t);
1006 pnc = get_negated_pnc(pnc, get_irn_mode(node));
1008 /* out is different from in: need copy default -> out */
1009 if (is_PsiCondCMov) {
1010 ia32_emit_cstring(env, "\tmovl ");
1011 ia32_emit_dest_register(env, node, 2);
1012 ia32_emit_cstring(env, ", ");
1013 ia32_emit_dest_register(env, node, 0);
1015 ia32_emit_cstring(env, "\tmovl ");
1016 ia32_emit_source_register(env, node, 3);
1017 ia32_emit_cstring(env, ", ");
1018 ia32_emit_dest_register(env, node, 0);
1020 ia32_emit_finish_line(env, node);
1023 if (is_PsiCondCMov) {
1024 ia32_emit_cstring(env, "\tcmov");
1025 ia32_emit_cmp_suffix(env, pnc);
1026 ia32_emit_cstring(env, "l ");
1027 ia32_emit_source_register(env, node, 1);
1028 ia32_emit_cstring(env, ", ");
1029 ia32_emit_dest_register(env, node, 0);
1031 ia32_emit_cstring(env, "\tcmov");
1032 ia32_emit_cmp_suffix(env, pnc);
1033 ia32_emit_cstring(env, "l ");
1034 ia32_emit_source_register(env, node, 2);
1035 ia32_emit_cstring(env, ", ");
1036 ia32_emit_dest_register(env, node, 0);
1038 ia32_emit_finish_line(env, node);
1041 static void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1042 CMov_emitter(env, node);
1045 static void emit_ia32_PsiCondCMov(ia32_emit_env_t *env, const ir_node *node) {
1046 CMov_emitter(env, node);
1049 static void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1050 CMov_emitter(env, node);
1053 static void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
1054 int pnc = get_ia32_pncode(node);
1055 const char *reg8bit;
1056 const arch_register_t *out;
1058 out = arch_get_irn_register(env->arch_env, node);
1059 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1061 if (is_ia32_CmpSet(node)) {
1062 ia32_emit_cstring(env, "\tcmp ");
1063 ia32_emit_binop(env, node);
1064 } else if (is_ia32_xCmpSet(node)) {
1065 ia32_emit_cstring(env, "\tucomis");
1066 ia32_emit_mode_suffix(env, get_irn_mode(get_irn_n(node, 2)));
1067 ia32_emit_char(env, ' ');
1068 ia32_emit_binop(env, node);
1069 } else if (is_ia32_PsiCondSet(node)) {
1070 ia32_emit_cstring(env, "\tcmp $0, ");
1071 ia32_emit_source_register(env, node, 0);
1073 assert(0 && "unsupported Set");
1075 ia32_emit_finish_line(env, node);
1077 /* use mov to clear target because it doesn't affect the eflags */
1078 ia32_emit_cstring(env, "\tmovl $0, %");
1079 ia32_emit_string(env, arch_register_get_name(out));
1080 ia32_emit_finish_line(env, node);
1082 ia32_emit_cstring(env, "\tset");
1083 ia32_emit_cmp_suffix(env, pnc);
1084 ia32_emit_cstring(env, " %");
1085 ia32_emit_string(env, reg8bit);
1086 ia32_emit_finish_line(env, node);
1089 static void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1090 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1093 static void emit_ia32_PsiCondSet(ia32_emit_env_t *env, const ir_node *node) {
1094 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 0)));
1097 static void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1098 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1101 static void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1103 long pnc = get_ia32_pncode(node);
1104 long unord = pnc & pn_Cmp_Uo;
1106 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1109 case pn_Cmp_Leg: /* odered */
1112 case pn_Cmp_Uo: /* unordered */
1116 case pn_Cmp_Eq: /* == */
1120 case pn_Cmp_Lt: /* < */
1124 case pn_Cmp_Le: /* <= */
1128 case pn_Cmp_Gt: /* > */
1132 case pn_Cmp_Ge: /* >= */
1136 case pn_Cmp_Lg: /* != */
1141 assert(sse_pnc >= 0 && "unsupported compare");
1143 if (unord && sse_pnc != 3) {
1145 We need a separate compare against unordered.
1146 Quick and Dirty solution:
1147 - get some memory on stack
1151 - and result and stored result
1154 ia32_emit_cstring(env, "\tsubl $8, %esp");
1155 ia32_emit_finish_line(env, node);
1157 ia32_emit_cstring(env, "\tcmpsd $3, ");
1158 ia32_emit_binop(env, node);
1159 ia32_emit_finish_line(env, node);
1161 ia32_emit_cstring(env, "\tmovsd ");
1162 ia32_emit_dest_register(env, node, 0);
1163 ia32_emit_cstring(env, ", (%esp)");
1164 ia32_emit_finish_line(env, node);
1167 ia32_emit_cstring(env, "\tcmpsd ");
1168 ia32_emit_irprintf(env, "%d, ", sse_pnc);
1169 ia32_emit_binop(env, node);
1170 ia32_emit_finish_line(env, node);
1172 if (unord && sse_pnc != 3) {
1173 ia32_emit_cstring(env, "\tandpd (%esp), ");
1174 ia32_emit_dest_register(env, node, 0);
1175 ia32_emit_finish_line(env, node);
1177 ia32_emit_cstring(env, "\taddl $8, %esp");
1178 ia32_emit_finish_line(env, node);
1182 /*********************************************************
1185 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1186 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1187 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1188 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1191 *********************************************************/
1193 /* jump table entry (target and corresponding number) */
1194 typedef struct _branch_t {
1199 /* jump table for switch generation */
1200 typedef struct _jmp_tbl_t {
1201 ir_node *defProj; /**< default target */
1202 int min_value; /**< smallest switch case */
1203 int max_value; /**< largest switch case */
1204 int num_branches; /**< number of jumps */
1205 char *label; /**< label of the jump table */
1206 branch_t *branches; /**< jump array */
1210 * Compare two variables of type branch_t. Used to sort all switch cases
1212 static int ia32_cmp_branch_t(const void *a, const void *b) {
1213 branch_t *b1 = (branch_t *)a;
1214 branch_t *b2 = (branch_t *)b;
1216 if (b1->value <= b2->value)
1223 * Emits code for a SwitchJmp (creates a jump table if
1224 * possible otherwise a cmp-jmp cascade). Port from
1227 static void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1228 unsigned long interval;
1233 const ir_edge_t *edge;
1235 /* fill the table structure */
1236 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1237 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1239 tbl.num_branches = get_irn_n_edges(node);
1240 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1241 tbl.min_value = INT_MAX;
1242 tbl.max_value = INT_MIN;
1245 /* go over all proj's and collect them */
1246 foreach_out_edge(node, edge) {
1247 proj = get_edge_src_irn(edge);
1248 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1250 pnc = get_Proj_proj(proj);
1252 /* create branch entry */
1253 tbl.branches[i].target = proj;
1254 tbl.branches[i].value = pnc;
1256 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1257 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1259 /* check for default proj */
1260 if (pnc == get_ia32_pncode(node)) {
1261 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1268 /* sort the branches by their number */
1269 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1271 /* two-complement's magic make this work without overflow */
1272 interval = tbl.max_value - tbl.min_value;
1274 /* emit the table */
1275 ia32_emit_cstring(env, "\tcmpl $");
1276 ia32_emit_irprintf(env, "%u, ", interval);
1277 ia32_emit_source_register(env, node, 0);
1278 ia32_emit_finish_line(env, node);
1280 ia32_emit_cstring(env, "\tja ");
1281 ia32_emit_cfop_target(env, tbl.defProj);
1282 ia32_emit_finish_line(env, node);
1284 if (tbl.num_branches > 1) {
1286 ia32_emit_cstring(env, "\tjmp *");
1287 ia32_emit_string(env, tbl.label);
1288 ia32_emit_cstring(env, "(,");
1289 ia32_emit_source_register(env, node, 0);
1290 ia32_emit_cstring(env, ",4)");
1291 ia32_emit_finish_line(env, node);
1293 ia32_switch_section(env->out, SECTION_RODATA);
1294 ia32_emit_cstring(env, "\t.align 4\n");
1295 ia32_write_line(env);
1297 ia32_emit_string(env, tbl.label);
1298 ia32_emit_cstring(env, ":\n");
1299 ia32_write_line(env);
1301 ia32_emit_cstring(env, ".long ");
1302 ia32_emit_cfop_target(env, tbl.branches[0].target);
1303 ia32_emit_finish_line(env, NULL);
1305 last_value = tbl.branches[0].value;
1306 for (i = 1; i < tbl.num_branches; ++i) {
1307 while (++last_value < tbl.branches[i].value) {
1308 ia32_emit_cstring(env, ".long ");
1309 ia32_emit_cfop_target(env, tbl.defProj);
1310 ia32_emit_finish_line(env, NULL);
1312 ia32_emit_cstring(env, ".long ");
1313 ia32_emit_cfop_target(env, tbl.branches[i].target);
1314 ia32_emit_finish_line(env, NULL);
1316 ia32_switch_section(env->out, SECTION_TEXT);
1318 /* one jump is enough */
1319 ia32_emit_cstring(env, "\tjmp ");
1320 ia32_emit_cfop_target(env, tbl.branches[0].target);
1321 ia32_emit_finish_line(env, node);
1331 * Emits code for a unconditional jump.
1333 static void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1334 ir_node *block, *next_block;
1336 /* for now, the code works for scheduled and non-schedules blocks */
1337 block = get_nodes_block(node);
1339 /* we have a block schedule */
1340 next_block = next_blk_sched(block);
1341 if (get_cfop_target_block(node) != next_block) {
1342 ia32_emit_cstring(env, "\tjmp ");
1343 ia32_emit_cfop_target(env, node);
1345 ia32_emit_cstring(env, "\t/* fallthrough to ");
1346 ia32_emit_cfop_target(env, node);
1347 ia32_emit_cstring(env, " */");
1349 ia32_emit_finish_line(env, node);
1352 /**********************************
1355 * | | ___ _ __ _ _| |_) |
1356 * | | / _ \| '_ \| | | | _ <
1357 * | |___| (_) | |_) | |_| | |_) |
1358 * \_____\___/| .__/ \__, |____/
1361 **********************************/
1364 * Emit movsb/w instructions to make mov count divideable by 4
1366 static void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1367 ia32_emit_cstring(env, "\tcld");
1368 ia32_emit_finish_line(env, NULL);
1372 ia32_emit_cstring(env, "\tmovsb");
1373 ia32_emit_finish_line(env, NULL);
1376 ia32_emit_cstring(env, "\tmovsw");
1377 ia32_emit_finish_line(env, NULL);
1380 ia32_emit_cstring(env, "\tmovsb");
1381 ia32_emit_finish_line(env, NULL);
1382 ia32_emit_cstring(env, "\tmovsw");
1383 ia32_emit_finish_line(env, NULL);
1389 * Emit rep movsd instruction for memcopy.
1391 static void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1392 tarval *tv = get_ia32_Immop_tarval(node);
1393 int rem = get_tarval_long(tv);
1395 emit_CopyB_prolog(env, rem);
1397 ia32_emit_cstring(env, "\trep movsd");
1398 ia32_emit_finish_line(env, node);
1402 * Emits unrolled memcopy.
1404 static void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1405 tarval *tv = get_ia32_Immop_tarval(node);
1406 int size = get_tarval_long(tv);
1408 emit_CopyB_prolog(env, size & 0x3);
1412 ia32_emit_cstring(env, "\tmovsd");
1413 ia32_emit_finish_line(env, NULL);
1419 /***************************
1423 * | | / _ \| '_ \ \ / /
1424 * | |___| (_) | | | \ V /
1425 * \_____\___/|_| |_|\_/
1427 ***************************/
1430 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1432 static void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1433 ir_mode *ls_mode = get_ia32_ls_mode(node);
1434 int ls_bits = get_mode_size_bits(ls_mode);
1436 ia32_emit_cstring(env, "\tcvt");
1438 if(is_ia32_Conv_I2FP(node)) {
1440 ia32_emit_cstring(env, "si2ss");
1442 ia32_emit_cstring(env, "si2sd");
1444 } else if(is_ia32_Conv_FP2I(node)) {
1446 ia32_emit_cstring(env, "ss2si");
1448 ia32_emit_cstring(env, "sd2si");
1451 assert(is_ia32_Conv_FP2FP(node));
1453 ia32_emit_cstring(env, "sd2ss");
1455 ia32_emit_cstring(env, "ss2sd");
1458 ia32_emit_char(env, ' ');
1460 switch(get_ia32_op_type(node)) {
1462 ia32_emit_dest_register(env, node, 0);
1463 ia32_emit_cstring(env, ", ");
1464 ia32_emit_source_register(env, node, 2);
1466 case ia32_AddrModeS:
1467 ia32_emit_dest_register(env, node, 0);
1468 ia32_emit_cstring(env, ", ");
1469 ia32_emit_am(env, node);
1472 assert(0 && "unsupported op type for Conv");
1474 ia32_emit_finish_line(env, node);
1477 static void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1478 emit_ia32_Conv_with_FP(env, node);
1481 static void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1482 emit_ia32_Conv_with_FP(env, node);
1485 static void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1486 emit_ia32_Conv_with_FP(env, node);
1490 * Emits code for an Int conversion.
1492 static void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1493 const char *sign_suffix;
1494 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1495 int smaller_bits = get_mode_size_bits(smaller_mode);
1497 const arch_register_t *in_reg, *out_reg;
1499 assert(!mode_is_float(smaller_mode));
1500 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1502 signed_mode = mode_is_signed(smaller_mode);
1503 if(smaller_bits == 32) {
1504 // this should not happen as it's no convert
1508 sign_suffix = signed_mode ? "s" : "z";
1511 switch(get_ia32_op_type(node)) {
1513 in_reg = get_in_reg(node, 2);
1514 out_reg = get_out_reg(node, 0);
1516 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1517 REGS_ARE_EQUAL(out_reg, in_reg) &&
1520 /* argument and result are both in EAX and */
1521 /* signedness is ok: -> use converts */
1522 if (smaller_bits == 8) {
1523 ia32_emit_cstring(env, "\tcbtw");
1524 } else if (smaller_bits == 16) {
1525 ia32_emit_cstring(env, "\tcwtl");
1529 } else if (REGS_ARE_EQUAL(out_reg, in_reg) && !signed_mode) {
1530 /* argument and result are in the same register */
1531 /* and signedness is ok: -> use and with mask */
1532 int mask = (1 << smaller_bits) - 1;
1533 ia32_emit_cstring(env, "\tandl $0x");
1534 ia32_emit_irprintf(env, "%x, ", mask);
1535 ia32_emit_dest_register(env, node, 0);
1537 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1539 ia32_emit_cstring(env, "\tmov");
1540 ia32_emit_string(env, sign_suffix);
1541 ia32_emit_mode_suffix(env, smaller_mode);
1542 ia32_emit_cstring(env, "l %");
1543 ia32_emit_string(env, sreg);
1544 ia32_emit_cstring(env, ", ");
1545 ia32_emit_dest_register(env, node, 0);
1548 case ia32_AddrModeS: {
1549 ia32_emit_cstring(env, "\tmov");
1550 ia32_emit_string(env, sign_suffix);
1551 ia32_emit_mode_suffix(env, smaller_mode);
1552 ia32_emit_cstring(env, "l %");
1553 ia32_emit_am(env, node);
1554 ia32_emit_cstring(env, ", ");
1555 ia32_emit_dest_register(env, node, 0);
1559 assert(0 && "unsupported op type for Conv");
1561 ia32_emit_finish_line(env, node);
1565 * Emits code for an 8Bit Int conversion.
1567 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1568 emit_ia32_Conv_I2I(env, node);
1572 /*******************************************
1575 * | |__ ___ _ __ ___ __| | ___ ___
1576 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1577 * | |_) | __/ | | | (_) | (_| | __/\__ \
1578 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1580 *******************************************/
1583 * Emits a backend call
1585 static void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1586 ir_entity *ent = be_Call_get_entity(node);
1588 ia32_emit_cstring(env, "\tcall ");
1590 ia32_emit_string(env, get_entity_ld_name(ent));
1592 ia32_emit_char(env, '*');
1593 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1595 ia32_emit_finish_line(env, node);
1599 * Emits code to increase stack pointer.
1601 static void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1602 int offs = be_get_IncSP_offset(node);
1608 ia32_emit_cstring(env, "\tsubl $");
1609 ia32_emit_irprintf(env, "%u, ", offs);
1610 ia32_emit_source_register(env, node, 0);
1612 ia32_emit_cstring(env, "\taddl $");
1613 ia32_emit_irprintf(env, "%u, ", -offs);
1614 ia32_emit_source_register(env, node, 0);
1616 ia32_emit_finish_line(env, node);
1620 * Emits code to set stack pointer.
1622 static void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1623 ia32_emit_cstring(env, "\tmovl ");
1624 ia32_emit_source_register(env, node, 2);
1625 ia32_emit_cstring(env, ", ");
1626 ia32_emit_dest_register(env, node, 0);
1627 ia32_emit_finish_line(env, node);
1631 * Emits code for Copy/CopyKeep.
1633 static void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op) {
1634 const arch_env_t *aenv = env->arch_env;
1636 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1637 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1640 if (mode_is_float(get_irn_mode(node))) {
1641 ia32_emit_cstring(env, "\tmovsd ");
1642 ia32_emit_source_register(env, node, 0);
1643 ia32_emit_cstring(env, ", ");
1644 ia32_emit_dest_register(env, node, 0);
1646 ia32_emit_cstring(env, "\tmovl ");
1647 ia32_emit_source_register(env, node, 0);
1648 ia32_emit_cstring(env, ", ");
1649 ia32_emit_dest_register(env, node, 0);
1651 ia32_emit_finish_line(env, node);
1654 static void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1655 Copy_emitter(env, node, be_get_Copy_op(node));
1658 static void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1659 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1663 * Emits code for exchange.
1665 static void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1666 const arch_register_t *in1, *in2;
1667 const arch_register_class_t *cls1, *cls2;
1669 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1670 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1672 cls1 = arch_register_get_class(in1);
1673 cls2 = arch_register_get_class(in2);
1675 assert(cls1 == cls2 && "Register class mismatch at Perm");
1677 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1679 if(emit_env->isa->opt_arch == arch_athlon) {
1680 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1681 // it is often beneficial to use the 3 xor trick instead of an xchg
1683 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1685 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1687 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1690 ia32_emit_cstring(env, "\txchg ");
1691 ia32_emit_source_register(env, node, 1);
1692 ia32_emit_cstring(env, ", ");
1693 ia32_emit_source_register(env, node, 0);
1694 ia32_emit_finish_line(env, node);
1698 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1699 ia32_emit_cstring(env, "\tpxorq ");
1700 ia32_emit_source_register(env, node, 1);
1701 ia32_emit_cstring(env, ", ");
1702 ia32_emit_source_register(env, node, 0);
1703 ia32_emit_finish_line(env, NULL);
1705 ia32_emit_cstring(env, "\tpxorq ");
1706 ia32_emit_source_register(env, node, 0);
1707 ia32_emit_cstring(env, ", ");
1708 ia32_emit_source_register(env, node, 1);
1709 ia32_emit_finish_line(env, NULL);
1711 ia32_emit_cstring(env, "\tpxorq ");
1712 ia32_emit_source_register(env, node, 1);
1713 ia32_emit_cstring(env, ", ");
1714 ia32_emit_source_register(env, node, 0);
1715 ia32_emit_finish_line(env, node);
1716 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1718 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1724 * Emits code for Constant loading.
1726 static void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1727 ir_mode *mode = get_irn_mode(node);
1728 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1730 if (imm_tp == ia32_ImmSymConst) {
1731 ia32_emit_cstring(env, "\tmovl $");
1732 ia32_emit_immediate(env, node);
1733 ia32_emit_cstring(env, ", ");
1734 ia32_emit_dest_register(env, node, 0);
1736 tarval *tv = get_ia32_Immop_tarval(node);
1737 assert(mode == mode_Iu);
1738 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1739 if (tarval_is_null(tv)) {
1740 if (env->isa->opt_arch == arch_pentium_4) {
1741 /* P4 prefers sub r, r, others xor r, r */
1742 ia32_emit_cstring(env, "\tsubl ");
1744 ia32_emit_cstring(env, "\txorl ");
1746 ia32_emit_dest_register(env, node, 0);
1747 ia32_emit_cstring(env, ", ");
1748 ia32_emit_dest_register(env, node, 0);
1750 ia32_emit_cstring(env, "\tmovl $");
1751 ia32_emit_immediate(env, node);
1752 ia32_emit_cstring(env, ", ");
1753 ia32_emit_dest_register(env, node, 0);
1756 ia32_emit_finish_line(env, node);
1760 * Emits code to load the TLS base
1762 static void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1763 ia32_emit_cstring(env, "\tmovl %gs:0, ");
1764 ia32_emit_dest_register(env, node, 0);
1765 ia32_emit_finish_line(env, node);
1768 static void emit_be_Return(ia32_emit_env_t *env, const ir_node *node) {
1769 ia32_emit_cstring(env, "\tret");
1770 ia32_emit_finish_line(env, node);
1773 static void emit_Nothing(ia32_emit_env_t *env, const ir_node *node) {
1777 /***********************************************************************************
1780 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1781 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1782 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1783 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1785 ***********************************************************************************/
1788 * Enters the emitter functions for handled nodes into the generic
1789 * pointer of an opcode.
1791 static void ia32_register_emitters(void) {
1793 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1794 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1795 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1796 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1797 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1798 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1800 /* first clear the generic function pointer for all ops */
1801 clear_irp_opcodes_generic_func();
1803 /* register all emitter functions defined in spec */
1804 ia32_register_spec_emitters();
1806 /* other ia32 emitter functions */
1812 IA32_EMIT(PsiCondCMov);
1814 IA32_EMIT(PsiCondSet);
1815 IA32_EMIT(SwitchJmp);
1818 IA32_EMIT(Conv_I2FP);
1819 IA32_EMIT(Conv_FP2I);
1820 IA32_EMIT(Conv_FP2FP);
1821 IA32_EMIT(Conv_I2I);
1822 IA32_EMIT(Conv_I2I8Bit);
1827 IA32_EMIT(xCmpCMov);
1828 IA32_EMIT(xCondJmp);
1829 IA32_EMIT2(fcomJmp, x87CondJmp);
1830 IA32_EMIT2(fcompJmp, x87CondJmp);
1831 IA32_EMIT2(fcomppJmp, x87CondJmp);
1832 IA32_EMIT2(fcomrJmp, x87CondJmp);
1833 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1834 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1836 /* benode emitter */
1862 static const char *last_name = NULL;
1863 static unsigned last_line = -1;
1864 static unsigned num = -1;
1867 * Emit the debug support for node node.
1869 static void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
1870 dbg_info *db = get_irn_dbg_info(node);
1872 const char *fname = be_retrieve_dbg_info(db, &lineno);
1874 if (! env->cg->birg->main_env->options->stabs_debug_support)
1878 if (last_name != fname) {
1880 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
1883 if (last_line != lineno) {
1887 snprintf(name, sizeof(name), ".LM%u", ++num);
1889 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
1890 fprintf(F, "%s:\n", name);
1895 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
1898 * Emits code for a node.
1900 static void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
1901 ir_op *op = get_irn_op(node);
1902 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1904 DBG((mod, LEVEL_1, "emitting code for %+F\n", node));
1906 if (op->ops.generic) {
1907 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1908 ia32_emit_dbg(env, node);
1909 (*func) (env, node);
1911 emit_Nothing(env, node);
1912 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
1917 * Emits gas alignment directives
1919 static void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
1920 ia32_emit_cstring(env, "\t.p2align ");
1921 ia32_emit_irprintf(env, "%u,,%u\n", align, skip);
1922 ia32_write_line(env);
1926 * Emits gas alignment directives for Functions depended on cpu architecture.
1928 static void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
1930 unsigned maximum_skip;
1945 maximum_skip = (1 << align) - 1;
1946 ia32_emit_alignment(env, align, maximum_skip);
1950 * Emits gas alignment directives for Labels depended on cpu architecture.
1952 static void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
1953 unsigned align; unsigned maximum_skip;
1968 maximum_skip = (1 << align) - 1;
1969 ia32_emit_alignment(env, align, maximum_skip);
1972 static int is_first_loop_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev_block) {
1973 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
1974 double block_freq, prev_freq;
1975 static const double DELTA = .0001;
1976 cpu_support cpu = env->isa->opt_arch;
1978 if(exec_freq == NULL)
1980 if(cpu == arch_i386 || cpu == arch_i486)
1983 block_freq = get_block_execfreq(exec_freq, block);
1984 prev_freq = get_block_execfreq(exec_freq, prev_block);
1986 if(block_freq < DELTA || prev_freq < DELTA)
1989 block_freq /= prev_freq;
1993 case arch_athlon_64:
1995 return block_freq > 3;
2000 return block_freq > 2;
2004 * Walks over the nodes in a block connected by scheduling edges
2005 * and emits code for each node.
2007 static void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block) {
2008 ir_graph *irg = get_irn_irg(block);
2009 ir_node *start_block = get_irg_start_block(irg);
2011 const ir_node *node;
2014 assert(is_Block(block));
2016 if (block == start_block)
2019 if (need_label && get_irn_arity(block) == 1) {
2020 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2022 if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2026 /* special case: if one of our cfg preds is a switch-jmp we need a label, */
2027 /* otherwise there might be jump table entries jumping to */
2028 /* non-existent (omitted) labels */
2029 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2030 ir_node *pred = get_Block_cfgpred(block, i);
2032 if (is_Proj(pred)) {
2033 assert(get_irn_mode(pred) == mode_X);
2034 if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
2044 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2046 /* align the loop headers */
2047 if (! is_first_loop_block(env, block, last_block)) {
2048 /* align blocks where the previous block has no fallthrough */
2049 arity = get_irn_arity(block);
2051 for (i = 0; i < arity; ++i) {
2052 ir_node *predblock = get_Block_cfgpred_block(block, i);
2054 if (predblock == last_block) {
2062 ia32_emit_align_label(env, env->isa->opt_arch);
2064 ia32_emit_cstring(env, BLOCK_PREFIX);
2065 ia32_emit_irprintf(env, "%d:", get_irn_node_nr(block));
2066 ia32_pad_comment(env);
2067 ia32_emit_cstring(env, " /* preds:");
2069 /* emit list of pred blocks in comment */
2070 arity = get_irn_arity(block);
2071 for (i = 0; i < arity; ++i) {
2072 ir_node *predblock = get_Block_cfgpred_block(block, i);
2073 ia32_emit_irprintf(env, " %d", get_irn_node_nr(predblock));
2076 if (exec_freq != NULL) {
2077 ia32_emit_irprintf(env, " freq: %f", get_block_execfreq(exec_freq, block));
2079 ia32_emit_cstring(env, " */\n");
2080 ia32_write_line(env);
2083 /* emit the contents of the block */
2084 ia32_emit_dbg(env, block);
2085 sched_foreach(block, node) {
2086 ia32_emit_node(env, node);
2091 * Emits code for function start.
2093 static void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2095 ir_entity *irg_ent = get_irg_entity(irg);
2096 const char *irg_name = get_entity_ld_name(irg_ent);
2097 cpu_support cpu = env->isa->opt_arch;
2098 const be_irg_t *birg = env->cg->birg;
2101 ia32_switch_section(F, SECTION_TEXT);
2102 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2103 ia32_emit_align_func(env, cpu);
2104 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2105 fprintf(F, ".globl %s\n", irg_name);
2107 ia32_dump_function_object(F, irg_name);
2108 fprintf(F, "%s:\n", irg_name);
2112 * Emits code for function end
2114 static void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2115 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2116 const be_irg_t *birg = env->cg->birg;
2119 ia32_dump_function_size(F, irg_name);
2120 be_dbg_method_end(birg->main_env->db_handle);
2126 * Sets labels for control flow nodes (jump target)
2128 static void ia32_gen_labels(ir_node *block, void *data) {
2130 int n = get_Block_n_cfgpreds(block);
2132 for (n--; n >= 0; n--) {
2133 pred = get_Block_cfgpred(block, n);
2134 set_irn_link(pred, block);
2139 * Main driver. Emits the code for one routine.
2141 void ia32_gen_routine(ia32_code_gen_t *cg, FILE *F, ir_graph *irg) {
2142 ia32_emit_env_t env;
2144 ir_node *last_block = NULL;
2146 struct obstack obst;
2148 obstack_init(&obst);
2151 env.arch_env = cg->arch_env;
2153 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2156 FIRM_DBG_REGISTER(env.mod, "firm.be.ia32.emitter");
2158 /* set the global arch_env (needed by print hooks) */
2159 arch_env = cg->arch_env;
2161 ia32_register_emitters();
2163 ia32_emit_func_prolog(&env, irg);
2164 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2166 n = ARR_LEN(cg->blk_sched);
2167 for (i = 0; i < n;) {
2170 block = cg->blk_sched[i];
2172 next_bl = i < n ? cg->blk_sched[i] : NULL;
2174 /* set here the link. the emitter expects to find the next block here */
2175 set_irn_link(block, next_bl);
2176 ia32_gen_block(&env, block, last_block);
2180 ia32_emit_func_epilog(&env, irg);