2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief This file implements the ia32 node emitter.
9 * @author Christian Wuerdig, Matthias Braun
11 * Summary table for x86 floatingpoint compares:
12 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
20 * pnc_Leg => NP (ordered)
42 #include "iredges_t.h"
46 #include "raw_bitset.h"
55 #include "beemitter.h"
59 #include "ia32_emitter.h"
60 #include "ia32_common_transform.h"
61 #include "gen_ia32_emitter.h"
62 #include "gen_ia32_regalloc_if.h"
63 #include "ia32_nodes_attr.h"
64 #include "ia32_new_nodes.h"
65 #include "ia32_architecture.h"
66 #include "bearch_ia32_t.h"
68 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
70 static const ia32_isa_t *isa;
71 static char pic_base_label[128];
72 static ir_label_t exc_label_id;
73 static int mark_spill_reload = 0;
76 static bool sp_relative;
77 static int frame_type_size;
78 static int callframe_offset;
80 /** Return the next block in Block schedule */
81 static ir_node *get_prev_block_sched(const ir_node *block)
83 return (ir_node*)get_irn_link(block);
86 /** Checks if the current block is a fall-through target. */
87 static int is_fallthrough(const ir_node *cfgpred)
91 if (!is_Proj(cfgpred))
93 pred = get_Proj_pred(cfgpred);
94 if (is_ia32_SwitchJmp(pred))
101 * returns non-zero if the given block needs a label
102 * because of being a jump-target (and not a fall-through)
104 static int block_needs_label(const ir_node *block)
107 int n_cfgpreds = get_Block_n_cfgpreds(block);
109 if (get_Block_entity(block) != NULL)
112 if (n_cfgpreds == 0) {
114 } else if (n_cfgpreds == 1) {
115 ir_node *cfgpred = get_Block_cfgpred(block, 0);
116 ir_node *cfgpred_block = get_nodes_block(cfgpred);
118 if (get_prev_block_sched(block) == cfgpred_block
119 && is_fallthrough(cfgpred)) {
128 * Add a number to a prefix. This number will not be used a second time.
130 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
132 static unsigned long id = 0;
133 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
138 * Emit the name of the 8bit low register
140 static void emit_8bit_register(const arch_register_t *reg)
142 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
143 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
146 be_emit_char(reg->name[1]); /* get the basic name of the register */
151 * Emit the name of the 8bit high register
153 static void emit_8bit_register_high(const arch_register_t *reg)
155 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
156 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
159 be_emit_char(reg->name[1]); /* get the basic name of the register */
163 static void emit_16bit_register(const arch_register_t *reg)
166 be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
170 * emit a register, possible shortened by a mode
172 * @param reg the register
173 * @param mode the mode of the register or NULL for full register
175 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
178 int size = get_mode_size_bits(mode);
180 case 8: emit_8bit_register(reg); return;
181 case 16: emit_16bit_register(reg); return;
183 assert(mode_is_float(mode) || size == 32);
187 be_emit_string(reg->name);
190 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
192 be_gas_emit_entity(entity);
194 if (get_entity_owner(entity) == get_tls_type()) {
195 if (!entity_has_definition(entity)) {
196 be_emit_cstring("@INDNTPOFF");
198 be_emit_cstring("@NTPOFF");
202 if (do_pic && !no_pic_adjust) {
204 be_emit_string(pic_base_label);
208 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
210 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
212 if (attr->symconst != NULL) {
215 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
217 if (attr->symconst == NULL || attr->offset != 0) {
218 if (attr->symconst != NULL) {
219 be_emit_irprintf("%+d", attr->offset);
221 be_emit_irprintf("0x%X", attr->offset);
226 static void emit_ia32_Immediate(const ir_node *node)
229 emit_ia32_Immediate_no_prefix(node);
232 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
234 assert(mode_is_int(mode) || mode_is_reference(mode));
235 switch (get_mode_size_bits(mode)) {
236 case 8: be_emit_char('b'); return;
237 case 16: be_emit_char('w'); return;
238 case 32: be_emit_char('l'); return;
239 /* gas docu says q is the suffix but gcc, objdump and icc use ll
241 case 64: be_emit_cstring("ll"); return;
243 panic("Can't output mode_suffix for %+F", mode);
246 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
250 /* we only need to emit the mode on address mode */
251 if (get_ia32_op_type(node) == ia32_Normal)
254 mode = get_ia32_ls_mode(node);
255 assert(mode != NULL);
257 if (mode_is_float(mode)) {
258 switch (get_mode_size_bits(mode)) {
259 case 32: be_emit_char('s'); return;
260 case 64: be_emit_char('l'); return;
261 /* long doubles have different sizes due to alignment on different
265 case 128: be_emit_char('t'); return;
268 assert(mode_is_int(mode) || mode_is_reference(mode));
269 switch (get_mode_size_bits(mode)) {
270 case 16: be_emit_char('s'); return;
271 case 32: be_emit_char('l'); return;
272 /* gas docu says q is the suffix but gcc, objdump and icc use ll
274 case 64: be_emit_cstring("ll"); return;
277 panic("Can't output mode_suffix for %+F", mode);
280 static char get_xmm_mode_suffix(ir_mode *mode)
282 assert(mode_is_float(mode));
283 switch (get_mode_size_bits(mode)) {
286 default: panic("Invalid XMM mode");
290 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
292 ir_mode *mode = get_ia32_ls_mode(node);
293 assert(mode != NULL);
294 be_emit_char(get_xmm_mode_suffix(mode));
298 * Returns the target block for a control flow node.
300 static ir_node *get_cfop_target_block(const ir_node *irn)
302 assert(get_irn_mode(irn) == mode_X);
303 return (ir_node*)get_irn_link(irn);
307 * Emits the target label for a control flow node.
309 static void ia32_emit_cfop_target(const ir_node *node)
311 ir_node *block = get_cfop_target_block(node);
312 be_gas_emit_block_name(block);
316 * Emit the suffix for a compare instruction.
318 static void ia32_emit_condition_code(ia32_condition_code_t cc)
321 case ia32_cc_overflow: be_emit_cstring("o"); return;
322 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
323 case ia32_cc_float_below:
324 case ia32_cc_float_unordered_below:
325 case ia32_cc_below: be_emit_cstring("b"); return;
326 case ia32_cc_float_above_equal:
327 case ia32_cc_float_unordered_above_equal:
328 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
329 case ia32_cc_float_equal:
330 case ia32_cc_equal: be_emit_cstring("e"); return;
331 case ia32_cc_float_not_equal:
332 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
333 case ia32_cc_float_below_equal:
334 case ia32_cc_float_unordered_below_equal:
335 case ia32_cc_below_equal: be_emit_cstring("be"); return;
336 case ia32_cc_float_above:
337 case ia32_cc_float_unordered_above:
338 case ia32_cc_above: be_emit_cstring("a"); return;
339 case ia32_cc_sign: be_emit_cstring("s"); return;
340 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
341 case ia32_cc_parity: be_emit_cstring("p"); return;
342 case ia32_cc_not_parity: be_emit_cstring("np"); return;
343 case ia32_cc_less: be_emit_cstring("l"); return;
344 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
345 case ia32_cc_less_equal: be_emit_cstring("le"); return;
346 case ia32_cc_greater: be_emit_cstring("g"); return;
347 case ia32_cc_float_parity_cases:
348 case ia32_cc_additional_float_cases:
351 panic("Invalid ia32 condition code");
354 typedef enum ia32_emit_mod_t {
356 EMIT_RESPECT_LS = 1U << 0,
357 EMIT_ALTERNATE_AM = 1U << 1,
359 EMIT_HIGH_REG = 1U << 3,
360 EMIT_LOW_REG = 1U << 4,
361 EMIT_16BIT_REG = 1U << 5
363 ENUM_BITSET(ia32_emit_mod_t)
366 * Emits address mode.
368 static void ia32_emit_am(ir_node const *const node)
370 ir_entity *ent = get_ia32_am_sc(node);
371 int offs = get_ia32_am_offs_int(node);
372 ir_node *base = get_irn_n(node, n_ia32_base);
373 int has_base = !is_ia32_NoReg_GP(base);
374 ir_node *idx = get_irn_n(node, n_ia32_index);
375 int has_index = !is_ia32_NoReg_GP(idx);
377 /* just to be sure... */
378 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
380 if (get_ia32_am_tls_segment(node))
381 be_emit_cstring("%gs:");
385 const ia32_attr_t *attr = get_ia32_attr_const(node);
386 if (is_ia32_am_sc_sign(node))
388 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
391 /* also handle special case if nothing is set */
392 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
394 be_emit_irprintf("%+d", offs);
396 be_emit_irprintf("%d", offs);
400 if (has_base || has_index) {
405 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
406 emit_register(reg, NULL);
409 /* emit index + scale */
411 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
414 emit_register(reg, NULL);
416 scale = get_ia32_am_scale(node);
418 be_emit_irprintf(",%d", 1 << scale);
425 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
427 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
434 const char *start = fmt;
435 ia32_emit_mod_t mod = EMIT_NONE;
437 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
440 be_emit_string_len(start, fmt - start);
445 be_emit_write_line();
459 case '*': mod |= EMIT_ALTERNATE_AM; break;
460 case '#': mod |= EMIT_RESPECT_LS; break;
461 case 'l': mod |= EMIT_LONG; break;
462 case '>': mod |= EMIT_HIGH_REG; break;
463 case '<': mod |= EMIT_LOW_REG; break;
464 case '^': mod |= EMIT_16BIT_REG; break;
473 arch_register_t const *reg;
483 if (get_ia32_op_type(node) == ia32_Normal) {
484 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
485 char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
486 be_emit_irprintf(fmt, attr->reg->name);
494 if (mod & EMIT_ALTERNATE_AM)
500 reg = va_arg(ap, const arch_register_t*);
501 if (get_ia32_op_type(node) == ia32_Normal) {
508 if (get_ia32_op_type(node) == ia32_Normal) {
515 default: goto unknown;
521 imm = get_irn_n(node, n_ia32_binary_right);
522 if (is_ia32_Immediate(imm)) {
523 emit_ia32_Immediate(imm);
524 be_emit_cstring(", ");
525 if (get_ia32_op_type(node) == ia32_Normal) {
526 goto destination_operand;
531 if (get_ia32_op_type(node) == ia32_Normal) {
532 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
533 emit_register(reg, get_ia32_ls_mode(node));
537 be_emit_cstring(", ");
539 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
540 emit_register(reg, get_ia32_ls_mode(node));
545 if (*fmt < '0' || '9' < *fmt)
547 reg = arch_get_irn_register_out(node, *fmt++ - '0');
552 ia32_emit_x87_mode_suffix(node);
553 } else if (*fmt == 'P') {
554 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
557 } else if (*fmt == 'R') {
558 /* NOTE: Work around a gas quirk for non-commutative operations if the
559 * destination register is not %st0. In this case r/non-r is swapped.
560 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
561 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
562 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
563 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
564 * In fact this corresponds to the encoding of the instruction:
565 * - The r suffix selects whether %st0 is on the left (no r) or on the
566 * right (r) side of the executed operation.
567 * - The placement of %st0 selects whether the result is written to
568 * %st0 (right) or the other register (left).
569 * This means that it is sufficient to test whether the operands are
570 * permuted. In particular it is not necessary to consider wether the
571 * result is to be placed into the explicit register operand. */
572 if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
574 } else if (*fmt == 'X') {
575 ia32_emit_xmm_mode_suffix(node);
576 } else if (*fmt == '0') {
578 be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
588 if (!(mod & EMIT_ALTERNATE_AM))
590 emit_ia32_Immediate_no_prefix(imm);
594 ia32_emit_cfop_target(node);
598 ir_mode *mode = get_ia32_ls_mode(node);
601 if (mod & EMIT_RESPECT_LS) {
602 if (get_mode_size_bits(mode) == 32)
604 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
606 ia32_emit_mode_suffix_mode(mode);
611 ia32_condition_code_t cc;
614 cc = (ia32_condition_code_t)va_arg(ap, int);
615 } else if ('0' <= *fmt && *fmt <= '9') {
616 cc = get_ia32_condcode(node);
617 cc = determine_final_cc(node, *fmt - '0', cc);
622 ia32_emit_condition_code(cc);
627 reg = va_arg(ap, const arch_register_t*);
629 if (mod & EMIT_ALTERNATE_AM)
631 if (mod & EMIT_HIGH_REG) {
632 emit_8bit_register_high(reg);
633 } else if (mod & EMIT_LOW_REG) {
634 emit_8bit_register(reg);
635 } else if (mod & EMIT_16BIT_REG) {
636 emit_16bit_register(reg);
638 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
646 if (*fmt < '0' || '9' < *fmt)
650 imm = get_irn_n(node, pos);
651 if (is_ia32_Immediate(imm)) {
654 reg = arch_get_irn_register_in(node, pos);
660 const char *str = va_arg(ap, const char*);
666 if (mod & EMIT_LONG) {
667 unsigned long num = va_arg(ap, unsigned long);
668 be_emit_irprintf("%lu", num);
670 unsigned num = va_arg(ap, unsigned);
671 be_emit_irprintf("%u", num);
676 if (mod & EMIT_LONG) {
677 long num = va_arg(ap, long);
678 be_emit_irprintf("%ld", num);
680 int num = va_arg(ap, int);
681 be_emit_irprintf("%d", num);
687 panic("unknown format conversion");
691 be_emit_finish_line_gas(node);
695 static void emit_ia32_IMul(const ir_node *node)
697 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
698 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
700 /* do we need the 3-address form? */
701 if (is_ia32_NoReg_GP(left) ||
702 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
703 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
705 ia32_emitf(node, "imul%M %#AS4, %#S3");
710 * walks up a tree of copies/perms/spills/reloads to find the original value
711 * that is moved around
713 static ir_node *find_original_value(ir_node *node)
715 if (irn_visited(node))
718 mark_irn_visited(node);
719 if (be_is_Copy(node)) {
720 return find_original_value(be_get_Copy_op(node));
721 } else if (be_is_CopyKeep(node)) {
722 return find_original_value(be_get_CopyKeep_op(node));
723 } else if (is_Proj(node)) {
724 ir_node *pred = get_Proj_pred(node);
725 if (be_is_Perm(pred)) {
726 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
727 } else if (be_is_MemPerm(pred)) {
728 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
729 } else if (is_ia32_Load(pred)) {
730 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
731 } else if (is_ia32_Store(pred)) {
732 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
736 } else if (is_Phi(node)) {
738 arity = get_irn_arity(node);
739 for (i = 0; i < arity; ++i) {
740 ir_node *in = get_irn_n(node, i);
741 ir_node *res = find_original_value(in);
752 static ia32_condition_code_t determine_final_cc(const ir_node *node,
753 int flags_pos, ia32_condition_code_t cc)
755 ir_node *flags = get_irn_n(node, flags_pos);
756 const ia32_attr_t *flags_attr;
757 flags = skip_Proj(flags);
759 if (is_ia32_Sahf(flags)) {
760 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
761 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
762 inc_irg_visited(current_ir_graph);
763 cmp = find_original_value(cmp);
765 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
768 flags_attr = get_ia32_attr_const(cmp);
770 flags_attr = get_ia32_attr_const(flags);
773 if (flags_attr->data.ins_permuted)
774 cc = ia32_invert_condition_code(cc);
779 * Emits an exception label for a given node.
781 static void ia32_emit_exc_label(const ir_node *node)
783 be_emit_string(be_gas_insn_label_prefix());
784 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
787 static int can_be_fallthrough(const ir_node *node)
789 ir_node *target_block = get_cfop_target_block(node);
790 ir_node *block = get_nodes_block(node);
791 return get_prev_block_sched(target_block) == block;
795 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
797 static void emit_ia32_Jcc(const ir_node *node)
799 int need_parity_label = 0;
800 ia32_condition_code_t cc = get_ia32_condcode(node);
802 cc = determine_final_cc(node, 0, cc);
805 ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
806 assert(proj_true && "Jcc without true Proj");
808 ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
809 assert(proj_false && "Jcc without false Proj");
811 if (can_be_fallthrough(proj_true)) {
812 /* exchange both proj's so the second one can be omitted */
813 const ir_node *t = proj_true;
815 proj_true = proj_false;
817 cc = ia32_negate_condition_code(cc);
820 if (cc & ia32_cc_float_parity_cases) {
821 /* Some floating point comparisons require a test of the parity flag,
822 * which indicates that the result is unordered */
823 if (cc & ia32_cc_negated) {
824 ia32_emitf(proj_true, "jp %L");
826 /* we need a local label if the false proj is a fallthrough
827 * as the falseblock might have no label emitted then */
828 if (can_be_fallthrough(proj_false)) {
829 need_parity_label = 1;
830 ia32_emitf(proj_false, "jp 1f");
832 ia32_emitf(proj_false, "jp %L");
836 ia32_emitf(proj_true, "j%PX %L", (int)cc);
837 if (need_parity_label) {
838 be_emit_cstring("1:\n");
839 be_emit_write_line();
842 /* the second Proj might be a fallthrough */
843 if (can_be_fallthrough(proj_false)) {
844 if (be_options.verbose_asm)
845 ia32_emitf(proj_false, "/* fallthrough to %L */");
847 ia32_emitf(proj_false, "jmp %L");
852 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
855 static void emit_ia32_Setcc(const ir_node *node)
857 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
859 ia32_condition_code_t cc = get_ia32_condcode(node);
860 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
861 if (cc & ia32_cc_float_parity_cases) {
862 if (cc & ia32_cc_negated) {
863 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
864 ia32_emitf(node, "setp %>R", dreg);
865 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
867 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
868 ia32_emitf(node, "setnp %>R", dreg);
869 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
872 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
876 static void emit_ia32_CMovcc(const ir_node *node)
878 const ia32_attr_t *attr = get_ia32_attr_const(node);
879 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
880 ia32_condition_code_t cc = get_ia32_condcode(node);
881 const arch_register_t *in_true;
882 const arch_register_t *in_false;
884 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
885 /* although you can't set ins_permuted in the constructor it might still
886 * be set by memory operand folding
887 * Permuting inputs of a cmov means the condition is negated!
889 if (attr->data.ins_permuted)
890 cc = ia32_negate_condition_code(cc);
892 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
893 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
895 /* should be same constraint fullfilled? */
896 if (out == in_false) {
897 /* yes -> nothing to do */
898 } else if (out == in_true) {
899 const arch_register_t *tmp;
901 assert(get_ia32_op_type(node) == ia32_Normal);
903 cc = ia32_negate_condition_code(cc);
910 ia32_emitf(node, "movl %R, %R", in_false, out);
913 if (cc & ia32_cc_float_parity_cases) {
914 panic("CMov with floatingpoint compare/parity not supported yet");
917 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
921 * Emits code for a SwitchJmp
923 static void emit_ia32_SwitchJmp(const ir_node *node)
925 ir_entity *jump_table = get_ia32_am_sc(node);
926 const ir_switch_table *table = get_ia32_switch_table(node);
928 ia32_emitf(node, "jmp %*AM");
929 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
933 * Emits code for a unconditional jump.
935 static void emit_ia32_Jmp(const ir_node *node)
937 /* we have a block schedule */
938 if (can_be_fallthrough(node)) {
939 if (be_options.verbose_asm)
940 ia32_emitf(node, "/* fallthrough to %L */");
942 ia32_emitf(node, "jmp %L");
947 * Emit an inline assembler operand.
949 * @param node the ia32_ASM node
950 * @param s points to the operand (a %c)
952 * @return pointer to the first char in s NOT in the current operand
954 static const char* emit_asm_operand(const ir_node *node, const char *s)
956 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
957 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
959 const arch_register_t *reg;
960 const ia32_asm_reg_t *asm_regs = attr->register_map;
961 const ia32_asm_reg_t *asm_reg;
970 /* parse modifiers */
973 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
999 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1006 if (sscanf(s, "%d%n", &num, &p) != 1) {
1007 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1014 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1016 "Error: Custom assembler references invalid input/output (%+F)\n",
1020 asm_reg = & asm_regs[num];
1021 assert(asm_reg->valid);
1024 if (asm_reg->use_input == 0) {
1025 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1027 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1029 /* might be an immediate value */
1030 if (is_ia32_Immediate(pred)) {
1031 emit_ia32_Immediate(pred);
1034 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1038 "Warning: no register assigned for %d asm op (%+F)\n",
1043 /* Emit the register. */
1044 if (asm_reg->memory) {
1046 emit_register(reg, NULL);
1050 case '\0': emit_register(reg, asm_reg->mode); break;
1051 case 'b': emit_8bit_register(reg); break;
1052 case 'h': emit_8bit_register_high(reg); break;
1053 case 'w': emit_16bit_register(reg); break;
1054 default: panic("Invalid asm op modifier");
1062 * Emits code for an ASM pseudo op.
1064 static void emit_ia32_Asm(const ir_node *node)
1066 const void *gen_attr = get_irn_generic_attr_const(node);
1067 const ia32_asm_attr_t *attr
1068 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1069 ident *asm_text = attr->asm_text;
1070 const char *s = get_id_str(asm_text);
1072 be_emit_cstring("#APP\n");
1073 be_emit_write_line();
1080 s = emit_asm_operand(node, s);
1086 be_emit_cstring("\n#NO_APP\n");
1087 be_emit_write_line();
1092 * Emit movsb/w instructions to make mov count divideable by 4
1094 static void emit_CopyB_prolog(unsigned size)
1097 ia32_emitf(NULL, "movsb");
1099 ia32_emitf(NULL, "movsw");
1103 * Emit rep movsd instruction for memcopy.
1105 static void emit_ia32_CopyB(const ir_node *node)
1107 unsigned size = get_ia32_copyb_size(node);
1109 emit_CopyB_prolog(size);
1110 ia32_emitf(node, "rep movsd");
1114 * Emits unrolled memcopy.
1116 static void emit_ia32_CopyB_i(const ir_node *node)
1118 unsigned size = get_ia32_copyb_size(node);
1120 emit_CopyB_prolog(size);
1124 ia32_emitf(NULL, "movsd");
1130 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1132 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1135 ir_mode *ls_mode = get_ia32_ls_mode(node);
1136 int ls_bits = get_mode_size_bits(ls_mode);
1137 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1139 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1142 static void emit_ia32_Conv_I2FP(const ir_node *node)
1144 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1147 static void emit_ia32_Conv_FP2I(const ir_node *node)
1149 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1152 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1154 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1158 * Emits code to increase stack pointer.
1160 static void emit_be_IncSP(const ir_node *node)
1162 int offs = be_get_IncSP_offset(node);
1168 ia32_emitf(node, "subl $%u, %D0", offs);
1170 ia32_emitf(node, "addl $%u, %D0", -offs);
1175 * Emits code for Copy/CopyKeep.
1177 static void Copy_emitter(const ir_node *node, const ir_node *op)
1179 const arch_register_t *in = arch_get_irn_register(op);
1180 const arch_register_t *out = arch_get_irn_register(node);
1185 /* copies of fp nodes aren't real... */
1186 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
1189 ia32_emitf(node, "movl %R, %R", in, out);
1192 static void emit_be_Copy(const ir_node *node)
1194 Copy_emitter(node, be_get_Copy_op(node));
1197 static void emit_be_CopyKeep(const ir_node *node)
1199 Copy_emitter(node, be_get_CopyKeep_op(node));
1203 * Emits code for exchange.
1205 static void emit_be_Perm(const ir_node *node)
1207 const arch_register_t *in0, *in1;
1209 in0 = arch_get_irn_register(get_irn_n(node, 0));
1210 in1 = arch_get_irn_register(get_irn_n(node, 1));
1212 arch_register_class_t const *const cls0 = in0->reg_class;
1213 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
1215 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1216 ia32_emitf(node, "xchg %R, %R", in1, in0);
1217 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1218 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1219 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1220 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1221 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
1224 panic("unexpected register class in be_Perm (%+F)", node);
1228 /* helper function for emit_ia32_Minus64Bit */
1229 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1231 ia32_emitf(node, "movl %R, %R", src, dst);
1234 /* helper function for emit_ia32_Minus64Bit */
1235 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1237 ia32_emitf(node, "negl %R", reg);
1240 /* helper function for emit_ia32_Minus64Bit */
1241 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1243 ia32_emitf(node, "sbbl $0, %R", reg);
1246 /* helper function for emit_ia32_Minus64Bit */
1247 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1249 ia32_emitf(node, "sbbl %R, %R", src, dst);
1252 /* helper function for emit_ia32_Minus64Bit */
1253 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1255 ia32_emitf(node, "xchgl %R, %R", src, dst);
1258 /* helper function for emit_ia32_Minus64Bit */
1259 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1261 ia32_emitf(node, "xorl %R, %R", reg, reg);
1264 static void emit_ia32_Minus64Bit(const ir_node *node)
1266 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1267 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1268 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1269 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1271 if (out_lo == in_lo) {
1272 if (out_hi != in_hi) {
1273 /* a -> a, b -> d */
1276 /* a -> a, b -> b */
1279 } else if (out_lo == in_hi) {
1280 if (out_hi == in_lo) {
1281 /* a -> b, b -> a */
1282 emit_xchg(node, in_lo, in_hi);
1285 /* a -> b, b -> d */
1286 emit_mov(node, in_hi, out_hi);
1287 emit_mov(node, in_lo, out_lo);
1291 if (out_hi == in_lo) {
1292 /* a -> c, b -> a */
1293 emit_mov(node, in_lo, out_lo);
1295 } else if (out_hi == in_hi) {
1296 /* a -> c, b -> b */
1297 emit_mov(node, in_lo, out_lo);
1300 /* a -> c, b -> d */
1301 emit_mov(node, in_lo, out_lo);
1307 emit_neg( node, out_hi);
1308 emit_neg( node, out_lo);
1309 emit_sbb0(node, out_hi);
1313 emit_zero(node, out_hi);
1314 emit_neg( node, out_lo);
1315 emit_sbb( node, in_hi, out_hi);
1318 static void emit_ia32_GetEIP(const ir_node *node)
1320 ia32_emitf(node, "call %s", pic_base_label);
1321 be_emit_irprintf("%s:\n", pic_base_label);
1322 be_emit_write_line();
1323 ia32_emitf(node, "popl %D0");
1326 static void emit_ia32_ClimbFrame(const ir_node *node)
1328 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1330 ia32_emitf(node, "movl %S0, %D0");
1331 ia32_emitf(node, "movl $%u, %S1", attr->count);
1332 be_gas_emit_block_name(node);
1333 be_emit_cstring(":\n");
1334 be_emit_write_line();
1335 ia32_emitf(node, "movl (%D0), %D0");
1336 ia32_emitf(node, "dec %S1");
1337 be_emit_cstring("\tjnz ");
1338 be_gas_emit_block_name(node);
1339 be_emit_finish_line_gas(node);
1342 static void emit_be_Return(const ir_node *node)
1344 unsigned pop = be_Return_get_pop(node);
1346 if (pop > 0 || be_Return_get_emit_pop(node)) {
1347 ia32_emitf(node, "ret $%u", pop);
1349 ia32_emitf(node, "ret");
1355 * Enters the emitter functions for handled nodes into the generic
1356 * pointer of an opcode.
1358 static void ia32_register_emitters(void)
1360 #define IA32_EMIT(a) be_set_emitter(op_ia32_##a, emit_ia32_##a)
1361 #define EMIT(a) be_set_emitter(op_##a, emit_##a)
1362 #define IGN(a) be_set_emitter(op_##a, be_emit_nothing)
1363 #define BE_EMIT(a) be_set_emitter(op_be_##a, emit_be_##a)
1364 #define BE_IGN(a) be_set_emitter(op_be_##a, be_emit_nothing)
1366 /* first clear the generic function pointer for all ops */
1367 ir_clear_opcodes_generic_func();
1369 /* register all emitter functions defined in spec */
1370 ia32_register_spec_emitters();
1372 /* other ia32 emitter functions */
1375 IA32_EMIT(Conv_FP2FP);
1376 IA32_EMIT(Conv_FP2I);
1377 IA32_EMIT(Conv_I2FP);
1384 IA32_EMIT(Minus64Bit);
1385 IA32_EMIT(SwitchJmp);
1386 IA32_EMIT(ClimbFrame);
1389 /* benode emitter */
1409 * Assign and emit an exception label if the current instruction can fail.
1411 static void ia32_assign_exc_label(ir_node *node)
1413 /* assign a new ID to the instruction */
1414 set_ia32_exc_label_id(node, ++exc_label_id);
1416 ia32_emit_exc_label(node);
1418 be_emit_pad_comment();
1419 be_emit_cstring("/* exception to Block ");
1420 ia32_emit_cfop_target(node);
1421 be_emit_cstring(" */\n");
1422 be_emit_write_line();
1426 * Emits code for a node.
1428 static void ia32_emit_node(ir_node *node)
1430 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1432 if (is_ia32_irn(node)) {
1433 if (get_ia32_exc_label(node)) {
1434 /* emit the exception label of this instruction */
1435 ia32_assign_exc_label(node);
1437 if (mark_spill_reload) {
1438 if (is_ia32_is_spill(node)) {
1439 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1441 if (is_ia32_is_reload(node)) {
1442 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1444 if (is_ia32_is_remat(node)) {
1445 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1453 int sp_change = arch_get_sp_bias(node);
1454 if (sp_change != 0) {
1455 assert(sp_change != SP_BIAS_RESET);
1456 callframe_offset += sp_change;
1457 be_dwarf_callframe_offset(callframe_offset);
1463 * Emits gas alignment directives
1465 static void ia32_emit_alignment(unsigned align, unsigned skip)
1467 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1471 * Emits gas alignment directives for Labels depended on cpu architecture.
1473 static void ia32_emit_align_label(void)
1475 unsigned align = ia32_cg_config.label_alignment;
1476 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1477 ia32_emit_alignment(align, maximum_skip);
1481 * Test whether a block should be aligned.
1482 * For cpus in the P4/Athlon class it is useful to align jump labels to
1483 * 16 bytes. However we should only do that if the alignment nops before the
1484 * label aren't executed more often than we have jumps to the label.
1486 static int should_align_block(const ir_node *block)
1488 static const double DELTA = .0001;
1489 ir_node *prev = get_prev_block_sched(block);
1490 double prev_freq = 0; /**< execfreq of the fallthrough block */
1491 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1495 if (ia32_cg_config.label_alignment_factor <= 0)
1498 block_freq = get_block_execfreq(block);
1499 if (block_freq < DELTA)
1502 n_cfgpreds = get_Block_n_cfgpreds(block);
1503 for (i = 0; i < n_cfgpreds; ++i) {
1504 const ir_node *pred = get_Block_cfgpred_block(block, i);
1505 double pred_freq = get_block_execfreq(pred);
1508 prev_freq += pred_freq;
1510 jmp_freq += pred_freq;
1514 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1517 jmp_freq /= prev_freq;
1519 return jmp_freq > ia32_cg_config.label_alignment_factor;
1523 * Emit the block header for a block.
1525 * @param block the block
1526 * @param prev_block the previous block
1528 static void ia32_emit_block_header(ir_node *block)
1530 ir_graph *const irg = get_Block_irg(block);
1531 if (block == get_irg_end_block(irg))
1534 if (ia32_cg_config.label_alignment > 0) {
1535 /* align the current block if:
1536 * a) if should be aligned due to its execution frequency
1537 * b) there is no fall-through here
1539 if (should_align_block(block)) {
1540 ia32_emit_align_label();
1542 /* if the predecessor block has no fall-through,
1543 we can always align the label. */
1545 int has_fallthrough = 0;
1547 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1548 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1549 if (can_be_fallthrough(cfg_pred)) {
1550 has_fallthrough = 1;
1555 if (!has_fallthrough)
1556 ia32_emit_align_label();
1560 int const need_label = block_needs_label(block);
1561 be_gas_begin_block(block, need_label);
1565 * Walks over the nodes in a block connected by scheduling edges
1566 * and emits code for each node.
1568 static void ia32_gen_block(ir_node *block)
1570 ia32_emit_block_header(block);
1573 ir_graph *irg = get_irn_irg(block);
1574 callframe_offset = 4; /* 4 bytes for the return address */
1575 /* ESP guessing, TODO perform a real ESP simulation */
1576 if (block != get_irg_start_block(irg)) {
1577 callframe_offset += frame_type_size;
1579 be_dwarf_callframe_offset(callframe_offset);
1582 /* emit the contents of the block */
1583 be_dwarf_location(get_irn_dbg_info(block));
1584 sched_foreach(block, node) {
1585 ia32_emit_node(node);
1589 typedef struct exc_entry {
1590 ir_node *exc_instr; /** The instruction that can issue an exception. */
1591 ir_node *block; /** The block to call then. */
1596 * Sets labels for control flow nodes (jump target).
1597 * Links control predecessors to there destination blocks.
1599 static void ia32_gen_labels(ir_node *block, void *data)
1601 exc_entry **exc_list = (exc_entry**)data;
1605 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1606 pred = get_Block_cfgpred(block, n);
1607 set_irn_link(pred, block);
1609 pred = skip_Proj(pred);
1610 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1615 ARR_APP1(exc_entry, *exc_list, e);
1616 set_irn_link(pred, block);
1622 * Compare two exception_entries.
1624 static int cmp_exc_entry(const void *a, const void *b)
1626 const exc_entry *ea = (const exc_entry*)a;
1627 const exc_entry *eb = (const exc_entry*)b;
1629 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1634 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1636 ir_entity *entity = get_irg_entity(irg);
1637 ir_type *type = get_entity_type(entity);
1638 size_t n_params = get_method_n_params(type);
1639 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1640 ir_type *arg_type = layout->arg_type;
1641 size_t n_members = get_compound_n_members(arg_type);
1642 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1645 for (i = 0; i < n_members; ++i) {
1646 ir_entity *member = get_compound_member(arg_type, i);
1648 if (!is_parameter_entity(member))
1650 param = get_entity_parameter_number(member);
1651 if (param == IR_VA_START_PARAMETER_NUMBER)
1653 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1654 infos[param].reg = NULL;
1655 infos[param].entity = member;
1662 * Main driver. Emits the code for one routine.
1664 void ia32_gen_routine(ir_graph *irg)
1666 ir_entity *entity = get_irg_entity(irg);
1667 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1668 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1669 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1670 ir_node **blk_sched = irg_data->blk_sched;
1671 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1672 parameter_dbg_info_t *infos;
1675 isa = (ia32_isa_t*) arch_env;
1676 do_pic = be_options.pic;
1678 be_gas_elf_type_char = '@';
1680 ia32_register_emitters();
1682 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1684 infos = construct_parameter_infos(irg);
1685 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1689 sp_relative = layout->sp_relative;
1690 if (layout->sp_relative) {
1691 ir_type *frame_type = get_irg_frame_type(irg);
1692 frame_type_size = get_type_size_bytes(frame_type);
1693 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1695 /* well not entirely correct here, we should emit this after the
1696 * "movl esp, ebp" */
1697 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1698 /* TODO: do not hardcode the following */
1699 be_dwarf_callframe_offset(8);
1700 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1703 /* we use links to point to target blocks */
1704 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1705 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1707 /* initialize next block links */
1708 n = ARR_LEN(blk_sched);
1709 for (i = 0; i < n; ++i) {
1710 ir_node *block = blk_sched[i];
1711 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1713 set_irn_link(block, prev);
1716 for (i = 0; i < n; ++i) {
1717 ir_node *block = blk_sched[i];
1719 ia32_gen_block(block);
1722 be_gas_emit_function_epilog(entity);
1724 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1726 /* Sort the exception table using the exception label id's.
1727 Those are ascending with ascending addresses. */
1728 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1732 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1733 be_emit_cstring("\t.long ");
1734 ia32_emit_exc_label(exc_list[e].exc_instr);
1736 be_emit_cstring("\t.long ");
1737 be_gas_emit_block_name(exc_list[e].block);
1741 DEL_ARR_F(exc_list);
1744 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1745 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1749 /* ==== Experimental binary emitter ==== */
1751 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1752 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1753 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1755 static void build_reg_map(void)
1757 reg_gp_map[REG_GP_EAX] = 0x0;
1758 reg_gp_map[REG_GP_ECX] = 0x1;
1759 reg_gp_map[REG_GP_EDX] = 0x2;
1760 reg_gp_map[REG_GP_EBX] = 0x3;
1761 reg_gp_map[REG_GP_ESP] = 0x4;
1762 reg_gp_map[REG_GP_EBP] = 0x5;
1763 reg_gp_map[REG_GP_ESI] = 0x6;
1764 reg_gp_map[REG_GP_EDI] = 0x7;
1767 /** Returns the encoding for a pnc field. */
1768 static unsigned char pnc2cc(ia32_condition_code_t cc)
1774 OP_8 = 0x00, /* 8bit operation. */
1775 OP_16_32 = 0x01, /* 16/32bit operation. */
1776 OP_MEM_SRC = 0x02, /* The memory operand is in the soruce position. */
1777 OP_IMM8 = 0x02, /* 8bit immediate, which gets sign extended for 16/32bit operation. */
1778 OP_16_32_IMM8 = 0x03, /* 16/32bit operation with sign extended 8bit immediate. */
1779 OP_EAX = 0x04, /* Short form of instruction with al/ax/eax as operand. */
1782 /** The mod encoding of the ModR/M */
1784 MOD_IND = 0x00, /**< [reg1] */
1785 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1786 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1787 MOD_REG = 0xC0 /**< reg1 */
1790 /** create R/M encoding for ModR/M */
1791 #define ENC_RM(x) (x)
1792 /** create REG encoding for ModR/M */
1793 #define ENC_REG(x) ((x) << 3)
1795 /** create encoding for a SIB byte */
1796 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1798 /* Node: The following routines are supposed to append bytes, words, dwords
1799 to the output stream.
1800 Currently the implementation is stupid in that it still creates output
1801 for an "assembler" in the form of .byte, .long
1802 We will change this when enough infrastructure is there to create complete
1803 machine code in memory/object files */
1805 static void bemit8(const unsigned char byte)
1807 be_emit_irprintf("\t.byte 0x%x\n", byte);
1808 be_emit_write_line();
1811 static void bemit16(const unsigned short u16)
1813 be_emit_irprintf("\t.word 0x%x\n", u16);
1814 be_emit_write_line();
1817 static void bemit32(const unsigned u32)
1819 be_emit_irprintf("\t.long 0x%x\n", u32);
1820 be_emit_write_line();
1824 * Emit address of an entity. If @p is_relative is true then a relative
1825 * offset from behind the address to the entity is created.
1827 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1830 if (entity == NULL) {
1835 /* the final version should remember the position in the bytestream
1836 and patch it with the correct address at linktime... */
1837 be_emit_cstring("\t.long ");
1840 be_gas_emit_entity(entity);
1842 if (get_entity_owner(entity) == get_tls_type()) {
1843 if (!entity_has_definition(entity)) {
1844 be_emit_cstring("@INDNTPOFF");
1846 be_emit_cstring("@NTPOFF");
1851 be_emit_cstring("-.");
1856 be_emit_irprintf("%+d", offset);
1859 be_emit_write_line();
1862 static void bemit_jmp_destination(const ir_node *dest_block)
1864 be_emit_cstring("\t.long ");
1865 be_gas_emit_block_name(dest_block);
1866 be_emit_cstring(" - . - 4\n");
1867 be_emit_write_line();
1870 /* end emit routines, all emitters following here should only use the functions
1873 typedef enum reg_modifier {
1878 /** Create a ModR/M byte for src1,src2 registers */
1879 static void bemit_modrr(const arch_register_t *src1,
1880 const arch_register_t *src2)
1882 unsigned char modrm = MOD_REG;
1883 modrm |= ENC_RM(reg_gp_map[src1->index]);
1884 modrm |= ENC_REG(reg_gp_map[src2->index]);
1888 /** Create a ModR/M8 byte for src1,src2 registers */
1889 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1890 reg_modifier_t high_part2, const arch_register_t *src2)
1892 unsigned char modrm = MOD_REG;
1893 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1894 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1898 /** Create a ModR/M byte for one register and extension */
1899 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1901 unsigned char modrm = MOD_REG;
1903 modrm |= ENC_RM(reg_gp_map[reg->index]);
1904 modrm |= ENC_REG(ext);
1908 /** Create a ModR/M8 byte for one register */
1909 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1911 unsigned char modrm = MOD_REG;
1912 assert(reg_gp_map[reg->index] < 4);
1913 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1919 * Calculate the size of an signed immediate in bytes.
1921 * @param offset an offset
1923 static unsigned get_signed_imm_size(int offset)
1925 if (-128 <= offset && offset < 128) {
1927 } else if (-32768 <= offset && offset < 32768) {
1935 * Emit an address mode.
1937 * @param reg content of the reg field: either a register index or an opcode extension
1938 * @param node the node
1940 static void bemit_mod_am(unsigned reg, const ir_node *node)
1942 ir_entity *ent = get_ia32_am_sc(node);
1943 int offs = get_ia32_am_offs_int(node);
1944 ir_node *base = get_irn_n(node, n_ia32_base);
1945 int has_base = !is_ia32_NoReg_GP(base);
1946 ir_node *idx = get_irn_n(node, n_ia32_index);
1947 int has_index = !is_ia32_NoReg_GP(idx);
1950 unsigned emitoffs = 0;
1951 bool emitsib = false;
1954 /* set the mod part depending on displacement */
1956 modrm |= MOD_IND_WORD_OFS;
1958 } else if (offs == 0) {
1961 } else if (-128 <= offs && offs < 128) {
1962 modrm |= MOD_IND_BYTE_OFS;
1965 modrm |= MOD_IND_WORD_OFS;
1970 const arch_register_t *base_reg = arch_get_irn_register(base);
1971 base_enc = reg_gp_map[base_reg->index];
1973 /* Use the EBP encoding + MOD_IND if NO base register. There is
1974 * always a 32bit offset present in this case. */
1980 /* Determine if we need a SIB byte. */
1982 const arch_register_t *reg_index = arch_get_irn_register(idx);
1983 int scale = get_ia32_am_scale(node);
1985 /* R/M set to ESP means SIB in 32bit mode. */
1986 modrm |= ENC_RM(0x04);
1987 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
1989 } else if (base_enc == 0x04) {
1990 /* for the above reason we are forced to emit a SIB when base is ESP.
1991 * Only the base is used, index must be ESP too, which means no index.
1993 modrm |= ENC_RM(0x04);
1994 sib = ENC_SIB(0, 0x04, 0x04);
1997 modrm |= ENC_RM(base_enc);
2000 /* We are forced to emit an 8bit offset as EBP base without offset is a
2001 * special case for SIB without base register. */
2002 if (base_enc == 0x05 && emitoffs == 0) {
2003 modrm |= MOD_IND_BYTE_OFS;
2007 modrm |= ENC_REG(reg);
2013 /* emit displacement */
2014 if (emitoffs == 8) {
2015 bemit8((unsigned) offs);
2016 } else if (emitoffs == 32) {
2017 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2024 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2027 if (get_ia32_op_type(node) == ia32_Normal) {
2028 const arch_register_t *in = arch_get_irn_register_in(node, input);
2029 bemit_modru(in, ext);
2031 bemit_mod_am(ext, node);
2035 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2037 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2038 bemit_unop(node, code, reg_gp_map[out->index], input);
2041 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2043 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2046 bemit8(size == 8 ? code : code + 1);
2047 bemit_mod_am(ext, node);
2050 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2053 bemit_unop_reg(node, code, input);
2056 static void bemit_immediate(const ir_node *node, bool relative)
2058 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2059 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2062 static void bemit_copy(const ir_node *copy)
2064 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2065 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2069 /* copies of fp nodes aren't real... */
2070 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
2073 assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
2075 bemit_modrr(in, out);
2078 static void bemit_perm(const ir_node *node)
2080 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2081 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2082 const arch_register_class_t *cls0 = in0->reg_class;
2084 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
2086 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2087 if (in0->index == REG_GP_EAX) {
2088 bemit8(0x90 + reg_gp_map[in1->index]);
2089 } else if (in1->index == REG_GP_EAX) {
2090 bemit8(0x90 + reg_gp_map[in0->index]);
2093 bemit_modrr(in0, in1);
2095 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2096 panic("unimplemented"); // TODO implement
2097 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2098 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2099 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2100 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
2103 panic("unexpected register class in be_Perm (%+F)", node);
2107 static void bemit_xor0(const ir_node *node)
2109 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2111 bemit_modrr(out, out);
2114 static void bemit_mov_const(const ir_node *node)
2116 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2117 bemit8(0xB8 + reg_gp_map[out->index]);
2118 bemit_immediate(node, false);
2124 static void bemit_binop(ir_node const *const node, unsigned const code)
2126 ir_mode *const ls_mode = get_ia32_ls_mode(node);
2127 unsigned size = ls_mode ? get_mode_size_bits(ls_mode) : 32;
2131 unsigned op = size == 8 ? OP_8 : OP_16_32;
2132 ir_node *const right = get_irn_n(node, n_ia32_binary_right);
2133 if (is_ia32_Immediate(right)) {
2134 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2135 /* Try to use the short form with 8bit sign extended immediate. */
2136 if (op != OP_8 && !attr->symconst && get_signed_imm_size(attr->offset) == 1) {
2141 /* Emit the main opcode. */
2142 if (get_ia32_op_type(node) == ia32_Normal) {
2143 arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_binary_left);
2144 /* Try to use the shorter al/ax/eax form. */
2145 if (dst->index == REG_GP_EAX && op != OP_16_32_IMM8) {
2146 bemit8(code << 3 | OP_EAX | op);
2149 bemit_modru(dst, code);
2153 bemit_mod_am(code, node);
2156 /* Emit the immediate. */
2158 case 8: bemit8(attr->offset); break;
2159 case 16: bemit16(attr->offset); break;
2160 case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
2163 bemit8(code << 3 | OP_MEM_SRC | op);
2164 arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_binary_left);
2165 if (get_ia32_op_type(node) == ia32_Normal) {
2166 arch_register_t const *const src = arch_get_irn_register(right);
2167 bemit_modrr(src, dst);
2169 bemit_mod_am(reg_gp_map[dst->index], node);
2175 * Create a function for a binop.
2177 #define BINOP(op, code) \
2178 static void bemit_##op(ir_node const *const node) \
2180 bemit_binop(node, code); \
2193 static void bemit_binop_mem(ir_node const *const node, unsigned const code)
2195 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2199 unsigned op = size == 8 ? OP_8 : OP_16_32;
2200 ir_node *const val = get_irn_n(node, n_ia32_unary_op);
2201 if (is_ia32_Immediate(val)) {
2202 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(val);
2203 /* Try to use the short form with 8bit sign extended immediate. */
2204 if (op != OP_8 && !attr->symconst && get_signed_imm_size(attr->offset) == 1) {
2209 /* Emit the main opcode. */
2211 bemit_mod_am(code, node);
2213 /* Emit the immediate. */
2215 case 8: bemit8(attr->offset); break;
2216 case 16: bemit16(attr->offset); break;
2217 case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
2220 bemit8(code << 3 | op);
2221 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node);
2225 #define BINOPMEM(op, code) \
2226 static void bemit_##op(ir_node const *const node) \
2228 bemit_binop_mem(node, code); \
2239 * Creates a function for an Unop with code /ext encoding.
2241 #define UNOP(op, code, ext, input) \
2242 static void bemit_ ## op(const ir_node *node) { \
2243 bemit_unop(node, code, ext, input); \
2246 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2247 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2248 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2249 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2250 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2251 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2253 /* TODO: am support for IJmp */
2254 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2256 #define SHIFT(op, ext) \
2257 static void bemit_##op(const ir_node *node) \
2259 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2260 ir_node *count = get_irn_n(node, 1); \
2261 if (is_ia32_Immediate(count)) { \
2262 int offset = get_ia32_immediate_attr_const(count)->offset; \
2263 if (offset == 1) { \
2265 bemit_modru(out, ext); \
2268 bemit_modru(out, ext); \
2273 bemit_modru(out, ext); \
2277 static void bemit_##op##mem(const ir_node *node) \
2280 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2283 count = get_irn_n(node, 1); \
2284 if (is_ia32_Immediate(count)) { \
2285 int offset = get_ia32_immediate_attr_const(count)->offset; \
2286 if (offset == 1) { \
2287 bemit8(size == 8 ? 0xD0 : 0xD1); \
2288 bemit_mod_am(ext, node); \
2290 bemit8(size == 8 ? 0xC0 : 0xC1); \
2291 bemit_mod_am(ext, node); \
2295 bemit8(size == 8 ? 0xD2 : 0xD3); \
2296 bemit_mod_am(ext, node); \
2306 static void bemit_shld(const ir_node *node)
2308 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2309 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2310 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2312 if (is_ia32_Immediate(count)) {
2314 bemit_modrr(out, in);
2315 bemit8(get_ia32_immediate_attr_const(count)->offset);
2318 bemit_modrr(out, in);
2322 static void bemit_shrd(const ir_node *node)
2324 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2325 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2326 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2328 if (is_ia32_Immediate(count)) {
2330 bemit_modrr(out, in);
2331 bemit8(get_ia32_immediate_attr_const(count)->offset);
2334 bemit_modrr(out, in);
2338 static void bemit_sbb0(ir_node const *const node)
2340 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2341 unsigned char const reg = reg_gp_map[out->index];
2343 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2347 * binary emitter for setcc.
2349 static void bemit_setcc(const ir_node *node)
2351 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2353 ia32_condition_code_t cc = get_ia32_condcode(node);
2354 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2355 if (cc & ia32_cc_float_parity_cases) {
2356 if (cc & ia32_cc_negated) {
2359 bemit8(0x90 | pnc2cc(cc));
2360 bemit_modrm8(REG_LOW, dreg);
2365 bemit_modrm8(REG_HIGH, dreg);
2367 /* orb %>dreg, %<dreg */
2369 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2373 bemit8(0x90 | pnc2cc(cc));
2374 bemit_modrm8(REG_LOW, dreg);
2379 bemit_modrm8(REG_HIGH, dreg);
2381 /* andb %>dreg, %<dreg */
2383 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2388 bemit8(0x90 | pnc2cc(cc));
2389 bemit_modrm8(REG_LOW, dreg);
2393 static void bemit_bsf(ir_node const *const node)
2395 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2398 static void bemit_bsr(ir_node const *const node)
2400 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2403 static void bemit_bswap(ir_node const *const node)
2406 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2409 static void bemit_bt(ir_node const *const node)
2412 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2413 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2414 if (is_ia32_Immediate(right)) {
2415 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2416 int const offset = attr->offset;
2417 assert(!attr->symconst);
2418 assert(get_signed_imm_size(offset) == 1);
2420 bemit_modru(lreg, 4);
2424 bemit_modrr(lreg, arch_get_irn_register(right));
2428 static void bemit_cmovcc(const ir_node *node)
2430 const ia32_attr_t *attr = get_ia32_attr_const(node);
2431 int ins_permuted = attr->data.ins_permuted;
2432 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2433 ia32_condition_code_t cc = get_ia32_condcode(node);
2434 const arch_register_t *in_true;
2435 const arch_register_t *in_false;
2437 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2439 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2440 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2442 /* should be same constraint fullfilled? */
2443 if (out == in_false) {
2444 /* yes -> nothing to do */
2445 } else if (out == in_true) {
2446 assert(get_ia32_op_type(node) == ia32_Normal);
2447 ins_permuted = !ins_permuted;
2451 bemit8(0x8B); // mov %in_false, %out
2452 bemit_modrr(in_false, out);
2456 cc = ia32_negate_condition_code(cc);
2458 if (cc & ia32_cc_float_parity_cases)
2459 panic("cmov can't handle parity float cases");
2462 bemit8(0x40 | pnc2cc(cc));
2463 if (get_ia32_op_type(node) == ia32_Normal) {
2464 bemit_modrr(in_true, out);
2466 bemit_mod_am(reg_gp_map[out->index], node);
2470 static void bemit_test(ir_node const *const node)
2472 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
2476 unsigned const op = size == 8 ? OP_8 : OP_16_32;
2477 ir_node *const right = get_irn_n(node, n_ia32_Test_right);
2478 if (is_ia32_Immediate(right)) {
2479 /* Emit the main opcode. */
2480 if (get_ia32_op_type(node) == ia32_Normal) {
2481 arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_Test_left);
2482 /* Try to use the shorter al/ax/eax form. */
2483 if (dst->index == REG_GP_EAX) {
2487 bemit_modru(dst, 0);
2491 bemit_mod_am(0, node);
2494 /* Emit the immediate. */
2495 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2497 case 8: bemit8(attr->offset); break;
2498 case 16: bemit16(attr->offset); break;
2499 case 32: bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false); break;
2503 arch_register_t const *const dst = arch_get_irn_register_in(node, n_ia32_Test_left);
2504 if (get_ia32_op_type(node) == ia32_Normal) {
2505 arch_register_t const *const src = arch_get_irn_register(right);
2506 bemit_modrr(src, dst);
2508 bemit_mod_am(reg_gp_map[dst->index], node);
2513 static void bemit_imul(const ir_node *node)
2515 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2516 /* Do we need the immediate form? */
2517 if (is_ia32_Immediate(right)) {
2518 int imm = get_ia32_immediate_attr_const(right)->offset;
2519 if (get_signed_imm_size(imm) == 1) {
2520 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2523 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2527 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2531 static void bemit_dec(const ir_node *node)
2533 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2534 bemit8(0x48 + reg_gp_map[out->index]);
2537 static void bemit_inc(const ir_node *node)
2539 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2540 bemit8(0x40 + reg_gp_map[out->index]);
2543 #define UNOPMEM(op, code, ext) \
2544 static void bemit_##op(const ir_node *node) \
2546 bemit_unop_mem(node, code, ext); \
2549 UNOPMEM(notmem, 0xF6, 2)
2550 UNOPMEM(negmem, 0xF6, 3)
2551 UNOPMEM(incmem, 0xFE, 0)
2552 UNOPMEM(decmem, 0xFE, 1)
2554 static void bemit_ldtls(const ir_node *node)
2556 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2558 bemit8(0x65); // gs:
2559 if (out->index == REG_GP_EAX) {
2560 bemit8(0xA1); // movl 0, %eax
2562 bemit8(0x8B); // movl 0, %reg
2563 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2571 static void bemit_lea(const ir_node *node)
2573 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2575 bemit_mod_am(reg_gp_map[out->index], node);
2578 /* helper function for bemit_minus64bit */
2579 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2581 bemit8(0x8B); // movl %src, %dst
2582 bemit_modrr(src, dst);
2585 /* helper function for bemit_minus64bit */
2586 static void bemit_helper_neg(const arch_register_t *reg)
2588 bemit8(0xF7); // negl %reg
2589 bemit_modru(reg, 3);
2592 /* helper function for bemit_minus64bit */
2593 static void bemit_helper_sbb0(const arch_register_t *reg)
2595 bemit8(0x83); // sbbl $0, %reg
2596 bemit_modru(reg, 3);
2600 /* helper function for bemit_minus64bit */
2601 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2603 bemit8(0x1B); // sbbl %src, %dst
2604 bemit_modrr(src, dst);
2607 /* helper function for bemit_minus64bit */
2608 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2610 if (src->index == REG_GP_EAX) {
2611 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2612 } else if (dst->index == REG_GP_EAX) {
2613 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2615 bemit8(0x87); // xchgl %src, %dst
2616 bemit_modrr(src, dst);
2620 /* helper function for bemit_minus64bit */
2621 static void bemit_helper_zero(const arch_register_t *reg)
2623 bemit8(0x33); // xorl %reg, %reg
2624 bemit_modrr(reg, reg);
2627 static void bemit_minus64bit(const ir_node *node)
2629 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2630 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2631 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2632 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2634 if (out_lo == in_lo) {
2635 if (out_hi != in_hi) {
2636 /* a -> a, b -> d */
2639 /* a -> a, b -> b */
2642 } else if (out_lo == in_hi) {
2643 if (out_hi == in_lo) {
2644 /* a -> b, b -> a */
2645 bemit_helper_xchg(in_lo, in_hi);
2648 /* a -> b, b -> d */
2649 bemit_helper_mov(in_hi, out_hi);
2650 bemit_helper_mov(in_lo, out_lo);
2654 if (out_hi == in_lo) {
2655 /* a -> c, b -> a */
2656 bemit_helper_mov(in_lo, out_lo);
2658 } else if (out_hi == in_hi) {
2659 /* a -> c, b -> b */
2660 bemit_helper_mov(in_lo, out_lo);
2663 /* a -> c, b -> d */
2664 bemit_helper_mov(in_lo, out_lo);
2670 bemit_helper_neg( out_hi);
2671 bemit_helper_neg( out_lo);
2672 bemit_helper_sbb0(out_hi);
2676 bemit_helper_zero(out_hi);
2677 bemit_helper_neg( out_lo);
2678 bemit_helper_sbb( in_hi, out_hi);
2682 * Emit a single opcode.
2684 #define EMIT_SINGLEOP(op, code) \
2685 static void bemit_ ## op(const ir_node *node) { \
2690 //EMIT_SINGLEOP(daa, 0x27)
2691 //EMIT_SINGLEOP(das, 0x2F)
2692 //EMIT_SINGLEOP(aaa, 0x37)
2693 //EMIT_SINGLEOP(aas, 0x3F)
2694 //EMIT_SINGLEOP(nop, 0x90)
2695 EMIT_SINGLEOP(cwtl, 0x98)
2696 EMIT_SINGLEOP(cltd, 0x99)
2697 //EMIT_SINGLEOP(fwait, 0x9B)
2698 EMIT_SINGLEOP(sahf, 0x9E)
2699 //EMIT_SINGLEOP(popf, 0x9D)
2700 EMIT_SINGLEOP(leave, 0xC9)
2701 EMIT_SINGLEOP(int3, 0xCC)
2702 //EMIT_SINGLEOP(iret, 0xCF)
2703 //EMIT_SINGLEOP(xlat, 0xD7)
2704 //EMIT_SINGLEOP(lock, 0xF0)
2705 EMIT_SINGLEOP(rep, 0xF3)
2706 //EMIT_SINGLEOP(halt, 0xF4)
2707 EMIT_SINGLEOP(cmc, 0xF5)
2708 EMIT_SINGLEOP(stc, 0xF9)
2709 //EMIT_SINGLEOP(cli, 0xFA)
2710 //EMIT_SINGLEOP(sti, 0xFB)
2711 //EMIT_SINGLEOP(std, 0xFD)
2714 * Emits a MOV out, [MEM].
2716 static void bemit_load(const ir_node *node)
2718 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2720 if (out->index == REG_GP_EAX) {
2721 ir_node *base = get_irn_n(node, n_ia32_base);
2722 int has_base = !is_ia32_NoReg_GP(base);
2723 ir_node *idx = get_irn_n(node, n_ia32_index);
2724 int has_index = !is_ia32_NoReg_GP(idx);
2725 if (!has_base && !has_index) {
2726 ir_entity *ent = get_ia32_am_sc(node);
2727 int offs = get_ia32_am_offs_int(node);
2728 /* load from constant address to EAX can be encoded
2731 bemit_entity(ent, 0, offs, false);
2736 bemit_mod_am(reg_gp_map[out->index], node);
2740 * Emits a MOV [mem], in.
2742 static void bemit_store(const ir_node *node)
2744 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2745 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2747 if (is_ia32_Immediate(value)) {
2750 bemit_mod_am(0, node);
2751 bemit8(get_ia32_immediate_attr_const(value)->offset);
2752 } else if (size == 16) {
2755 bemit_mod_am(0, node);
2756 bemit16(get_ia32_immediate_attr_const(value)->offset);
2759 bemit_mod_am(0, node);
2760 bemit_immediate(value, false);
2763 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2765 if (in->index == REG_GP_EAX) {
2766 ir_node *base = get_irn_n(node, n_ia32_base);
2767 int has_base = !is_ia32_NoReg_GP(base);
2768 ir_node *idx = get_irn_n(node, n_ia32_index);
2769 int has_index = !is_ia32_NoReg_GP(idx);
2770 if (!has_base && !has_index) {
2771 ir_entity *ent = get_ia32_am_sc(node);
2772 int offs = get_ia32_am_offs_int(node);
2773 /* store to constant address from EAX can be encoded as
2774 * 0xA2/0xA3 [offset]*/
2782 bemit_entity(ent, 0, offs, false);
2794 bemit_mod_am(reg_gp_map[in->index], node);
2798 static void bemit_conv_i2i(const ir_node *node)
2803 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
2804 unsigned opcode = 0xB6;
2805 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
2806 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
2807 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
2810 static void bemit_popcnt(ir_node const *const node)
2813 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
2819 static void bemit_push(const ir_node *node)
2821 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
2823 if (is_ia32_Immediate(value)) {
2824 const ia32_immediate_attr_t *attr
2825 = get_ia32_immediate_attr_const(value);
2826 unsigned size = get_signed_imm_size(attr->offset);
2832 bemit8((unsigned char)attr->offset);
2837 bemit_immediate(value, false);
2840 } else if (is_ia32_NoReg_GP(value)) {
2842 bemit_mod_am(6, node);
2844 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
2845 bemit8(0x50 + reg_gp_map[reg->index]);
2852 static void bemit_pop(const ir_node *node)
2854 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
2855 bemit8(0x58 + reg_gp_map[reg->index]);
2858 static void bemit_popmem(const ir_node *node)
2861 bemit_mod_am(0, node);
2864 static void bemit_call(const ir_node *node)
2866 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
2868 if (is_ia32_Immediate(proc)) {
2870 bemit_immediate(proc, true);
2872 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
2876 static void bemit_jmp(const ir_node *dest_block)
2879 bemit_jmp_destination(dest_block);
2882 static void bemit_jump(const ir_node *node)
2884 if (can_be_fallthrough(node))
2887 bemit_jmp(get_cfop_target_block(node));
2890 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
2892 unsigned char cc = pnc2cc(pnc);
2895 bemit_jmp_destination(dest_block);
2898 static void bemit_jp(bool odd, const ir_node *dest_block)
2902 bemit_jmp_destination(dest_block);
2905 static void bemit_ia32_jcc(const ir_node *node)
2907 ia32_condition_code_t cc = get_ia32_condcode(node);
2908 const ir_node *dest_true;
2909 const ir_node *dest_false;
2911 cc = determine_final_cc(node, 0, cc);
2913 /* get both Projs */
2914 ir_node const *proj_true = be_get_Proj_for_pn(node, pn_ia32_Jcc_true);
2915 assert(proj_true && "Jcc without true Proj");
2917 ir_node const *proj_false = be_get_Proj_for_pn(node, pn_ia32_Jcc_false);
2918 assert(proj_false && "Jcc without false Proj");
2920 if (can_be_fallthrough(proj_true)) {
2921 /* exchange both proj's so the second one can be omitted */
2922 const ir_node *t = proj_true;
2924 proj_true = proj_false;
2926 cc = ia32_negate_condition_code(cc);
2929 dest_true = get_cfop_target_block(proj_true);
2930 dest_false = get_cfop_target_block(proj_false);
2932 if (cc & ia32_cc_float_parity_cases) {
2933 /* Some floating point comparisons require a test of the parity flag,
2934 * which indicates that the result is unordered */
2935 if (cc & ia32_cc_negated) {
2936 bemit_jp(false, dest_true);
2938 /* we need a local label if the false proj is a fallthrough
2939 * as the falseblock might have no label emitted then */
2940 if (can_be_fallthrough(proj_false)) {
2942 bemit8(0x06); // jp + 6
2944 bemit_jp(false, dest_false);
2948 bemit_jcc(cc, dest_true);
2950 /* the second Proj might be a fallthrough */
2951 if (can_be_fallthrough(proj_false)) {
2952 /* it's a fallthrough */
2954 bemit_jmp(dest_false);
2958 static void bemit_switchjmp(const ir_node *node)
2960 ir_entity *jump_table = get_ia32_am_sc(node);
2961 const ir_switch_table *table = get_ia32_switch_table(node);
2963 bemit8(0xFF); // jmp *tbl.label(,%in,4)
2964 bemit_mod_am(0x05, node);
2966 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
2972 static void bemit_return(const ir_node *node)
2974 unsigned pop = be_Return_get_pop(node);
2975 if (pop > 0 || be_Return_get_emit_pop(node)) {
2977 assert(pop <= 0xffff);
2984 static void bemit_subsp(const ir_node *node)
2986 const arch_register_t *out;
2989 /* mov %esp, %out */
2991 out = arch_get_irn_register_out(node, 1);
2992 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
2995 static void bemit_incsp(const ir_node *node)
2998 const arch_register_t *reg;
3002 offs = be_get_IncSP_offset(node);
3013 size = get_signed_imm_size(offs);
3014 bemit8(size == 1 ? 0x83 : 0x81);
3016 reg = arch_get_irn_register_out(node, 0);
3017 bemit_modru(reg, ext);
3026 static void bemit_copybi(const ir_node *node)
3028 unsigned size = get_ia32_copyb_size(node);
3030 bemit8(0xA4); // movsb
3033 bemit8(0xA5); // movsw
3037 bemit8(0xA5); // movsl
3041 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3043 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3044 unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
3045 if (get_ia32_op_type(node) == ia32_Normal) {
3046 assert(!attr->pop || attr->res_in_reg);
3048 unsigned char op0 = 0xD8;
3049 if (attr->res_in_reg) op0 |= 0x04;
3050 if (attr->pop) op0 |= 0x02;
3053 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
3058 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3059 bemit8(size == 32 ? 0xD8 : 0xDC);
3060 bemit_mod_am(op, node);
3064 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3067 bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
3070 static void bemit_fabs(const ir_node *node)
3078 static void bemit_fadd(const ir_node *node)
3080 bemit_fbinop(node, 0, 0);
3083 static void bemit_fchs(const ir_node *node)
3091 static void bemit_fdiv(const ir_node *node)
3093 bemit_fbinop(node, 6, 7);
3096 static void bemit_ffreep(ir_node const *const node)
3098 bemit_fop_reg(node, 0xDF, 0xC0);
3101 static void bemit_fild(const ir_node *node)
3103 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3105 bemit8(0xDF); // filds
3106 bemit_mod_am(0, node);
3110 bemit8(0xDB); // fildl
3111 bemit_mod_am(0, node);
3115 bemit8(0xDF); // fildll
3116 bemit_mod_am(5, node);
3120 panic("invalid mode size");
3124 static void bemit_fist(const ir_node *node)
3127 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3129 case 16: bemit8(0xDF); op = 2; break; // fist[p]s
3130 case 32: bemit8(0xDB); op = 2; break; // fist[p]l
3131 case 64: bemit8(0xDF); op = 6; break; // fistpll
3132 default: panic("invalid mode size");
3134 if (get_ia32_x87_attr_const(node)->pop)
3136 // There is only a pop variant for 64 bit integer store.
3137 assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
3138 bemit_mod_am(op, node);
3141 static void bemit_fisttp(ir_node const *const node)
3143 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3144 case 16: bemit8(0xDF); break; // fisttps
3145 case 32: bemit8(0xDB); break; // fisttpl
3146 case 64: bemit8(0xDD); break; // fisttpll
3147 default: panic("Invalid mode size");
3149 bemit_mod_am(1, node);
3152 static void bemit_fld(const ir_node *node)
3154 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3156 bemit8(0xD9); // flds
3157 bemit_mod_am(0, node);
3161 bemit8(0xDD); // fldl
3162 bemit_mod_am(0, node);
3167 bemit8(0xDB); // fldt
3168 bemit_mod_am(5, node);
3172 panic("invalid mode size");
3176 static void bemit_fld1(const ir_node *node)
3180 bemit8(0xE8); // fld1
3183 static void bemit_fldcw(const ir_node *node)
3185 bemit8(0xD9); // fldcw
3186 bemit_mod_am(5, node);
3189 static void bemit_fldz(const ir_node *node)
3193 bemit8(0xEE); // fldz
3196 static void bemit_fmul(const ir_node *node)
3198 bemit_fbinop(node, 1, 1);
3201 static void bemit_fpop(const ir_node *node)
3203 bemit_fop_reg(node, 0xDD, 0xD8);
3206 static void bemit_fpush(const ir_node *node)
3208 bemit_fop_reg(node, 0xD9, 0xC0);
3211 static void bemit_fpushcopy(const ir_node *node)
3213 bemit_fop_reg(node, 0xD9, 0xC0);
3216 static void bemit_fst(const ir_node *node)
3219 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3221 case 32: bemit8(0xD9); op = 2; break; // fst[p]s
3222 case 64: bemit8(0xDD); op = 2; break; // fst[p]l
3224 case 96: bemit8(0xDB); op = 6; break; // fstpt
3225 default: panic("invalid mode size");
3227 if (get_ia32_x87_attr_const(node)->pop)
3229 // There is only a pop variant for long double store.
3230 assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
3231 bemit_mod_am(op, node);
3234 static void bemit_fsub(const ir_node *node)
3236 bemit_fbinop(node, 4, 5);
3239 static void bemit_fnstcw(const ir_node *node)
3241 bemit8(0xD9); // fnstcw
3242 bemit_mod_am(7, node);
3245 static void bemit_fnstsw(void)
3247 bemit8(0xDF); // fnstsw %ax
3251 static void bemit_ftstfnstsw(const ir_node *node)
3255 bemit8(0xD9); // ftst
3260 static void bemit_fucomi(const ir_node *node)
3262 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3263 bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
3264 bemit8(0xE8 + attr->reg->index);
3267 static void bemit_fucomfnstsw(const ir_node *node)
3269 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3270 bemit8(0xDD); // fucom[p]
3271 bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
3275 static void bemit_fucomppfnstsw(const ir_node *node)
3279 bemit8(0xDA); // fucompp
3284 static void bemit_fxch(const ir_node *node)
3286 bemit_fop_reg(node, 0xD9, 0xC8);
3289 static void ia32_register_binary_emitters(void)
3291 /* first clear the generic function pointer for all ops */
3292 ir_clear_opcodes_generic_func();
3294 /* benode emitter */
3295 be_set_emitter(op_be_Copy, bemit_copy);
3296 be_set_emitter(op_be_CopyKeep, bemit_copy);
3297 be_set_emitter(op_be_IncSP, bemit_incsp);
3298 be_set_emitter(op_be_Perm, bemit_perm);
3299 be_set_emitter(op_be_Return, bemit_return);
3300 be_set_emitter(op_ia32_Adc, bemit_adc);
3301 be_set_emitter(op_ia32_Add, bemit_add);
3302 be_set_emitter(op_ia32_AddMem, bemit_addmem);
3303 be_set_emitter(op_ia32_And, bemit_and);
3304 be_set_emitter(op_ia32_AndMem, bemit_andmem);
3305 be_set_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3306 be_set_emitter(op_ia32_Breakpoint, bemit_int3);
3307 be_set_emitter(op_ia32_Bsf, bemit_bsf);
3308 be_set_emitter(op_ia32_Bsr, bemit_bsr);
3309 be_set_emitter(op_ia32_Bswap, bemit_bswap);
3310 be_set_emitter(op_ia32_Bt, bemit_bt);
3311 be_set_emitter(op_ia32_CMovcc, bemit_cmovcc);
3312 be_set_emitter(op_ia32_Call, bemit_call);
3313 be_set_emitter(op_ia32_Cltd, bemit_cltd);
3314 be_set_emitter(op_ia32_Cmc, bemit_cmc);
3315 be_set_emitter(op_ia32_Cmp, bemit_cmp);
3316 be_set_emitter(op_ia32_Const, bemit_mov_const);
3317 be_set_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3318 be_set_emitter(op_ia32_CopyB_i, bemit_copybi);
3319 be_set_emitter(op_ia32_Cwtl, bemit_cwtl);
3320 be_set_emitter(op_ia32_Dec, bemit_dec);
3321 be_set_emitter(op_ia32_DecMem, bemit_decmem);
3322 be_set_emitter(op_ia32_Div, bemit_div);
3323 be_set_emitter(op_ia32_FldCW, bemit_fldcw);
3324 be_set_emitter(op_ia32_FnstCW, bemit_fnstcw);
3325 be_set_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3326 be_set_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3327 be_set_emitter(op_ia32_Fucomi, bemit_fucomi);
3328 be_set_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3329 be_set_emitter(op_ia32_IDiv, bemit_idiv);
3330 be_set_emitter(op_ia32_IJmp, bemit_ijmp);
3331 be_set_emitter(op_ia32_IMul, bemit_imul);
3332 be_set_emitter(op_ia32_IMul1OP, bemit_imul1op);
3333 be_set_emitter(op_ia32_Inc, bemit_inc);
3334 be_set_emitter(op_ia32_IncMem, bemit_incmem);
3335 be_set_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3336 be_set_emitter(op_ia32_Jmp, bemit_jump);
3337 be_set_emitter(op_ia32_LdTls, bemit_ldtls);
3338 be_set_emitter(op_ia32_Lea, bemit_lea);
3339 be_set_emitter(op_ia32_Leave, bemit_leave);
3340 be_set_emitter(op_ia32_Load, bemit_load);
3341 be_set_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3342 be_set_emitter(op_ia32_Mul, bemit_mul);
3343 be_set_emitter(op_ia32_Neg, bemit_neg);
3344 be_set_emitter(op_ia32_NegMem, bemit_negmem);
3345 be_set_emitter(op_ia32_Not, bemit_not);
3346 be_set_emitter(op_ia32_NotMem, bemit_notmem);
3347 be_set_emitter(op_ia32_Or, bemit_or);
3348 be_set_emitter(op_ia32_OrMem, bemit_ormem);
3349 be_set_emitter(op_ia32_Pop, bemit_pop);
3350 be_set_emitter(op_ia32_PopEbp, bemit_pop);
3351 be_set_emitter(op_ia32_PopMem, bemit_popmem);
3352 be_set_emitter(op_ia32_Popcnt, bemit_popcnt);
3353 be_set_emitter(op_ia32_Push, bemit_push);
3354 be_set_emitter(op_ia32_RepPrefix, bemit_rep);
3355 be_set_emitter(op_ia32_Rol, bemit_rol);
3356 be_set_emitter(op_ia32_RolMem, bemit_rolmem);
3357 be_set_emitter(op_ia32_Ror, bemit_ror);
3358 be_set_emitter(op_ia32_RorMem, bemit_rormem);
3359 be_set_emitter(op_ia32_Sahf, bemit_sahf);
3360 be_set_emitter(op_ia32_Sar, bemit_sar);
3361 be_set_emitter(op_ia32_SarMem, bemit_sarmem);
3362 be_set_emitter(op_ia32_Sbb, bemit_sbb);
3363 be_set_emitter(op_ia32_Sbb0, bemit_sbb0);
3364 be_set_emitter(op_ia32_Setcc, bemit_setcc);
3365 be_set_emitter(op_ia32_Shl, bemit_shl);
3366 be_set_emitter(op_ia32_ShlD, bemit_shld);
3367 be_set_emitter(op_ia32_ShlMem, bemit_shlmem);
3368 be_set_emitter(op_ia32_Shr, bemit_shr);
3369 be_set_emitter(op_ia32_ShrD, bemit_shrd);
3370 be_set_emitter(op_ia32_ShrMem, bemit_shrmem);
3371 be_set_emitter(op_ia32_Stc, bemit_stc);
3372 be_set_emitter(op_ia32_Store, bemit_store);
3373 be_set_emitter(op_ia32_Sub, bemit_sub);
3374 be_set_emitter(op_ia32_SubMem, bemit_submem);
3375 be_set_emitter(op_ia32_SubSP, bemit_subsp);
3376 be_set_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3377 be_set_emitter(op_ia32_Test, bemit_test);
3378 be_set_emitter(op_ia32_Xor, bemit_xor);
3379 be_set_emitter(op_ia32_Xor0, bemit_xor0);
3380 be_set_emitter(op_ia32_XorMem, bemit_xormem);
3381 be_set_emitter(op_ia32_fabs, bemit_fabs);
3382 be_set_emitter(op_ia32_fadd, bemit_fadd);
3383 be_set_emitter(op_ia32_fchs, bemit_fchs);
3384 be_set_emitter(op_ia32_fdiv, bemit_fdiv);
3385 be_set_emitter(op_ia32_ffreep, bemit_ffreep);
3386 be_set_emitter(op_ia32_fild, bemit_fild);
3387 be_set_emitter(op_ia32_fist, bemit_fist);
3388 be_set_emitter(op_ia32_fisttp, bemit_fisttp);
3389 be_set_emitter(op_ia32_fld, bemit_fld);
3390 be_set_emitter(op_ia32_fld1, bemit_fld1);
3391 be_set_emitter(op_ia32_fldz, bemit_fldz);
3392 be_set_emitter(op_ia32_fmul, bemit_fmul);
3393 be_set_emitter(op_ia32_fpop, bemit_fpop);
3394 be_set_emitter(op_ia32_fpush, bemit_fpush);
3395 be_set_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3396 be_set_emitter(op_ia32_fst, bemit_fst);
3397 be_set_emitter(op_ia32_fsub, bemit_fsub);
3398 be_set_emitter(op_ia32_fxch, bemit_fxch);
3400 /* ignore the following nodes */
3401 be_set_emitter(op_Phi, be_emit_nothing);
3402 be_set_emitter(op_be_Keep, be_emit_nothing);
3403 be_set_emitter(op_be_Start, be_emit_nothing);
3404 be_set_emitter(op_ia32_ProduceVal, be_emit_nothing);
3405 be_set_emitter(op_ia32_Unknown, be_emit_nothing);
3408 static void gen_binary_block(ir_node *block)
3410 ia32_emit_block_header(block);
3412 /* emit the contents of the block */
3413 sched_foreach(block, node) {
3414 ia32_emit_node(node);
3418 void ia32_gen_binary_routine(ir_graph *irg)
3420 ir_entity *entity = get_irg_entity(irg);
3421 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3422 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3423 ir_node **blk_sched = irg_data->blk_sched;
3425 parameter_dbg_info_t *infos;
3427 isa = (ia32_isa_t*) arch_env;
3429 ia32_register_binary_emitters();
3431 infos = construct_parameter_infos(irg);
3432 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3436 /* we use links to point to target blocks */
3437 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3438 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3440 /* initialize next block links */
3441 n = ARR_LEN(blk_sched);
3442 for (i = 0; i < n; ++i) {
3443 ir_node *block = blk_sched[i];
3444 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3446 set_irn_link(block, prev);
3449 for (i = 0; i < n; ++i) {
3450 ir_node *block = blk_sched[i];
3451 gen_binary_block(block);
3454 be_gas_emit_function_epilog(entity);
3456 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3460 void ia32_init_emitter(void)
3462 lc_opt_entry_t *be_grp;
3463 lc_opt_entry_t *ia32_grp;
3465 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3466 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3468 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3472 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");