2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "ia32_emitter.h"
28 #include "gen_ia32_emitter.h"
29 #include "gen_ia32_regalloc_if.h"
30 #include "ia32_nodes_attr.h"
31 #include "ia32_new_nodes.h"
32 #include "ia32_map_regs.h"
33 #include "bearch_ia32_t.h"
35 #define BLOCK_PREFIX(x) ".L" x
37 #define SNPRINTF_BUF_LEN 128
39 /* global arch_env for lc_printf functions */
40 static const arch_env_t *arch_env = NULL;
42 /** by default, we generate assembler code for the Linux gas */
43 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
46 * Switch to a new section
48 void ia32_switch_section(FILE *F, section_t sec) {
49 static section_t curr_sec = NO_SECTION;
50 static const char *text[ASM_MAX][SECTION_MAX] = {
52 ".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
55 ".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text"
72 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
76 static void ia32_dump_function_object(FILE *F, const char *name)
78 switch (asm_flavour) {
80 fprintf(F, "\t.type\t%s, @function\n", name);
83 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
88 static void ia32_dump_function_size(FILE *F, const char *name)
90 switch (asm_flavour) {
92 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
97 /*************************************************************
99 * (_) | | / _| | | | |
100 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
101 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
102 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
103 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
106 *************************************************************/
108 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
110 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
111 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
112 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
116 * returns true if a node has x87 registers
118 static INLINE int has_x87_register(const ir_node *n) {
119 return is_irn_machine_user(n, 0);
122 /* We always pass the ir_node which is a pointer. */
123 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
124 return lc_arg_type_ptr;
129 * Returns the register at in position pos.
131 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
133 const arch_register_t *reg = NULL;
135 assert(get_irn_arity(irn) > pos && "Invalid IN position");
137 /* The out register of the operator at position pos is the
138 in register we need. */
139 op = get_irn_n(irn, pos);
141 reg = arch_get_irn_register(arch_env, op);
143 assert(reg && "no in register found");
145 /* in case of unknown: just return a register */
146 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
147 reg = &ia32_gp_regs[REG_EAX];
148 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
149 reg = &ia32_xmm_regs[REG_XMM0];
150 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
151 reg = &ia32_vfp_regs[REG_VF0];
157 * Returns the register at out position pos.
159 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
161 const arch_register_t *reg = NULL;
163 /* 1st case: irn is not of mode_T, so it has only */
164 /* one OUT register -> good */
165 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
166 /* Proj with the corresponding projnum for the register */
168 if (get_irn_mode(irn) != mode_T) {
169 reg = arch_get_irn_register(arch_env, irn);
171 else if (is_ia32_irn(irn)) {
172 reg = get_ia32_out_reg(irn, pos);
175 const ir_edge_t *edge;
177 foreach_out_edge(irn, edge) {
178 proj = get_edge_src_irn(edge);
179 assert(is_Proj(proj) && "non-Proj from mode_T node");
180 if (get_Proj_proj(proj) == pos) {
181 reg = arch_get_irn_register(arch_env, proj);
187 assert(reg && "no out register found");
197 * Returns the name of the in register at position pos.
199 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
200 const arch_register_t *reg;
202 if (in_out == IN_REG) {
203 reg = get_in_reg(irn, pos);
205 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
206 /* FIXME: works for binop only */
207 assert(2 <= pos && pos <= 3);
208 reg = get_ia32_attr(irn)->x87[pos - 2];
212 /* destination address mode nodes don't have outputs */
213 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
217 reg = get_out_reg(irn, pos);
218 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
219 reg = get_ia32_attr(irn)->x87[pos + 2];
221 return arch_register_get_name(reg);
225 * Get the register name for a node.
227 static int ia32_get_reg_name(lc_appendable_t *app,
228 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
231 ir_node *irn = arg->v_ptr;
232 int nr = occ->width - 1;
235 return lc_appendable_snadd(app, "(null)", 6);
237 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
239 /* append the stupid % to register names */
240 lc_appendable_chadd(app, '%');
241 return lc_appendable_snadd(app, buf, strlen(buf));
245 * Get the x87 register name for a node.
247 static int ia32_get_x87_name(lc_appendable_t *app,
248 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
251 ir_node *irn = arg->v_ptr;
252 int nr = occ->width - 1;
256 return lc_appendable_snadd(app, "(null)", 6);
258 attr = get_ia32_attr(irn);
259 buf = attr->x87[nr]->name;
260 lc_appendable_chadd(app, '%');
261 return lc_appendable_snadd(app, buf, strlen(buf));
265 * Returns the tarval, offset or scale of an ia32 as a string.
267 static int ia32_const_to_str(lc_appendable_t *app,
268 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
271 ir_node *irn = arg->v_ptr;
274 return lc_arg_append(app, occ, "(null)", 6);
276 if (occ->conversion == 'C') {
277 buf = get_ia32_cnst(irn);
280 buf = get_ia32_am_offs(irn);
283 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
287 * Determines the SSE suffix depending on the mode.
289 static int ia32_get_mode_suffix(lc_appendable_t *app,
290 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
292 ir_node *irn = arg->v_ptr;
293 ir_mode *mode = get_irn_mode(irn);
295 if (mode == mode_T) {
296 mode = get_ia32_res_mode(irn);
298 mode = get_ia32_ls_mode(irn);
302 return lc_arg_append(app, occ, "(null)", 6);
304 if (mode_is_float(mode)) {
305 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
308 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
313 * Return the ia32 printf arg environment.
314 * We use the firm environment with some additional handlers.
316 const lc_arg_env_t *ia32_get_arg_env(void) {
317 static lc_arg_env_t *env = NULL;
319 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
320 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
321 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
322 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
325 /* extend the firm printer */
326 env = firm_get_arg_env();
328 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
329 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
330 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
331 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
332 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
333 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
339 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
340 switch(get_mode_size_bits(mode)) {
342 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
344 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
346 return (char *)arch_register_get_name(reg);
351 * Emits registers and/or address mode of a binary operation.
353 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
354 static char *buf = NULL;
356 /* verify that this function is never called on non-AM supporting operations */
357 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
359 #define PRODUCES_RESULT(n) \
360 (!(is_ia32_St(n) || \
361 is_ia32_Store8Bit(n) || \
362 is_ia32_CondJmp(n) || \
363 is_ia32_xCondJmp(n) || \
364 is_ia32_CmpSet(n) || \
365 is_ia32_xCmpSet(n) || \
366 is_ia32_SwitchJmp(n)))
369 buf = xcalloc(1, SNPRINTF_BUF_LEN);
372 memset(buf, 0, SNPRINTF_BUF_LEN);
375 switch(get_ia32_op_type(n)) {
377 if (is_ia32_ImmConst(n)) {
378 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
380 else if (is_ia32_ImmSymConst(n)) {
381 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
384 const arch_register_t *in1 = get_in_reg(n, 2);
385 const arch_register_t *in2 = get_in_reg(n, 3);
386 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
387 const arch_register_t *in;
390 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
391 out = out ? out : in1;
392 in_name = arch_register_get_name(in);
394 if (is_ia32_emit_cl(n)) {
395 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
399 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
403 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
404 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
405 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
408 if (PRODUCES_RESULT(n)) {
409 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
412 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
417 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
418 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
419 ia32_emit_am(n, env),
420 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
421 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
424 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
425 ir_mode *mode = get_ia32_res_mode(n);
428 mode = mode ? mode : get_ia32_ls_mode(n);
429 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
431 if (is_ia32_emit_cl(n)) {
432 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
436 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
440 assert(0 && "unsupported op type");
443 #undef PRODUCES_RESULT
449 * Returns the xxx PTR string for a given mode
451 * @param mode the mode
452 * @param x87_insn if non-zero returns the string for a x87 instruction
453 * else for a SSE instruction
455 static const char *pointer_size(ir_mode *mode, int x87_insn)
458 switch (get_mode_size_bits(mode)) {
459 case 8: return "BYTE PTR";
460 case 16: return "WORD PTR";
461 case 32: return "DWORD PTR";
467 case 96: return "XWORD PTR";
468 default: return NULL;
475 * Emits registers and/or address mode of a binary operation.
477 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
478 static char *buf = NULL;
480 /* verify that this function is never called on non-AM supporting operations */
481 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
484 buf = xcalloc(1, SNPRINTF_BUF_LEN);
487 memset(buf, 0, SNPRINTF_BUF_LEN);
490 switch(get_ia32_op_type(n)) {
492 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
493 ir_mode *mode = get_ia32_ls_mode(n);
494 const char *p = pointer_size(mode, 1);
495 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
498 ia32_attr_t *attr = get_ia32_attr(n);
499 const arch_register_t *in1 = attr->x87[0];
500 const arch_register_t *in2 = attr->x87[1];
501 const arch_register_t *out = attr->x87[2];
502 const arch_register_t *in;
505 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
506 out = out ? out : in1;
507 in_name = arch_register_get_name(in);
509 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
514 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
517 assert(0 && "unsupported op type");
524 * Emits registers and/or address mode of a unary operation.
526 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
527 static char *buf = NULL;
530 buf = xcalloc(1, SNPRINTF_BUF_LEN);
533 memset(buf, 0, SNPRINTF_BUF_LEN);
536 switch(get_ia32_op_type(n)) {
538 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
539 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
542 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
543 /* MulS and Mulh implicitly multiply by EAX */
544 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
547 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
551 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
555 Mulh is emitted via emit_unop
556 imul [MEM] means EDX:EAX <- EAX * [MEM]
558 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
559 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
562 assert(0 && "unsupported op type");
569 * Emits address mode.
571 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
572 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
576 static struct obstack *obst = NULL;
577 ir_mode *mode = get_ia32_ls_mode(n);
579 if (! is_ia32_Lea(n))
580 assert(mode && "AM node must have ls_mode attribute set.");
583 obst = xcalloc(1, sizeof(*obst));
586 obstack_free(obst, NULL);
589 /* obstack_free with NULL results in an uninitialized obstack */
592 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
594 obstack_printf(obst, "%s ", p);
596 /* emit address mode symconst */
597 if (get_ia32_am_sc(n)) {
598 if (is_ia32_am_sc_sign(n))
599 obstack_printf(obst, "-");
600 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
603 if (am_flav & ia32_B) {
604 obstack_printf(obst, "[");
605 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
609 if (am_flav & ia32_I) {
611 obstack_printf(obst, "+");
614 obstack_printf(obst, "[");
617 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
619 if (am_flav & ia32_S) {
620 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
626 if (am_flav & ia32_O) {
627 s = get_ia32_am_offs(n);
630 /* omit explicit + if there was no base or index */
632 obstack_printf(obst, "[");
637 obstack_printf(obst, s);
643 obstack_printf(obst, "] ");
645 obstack_1grow(obst, '\0');
646 s = obstack_finish(obst);
654 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
656 static char buf[SNPRINTF_BUF_LEN];
657 ir_mode *mode = get_ia32_ls_mode(irn);
658 const char *adr = get_ia32_cnst(irn);
659 const char *pref = pointer_size(mode, has_x87_register(irn));
661 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
666 * Formated print of commands and comments.
668 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
670 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
673 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
675 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
681 * Add a number to a prefix. This number will not be used a second time.
683 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
684 static unsigned long id = 0;
685 snprintf(buf, buflen, "%s%lu", prefix, ++id);
691 /*************************************************
694 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
695 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
696 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
697 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
699 *************************************************/
702 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
705 * coding of conditions
707 struct cmp2conditon_t {
713 * positive conditions for signed compares
715 static const struct cmp2conditon_t cmp2condition_s[] = {
716 { NULL, pn_Cmp_False }, /* always false */
717 { "e", pn_Cmp_Eq }, /* == */
718 { "l", pn_Cmp_Lt }, /* < */
719 { "le", pn_Cmp_Le }, /* <= */
720 { "g", pn_Cmp_Gt }, /* > */
721 { "ge", pn_Cmp_Ge }, /* >= */
722 { "ne", pn_Cmp_Lg }, /* != */
723 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
724 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
725 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
726 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
727 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
728 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
729 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
730 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
731 { NULL, pn_Cmp_True }, /* always true */
735 * positive conditions for unsigned compares
737 static const struct cmp2conditon_t cmp2condition_u[] = {
738 { NULL, pn_Cmp_False }, /* always false */
739 { "e", pn_Cmp_Eq }, /* == */
740 { "b", pn_Cmp_Lt }, /* < */
741 { "be", pn_Cmp_Le }, /* <= */
742 { "a", pn_Cmp_Gt }, /* > */
743 { "ae", pn_Cmp_Ge }, /* >= */
744 { "ne", pn_Cmp_Lg }, /* != */
745 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
746 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
747 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
748 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
749 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
750 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
751 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
752 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
753 { NULL, pn_Cmp_True }, /* always true */
757 * returns the condition code
759 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
761 assert(cmp2condition_s[cmp_code].num == cmp_code);
762 assert(cmp2condition_u[cmp_code].num == cmp_code);
764 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
768 * Returns the target block for a control flow node.
770 static ir_node *get_cfop_target_block(const ir_node *irn) {
771 return get_irn_link(irn);
775 * Returns the target label for a control flow node.
777 static char *get_cfop_target(const ir_node *irn, char *buf) {
778 ir_node *bl = get_cfop_target_block(irn);
780 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
784 /** Return the next block in Block schedule */
785 static ir_node *next_blk_sched(const ir_node *block) {
786 return get_irn_link(block);
790 * Returns the Proj with projection number proj and NOT mode_M
792 static ir_node *get_proj(const ir_node *irn, long proj) {
793 const ir_edge_t *edge;
796 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
798 foreach_out_edge(irn, edge) {
799 src = get_edge_src_irn(edge);
801 assert(is_Proj(src) && "Proj expected");
802 if (get_irn_mode(src) == mode_M)
805 if (get_Proj_proj(src) == proj)
812 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
814 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
815 const ir_node *proj1, *proj2 = NULL;
816 const ir_node *block, *next_bl = NULL;
817 char buf[SNPRINTF_BUF_LEN];
818 char cmd_buf[SNPRINTF_BUF_LEN];
819 char cmnt_buf[SNPRINTF_BUF_LEN];
822 /* get both Proj's */
823 proj1 = get_proj(irn, pn_Cond_true);
824 assert(proj1 && "CondJmp without true Proj");
826 proj2 = get_proj(irn, pn_Cond_false);
827 assert(proj2 && "CondJmp without false Proj");
829 /* for now, the code works for scheduled and non-schedules blocks */
830 block = get_nodes_block(irn);
832 /* we have a block schedule */
833 next_bl = next_blk_sched(block);
835 if (get_cfop_target_block(proj1) == next_bl) {
836 /* exchange both proj's so the second one can be omitted */
837 const ir_node *t = proj1;
842 /* the first Proj must always be created */
843 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
844 if (get_Proj_proj(proj1) == pn_Cond_true) {
845 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
846 get_cmp_suffix(get_ia32_pncode(irn), is_unsigned),
847 get_cfop_target(proj1, buf));
848 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */");
851 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
852 get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode), is_unsigned),
853 get_cfop_target(proj1, buf));
854 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */");
858 /* the second Proj might be a fallthrough */
859 if (get_cfop_target_block(proj2) != next_bl) {
860 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
861 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
865 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf));
871 * Emits code for conditional jump.
873 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
875 char cmd_buf[SNPRINTF_BUF_LEN];
876 char cmnt_buf[SNPRINTF_BUF_LEN];
878 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
879 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
881 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
885 * Emits code for conditional jump with two variables.
887 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
888 CondJmp_emitter(irn, env);
892 * Emits code for conditional test and jump.
894 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
896 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
899 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
900 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
901 char cmd_buf[SNPRINTF_BUF_LEN];
902 char cmnt_buf[SNPRINTF_BUF_LEN];
905 op2 = arch_register_get_name(get_in_reg(irn, 1));
907 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
908 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
911 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
917 * Emits code for conditional test and jump with two variables.
919 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
920 TestJmp_emitter(irn, env);
923 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
925 char cmd_buf[SNPRINTF_BUF_LEN];
926 char cmnt_buf[SNPRINTF_BUF_LEN];
928 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
929 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
931 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
934 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
936 char cmd_buf[SNPRINTF_BUF_LEN];
937 char cmnt_buf[SNPRINTF_BUF_LEN];
939 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
940 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
942 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
946 * Emits code for conditional SSE floating point jump with two variables.
948 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
950 char cmd_buf[SNPRINTF_BUF_LEN];
951 char cmnt_buf[SNPRINTF_BUF_LEN];
953 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
954 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
956 finish_CondJmp(F, irn, mode_F);
961 * Emits code for conditional x87 floating point jump with two variables.
963 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
965 char cmd_buf[SNPRINTF_BUF_LEN];
966 char cmnt_buf[SNPRINTF_BUF_LEN];
967 ia32_attr_t *attr = get_ia32_attr(irn);
968 const char *reg = attr->x87[1]->name;
969 const char *instr = "fcom";
972 switch (get_ia32_pncode(irn)) {
973 case iro_ia32_fcomrJmp:
975 case iro_ia32_fcomJmp:
979 case iro_ia32_fcomrpJmp:
981 case iro_ia32_fcompJmp:
984 case iro_ia32_fcomrppJmp:
986 case iro_ia32_fcomppJmp:
993 set_ia32_pncode(irn, (long)get_negated_pnc(get_ia32_pncode(irn), mode_Is));
995 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s", instr, reg);
996 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
998 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
999 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1001 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1002 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1005 finish_CondJmp(F, irn, mode_Is);
1008 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1010 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1011 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1012 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1013 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1014 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1016 char cmd_buf[SNPRINTF_BUF_LEN];
1017 char cmnt_buf[SNPRINTF_BUF_LEN];
1018 const arch_register_t *in1, *in2, *out;
1020 out = arch_get_irn_register(env->arch_env, irn);
1021 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2 - is_PsiCondCMov));
1022 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3 - is_PsiCondCMov));
1024 /* we have to emit the cmp first, because the destination register */
1025 /* could be one of the compare registers */
1026 if (is_ia32_CmpCMov(irn)) {
1027 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1029 else if (is_ia32_xCmpCMov(irn)) {
1030 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1032 else if (is_PsiCondCMov) {
1033 /* omit compare because flags are already set by And/Or */
1034 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1037 assert(0 && "unsupported CMov");
1039 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1042 if (REGS_ARE_EQUAL(out, in2)) {
1043 /* best case: default in == out -> do nothing */
1045 else if (REGS_ARE_EQUAL(out, in1)) {
1046 /* true in == out -> need complement compare and exchange true and default in */
1047 ir_node *t = get_irn_n(irn, 2);
1048 set_irn_n(irn, 2, get_irn_n(irn, 3));
1049 set_irn_n(irn, 3, t);
1051 cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), is_unsigned);
1055 /* out is different from in: need copy default -> out */
1056 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1057 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1061 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1062 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1066 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1067 CMov_emitter(irn, env);
1070 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1071 CMov_emitter(irn, env);
1074 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1075 CMov_emitter(irn, env);
1078 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1080 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1081 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1082 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1083 const char *reg8bit;
1085 char cmd_buf[SNPRINTF_BUF_LEN];
1086 char cmnt_buf[SNPRINTF_BUF_LEN];
1087 const arch_register_t *out;
1089 out = arch_get_irn_register(env->arch_env, irn);
1090 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1092 if (is_ia32_CmpSet(irn)) {
1093 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1095 else if (is_ia32_xCmpSet(irn)) {
1096 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1098 else if (is_ia32_PsiCondSet(irn)) {
1099 /* omit compare because flags are already set by And/Or */
1100 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1103 assert(0 && "unsupported Set");
1105 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1108 /* use mov to clear target because it doesn't affect the eflags */
1109 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1110 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1113 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1114 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1118 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1119 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1122 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1123 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1126 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1127 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1130 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1132 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1134 char cmd_buf[SNPRINTF_BUF_LEN];
1135 char cmnt_buf[SNPRINTF_BUF_LEN];
1137 switch (get_ia32_pncode(irn)) {
1138 case pn_Cmp_Leg: /* odered */
1141 case pn_Cmp_Uo: /* unordered */
1144 case pn_Cmp_Ue: /* == */
1147 case pn_Cmp_Ul: /* < */
1150 case pn_Cmp_Ule: /* <= */
1153 case pn_Cmp_Ug: /* > */
1156 case pn_Cmp_Uge: /* >= */
1159 case pn_Cmp_Ne: /* != */
1164 assert(sse_pnc >= 0 && "unsupported floating point compare");
1166 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmps%M %s, %d", irn, ia32_emit_binop(irn, env), sse_pnc);
1167 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare with result in %1D */", irn);
1171 /*********************************************************
1174 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1175 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1176 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1177 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1180 *********************************************************/
1182 /* jump table entry (target and corresponding number) */
1183 typedef struct _branch_t {
1188 /* jump table for switch generation */
1189 typedef struct _jmp_tbl_t {
1190 ir_node *defProj; /**< default target */
1191 int min_value; /**< smallest switch case */
1192 int max_value; /**< largest switch case */
1193 int num_branches; /**< number of jumps */
1194 char *label; /**< label of the jump table */
1195 branch_t *branches; /**< jump array */
1199 * Compare two variables of type branch_t. Used to sort all switch cases
1201 static int ia32_cmp_branch_t(const void *a, const void *b) {
1202 branch_t *b1 = (branch_t *)a;
1203 branch_t *b2 = (branch_t *)b;
1205 if (b1->value <= b2->value)
1212 * Emits code for a SwitchJmp (creates a jump table if
1213 * possible otherwise a cmp-jmp cascade). Port from
1216 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1217 unsigned long interval;
1218 char buf[SNPRINTF_BUF_LEN];
1219 int last_value, i, pn;
1222 const ir_edge_t *edge;
1223 const lc_arg_env_t *env = ia32_get_arg_env();
1224 FILE *F = emit_env->out;
1225 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1227 /* fill the table structure */
1228 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1229 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1231 tbl.num_branches = get_irn_n_edges(irn);
1232 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1233 tbl.min_value = INT_MAX;
1234 tbl.max_value = INT_MIN;
1237 /* go over all proj's and collect them */
1238 foreach_out_edge(irn, edge) {
1239 proj = get_edge_src_irn(edge);
1240 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1242 pn = get_Proj_proj(proj);
1244 /* create branch entry */
1245 tbl.branches[i].target = proj;
1246 tbl.branches[i].value = pn;
1248 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1249 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1251 /* check for default proj */
1252 if (pn == get_ia32_pncode(irn)) {
1253 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1260 /* sort the branches by their number */
1261 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1263 /* two-complement's magic make this work without overflow */
1264 interval = tbl.max_value - tbl.min_value;
1266 /* emit the table */
1267 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1268 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1271 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1272 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1275 if (tbl.num_branches > 1) {
1278 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1279 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1282 ia32_switch_section(F, SECTION_RODATA);
1283 fprintf(F, "\t.align 4\n");
1285 fprintf(F, "%s:\n", tbl.label);
1287 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1288 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1291 last_value = tbl.branches[0].value;
1292 for (i = 1; i < tbl.num_branches; ++i) {
1293 while (++last_value < tbl.branches[i].value) {
1294 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1295 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1298 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1299 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1302 ia32_switch_section(F, SECTION_TEXT);
1305 /* one jump is enough */
1306 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1307 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1318 * Emits code for a unconditional jump.
1320 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1321 ir_node *block, *next_bl;
1323 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1325 /* for now, the code works for scheduled and non-schedules blocks */
1326 block = get_nodes_block(irn);
1328 /* we have a block schedule */
1329 next_bl = next_blk_sched(block);
1330 if (get_cfop_target_block(irn) != next_bl) {
1331 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1332 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1336 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1341 /****************************
1344 * _ __ _ __ ___ _ ___
1345 * | '_ \| '__/ _ \| |/ __|
1346 * | |_) | | | (_) | |\__ \
1347 * | .__/|_| \___/| ||___/
1350 ****************************/
1353 * Emits code for a proj -> node
1355 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1356 ir_node *pred = get_Proj_pred(irn);
1358 if (get_irn_op(pred) == op_Start) {
1359 switch(get_Proj_proj(irn)) {
1360 case pn_Start_X_initial_exec:
1369 /**********************************
1372 * | | ___ _ __ _ _| |_) |
1373 * | | / _ \| '_ \| | | | _ <
1374 * | |___| (_) | |_) | |_| | |_) |
1375 * \_____\___/| .__/ \__, |____/
1378 **********************************/
1381 * Emit movsb/w instructions to make mov count divideable by 4
1383 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1384 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1386 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1388 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1389 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1394 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1395 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1399 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1400 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1404 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1405 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1407 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1408 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1416 * Emit rep movsd instruction for memcopy.
1418 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1419 FILE *F = emit_env->out;
1420 tarval *tv = get_ia32_Immop_tarval(irn);
1421 int rem = get_tarval_long(tv);
1422 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1424 emit_CopyB_prolog(F, irn, rem);
1426 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1427 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1432 * Emits unrolled memcopy.
1434 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1435 tarval *tv = get_ia32_Immop_tarval(irn);
1436 int size = get_tarval_long(tv);
1437 FILE *F = emit_env->out;
1438 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1440 emit_CopyB_prolog(F, irn, size & 0x3);
1444 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1445 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1452 /***************************
1456 * | | / _ \| '_ \ \ / /
1457 * | |___| (_) | | | \ V /
1458 * \_____\___/|_| |_|\_/
1460 ***************************/
1463 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1465 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1466 FILE *F = emit_env->out;
1467 const lc_arg_env_t *env = ia32_get_arg_env();
1468 ir_mode *src_mode = get_ia32_src_mode(irn);
1469 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1470 char *from, *to, buf[64];
1471 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1473 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1474 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1476 switch(get_ia32_op_type(irn)) {
1478 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1480 case ia32_AddrModeS:
1481 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1484 assert(0 && "unsupported op type for Conv");
1487 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1488 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1492 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1493 emit_ia32_Conv_with_FP(irn, emit_env);
1496 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1497 emit_ia32_Conv_with_FP(irn, emit_env);
1500 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1501 emit_ia32_Conv_with_FP(irn, emit_env);
1505 * Emits code for an Int conversion.
1507 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1508 FILE *F = emit_env->out;
1509 const lc_arg_env_t *env = ia32_get_arg_env();
1510 char *move_cmd = "movzx";
1511 char *conv_cmd = NULL;
1512 ir_mode *src_mode = get_ia32_src_mode(irn);
1513 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1515 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1516 const arch_register_t *in_reg, *out_reg;
1518 n = get_mode_size_bits(src_mode);
1519 m = get_mode_size_bits(tgt_mode);
1521 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1523 if (n == 8 || m == 8)
1525 else if (n == 16 || m == 16)
1528 assert(0 && "unsupported Conv_I2I");
1531 switch(get_ia32_op_type(irn)) {
1533 in_reg = get_in_reg(irn, 2);
1534 out_reg = get_out_reg(irn, 0);
1536 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1537 REGS_ARE_EQUAL(out_reg, in_reg) &&
1538 mode_is_signed(n < m ? src_mode : tgt_mode))
1540 /* argument and result are both in EAX and */
1541 /* signedness is ok: -> use converts */
1542 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1544 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1545 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1547 /* argument and result are in the same register */
1548 /* and signedness is ok: -> use and with mask */
1549 int mask = (1 << (n < m ? n : m)) - 1;
1550 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1553 /* use move w/o sign extension */
1554 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1555 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1559 case ia32_AddrModeS:
1560 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1561 move_cmd, irn, ia32_emit_am(irn, emit_env));
1564 assert(0 && "unsupported op type for Conv");
1567 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1568 irn, n, src_mode, m, tgt_mode);
1574 * Emits code for an 8Bit Int conversion.
1576 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1577 emit_ia32_Conv_I2I(irn, emit_env);
1581 /*******************************************
1584 * | |__ ___ _ __ ___ __| | ___ ___
1585 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1586 * | |_) | __/ | | | (_) | (_| | __/\__ \
1587 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1589 *******************************************/
1592 * Emits a backend call
1594 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1595 FILE *F = emit_env->out;
1596 entity *ent = be_Call_get_entity(irn);
1597 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1600 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1603 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1606 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1612 * Emits code to increase stack pointer.
1614 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1615 FILE *F = emit_env->out;
1616 unsigned offs = be_get_IncSP_offset(irn);
1617 be_stack_dir_t dir = be_get_IncSP_direction(irn);
1618 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1621 if (dir == be_stack_dir_expand)
1622 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1624 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, offs);
1625 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1628 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1629 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1636 * Emits code to set stack pointer.
1638 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1639 FILE *F = emit_env->out;
1640 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1642 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1643 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1648 * Emits code for Copy/CopyKeep.
1650 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1651 FILE *F = emit_env->out;
1652 const arch_env_t *aenv = emit_env->arch_env;
1653 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1655 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1656 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1659 if (mode_is_float(get_irn_mode(irn)))
1660 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1662 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1663 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1667 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1668 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1671 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1672 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1676 * Emits code for exchange.
1678 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1679 FILE *F = emit_env->out;
1680 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1681 const arch_register_t *in1, *in2;
1682 const arch_register_class_t *cls1, *cls2;
1684 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1685 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1687 cls1 = arch_register_get_class(in1);
1688 cls2 = arch_register_get_class(in2);
1690 assert(cls1 == cls2 && "Register class mismatch at Perm");
1692 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1693 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1695 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1696 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1697 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1699 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1700 assert(0 && "Perm with vfp should not happen");
1702 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1703 assert(0 && "Perm with st(X) should not happen");
1706 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1711 * Emits code for Constant loading.
1713 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1715 char cmd_buf[256], cmnt_buf[256];
1716 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1718 if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
1719 const char *instr = "xor";
1720 if (env->isa->opt_arch == arch_pentium_4) {
1721 /* P4 prefers sub r, r, others xor r, r */
1724 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1725 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1728 if (get_ia32_op_type(n) == ia32_SymConst) {
1729 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1730 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1733 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1734 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1737 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1740 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1742 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1744 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1749 /***********************************************************************************
1752 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1753 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1754 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1755 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1757 ***********************************************************************************/
1760 * Enters the emitter functions for handled nodes into the generic
1761 * pointer of an opcode.
1763 static void ia32_register_emitters(void) {
1765 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1766 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1767 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1768 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1770 /* first clear the generic function pointer for all ops */
1771 clear_irp_opcodes_generic_func();
1773 /* register all emitter functions defined in spec */
1774 ia32_register_spec_emitters();
1776 /* other ia32 emitter functions */
1782 IA32_EMIT(PsiCondCMov);
1784 IA32_EMIT(PsiCondSet);
1785 IA32_EMIT(SwitchJmp);
1788 IA32_EMIT(Conv_I2FP);
1789 IA32_EMIT(Conv_FP2I);
1790 IA32_EMIT(Conv_FP2FP);
1791 IA32_EMIT(Conv_I2I);
1792 IA32_EMIT(Conv_I2I8Bit);
1796 IA32_EMIT(xCmpCMov);
1797 IA32_EMIT(xCondJmp);
1798 IA32_EMIT2(fcomJmp, x87CondJmp);
1799 IA32_EMIT2(fcompJmp, x87CondJmp);
1800 IA32_EMIT2(fcomppJmp, x87CondJmp);
1801 IA32_EMIT2(fcomrJmp, x87CondJmp);
1802 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1803 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1805 /* benode emitter */
1825 * Emits code for a node.
1827 static void ia32_emit_node(const ir_node *irn, void *env) {
1828 ia32_emit_env_t *emit_env = env;
1829 FILE *F = emit_env->out;
1830 ir_op *op = get_irn_op(irn);
1831 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
1833 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
1835 if (op->ops.generic) {
1836 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
1840 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", irn, irn);
1845 * Emits gas alignment directives
1847 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
1848 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
1852 * Emits gas alignment directives for Functions depended on cpu architecture.
1854 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
1855 unsigned align; unsigned maximum_skip;
1857 /* gcc doesn't emit alignment for p4 ?*/
1858 if (cpu == arch_pentium_4)
1863 align = 2; maximum_skip = 3;
1866 align = 4; maximum_skip = 15;
1869 align = 5; maximum_skip = 31;
1872 align = 4; maximum_skip = 15;
1874 ia32_emit_alignment(F, align, maximum_skip);
1878 * Emits gas alignment directives for Labels depended on cpu architecture.
1880 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
1881 unsigned align; unsigned maximum_skip;
1883 /* gcc doesn't emit alignment for p4 ?*/
1884 if (cpu == arch_pentium_4)
1889 align = 2; maximum_skip = 3;
1892 align = 4; maximum_skip = 15;
1895 align = 5; maximum_skip = 7;
1898 align = 4; maximum_skip = 7;
1900 ia32_emit_alignment(F, align, maximum_skip);
1904 * Walks over the nodes in a block connected by scheduling edges
1905 * and emits code for each node.
1907 static void ia32_gen_block(ir_node *block, void *env) {
1908 ia32_emit_env_t *emit_env = env;
1910 int need_label = block != get_irg_start_block(get_irn_irg(block));
1912 if (! is_Block(block))
1915 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
1916 /* if the extended block scheduler is used, only leader blocks need
1918 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
1922 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
1923 fprintf(emit_env->out, BLOCK_PREFIX("%ld:\n"), get_irn_node_nr(block));
1926 sched_foreach(block, irn) {
1927 ia32_emit_node(irn, env);
1932 * Emits code for function start.
1934 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
1935 entity *irg_ent = get_irg_entity(irg);
1936 const char *irg_name = get_entity_ld_name(irg_ent);
1939 ia32_switch_section(F, SECTION_TEXT);
1940 ia32_emit_align_func(F, cpu);
1941 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
1942 fprintf(F, ".globl %s\n", irg_name);
1944 ia32_dump_function_object(F, irg_name);
1945 fprintf(F, "%s:\n", irg_name);
1949 * Emits code for function end
1951 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
1952 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
1954 ia32_dump_function_size(F, irg_name);
1960 * Sets labels for control flow nodes (jump target)
1961 * TODO: Jump optimization
1963 static void ia32_gen_labels(ir_node *block, void *env) {
1965 int n = get_Block_n_cfgpreds(block);
1967 for (n--; n >= 0; n--) {
1968 pred = get_Block_cfgpred(block, n);
1969 set_irn_link(pred, block);
1974 * Main driver. Emits the code for one routine.
1976 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
1977 ia32_emit_env_t emit_env;
1981 emit_env.arch_env = cg->arch_env;
1983 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
1984 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
1986 /* set the global arch_env (needed by print hooks) */
1987 arch_env = cg->arch_env;
1989 ia32_register_emitters();
1991 ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
1992 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
1994 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
1995 int i, n = ARR_LEN(cg->blk_sched);
1997 for (i = 0; i < n;) {
2000 block = cg->blk_sched[i];
2002 next_bl = i < n ? cg->blk_sched[i] : NULL;
2004 /* set here the link. the emitter expects to find the next block here */
2005 set_irn_link(block, next_bl);
2006 ia32_gen_block(block, &emit_env);
2010 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2011 in the block schedule. As this number should NEVER be equal the next block,
2012 we does not need a clear block link here. */
2013 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2016 ia32_emit_func_epilog(F, irg);