2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
72 #include "ia32_emitter.h"
73 #include "ia32_common_transform.h"
74 #include "gen_ia32_emitter.h"
75 #include "gen_ia32_regalloc_if.h"
76 #include "ia32_nodes_attr.h"
77 #include "ia32_new_nodes.h"
78 #include "ia32_architecture.h"
79 #include "bearch_ia32_t.h"
81 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
83 static const ia32_isa_t *isa;
84 static char pic_base_label[128];
85 static ir_label_t exc_label_id;
86 static int mark_spill_reload = 0;
89 static bool sp_relative;
90 static int frame_type_size;
91 static int callframe_offset;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (get_Block_entity(block) != NULL)
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Add a number to a prefix. This number will not be used a second time.
143 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
145 static unsigned long id = 0;
146 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
151 * Emit the name of the 8bit low register
153 static void emit_8bit_register(const arch_register_t *reg)
155 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
156 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
159 be_emit_char(reg->name[1]); /* get the basic name of the register */
164 * Emit the name of the 8bit high register
166 static void emit_8bit_register_high(const arch_register_t *reg)
168 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
169 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
172 be_emit_char(reg->name[1]); /* get the basic name of the register */
176 static void emit_16bit_register(const arch_register_t *reg)
179 be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
183 * emit a register, possible shortened by a mode
185 * @param reg the register
186 * @param mode the mode of the register or NULL for full register
188 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
191 int size = get_mode_size_bits(mode);
193 case 8: emit_8bit_register(reg); return;
194 case 16: emit_16bit_register(reg); return;
196 assert(mode_is_float(mode) || size == 32);
200 be_emit_string(reg->name);
203 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
205 be_gas_emit_entity(entity);
207 if (get_entity_owner(entity) == get_tls_type()) {
208 if (!entity_has_definition(entity)) {
209 be_emit_cstring("@INDNTPOFF");
211 be_emit_cstring("@NTPOFF");
215 if (do_pic && !no_pic_adjust) {
217 be_emit_string(pic_base_label);
221 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
223 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
225 if (attr->symconst != NULL) {
228 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
230 if (attr->symconst == NULL || attr->offset != 0) {
231 if (attr->symconst != NULL) {
232 be_emit_irprintf("%+d", attr->offset);
234 be_emit_irprintf("0x%X", attr->offset);
239 static void emit_ia32_Immediate(const ir_node *node)
242 emit_ia32_Immediate_no_prefix(node);
245 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
247 assert(mode_is_int(mode) || mode_is_reference(mode));
248 switch (get_mode_size_bits(mode)) {
249 case 8: be_emit_char('b'); return;
250 case 16: be_emit_char('w'); return;
251 case 32: be_emit_char('l'); return;
252 /* gas docu says q is the suffix but gcc, objdump and icc use ll
254 case 64: be_emit_cstring("ll"); return;
256 panic("Can't output mode_suffix for %+F", mode);
259 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
263 /* we only need to emit the mode on address mode */
264 if (get_ia32_op_type(node) == ia32_Normal)
267 mode = get_ia32_ls_mode(node);
268 assert(mode != NULL);
270 if (mode_is_float(mode)) {
271 switch (get_mode_size_bits(mode)) {
272 case 32: be_emit_char('s'); return;
273 case 64: be_emit_char('l'); return;
274 /* long doubles have different sizes due to alignment on different
278 case 128: be_emit_char('t'); return;
281 assert(mode_is_int(mode) || mode_is_reference(mode));
282 switch (get_mode_size_bits(mode)) {
283 case 16: be_emit_char('s'); return;
284 case 32: be_emit_char('l'); return;
285 /* gas docu says q is the suffix but gcc, objdump and icc use ll
287 case 64: be_emit_cstring("ll"); return;
290 panic("Can't output mode_suffix for %+F", mode);
293 static char get_xmm_mode_suffix(ir_mode *mode)
295 assert(mode_is_float(mode));
296 switch (get_mode_size_bits(mode)) {
299 default: panic("Invalid XMM mode");
303 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
305 ir_mode *mode = get_ia32_ls_mode(node);
306 assert(mode != NULL);
307 be_emit_char(get_xmm_mode_suffix(mode));
311 * Returns the target block for a control flow node.
313 static ir_node *get_cfop_target_block(const ir_node *irn)
315 assert(get_irn_mode(irn) == mode_X);
316 return (ir_node*)get_irn_link(irn);
320 * Emits the target label for a control flow node.
322 static void ia32_emit_cfop_target(const ir_node *node)
324 ir_node *block = get_cfop_target_block(node);
325 be_gas_emit_block_name(block);
329 * Emit the suffix for a compare instruction.
331 static void ia32_emit_condition_code(ia32_condition_code_t cc)
334 case ia32_cc_overflow: be_emit_cstring("o"); return;
335 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
336 case ia32_cc_float_below:
337 case ia32_cc_float_unordered_below:
338 case ia32_cc_below: be_emit_cstring("b"); return;
339 case ia32_cc_float_above_equal:
340 case ia32_cc_float_unordered_above_equal:
341 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
342 case ia32_cc_float_equal:
343 case ia32_cc_equal: be_emit_cstring("e"); return;
344 case ia32_cc_float_not_equal:
345 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
346 case ia32_cc_float_below_equal:
347 case ia32_cc_float_unordered_below_equal:
348 case ia32_cc_below_equal: be_emit_cstring("be"); return;
349 case ia32_cc_float_above:
350 case ia32_cc_float_unordered_above:
351 case ia32_cc_above: be_emit_cstring("a"); return;
352 case ia32_cc_sign: be_emit_cstring("s"); return;
353 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
354 case ia32_cc_parity: be_emit_cstring("p"); return;
355 case ia32_cc_not_parity: be_emit_cstring("np"); return;
356 case ia32_cc_less: be_emit_cstring("l"); return;
357 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
358 case ia32_cc_less_equal: be_emit_cstring("le"); return;
359 case ia32_cc_greater: be_emit_cstring("g"); return;
360 case ia32_cc_float_parity_cases:
361 case ia32_cc_additional_float_cases:
364 panic("Invalid ia32 condition code");
367 typedef enum ia32_emit_mod_t {
369 EMIT_RESPECT_LS = 1U << 0,
370 EMIT_ALTERNATE_AM = 1U << 1,
372 EMIT_HIGH_REG = 1U << 3,
373 EMIT_LOW_REG = 1U << 4,
374 EMIT_16BIT_REG = 1U << 5
376 ENUM_BITSET(ia32_emit_mod_t)
379 * Emits address mode.
381 static void ia32_emit_am(ir_node const *const node)
383 ir_entity *ent = get_ia32_am_sc(node);
384 int offs = get_ia32_am_offs_int(node);
385 ir_node *base = get_irn_n(node, n_ia32_base);
386 int has_base = !is_ia32_NoReg_GP(base);
387 ir_node *idx = get_irn_n(node, n_ia32_index);
388 int has_index = !is_ia32_NoReg_GP(idx);
390 /* just to be sure... */
391 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
393 if (get_ia32_am_tls_segment(node))
394 be_emit_cstring("%gs:");
398 const ia32_attr_t *attr = get_ia32_attr_const(node);
399 if (is_ia32_am_sc_sign(node))
401 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
404 /* also handle special case if nothing is set */
405 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
407 be_emit_irprintf("%+d", offs);
409 be_emit_irprintf("%d", offs);
413 if (has_base || has_index) {
418 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
419 emit_register(reg, NULL);
422 /* emit index + scale */
424 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
427 emit_register(reg, NULL);
429 scale = get_ia32_am_scale(node);
431 be_emit_irprintf(",%d", 1 << scale);
438 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
440 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
447 const char *start = fmt;
448 ia32_emit_mod_t mod = EMIT_NONE;
450 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
453 be_emit_string_len(start, fmt - start);
458 be_emit_write_line();
472 case '*': mod |= EMIT_ALTERNATE_AM; break;
473 case '#': mod |= EMIT_RESPECT_LS; break;
474 case 'l': mod |= EMIT_LONG; break;
475 case '>': mod |= EMIT_HIGH_REG; break;
476 case '<': mod |= EMIT_LOW_REG; break;
477 case '^': mod |= EMIT_16BIT_REG; break;
486 arch_register_t const *reg;
496 if (get_ia32_op_type(node) == ia32_Normal) {
497 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
498 char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
499 be_emit_irprintf(fmt, attr->reg->name);
507 if (mod & EMIT_ALTERNATE_AM)
513 reg = va_arg(ap, const arch_register_t*);
514 if (get_ia32_op_type(node) == ia32_Normal) {
521 if (get_ia32_op_type(node) == ia32_Normal) {
528 default: goto unknown;
534 imm = get_irn_n(node, n_ia32_binary_right);
535 if (is_ia32_Immediate(imm)) {
536 emit_ia32_Immediate(imm);
537 be_emit_cstring(", ");
538 if (get_ia32_op_type(node) == ia32_Normal) {
539 goto destination_operand;
544 if (get_ia32_op_type(node) == ia32_Normal) {
545 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
546 emit_register(reg, get_ia32_ls_mode(node));
550 be_emit_cstring(", ");
552 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
553 emit_register(reg, get_ia32_ls_mode(node));
558 if (*fmt < '0' || '9' < *fmt)
560 reg = arch_get_irn_register_out(node, *fmt++ - '0');
565 ia32_emit_x87_mode_suffix(node);
566 } else if (*fmt == 'P') {
567 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
570 } else if (*fmt == 'R') {
571 /* NOTE: Work around a gas quirk for non-commutative operations if the
572 * destination register is not %st0. In this case r/non-r is swapped.
573 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
574 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
575 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
576 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
577 * In fact this corresponds to the encoding of the instruction:
578 * - The r suffix selects whether %st0 is on the left (no r) or on the
579 * right (r) side of the executed operation.
580 * - The placement of %st0 selects whether the result is written to
581 * %st0 (right) or the other register (left).
582 * This means that it is sufficient to test whether the operands are
583 * permuted. In particular it is not necessary to consider wether the
584 * result is to be placed into the explicit register operand. */
585 if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
587 } else if (*fmt == 'X') {
588 ia32_emit_xmm_mode_suffix(node);
589 } else if (*fmt == '0') {
591 be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
601 if (!(mod & EMIT_ALTERNATE_AM))
603 emit_ia32_Immediate_no_prefix(imm);
607 ia32_emit_cfop_target(node);
611 ir_mode *mode = get_ia32_ls_mode(node);
614 if (mod & EMIT_RESPECT_LS) {
615 if (get_mode_size_bits(mode) == 32)
617 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
619 ia32_emit_mode_suffix_mode(mode);
624 ia32_condition_code_t cc;
627 cc = (ia32_condition_code_t)va_arg(ap, int);
628 } else if ('0' <= *fmt && *fmt <= '9') {
629 cc = get_ia32_condcode(node);
630 cc = determine_final_cc(node, *fmt - '0', cc);
635 ia32_emit_condition_code(cc);
640 reg = va_arg(ap, const arch_register_t*);
642 if (mod & EMIT_ALTERNATE_AM)
644 if (mod & EMIT_HIGH_REG) {
645 emit_8bit_register_high(reg);
646 } else if (mod & EMIT_LOW_REG) {
647 emit_8bit_register(reg);
648 } else if (mod & EMIT_16BIT_REG) {
649 emit_16bit_register(reg);
651 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
659 if (*fmt < '0' || '9' < *fmt)
663 imm = get_irn_n(node, pos);
664 if (is_ia32_Immediate(imm)) {
667 reg = arch_get_irn_register_in(node, pos);
673 const char *str = va_arg(ap, const char*);
679 if (mod & EMIT_LONG) {
680 unsigned long num = va_arg(ap, unsigned long);
681 be_emit_irprintf("%lu", num);
683 unsigned num = va_arg(ap, unsigned);
684 be_emit_irprintf("%u", num);
689 if (mod & EMIT_LONG) {
690 long num = va_arg(ap, long);
691 be_emit_irprintf("%ld", num);
693 int num = va_arg(ap, int);
694 be_emit_irprintf("%d", num);
700 panic("unknown format conversion");
704 be_emit_finish_line_gas(node);
708 static void emit_ia32_IMul(const ir_node *node)
710 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
711 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
713 /* do we need the 3-address form? */
714 if (is_ia32_NoReg_GP(left) ||
715 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
716 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
718 ia32_emitf(node, "imul%M %#AS4, %#S3");
723 * walks up a tree of copies/perms/spills/reloads to find the original value
724 * that is moved around
726 static ir_node *find_original_value(ir_node *node)
728 if (irn_visited(node))
731 mark_irn_visited(node);
732 if (be_is_Copy(node)) {
733 return find_original_value(be_get_Copy_op(node));
734 } else if (be_is_CopyKeep(node)) {
735 return find_original_value(be_get_CopyKeep_op(node));
736 } else if (is_Proj(node)) {
737 ir_node *pred = get_Proj_pred(node);
738 if (be_is_Perm(pred)) {
739 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
740 } else if (be_is_MemPerm(pred)) {
741 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
742 } else if (is_ia32_Load(pred)) {
743 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
744 } else if (is_ia32_Store(pred)) {
745 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
749 } else if (is_Phi(node)) {
751 arity = get_irn_arity(node);
752 for (i = 0; i < arity; ++i) {
753 ir_node *in = get_irn_n(node, i);
754 ir_node *res = find_original_value(in);
765 static ia32_condition_code_t determine_final_cc(const ir_node *node,
766 int flags_pos, ia32_condition_code_t cc)
768 ir_node *flags = get_irn_n(node, flags_pos);
769 const ia32_attr_t *flags_attr;
770 flags = skip_Proj(flags);
772 if (is_ia32_Sahf(flags)) {
773 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
774 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
775 inc_irg_visited(current_ir_graph);
776 cmp = find_original_value(cmp);
778 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
781 flags_attr = get_ia32_attr_const(cmp);
783 flags_attr = get_ia32_attr_const(flags);
786 if (flags_attr->data.ins_permuted)
787 cc = ia32_invert_condition_code(cc);
792 * Emits an exception label for a given node.
794 static void ia32_emit_exc_label(const ir_node *node)
796 be_emit_string(be_gas_insn_label_prefix());
797 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
801 * Returns the Proj with projection number proj and NOT mode_M
803 static ir_node *get_proj(const ir_node *node, long proj)
807 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
809 foreach_out_edge(node, edge) {
810 src = get_edge_src_irn(edge);
812 assert(is_Proj(src) && "Proj expected");
813 if (get_irn_mode(src) == mode_M)
816 if (get_Proj_proj(src) == proj)
822 static int can_be_fallthrough(const ir_node *node)
824 ir_node *target_block = get_cfop_target_block(node);
825 ir_node *block = get_nodes_block(node);
826 return get_prev_block_sched(target_block) == block;
830 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
832 static void emit_ia32_Jcc(const ir_node *node)
834 int need_parity_label = 0;
835 ia32_condition_code_t cc = get_ia32_condcode(node);
836 const ir_node *proj_true;
837 const ir_node *proj_false;
839 cc = determine_final_cc(node, 0, cc);
842 proj_true = get_proj(node, pn_ia32_Jcc_true);
843 assert(proj_true && "Jcc without true Proj");
845 proj_false = get_proj(node, pn_ia32_Jcc_false);
846 assert(proj_false && "Jcc without false Proj");
848 if (can_be_fallthrough(proj_true)) {
849 /* exchange both proj's so the second one can be omitted */
850 const ir_node *t = proj_true;
852 proj_true = proj_false;
854 cc = ia32_negate_condition_code(cc);
857 if (cc & ia32_cc_float_parity_cases) {
858 /* Some floating point comparisons require a test of the parity flag,
859 * which indicates that the result is unordered */
860 if (cc & ia32_cc_negated) {
861 ia32_emitf(proj_true, "jp %L");
863 /* we need a local label if the false proj is a fallthrough
864 * as the falseblock might have no label emitted then */
865 if (can_be_fallthrough(proj_false)) {
866 need_parity_label = 1;
867 ia32_emitf(proj_false, "jp 1f");
869 ia32_emitf(proj_false, "jp %L");
873 ia32_emitf(proj_true, "j%PX %L", (int)cc);
874 if (need_parity_label) {
875 be_emit_cstring("1:\n");
876 be_emit_write_line();
879 /* the second Proj might be a fallthrough */
880 if (can_be_fallthrough(proj_false)) {
881 if (be_options.verbose_asm)
882 ia32_emitf(proj_false, "/* fallthrough to %L */");
884 ia32_emitf(proj_false, "jmp %L");
889 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
892 static void emit_ia32_Setcc(const ir_node *node)
894 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
896 ia32_condition_code_t cc = get_ia32_condcode(node);
897 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
898 if (cc & ia32_cc_float_parity_cases) {
899 if (cc & ia32_cc_negated) {
900 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
901 ia32_emitf(node, "setp %>R", dreg);
902 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
904 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
905 ia32_emitf(node, "setnp %>R", dreg);
906 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
909 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
913 static void emit_ia32_CMovcc(const ir_node *node)
915 const ia32_attr_t *attr = get_ia32_attr_const(node);
916 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
917 ia32_condition_code_t cc = get_ia32_condcode(node);
918 const arch_register_t *in_true;
919 const arch_register_t *in_false;
921 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
922 /* although you can't set ins_permuted in the constructor it might still
923 * be set by memory operand folding
924 * Permuting inputs of a cmov means the condition is negated!
926 if (attr->data.ins_permuted)
927 cc = ia32_negate_condition_code(cc);
929 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
930 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
932 /* should be same constraint fullfilled? */
933 if (out == in_false) {
934 /* yes -> nothing to do */
935 } else if (out == in_true) {
936 const arch_register_t *tmp;
938 assert(get_ia32_op_type(node) == ia32_Normal);
940 cc = ia32_negate_condition_code(cc);
947 ia32_emitf(node, "movl %R, %R", in_false, out);
950 if (cc & ia32_cc_float_parity_cases) {
951 panic("CMov with floatingpoint compare/parity not supported yet");
954 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
958 * Emits code for a SwitchJmp
960 static void emit_ia32_SwitchJmp(const ir_node *node)
962 ir_entity *jump_table = get_ia32_am_sc(node);
963 const ir_switch_table *table = get_ia32_switch_table(node);
965 ia32_emitf(node, "jmp %*AM");
966 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
970 * Emits code for a unconditional jump.
972 static void emit_ia32_Jmp(const ir_node *node)
974 /* we have a block schedule */
975 if (can_be_fallthrough(node)) {
976 if (be_options.verbose_asm)
977 ia32_emitf(node, "/* fallthrough to %L */");
979 ia32_emitf(node, "jmp %L");
984 * Emit an inline assembler operand.
986 * @param node the ia32_ASM node
987 * @param s points to the operand (a %c)
989 * @return pointer to the first char in s NOT in the current operand
991 static const char* emit_asm_operand(const ir_node *node, const char *s)
993 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
994 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
996 const arch_register_t *reg;
997 const ia32_asm_reg_t *asm_regs = attr->register_map;
998 const ia32_asm_reg_t *asm_reg;
1007 /* parse modifiers */
1010 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1036 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1043 if (sscanf(s, "%d%n", &num, &p) != 1) {
1044 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1051 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1053 "Error: Custom assembler references invalid input/output (%+F)\n",
1057 asm_reg = & asm_regs[num];
1058 assert(asm_reg->valid);
1061 if (asm_reg->use_input == 0) {
1062 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1064 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1066 /* might be an immediate value */
1067 if (is_ia32_Immediate(pred)) {
1068 emit_ia32_Immediate(pred);
1071 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1075 "Warning: no register assigned for %d asm op (%+F)\n",
1080 if (asm_reg->memory) {
1085 if (modifier != 0) {
1088 emit_8bit_register(reg);
1091 emit_8bit_register_high(reg);
1094 emit_16bit_register(reg);
1097 panic("Invalid asm op modifier");
1100 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1103 if (asm_reg->memory) {
1111 * Emits code for an ASM pseudo op.
1113 static void emit_ia32_Asm(const ir_node *node)
1115 const void *gen_attr = get_irn_generic_attr_const(node);
1116 const ia32_asm_attr_t *attr
1117 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1118 ident *asm_text = attr->asm_text;
1119 const char *s = get_id_str(asm_text);
1121 be_emit_cstring("#APP\n");
1122 be_emit_write_line();
1129 s = emit_asm_operand(node, s);
1135 be_emit_cstring("\n#NO_APP\n");
1136 be_emit_write_line();
1141 * Emit movsb/w instructions to make mov count divideable by 4
1143 static void emit_CopyB_prolog(unsigned size)
1146 ia32_emitf(NULL, "movsb");
1148 ia32_emitf(NULL, "movsw");
1152 * Emit rep movsd instruction for memcopy.
1154 static void emit_ia32_CopyB(const ir_node *node)
1156 unsigned size = get_ia32_copyb_size(node);
1158 emit_CopyB_prolog(size);
1159 ia32_emitf(node, "rep movsd");
1163 * Emits unrolled memcopy.
1165 static void emit_ia32_CopyB_i(const ir_node *node)
1167 unsigned size = get_ia32_copyb_size(node);
1169 emit_CopyB_prolog(size);
1173 ia32_emitf(NULL, "movsd");
1179 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1181 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1184 ir_mode *ls_mode = get_ia32_ls_mode(node);
1185 int ls_bits = get_mode_size_bits(ls_mode);
1186 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1188 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1191 static void emit_ia32_Conv_I2FP(const ir_node *node)
1193 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1196 static void emit_ia32_Conv_FP2I(const ir_node *node)
1198 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1201 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1203 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1207 * Emits code to increase stack pointer.
1209 static void emit_be_IncSP(const ir_node *node)
1211 int offs = be_get_IncSP_offset(node);
1217 ia32_emitf(node, "subl $%u, %D0", offs);
1219 ia32_emitf(node, "addl $%u, %D0", -offs);
1224 * Emits code for Copy/CopyKeep.
1226 static void Copy_emitter(const ir_node *node, const ir_node *op)
1228 const arch_register_t *in = arch_get_irn_register(op);
1229 const arch_register_t *out = arch_get_irn_register(node);
1234 /* copies of fp nodes aren't real... */
1235 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
1238 ia32_emitf(node, "movl %R, %R", in, out);
1241 static void emit_be_Copy(const ir_node *node)
1243 Copy_emitter(node, be_get_Copy_op(node));
1246 static void emit_be_CopyKeep(const ir_node *node)
1248 Copy_emitter(node, be_get_CopyKeep_op(node));
1252 * Emits code for exchange.
1254 static void emit_be_Perm(const ir_node *node)
1256 const arch_register_t *in0, *in1;
1258 in0 = arch_get_irn_register(get_irn_n(node, 0));
1259 in1 = arch_get_irn_register(get_irn_n(node, 1));
1261 arch_register_class_t const *const cls0 = in0->reg_class;
1262 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
1264 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1265 ia32_emitf(node, "xchg %R, %R", in1, in0);
1266 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1267 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1268 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1269 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1270 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
1273 panic("unexpected register class in be_Perm (%+F)", node);
1277 /* helper function for emit_ia32_Minus64Bit */
1278 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1280 ia32_emitf(node, "movl %R, %R", src, dst);
1283 /* helper function for emit_ia32_Minus64Bit */
1284 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1286 ia32_emitf(node, "negl %R", reg);
1289 /* helper function for emit_ia32_Minus64Bit */
1290 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1292 ia32_emitf(node, "sbbl $0, %R", reg);
1295 /* helper function for emit_ia32_Minus64Bit */
1296 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1298 ia32_emitf(node, "sbbl %R, %R", src, dst);
1301 /* helper function for emit_ia32_Minus64Bit */
1302 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1304 ia32_emitf(node, "xchgl %R, %R", src, dst);
1307 /* helper function for emit_ia32_Minus64Bit */
1308 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1310 ia32_emitf(node, "xorl %R, %R", reg, reg);
1313 static void emit_ia32_Minus64Bit(const ir_node *node)
1315 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1316 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1317 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1318 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1320 if (out_lo == in_lo) {
1321 if (out_hi != in_hi) {
1322 /* a -> a, b -> d */
1325 /* a -> a, b -> b */
1328 } else if (out_lo == in_hi) {
1329 if (out_hi == in_lo) {
1330 /* a -> b, b -> a */
1331 emit_xchg(node, in_lo, in_hi);
1334 /* a -> b, b -> d */
1335 emit_mov(node, in_hi, out_hi);
1336 emit_mov(node, in_lo, out_lo);
1340 if (out_hi == in_lo) {
1341 /* a -> c, b -> a */
1342 emit_mov(node, in_lo, out_lo);
1344 } else if (out_hi == in_hi) {
1345 /* a -> c, b -> b */
1346 emit_mov(node, in_lo, out_lo);
1349 /* a -> c, b -> d */
1350 emit_mov(node, in_lo, out_lo);
1356 emit_neg( node, out_hi);
1357 emit_neg( node, out_lo);
1358 emit_sbb0(node, out_hi);
1362 emit_zero(node, out_hi);
1363 emit_neg( node, out_lo);
1364 emit_sbb( node, in_hi, out_hi);
1367 static void emit_ia32_GetEIP(const ir_node *node)
1369 ia32_emitf(node, "call %s", pic_base_label);
1370 be_emit_irprintf("%s:\n", pic_base_label);
1371 be_emit_write_line();
1372 ia32_emitf(node, "popl %D0");
1375 static void emit_ia32_ClimbFrame(const ir_node *node)
1377 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1379 ia32_emitf(node, "movl %S0, %D0");
1380 ia32_emitf(node, "movl $%u, %S1", attr->count);
1381 be_gas_emit_block_name(node);
1382 be_emit_cstring(":\n");
1383 be_emit_write_line();
1384 ia32_emitf(node, "movl (%D0), %D0");
1385 ia32_emitf(node, "dec %S1");
1386 be_emit_cstring("\tjnz ");
1387 be_gas_emit_block_name(node);
1388 be_emit_finish_line_gas(node);
1391 static void emit_be_Return(const ir_node *node)
1393 unsigned pop = be_Return_get_pop(node);
1395 if (pop > 0 || be_Return_get_emit_pop(node)) {
1396 ia32_emitf(node, "ret $%u", pop);
1398 ia32_emitf(node, "ret");
1402 static void emit_Nothing(const ir_node *node)
1409 * Enters the emitter functions for handled nodes into the generic
1410 * pointer of an opcode.
1412 static void ia32_register_emitters(void)
1414 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1415 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1416 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1417 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1418 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1420 /* first clear the generic function pointer for all ops */
1421 ir_clear_opcodes_generic_func();
1423 /* register all emitter functions defined in spec */
1424 ia32_register_spec_emitters();
1426 /* other ia32 emitter functions */
1429 IA32_EMIT(Conv_FP2FP);
1430 IA32_EMIT(Conv_FP2I);
1431 IA32_EMIT(Conv_I2FP);
1438 IA32_EMIT(Minus64Bit);
1439 IA32_EMIT(SwitchJmp);
1440 IA32_EMIT(ClimbFrame);
1443 /* benode emitter */
1462 typedef void (*emit_func_ptr) (const ir_node *);
1465 * Assign and emit an exception label if the current instruction can fail.
1467 static void ia32_assign_exc_label(ir_node *node)
1469 /* assign a new ID to the instruction */
1470 set_ia32_exc_label_id(node, ++exc_label_id);
1472 ia32_emit_exc_label(node);
1474 be_emit_pad_comment();
1475 be_emit_cstring("/* exception to Block ");
1476 ia32_emit_cfop_target(node);
1477 be_emit_cstring(" */\n");
1478 be_emit_write_line();
1482 * Emits code for a node.
1484 static void ia32_emit_node(ir_node *node)
1486 ir_op *op = get_irn_op(node);
1488 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1490 if (is_ia32_irn(node)) {
1491 if (get_ia32_exc_label(node)) {
1492 /* emit the exception label of this instruction */
1493 ia32_assign_exc_label(node);
1495 if (mark_spill_reload) {
1496 if (is_ia32_is_spill(node)) {
1497 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1499 if (is_ia32_is_reload(node)) {
1500 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1502 if (is_ia32_is_remat(node)) {
1503 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1507 if (op->ops.generic) {
1508 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1510 be_dwarf_location(get_irn_dbg_info(node));
1515 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, get_irn_irg(node));
1520 int sp_change = arch_get_sp_bias(node);
1521 if (sp_change != 0) {
1522 assert(sp_change != SP_BIAS_RESET);
1523 callframe_offset += sp_change;
1524 be_dwarf_callframe_offset(callframe_offset);
1530 * Emits gas alignment directives
1532 static void ia32_emit_alignment(unsigned align, unsigned skip)
1534 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1538 * Emits gas alignment directives for Labels depended on cpu architecture.
1540 static void ia32_emit_align_label(void)
1542 unsigned align = ia32_cg_config.label_alignment;
1543 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1544 ia32_emit_alignment(align, maximum_skip);
1548 * Test whether a block should be aligned.
1549 * For cpus in the P4/Athlon class it is useful to align jump labels to
1550 * 16 bytes. However we should only do that if the alignment nops before the
1551 * label aren't executed more often than we have jumps to the label.
1553 static int should_align_block(const ir_node *block)
1555 static const double DELTA = .0001;
1556 ir_node *prev = get_prev_block_sched(block);
1557 double prev_freq = 0; /**< execfreq of the fallthrough block */
1558 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1562 if (ia32_cg_config.label_alignment_factor <= 0)
1565 block_freq = get_block_execfreq(block);
1566 if (block_freq < DELTA)
1569 n_cfgpreds = get_Block_n_cfgpreds(block);
1570 for (i = 0; i < n_cfgpreds; ++i) {
1571 const ir_node *pred = get_Block_cfgpred_block(block, i);
1572 double pred_freq = get_block_execfreq(pred);
1575 prev_freq += pred_freq;
1577 jmp_freq += pred_freq;
1581 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1584 jmp_freq /= prev_freq;
1586 return jmp_freq > ia32_cg_config.label_alignment_factor;
1590 * Emit the block header for a block.
1592 * @param block the block
1593 * @param prev_block the previous block
1595 static void ia32_emit_block_header(ir_node *block)
1597 ir_graph *const irg = get_Block_irg(block);
1598 if (block == get_irg_end_block(irg))
1601 if (ia32_cg_config.label_alignment > 0) {
1602 /* align the current block if:
1603 * a) if should be aligned due to its execution frequency
1604 * b) there is no fall-through here
1606 if (should_align_block(block)) {
1607 ia32_emit_align_label();
1609 /* if the predecessor block has no fall-through,
1610 we can always align the label. */
1612 int has_fallthrough = 0;
1614 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1615 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1616 if (can_be_fallthrough(cfg_pred)) {
1617 has_fallthrough = 1;
1622 if (!has_fallthrough)
1623 ia32_emit_align_label();
1627 int const need_label = block_needs_label(block);
1628 be_gas_begin_block(block, need_label);
1632 * Walks over the nodes in a block connected by scheduling edges
1633 * and emits code for each node.
1635 static void ia32_gen_block(ir_node *block)
1637 ia32_emit_block_header(block);
1640 ir_graph *irg = get_irn_irg(block);
1641 callframe_offset = 4; /* 4 bytes for the return address */
1642 /* ESP guessing, TODO perform a real ESP simulation */
1643 if (block != get_irg_start_block(irg)) {
1644 callframe_offset += frame_type_size;
1646 be_dwarf_callframe_offset(callframe_offset);
1649 /* emit the contents of the block */
1650 be_dwarf_location(get_irn_dbg_info(block));
1651 sched_foreach(block, node) {
1652 ia32_emit_node(node);
1656 typedef struct exc_entry {
1657 ir_node *exc_instr; /** The instruction that can issue an exception. */
1658 ir_node *block; /** The block to call then. */
1663 * Sets labels for control flow nodes (jump target).
1664 * Links control predecessors to there destination blocks.
1666 static void ia32_gen_labels(ir_node *block, void *data)
1668 exc_entry **exc_list = (exc_entry**)data;
1672 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1673 pred = get_Block_cfgpred(block, n);
1674 set_irn_link(pred, block);
1676 pred = skip_Proj(pred);
1677 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1682 ARR_APP1(exc_entry, *exc_list, e);
1683 set_irn_link(pred, block);
1689 * Compare two exception_entries.
1691 static int cmp_exc_entry(const void *a, const void *b)
1693 const exc_entry *ea = (const exc_entry*)a;
1694 const exc_entry *eb = (const exc_entry*)b;
1696 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1701 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1703 ir_entity *entity = get_irg_entity(irg);
1704 ir_type *type = get_entity_type(entity);
1705 size_t n_params = get_method_n_params(type);
1706 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1707 ir_type *arg_type = layout->arg_type;
1708 size_t n_members = get_compound_n_members(arg_type);
1709 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1712 for (i = 0; i < n_members; ++i) {
1713 ir_entity *member = get_compound_member(arg_type, i);
1715 if (!is_parameter_entity(member))
1717 param = get_entity_parameter_number(member);
1718 if (param == IR_VA_START_PARAMETER_NUMBER)
1720 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1721 infos[param].reg = NULL;
1722 infos[param].entity = member;
1729 * Main driver. Emits the code for one routine.
1731 void ia32_gen_routine(ir_graph *irg)
1733 ir_entity *entity = get_irg_entity(irg);
1734 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1735 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1736 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1737 ir_node **blk_sched = irg_data->blk_sched;
1738 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1739 parameter_dbg_info_t *infos;
1742 isa = (ia32_isa_t*) arch_env;
1743 do_pic = be_options.pic;
1745 be_gas_elf_type_char = '@';
1747 ia32_register_emitters();
1749 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1751 infos = construct_parameter_infos(irg);
1752 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1756 sp_relative = layout->sp_relative;
1757 if (layout->sp_relative) {
1758 ir_type *frame_type = get_irg_frame_type(irg);
1759 frame_type_size = get_type_size_bytes(frame_type);
1760 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1762 /* well not entirely correct here, we should emit this after the
1763 * "movl esp, ebp" */
1764 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1765 /* TODO: do not hardcode the following */
1766 be_dwarf_callframe_offset(8);
1767 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1770 /* we use links to point to target blocks */
1771 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1772 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1774 /* initialize next block links */
1775 n = ARR_LEN(blk_sched);
1776 for (i = 0; i < n; ++i) {
1777 ir_node *block = blk_sched[i];
1778 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1780 set_irn_link(block, prev);
1783 for (i = 0; i < n; ++i) {
1784 ir_node *block = blk_sched[i];
1786 ia32_gen_block(block);
1789 be_gas_emit_function_epilog(entity);
1791 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1793 /* Sort the exception table using the exception label id's.
1794 Those are ascending with ascending addresses. */
1795 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1799 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1800 be_emit_cstring("\t.long ");
1801 ia32_emit_exc_label(exc_list[e].exc_instr);
1803 be_emit_cstring("\t.long ");
1804 be_gas_emit_block_name(exc_list[e].block);
1808 DEL_ARR_F(exc_list);
1811 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1812 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1816 /* ==== Experimental binary emitter ==== */
1818 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1819 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1820 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1822 static void build_reg_map(void)
1824 reg_gp_map[REG_GP_EAX] = 0x0;
1825 reg_gp_map[REG_GP_ECX] = 0x1;
1826 reg_gp_map[REG_GP_EDX] = 0x2;
1827 reg_gp_map[REG_GP_EBX] = 0x3;
1828 reg_gp_map[REG_GP_ESP] = 0x4;
1829 reg_gp_map[REG_GP_EBP] = 0x5;
1830 reg_gp_map[REG_GP_ESI] = 0x6;
1831 reg_gp_map[REG_GP_EDI] = 0x7;
1834 /** Returns the encoding for a pnc field. */
1835 static unsigned char pnc2cc(ia32_condition_code_t cc)
1840 /** Sign extension bit values for binops */
1842 UNSIGNED_IMM = 0, /**< unsigned immediate */
1843 SIGNEXT_IMM = 2, /**< sign extended immediate */
1846 /** The mod encoding of the ModR/M */
1848 MOD_IND = 0x00, /**< [reg1] */
1849 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1850 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1851 MOD_REG = 0xC0 /**< reg1 */
1854 /** create R/M encoding for ModR/M */
1855 #define ENC_RM(x) (x)
1856 /** create REG encoding for ModR/M */
1857 #define ENC_REG(x) ((x) << 3)
1859 /** create encoding for a SIB byte */
1860 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1862 /* Node: The following routines are supposed to append bytes, words, dwords
1863 to the output stream.
1864 Currently the implementation is stupid in that it still creates output
1865 for an "assembler" in the form of .byte, .long
1866 We will change this when enough infrastructure is there to create complete
1867 machine code in memory/object files */
1869 static void bemit8(const unsigned char byte)
1871 be_emit_irprintf("\t.byte 0x%x\n", byte);
1872 be_emit_write_line();
1875 static void bemit16(const unsigned short u16)
1877 be_emit_irprintf("\t.word 0x%x\n", u16);
1878 be_emit_write_line();
1881 static void bemit32(const unsigned u32)
1883 be_emit_irprintf("\t.long 0x%x\n", u32);
1884 be_emit_write_line();
1888 * Emit address of an entity. If @p is_relative is true then a relative
1889 * offset from behind the address to the entity is created.
1891 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1894 if (entity == NULL) {
1899 /* the final version should remember the position in the bytestream
1900 and patch it with the correct address at linktime... */
1901 be_emit_cstring("\t.long ");
1904 be_gas_emit_entity(entity);
1906 if (get_entity_owner(entity) == get_tls_type()) {
1907 if (!entity_has_definition(entity)) {
1908 be_emit_cstring("@INDNTPOFF");
1910 be_emit_cstring("@NTPOFF");
1915 be_emit_cstring("-.");
1920 be_emit_irprintf("%+d", offset);
1923 be_emit_write_line();
1926 static void bemit_jmp_destination(const ir_node *dest_block)
1928 be_emit_cstring("\t.long ");
1929 be_gas_emit_block_name(dest_block);
1930 be_emit_cstring(" - . - 4\n");
1931 be_emit_write_line();
1934 /* end emit routines, all emitters following here should only use the functions
1937 typedef enum reg_modifier {
1942 /** Create a ModR/M byte for src1,src2 registers */
1943 static void bemit_modrr(const arch_register_t *src1,
1944 const arch_register_t *src2)
1946 unsigned char modrm = MOD_REG;
1947 modrm |= ENC_RM(reg_gp_map[src1->index]);
1948 modrm |= ENC_REG(reg_gp_map[src2->index]);
1952 /** Create a ModR/M8 byte for src1,src2 registers */
1953 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1954 reg_modifier_t high_part2, const arch_register_t *src2)
1956 unsigned char modrm = MOD_REG;
1957 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1958 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1962 /** Create a ModR/M byte for one register and extension */
1963 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1965 unsigned char modrm = MOD_REG;
1967 modrm |= ENC_RM(reg_gp_map[reg->index]);
1968 modrm |= ENC_REG(ext);
1972 /** Create a ModR/M8 byte for one register */
1973 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1975 unsigned char modrm = MOD_REG;
1976 assert(reg_gp_map[reg->index] < 4);
1977 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1983 * Calculate the size of an signed immediate in bytes.
1985 * @param offset an offset
1987 static unsigned get_signed_imm_size(int offset)
1989 if (-128 <= offset && offset < 128) {
1991 } else if (-32768 <= offset && offset < 32768) {
1999 * Emit an address mode.
2001 * @param reg content of the reg field: either a register index or an opcode extension
2002 * @param node the node
2004 static void bemit_mod_am(unsigned reg, const ir_node *node)
2006 ir_entity *ent = get_ia32_am_sc(node);
2007 int offs = get_ia32_am_offs_int(node);
2008 ir_node *base = get_irn_n(node, n_ia32_base);
2009 int has_base = !is_ia32_NoReg_GP(base);
2010 ir_node *idx = get_irn_n(node, n_ia32_index);
2011 int has_index = !is_ia32_NoReg_GP(idx);
2014 unsigned emitoffs = 0;
2015 bool emitsib = false;
2018 /* set the mod part depending on displacement */
2020 modrm |= MOD_IND_WORD_OFS;
2022 } else if (offs == 0) {
2025 } else if (-128 <= offs && offs < 128) {
2026 modrm |= MOD_IND_BYTE_OFS;
2029 modrm |= MOD_IND_WORD_OFS;
2034 const arch_register_t *base_reg = arch_get_irn_register(base);
2035 base_enc = reg_gp_map[base_reg->index];
2037 /* Use the EBP encoding + MOD_IND if NO base register. There is
2038 * always a 32bit offset present in this case. */
2044 /* Determine if we need a SIB byte. */
2046 const arch_register_t *reg_index = arch_get_irn_register(idx);
2047 int scale = get_ia32_am_scale(node);
2049 /* R/M set to ESP means SIB in 32bit mode. */
2050 modrm |= ENC_RM(0x04);
2051 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2053 } else if (base_enc == 0x04) {
2054 /* for the above reason we are forced to emit a SIB when base is ESP.
2055 * Only the base is used, index must be ESP too, which means no index.
2057 modrm |= ENC_RM(0x04);
2058 sib = ENC_SIB(0, 0x04, 0x04);
2061 modrm |= ENC_RM(base_enc);
2064 /* We are forced to emit an 8bit offset as EBP base without offset is a
2065 * special case for SIB without base register. */
2066 if (base_enc == 0x05 && emitoffs == 0) {
2067 modrm |= MOD_IND_BYTE_OFS;
2071 modrm |= ENC_REG(reg);
2077 /* emit displacement */
2078 if (emitoffs == 8) {
2079 bemit8((unsigned) offs);
2080 } else if (emitoffs == 32) {
2081 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2086 * Emit a binop with a immediate operand.
2088 * @param node the node to emit
2089 * @param opcode_eax the opcode for the op eax, imm variant
2090 * @param opcode the opcode for the reg, imm variant
2091 * @param ruval the opcode extension for opcode
2093 static void bemit_binop_with_imm(
2094 const ir_node *node,
2095 unsigned char opcode_ax,
2096 unsigned char opcode, unsigned char ruval)
2098 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2099 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2100 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2103 /* Some instructions (test) have no short form with 32bit value + 8bit
2105 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2108 /* check for sign extension */
2109 size = get_signed_imm_size(attr->offset);
2114 bemit8(opcode | SIGNEXT_IMM);
2115 /* cmp has this special mode */
2116 if (get_ia32_op_type(node) == ia32_Normal) {
2117 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2118 bemit_modru(reg, ruval);
2120 bemit_mod_am(ruval, node);
2122 bemit8((unsigned char)attr->offset);
2126 if (get_ia32_op_type(node) == ia32_Normal) {
2127 /* check for eax variant: this variant is shorter for 32bit immediates only */
2128 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2129 if (reg->index == REG_GP_EAX) {
2133 bemit_modru(reg, ruval);
2137 bemit_mod_am(ruval, node);
2139 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2142 panic("invalid imm size?!?");
2148 static void bemit_binop_2(const ir_node *node, unsigned code)
2150 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2152 if (get_ia32_op_type(node) == ia32_Normal) {
2153 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2154 bemit_modrr(op2, out);
2156 bemit_mod_am(reg_gp_map[out->index], node);
2163 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2165 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2166 if (is_ia32_Immediate(right)) {
2167 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2169 bemit_binop_2(node, opcodes[0]);
2176 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2179 if (get_ia32_op_type(node) == ia32_Normal) {
2180 const arch_register_t *in = arch_get_irn_register_in(node, input);
2181 bemit_modru(in, ext);
2183 bemit_mod_am(ext, node);
2187 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2189 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2190 bemit_unop(node, code, reg_gp_map[out->index], input);
2193 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2195 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2198 bemit8(size == 8 ? code : code + 1);
2199 bemit_mod_am(ext, node);
2202 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2205 bemit_unop_reg(node, code, input);
2208 static void bemit_immediate(const ir_node *node, bool relative)
2210 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2211 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2214 static void bemit_copy(const ir_node *copy)
2216 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2217 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2221 /* copies of fp nodes aren't real... */
2222 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
2225 assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
2227 bemit_modrr(in, out);
2230 static void bemit_perm(const ir_node *node)
2232 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2233 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2234 const arch_register_class_t *cls0 = in0->reg_class;
2236 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
2238 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2239 if (in0->index == REG_GP_EAX) {
2240 bemit8(0x90 + reg_gp_map[in1->index]);
2241 } else if (in1->index == REG_GP_EAX) {
2242 bemit8(0x90 + reg_gp_map[in0->index]);
2245 bemit_modrr(in0, in1);
2247 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2248 panic("unimplemented"); // TODO implement
2249 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2250 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2251 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2252 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
2255 panic("unexpected register class in be_Perm (%+F)", node);
2259 static void bemit_xor0(const ir_node *node)
2261 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2263 bemit_modrr(out, out);
2266 static void bemit_mov_const(const ir_node *node)
2268 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2269 bemit8(0xB8 + reg_gp_map[out->index]);
2270 bemit_immediate(node, false);
2274 * Creates a function for a Binop with 3 possible encodings.
2276 #define BINOP(op, op0, op1, op2, op2_ext) \
2277 static void bemit_ ## op(const ir_node *node) { \
2278 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2279 bemit_binop(node, op ## _codes); \
2282 /* insn def eax,imm imm */
2283 BINOP(add, 0x03, 0x05, 0x81, 0)
2284 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2285 BINOP(adc, 0x13, 0x15, 0x81, 2)
2286 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2287 BINOP(and, 0x23, 0x25, 0x81, 4)
2288 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2289 BINOP(xor, 0x33, 0x35, 0x81, 6)
2290 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2292 #define BINOPMEM(op, ext) \
2293 static void bemit_##op(const ir_node *node) \
2296 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2299 val = get_irn_n(node, n_ia32_unary_op); \
2300 if (is_ia32_Immediate(val)) { \
2301 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2302 int offset = attr->offset; \
2303 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2305 bemit_mod_am(ext, node); \
2309 bemit_mod_am(ext, node); \
2313 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2317 bemit8(ext << 3 | 1); \
2318 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2322 static void bemit_##op##8bit(const ir_node *node) \
2324 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2325 if (is_ia32_Immediate(val)) { \
2327 bemit_mod_am(ext, node); \
2328 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2331 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2343 * Creates a function for an Unop with code /ext encoding.
2345 #define UNOP(op, code, ext, input) \
2346 static void bemit_ ## op(const ir_node *node) { \
2347 bemit_unop(node, code, ext, input); \
2350 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2351 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2352 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2353 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2354 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2355 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2357 /* TODO: am support for IJmp */
2358 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2360 #define SHIFT(op, ext) \
2361 static void bemit_##op(const ir_node *node) \
2363 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2364 ir_node *count = get_irn_n(node, 1); \
2365 if (is_ia32_Immediate(count)) { \
2366 int offset = get_ia32_immediate_attr_const(count)->offset; \
2367 if (offset == 1) { \
2369 bemit_modru(out, ext); \
2372 bemit_modru(out, ext); \
2377 bemit_modru(out, ext); \
2381 static void bemit_##op##mem(const ir_node *node) \
2384 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2387 count = get_irn_n(node, 1); \
2388 if (is_ia32_Immediate(count)) { \
2389 int offset = get_ia32_immediate_attr_const(count)->offset; \
2390 if (offset == 1) { \
2391 bemit8(size == 8 ? 0xD0 : 0xD1); \
2392 bemit_mod_am(ext, node); \
2394 bemit8(size == 8 ? 0xC0 : 0xC1); \
2395 bemit_mod_am(ext, node); \
2399 bemit8(size == 8 ? 0xD2 : 0xD3); \
2400 bemit_mod_am(ext, node); \
2410 static void bemit_shld(const ir_node *node)
2412 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2413 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2414 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2416 if (is_ia32_Immediate(count)) {
2418 bemit_modrr(out, in);
2419 bemit8(get_ia32_immediate_attr_const(count)->offset);
2422 bemit_modrr(out, in);
2426 static void bemit_shrd(const ir_node *node)
2428 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2429 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2430 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2432 if (is_ia32_Immediate(count)) {
2434 bemit_modrr(out, in);
2435 bemit8(get_ia32_immediate_attr_const(count)->offset);
2438 bemit_modrr(out, in);
2442 static void bemit_sbb0(ir_node const *const node)
2444 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2445 unsigned char const reg = reg_gp_map[out->index];
2447 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2451 * binary emitter for setcc.
2453 static void bemit_setcc(const ir_node *node)
2455 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2457 ia32_condition_code_t cc = get_ia32_condcode(node);
2458 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2459 if (cc & ia32_cc_float_parity_cases) {
2460 if (cc & ia32_cc_negated) {
2463 bemit8(0x90 | pnc2cc(cc));
2464 bemit_modrm8(REG_LOW, dreg);
2469 bemit_modrm8(REG_HIGH, dreg);
2471 /* orb %>dreg, %<dreg */
2473 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2477 bemit8(0x90 | pnc2cc(cc));
2478 bemit_modrm8(REG_LOW, dreg);
2483 bemit_modrm8(REG_HIGH, dreg);
2485 /* andb %>dreg, %<dreg */
2487 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2492 bemit8(0x90 | pnc2cc(cc));
2493 bemit_modrm8(REG_LOW, dreg);
2497 static void bemit_bsf(ir_node const *const node)
2499 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2502 static void bemit_bsr(ir_node const *const node)
2504 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2507 static void bemit_bswap(ir_node const *const node)
2510 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2513 static void bemit_bt(ir_node const *const node)
2516 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2517 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2518 if (is_ia32_Immediate(right)) {
2519 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2520 int const offset = attr->offset;
2521 assert(!attr->symconst);
2522 assert(get_signed_imm_size(offset) == 1);
2524 bemit_modru(lreg, 4);
2528 bemit_modrr(lreg, arch_get_irn_register(right));
2532 static void bemit_cmovcc(const ir_node *node)
2534 const ia32_attr_t *attr = get_ia32_attr_const(node);
2535 int ins_permuted = attr->data.ins_permuted;
2536 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2537 ia32_condition_code_t cc = get_ia32_condcode(node);
2538 const arch_register_t *in_true;
2539 const arch_register_t *in_false;
2541 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2543 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2544 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2546 /* should be same constraint fullfilled? */
2547 if (out == in_false) {
2548 /* yes -> nothing to do */
2549 } else if (out == in_true) {
2550 assert(get_ia32_op_type(node) == ia32_Normal);
2551 ins_permuted = !ins_permuted;
2555 bemit8(0x8B); // mov %in_false, %out
2556 bemit_modrr(in_false, out);
2560 cc = ia32_negate_condition_code(cc);
2562 if (cc & ia32_cc_float_parity_cases)
2563 panic("cmov can't handle parity float cases");
2566 bemit8(0x40 | pnc2cc(cc));
2567 if (get_ia32_op_type(node) == ia32_Normal) {
2568 bemit_modrr(in_true, out);
2570 bemit_mod_am(reg_gp_map[out->index], node);
2574 static void bemit_cmp(const ir_node *node)
2576 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2582 right = get_irn_n(node, n_ia32_binary_right);
2583 if (is_ia32_Immediate(right)) {
2584 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2585 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2586 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2589 if (attr->symconst != NULL) {
2592 /* check for sign extension */
2593 size = get_signed_imm_size(attr->offset);
2598 bemit8(0x81 | SIGNEXT_IMM);
2599 /* cmp has this special mode */
2600 if (get_ia32_op_type(node) == ia32_Normal) {
2601 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2602 bemit_modru(reg, 7);
2604 bemit_mod_am(7, node);
2606 bemit8((unsigned char)attr->offset);
2610 /* check for eax variant: this variant is shorter for 32bit immediates only */
2611 if (get_ia32_op_type(node) == ia32_Normal) {
2612 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2613 if (reg->index == REG_GP_EAX) {
2617 bemit_modru(reg, 7);
2621 bemit_mod_am(7, node);
2623 if (ls_size == 16) {
2624 bemit16(attr->offset);
2626 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2630 panic("invalid imm size?!?");
2632 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2634 if (get_ia32_op_type(node) == ia32_Normal) {
2635 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2636 bemit_modrr(op2, out);
2638 bemit_mod_am(reg_gp_map[out->index], node);
2643 static void bemit_cmp8bit(const ir_node *node)
2645 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2646 if (is_ia32_Immediate(right)) {
2647 if (get_ia32_op_type(node) == ia32_Normal) {
2648 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2649 if (out->index == REG_GP_EAX) {
2653 bemit_modru(out, 7);
2657 bemit_mod_am(7, node);
2659 bemit8(get_ia32_immediate_attr_const(right)->offset);
2661 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2663 if (get_ia32_op_type(node) == ia32_Normal) {
2664 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2665 bemit_modrr(out, in);
2667 bemit_mod_am(reg_gp_map[out->index], node);
2672 static void bemit_test8bit(const ir_node *node)
2674 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2675 if (is_ia32_Immediate(right)) {
2676 if (get_ia32_op_type(node) == ia32_Normal) {
2677 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2678 if (out->index == REG_GP_EAX) {
2682 bemit_modru(out, 0);
2686 bemit_mod_am(0, node);
2688 bemit8(get_ia32_immediate_attr_const(right)->offset);
2690 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2692 if (get_ia32_op_type(node) == ia32_Normal) {
2693 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2694 bemit_modrr(out, in);
2696 bemit_mod_am(reg_gp_map[out->index], node);
2701 static void bemit_imul(const ir_node *node)
2703 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2704 /* Do we need the immediate form? */
2705 if (is_ia32_Immediate(right)) {
2706 int imm = get_ia32_immediate_attr_const(right)->offset;
2707 if (get_signed_imm_size(imm) == 1) {
2708 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2711 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2715 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2719 static void bemit_dec(const ir_node *node)
2721 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2722 bemit8(0x48 + reg_gp_map[out->index]);
2725 static void bemit_inc(const ir_node *node)
2727 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2728 bemit8(0x40 + reg_gp_map[out->index]);
2731 #define UNOPMEM(op, code, ext) \
2732 static void bemit_##op(const ir_node *node) \
2734 bemit_unop_mem(node, code, ext); \
2737 UNOPMEM(notmem, 0xF6, 2)
2738 UNOPMEM(negmem, 0xF6, 3)
2739 UNOPMEM(incmem, 0xFE, 0)
2740 UNOPMEM(decmem, 0xFE, 1)
2742 static void bemit_ldtls(const ir_node *node)
2744 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2746 bemit8(0x65); // gs:
2747 if (out->index == REG_GP_EAX) {
2748 bemit8(0xA1); // movl 0, %eax
2750 bemit8(0x8B); // movl 0, %reg
2751 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2759 static void bemit_lea(const ir_node *node)
2761 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2763 bemit_mod_am(reg_gp_map[out->index], node);
2766 /* helper function for bemit_minus64bit */
2767 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2769 bemit8(0x8B); // movl %src, %dst
2770 bemit_modrr(src, dst);
2773 /* helper function for bemit_minus64bit */
2774 static void bemit_helper_neg(const arch_register_t *reg)
2776 bemit8(0xF7); // negl %reg
2777 bemit_modru(reg, 3);
2780 /* helper function for bemit_minus64bit */
2781 static void bemit_helper_sbb0(const arch_register_t *reg)
2783 bemit8(0x83); // sbbl $0, %reg
2784 bemit_modru(reg, 3);
2788 /* helper function for bemit_minus64bit */
2789 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2791 bemit8(0x1B); // sbbl %src, %dst
2792 bemit_modrr(src, dst);
2795 /* helper function for bemit_minus64bit */
2796 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2798 if (src->index == REG_GP_EAX) {
2799 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2800 } else if (dst->index == REG_GP_EAX) {
2801 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2803 bemit8(0x87); // xchgl %src, %dst
2804 bemit_modrr(src, dst);
2808 /* helper function for bemit_minus64bit */
2809 static void bemit_helper_zero(const arch_register_t *reg)
2811 bemit8(0x33); // xorl %reg, %reg
2812 bemit_modrr(reg, reg);
2815 static void bemit_minus64bit(const ir_node *node)
2817 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2818 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2819 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2820 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2822 if (out_lo == in_lo) {
2823 if (out_hi != in_hi) {
2824 /* a -> a, b -> d */
2827 /* a -> a, b -> b */
2830 } else if (out_lo == in_hi) {
2831 if (out_hi == in_lo) {
2832 /* a -> b, b -> a */
2833 bemit_helper_xchg(in_lo, in_hi);
2836 /* a -> b, b -> d */
2837 bemit_helper_mov(in_hi, out_hi);
2838 bemit_helper_mov(in_lo, out_lo);
2842 if (out_hi == in_lo) {
2843 /* a -> c, b -> a */
2844 bemit_helper_mov(in_lo, out_lo);
2846 } else if (out_hi == in_hi) {
2847 /* a -> c, b -> b */
2848 bemit_helper_mov(in_lo, out_lo);
2851 /* a -> c, b -> d */
2852 bemit_helper_mov(in_lo, out_lo);
2858 bemit_helper_neg( out_hi);
2859 bemit_helper_neg( out_lo);
2860 bemit_helper_sbb0(out_hi);
2864 bemit_helper_zero(out_hi);
2865 bemit_helper_neg( out_lo);
2866 bemit_helper_sbb( in_hi, out_hi);
2870 * Emit a single opcode.
2872 #define EMIT_SINGLEOP(op, code) \
2873 static void bemit_ ## op(const ir_node *node) { \
2878 //EMIT_SINGLEOP(daa, 0x27)
2879 //EMIT_SINGLEOP(das, 0x2F)
2880 //EMIT_SINGLEOP(aaa, 0x37)
2881 //EMIT_SINGLEOP(aas, 0x3F)
2882 //EMIT_SINGLEOP(nop, 0x90)
2883 EMIT_SINGLEOP(cwtl, 0x98)
2884 EMIT_SINGLEOP(cltd, 0x99)
2885 //EMIT_SINGLEOP(fwait, 0x9B)
2886 EMIT_SINGLEOP(sahf, 0x9E)
2887 //EMIT_SINGLEOP(popf, 0x9D)
2888 EMIT_SINGLEOP(leave, 0xC9)
2889 EMIT_SINGLEOP(int3, 0xCC)
2890 //EMIT_SINGLEOP(iret, 0xCF)
2891 //EMIT_SINGLEOP(xlat, 0xD7)
2892 //EMIT_SINGLEOP(lock, 0xF0)
2893 EMIT_SINGLEOP(rep, 0xF3)
2894 //EMIT_SINGLEOP(halt, 0xF4)
2895 EMIT_SINGLEOP(cmc, 0xF5)
2896 EMIT_SINGLEOP(stc, 0xF9)
2897 //EMIT_SINGLEOP(cli, 0xFA)
2898 //EMIT_SINGLEOP(sti, 0xFB)
2899 //EMIT_SINGLEOP(std, 0xFD)
2902 * Emits a MOV out, [MEM].
2904 static void bemit_load(const ir_node *node)
2906 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2908 if (out->index == REG_GP_EAX) {
2909 ir_node *base = get_irn_n(node, n_ia32_base);
2910 int has_base = !is_ia32_NoReg_GP(base);
2911 ir_node *idx = get_irn_n(node, n_ia32_index);
2912 int has_index = !is_ia32_NoReg_GP(idx);
2913 if (!has_base && !has_index) {
2914 ir_entity *ent = get_ia32_am_sc(node);
2915 int offs = get_ia32_am_offs_int(node);
2916 /* load from constant address to EAX can be encoded
2919 bemit_entity(ent, 0, offs, false);
2924 bemit_mod_am(reg_gp_map[out->index], node);
2928 * Emits a MOV [mem], in.
2930 static void bemit_store(const ir_node *node)
2932 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2933 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2935 if (is_ia32_Immediate(value)) {
2938 bemit_mod_am(0, node);
2939 bemit8(get_ia32_immediate_attr_const(value)->offset);
2940 } else if (size == 16) {
2943 bemit_mod_am(0, node);
2944 bemit16(get_ia32_immediate_attr_const(value)->offset);
2947 bemit_mod_am(0, node);
2948 bemit_immediate(value, false);
2951 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2953 if (in->index == REG_GP_EAX) {
2954 ir_node *base = get_irn_n(node, n_ia32_base);
2955 int has_base = !is_ia32_NoReg_GP(base);
2956 ir_node *idx = get_irn_n(node, n_ia32_index);
2957 int has_index = !is_ia32_NoReg_GP(idx);
2958 if (!has_base && !has_index) {
2959 ir_entity *ent = get_ia32_am_sc(node);
2960 int offs = get_ia32_am_offs_int(node);
2961 /* store to constant address from EAX can be encoded as
2962 * 0xA2/0xA3 [offset]*/
2970 bemit_entity(ent, 0, offs, false);
2982 bemit_mod_am(reg_gp_map[in->index], node);
2986 static void bemit_conv_i2i(const ir_node *node)
2991 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
2992 unsigned opcode = 0xB6;
2993 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
2994 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
2995 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
2998 static void bemit_popcnt(ir_node const *const node)
3001 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
3007 static void bemit_push(const ir_node *node)
3009 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3011 if (is_ia32_Immediate(value)) {
3012 const ia32_immediate_attr_t *attr
3013 = get_ia32_immediate_attr_const(value);
3014 unsigned size = get_signed_imm_size(attr->offset);
3020 bemit8((unsigned char)attr->offset);
3025 bemit_immediate(value, false);
3028 } else if (is_ia32_NoReg_GP(value)) {
3030 bemit_mod_am(6, node);
3032 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3033 bemit8(0x50 + reg_gp_map[reg->index]);
3040 static void bemit_pop(const ir_node *node)
3042 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3043 bemit8(0x58 + reg_gp_map[reg->index]);
3046 static void bemit_popmem(const ir_node *node)
3049 bemit_mod_am(0, node);
3052 static void bemit_call(const ir_node *node)
3054 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3056 if (is_ia32_Immediate(proc)) {
3058 bemit_immediate(proc, true);
3060 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3064 static void bemit_jmp(const ir_node *dest_block)
3067 bemit_jmp_destination(dest_block);
3070 static void bemit_jump(const ir_node *node)
3072 if (can_be_fallthrough(node))
3075 bemit_jmp(get_cfop_target_block(node));
3078 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3080 unsigned char cc = pnc2cc(pnc);
3083 bemit_jmp_destination(dest_block);
3086 static void bemit_jp(bool odd, const ir_node *dest_block)
3090 bemit_jmp_destination(dest_block);
3093 static void bemit_ia32_jcc(const ir_node *node)
3095 ia32_condition_code_t cc = get_ia32_condcode(node);
3096 const ir_node *proj_true;
3097 const ir_node *proj_false;
3098 const ir_node *dest_true;
3099 const ir_node *dest_false;
3101 cc = determine_final_cc(node, 0, cc);
3103 /* get both Projs */
3104 proj_true = get_proj(node, pn_ia32_Jcc_true);
3105 assert(proj_true && "Jcc without true Proj");
3107 proj_false = get_proj(node, pn_ia32_Jcc_false);
3108 assert(proj_false && "Jcc without false Proj");
3110 if (can_be_fallthrough(proj_true)) {
3111 /* exchange both proj's so the second one can be omitted */
3112 const ir_node *t = proj_true;
3114 proj_true = proj_false;
3116 cc = ia32_negate_condition_code(cc);
3119 dest_true = get_cfop_target_block(proj_true);
3120 dest_false = get_cfop_target_block(proj_false);
3122 if (cc & ia32_cc_float_parity_cases) {
3123 /* Some floating point comparisons require a test of the parity flag,
3124 * which indicates that the result is unordered */
3125 if (cc & ia32_cc_negated) {
3126 bemit_jp(false, dest_true);
3128 /* we need a local label if the false proj is a fallthrough
3129 * as the falseblock might have no label emitted then */
3130 if (can_be_fallthrough(proj_false)) {
3132 bemit8(0x06); // jp + 6
3134 bemit_jp(false, dest_false);
3138 bemit_jcc(cc, dest_true);
3140 /* the second Proj might be a fallthrough */
3141 if (can_be_fallthrough(proj_false)) {
3142 /* it's a fallthrough */
3144 bemit_jmp(dest_false);
3148 static void bemit_switchjmp(const ir_node *node)
3150 ir_entity *jump_table = get_ia32_am_sc(node);
3151 const ir_switch_table *table = get_ia32_switch_table(node);
3153 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3154 bemit_mod_am(0x05, node);
3156 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3162 static void bemit_return(const ir_node *node)
3164 unsigned pop = be_Return_get_pop(node);
3165 if (pop > 0 || be_Return_get_emit_pop(node)) {
3167 assert(pop <= 0xffff);
3174 static void bemit_subsp(const ir_node *node)
3176 const arch_register_t *out;
3179 /* mov %esp, %out */
3181 out = arch_get_irn_register_out(node, 1);
3182 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3185 static void bemit_incsp(const ir_node *node)
3188 const arch_register_t *reg;
3192 offs = be_get_IncSP_offset(node);
3203 size = get_signed_imm_size(offs);
3204 bemit8(size == 1 ? 0x83 : 0x81);
3206 reg = arch_get_irn_register_out(node, 0);
3207 bemit_modru(reg, ext);
3216 static void bemit_copybi(const ir_node *node)
3218 unsigned size = get_ia32_copyb_size(node);
3220 bemit8(0xA4); // movsb
3223 bemit8(0xA5); // movsw
3227 bemit8(0xA5); // movsl
3231 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3233 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3234 unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
3235 if (get_ia32_op_type(node) == ia32_Normal) {
3236 assert(!attr->pop || attr->res_in_reg);
3238 unsigned char op0 = 0xD8;
3239 if (attr->res_in_reg) op0 |= 0x04;
3240 if (attr->pop) op0 |= 0x02;
3243 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
3248 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3249 bemit8(size == 32 ? 0xD8 : 0xDC);
3250 bemit_mod_am(op, node);
3254 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3257 bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
3260 static void bemit_fabs(const ir_node *node)
3268 static void bemit_fadd(const ir_node *node)
3270 bemit_fbinop(node, 0, 0);
3273 static void bemit_fchs(const ir_node *node)
3281 static void bemit_fdiv(const ir_node *node)
3283 bemit_fbinop(node, 6, 7);
3286 static void bemit_ffreep(ir_node const *const node)
3288 bemit_fop_reg(node, 0xDF, 0xC0);
3291 static void bemit_fild(const ir_node *node)
3293 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3295 bemit8(0xDF); // filds
3296 bemit_mod_am(0, node);
3300 bemit8(0xDB); // fildl
3301 bemit_mod_am(0, node);
3305 bemit8(0xDF); // fildll
3306 bemit_mod_am(5, node);
3310 panic("invalid mode size");
3314 static void bemit_fist(const ir_node *node)
3317 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3319 case 16: bemit8(0xDF); op = 2; break; // fist[p]s
3320 case 32: bemit8(0xDB); op = 2; break; // fist[p]l
3321 case 64: bemit8(0xDF); op = 6; break; // fistpll
3322 default: panic("invalid mode size");
3324 if (get_ia32_x87_attr_const(node)->pop)
3326 // There is only a pop variant for 64 bit integer store.
3327 assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
3328 bemit_mod_am(op, node);
3331 static void bemit_fisttp(ir_node const *const node)
3333 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3334 case 16: bemit8(0xDF); break; // fisttps
3335 case 32: bemit8(0xDB); break; // fisttpl
3336 case 64: bemit8(0xDD); break; // fisttpll
3337 default: panic("Invalid mode size");
3339 bemit_mod_am(1, node);
3342 static void bemit_fld(const ir_node *node)
3344 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3346 bemit8(0xD9); // flds
3347 bemit_mod_am(0, node);
3351 bemit8(0xDD); // fldl
3352 bemit_mod_am(0, node);
3357 bemit8(0xDB); // fldt
3358 bemit_mod_am(5, node);
3362 panic("invalid mode size");
3366 static void bemit_fld1(const ir_node *node)
3370 bemit8(0xE8); // fld1
3373 static void bemit_fldcw(const ir_node *node)
3375 bemit8(0xD9); // fldcw
3376 bemit_mod_am(5, node);
3379 static void bemit_fldz(const ir_node *node)
3383 bemit8(0xEE); // fldz
3386 static void bemit_fmul(const ir_node *node)
3388 bemit_fbinop(node, 1, 1);
3391 static void bemit_fpop(const ir_node *node)
3393 bemit_fop_reg(node, 0xDD, 0xD8);
3396 static void bemit_fpush(const ir_node *node)
3398 bemit_fop_reg(node, 0xD9, 0xC0);
3401 static void bemit_fpushcopy(const ir_node *node)
3403 bemit_fop_reg(node, 0xD9, 0xC0);
3406 static void bemit_fst(const ir_node *node)
3409 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3411 case 32: bemit8(0xD9); op = 2; break; // fst[p]s
3412 case 64: bemit8(0xDD); op = 2; break; // fst[p]l
3414 case 96: bemit8(0xDB); op = 6; break; // fstpt
3415 default: panic("invalid mode size");
3417 if (get_ia32_x87_attr_const(node)->pop)
3419 // There is only a pop variant for long double store.
3420 assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
3421 bemit_mod_am(op, node);
3424 static void bemit_fsub(const ir_node *node)
3426 bemit_fbinop(node, 4, 5);
3429 static void bemit_fnstcw(const ir_node *node)
3431 bemit8(0xD9); // fnstcw
3432 bemit_mod_am(7, node);
3435 static void bemit_fnstsw(void)
3437 bemit8(0xDF); // fnstsw %ax
3441 static void bemit_ftstfnstsw(const ir_node *node)
3445 bemit8(0xD9); // ftst
3450 static void bemit_fucomi(const ir_node *node)
3452 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3453 bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
3454 bemit8(0xE8 + attr->reg->index);
3457 static void bemit_fucomfnstsw(const ir_node *node)
3459 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3460 bemit8(0xDD); // fucom[p]
3461 bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
3465 static void bemit_fucomppfnstsw(const ir_node *node)
3469 bemit8(0xDA); // fucompp
3474 static void bemit_fxch(const ir_node *node)
3476 bemit_fop_reg(node, 0xD9, 0xC8);
3480 * The type of a emitter function.
3482 typedef void (*emit_func) (const ir_node *);
3485 * Set a node emitter. Make it a bit more type safe.
3487 static void register_emitter(ir_op *op, emit_func func)
3489 op->ops.generic = (op_func) func;
3492 static void ia32_register_binary_emitters(void)
3494 /* first clear the generic function pointer for all ops */
3495 ir_clear_opcodes_generic_func();
3497 /* benode emitter */
3498 register_emitter(op_be_Copy, bemit_copy);
3499 register_emitter(op_be_CopyKeep, bemit_copy);
3500 register_emitter(op_be_IncSP, bemit_incsp);
3501 register_emitter(op_be_Perm, bemit_perm);
3502 register_emitter(op_be_Return, bemit_return);
3503 register_emitter(op_ia32_Adc, bemit_adc);
3504 register_emitter(op_ia32_Add, bemit_add);
3505 register_emitter(op_ia32_AddMem, bemit_addmem);
3506 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3507 register_emitter(op_ia32_And, bemit_and);
3508 register_emitter(op_ia32_AndMem, bemit_andmem);
3509 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3510 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3511 register_emitter(op_ia32_Breakpoint, bemit_int3);
3512 register_emitter(op_ia32_Bsf, bemit_bsf);
3513 register_emitter(op_ia32_Bsr, bemit_bsr);
3514 register_emitter(op_ia32_Bswap, bemit_bswap);
3515 register_emitter(op_ia32_Bt, bemit_bt);
3516 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3517 register_emitter(op_ia32_Call, bemit_call);
3518 register_emitter(op_ia32_Cltd, bemit_cltd);
3519 register_emitter(op_ia32_Cmc, bemit_cmc);
3520 register_emitter(op_ia32_Cmp, bemit_cmp);
3521 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3522 register_emitter(op_ia32_Const, bemit_mov_const);
3523 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3524 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3525 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3526 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3527 register_emitter(op_ia32_Dec, bemit_dec);
3528 register_emitter(op_ia32_DecMem, bemit_decmem);
3529 register_emitter(op_ia32_Div, bemit_div);
3530 register_emitter(op_ia32_FldCW, bemit_fldcw);
3531 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3532 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3533 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3534 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3535 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3536 register_emitter(op_ia32_IDiv, bemit_idiv);
3537 register_emitter(op_ia32_IJmp, bemit_ijmp);
3538 register_emitter(op_ia32_IMul, bemit_imul);
3539 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3540 register_emitter(op_ia32_Inc, bemit_inc);
3541 register_emitter(op_ia32_IncMem, bemit_incmem);
3542 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3543 register_emitter(op_ia32_Jmp, bemit_jump);
3544 register_emitter(op_ia32_LdTls, bemit_ldtls);
3545 register_emitter(op_ia32_Lea, bemit_lea);
3546 register_emitter(op_ia32_Leave, bemit_leave);
3547 register_emitter(op_ia32_Load, bemit_load);
3548 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3549 register_emitter(op_ia32_Mul, bemit_mul);
3550 register_emitter(op_ia32_Neg, bemit_neg);
3551 register_emitter(op_ia32_NegMem, bemit_negmem);
3552 register_emitter(op_ia32_Not, bemit_not);
3553 register_emitter(op_ia32_NotMem, bemit_notmem);
3554 register_emitter(op_ia32_Or, bemit_or);
3555 register_emitter(op_ia32_OrMem, bemit_ormem);
3556 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3557 register_emitter(op_ia32_Pop, bemit_pop);
3558 register_emitter(op_ia32_PopEbp, bemit_pop);
3559 register_emitter(op_ia32_PopMem, bemit_popmem);
3560 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3561 register_emitter(op_ia32_Push, bemit_push);
3562 register_emitter(op_ia32_RepPrefix, bemit_rep);
3563 register_emitter(op_ia32_Rol, bemit_rol);
3564 register_emitter(op_ia32_RolMem, bemit_rolmem);
3565 register_emitter(op_ia32_Ror, bemit_ror);
3566 register_emitter(op_ia32_RorMem, bemit_rormem);
3567 register_emitter(op_ia32_Sahf, bemit_sahf);
3568 register_emitter(op_ia32_Sar, bemit_sar);
3569 register_emitter(op_ia32_SarMem, bemit_sarmem);
3570 register_emitter(op_ia32_Sbb, bemit_sbb);
3571 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3572 register_emitter(op_ia32_Setcc, bemit_setcc);
3573 register_emitter(op_ia32_Shl, bemit_shl);
3574 register_emitter(op_ia32_ShlD, bemit_shld);
3575 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3576 register_emitter(op_ia32_Shr, bemit_shr);
3577 register_emitter(op_ia32_ShrD, bemit_shrd);
3578 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3579 register_emitter(op_ia32_Stc, bemit_stc);
3580 register_emitter(op_ia32_Store, bemit_store);
3581 register_emitter(op_ia32_Store8Bit, bemit_store);
3582 register_emitter(op_ia32_Sub, bemit_sub);
3583 register_emitter(op_ia32_SubMem, bemit_submem);
3584 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3585 register_emitter(op_ia32_SubSP, bemit_subsp);
3586 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3587 register_emitter(op_ia32_Test, bemit_test);
3588 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3589 register_emitter(op_ia32_Xor, bemit_xor);
3590 register_emitter(op_ia32_Xor0, bemit_xor0);
3591 register_emitter(op_ia32_XorMem, bemit_xormem);
3592 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3593 register_emitter(op_ia32_fabs, bemit_fabs);
3594 register_emitter(op_ia32_fadd, bemit_fadd);
3595 register_emitter(op_ia32_fchs, bemit_fchs);
3596 register_emitter(op_ia32_fdiv, bemit_fdiv);
3597 register_emitter(op_ia32_ffreep, bemit_ffreep);
3598 register_emitter(op_ia32_fild, bemit_fild);
3599 register_emitter(op_ia32_fist, bemit_fist);
3600 register_emitter(op_ia32_fisttp, bemit_fisttp);
3601 register_emitter(op_ia32_fld, bemit_fld);
3602 register_emitter(op_ia32_fld1, bemit_fld1);
3603 register_emitter(op_ia32_fldz, bemit_fldz);
3604 register_emitter(op_ia32_fmul, bemit_fmul);
3605 register_emitter(op_ia32_fpop, bemit_fpop);
3606 register_emitter(op_ia32_fpush, bemit_fpush);
3607 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3608 register_emitter(op_ia32_fst, bemit_fst);
3609 register_emitter(op_ia32_fsub, bemit_fsub);
3610 register_emitter(op_ia32_fxch, bemit_fxch);
3612 /* ignore the following nodes */
3613 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3614 register_emitter(op_ia32_Unknown, emit_Nothing);
3615 register_emitter(op_be_Keep, emit_Nothing);
3616 register_emitter(op_be_Start, emit_Nothing);
3617 register_emitter(op_Phi, emit_Nothing);
3618 register_emitter(op_Start, emit_Nothing);
3621 static void gen_binary_block(ir_node *block)
3623 ia32_emit_block_header(block);
3625 /* emit the contents of the block */
3626 sched_foreach(block, node) {
3627 ia32_emit_node(node);
3631 void ia32_gen_binary_routine(ir_graph *irg)
3633 ir_entity *entity = get_irg_entity(irg);
3634 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3635 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3636 ir_node **blk_sched = irg_data->blk_sched;
3638 parameter_dbg_info_t *infos;
3640 isa = (ia32_isa_t*) arch_env;
3642 ia32_register_binary_emitters();
3644 infos = construct_parameter_infos(irg);
3645 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3649 /* we use links to point to target blocks */
3650 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3651 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3653 /* initialize next block links */
3654 n = ARR_LEN(blk_sched);
3655 for (i = 0; i < n; ++i) {
3656 ir_node *block = blk_sched[i];
3657 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3659 set_irn_link(block, prev);
3662 for (i = 0; i < n; ++i) {
3663 ir_node *block = blk_sched[i];
3664 gen_binary_block(block);
3667 be_gas_emit_function_epilog(entity);
3669 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3673 void ia32_init_emitter(void)
3675 lc_opt_entry_t *be_grp;
3676 lc_opt_entry_t *ia32_grp;
3678 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3679 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3681 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3685 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");