2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
43 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../benode.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
73 static char pic_base_label[128];
74 static ir_label_t exc_label_id;
75 static int mark_spill_reload = 0;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 /** Checks if the current block is a fall-through target. */
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
99 * returns non-zero if the given block needs a label
100 * because of being a jump-target (and not a fall-through)
102 static int block_needs_label(const ir_node *block)
105 int n_cfgpreds = get_Block_n_cfgpreds(block);
107 if (has_Block_entity(block))
110 if (n_cfgpreds == 0) {
112 } else if (n_cfgpreds == 1) {
113 ir_node *cfgpred = get_Block_cfgpred(block, 0);
114 ir_node *cfgpred_block = get_nodes_block(cfgpred);
116 if (get_prev_block_sched(block) == cfgpred_block
117 && is_fallthrough(cfgpred)) {
126 * Returns the register at in position pos.
128 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
131 const arch_register_t *reg = NULL;
133 assert(get_irn_arity(irn) > pos && "Invalid IN position");
135 /* The out register of the operator at position pos is the
136 in register we need. */
137 op = get_irn_n(irn, pos);
139 reg = arch_get_irn_register(op);
141 assert(reg && "no in register found");
143 if (reg == &ia32_gp_regs[REG_GP_NOREG])
144 panic("trying to emit noreg for %+F input %d", irn, pos);
146 /* in case of unknown register: just return a valid register */
147 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
148 const arch_register_req_t *req = arch_get_register_req(irn, pos);
150 if (arch_register_req_is(req, limited)) {
151 /* in case of limited requirements: get the first allowed register */
152 unsigned idx = rbitset_next(req->limited, 0, 1);
153 reg = arch_register_for_index(req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%lu", prefix, ++id);
208 /*************************************************************
210 * (_) | | / _| | | | |
211 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
212 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
213 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
214 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
217 *************************************************************/
220 * Emit the name of the 8bit low register
222 static void emit_8bit_register(const arch_register_t *reg)
224 const char *reg_name = arch_register_get_name(reg);
227 be_emit_char(reg_name[1]);
232 * Emit the name of the 8bit high register
234 static void emit_8bit_register_high(const arch_register_t *reg)
236 const char *reg_name = arch_register_get_name(reg);
239 be_emit_char(reg_name[1]);
243 static void emit_16bit_register(const arch_register_t *reg)
245 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
248 be_emit_string(reg_name);
252 * emit a register, possible shortened by a mode
254 * @param reg the register
255 * @param mode the mode of the register or NULL for full register
257 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
259 const char *reg_name;
262 int size = get_mode_size_bits(mode);
264 case 8: emit_8bit_register(reg); return;
265 case 16: emit_16bit_register(reg); return;
267 assert(mode_is_float(mode) || size == 32);
270 reg_name = arch_register_get_name(reg);
273 be_emit_string(reg_name);
276 void ia32_emit_source_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_in_reg(node, pos);
280 emit_register(reg, NULL);
283 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
285 set_entity_backend_marked(entity, 1);
286 be_gas_emit_entity(entity);
288 if (get_entity_owner(entity) == get_tls_type()) {
289 if (get_entity_visibility(entity) == visibility_external_allocated) {
290 be_emit_cstring("@INDNTPOFF");
292 be_emit_cstring("@NTPOFF");
296 if (do_pic && !no_pic_adjust) {
298 be_emit_string(pic_base_label);
302 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
304 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
306 if (attr->symconst != NULL) {
309 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
311 if (attr->symconst == NULL || attr->offset != 0) {
312 if (attr->symconst != NULL) {
313 be_emit_irprintf("%+d", attr->offset);
315 be_emit_irprintf("0x%X", attr->offset);
320 static void emit_ia32_Immediate(const ir_node *node)
323 emit_ia32_Immediate_no_prefix(node);
326 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
328 const arch_register_t *reg;
329 const ir_node *in = get_irn_n(node, pos);
330 if (is_ia32_Immediate(in)) {
331 emit_ia32_Immediate(in);
335 reg = get_in_reg(node, pos);
336 emit_8bit_register(reg);
339 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_in_reg(node, pos);
342 emit_8bit_register_high(reg);
345 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
347 const arch_register_t *reg;
348 const ir_node *in = get_irn_n(node, pos);
349 if (is_ia32_Immediate(in)) {
350 emit_ia32_Immediate(in);
354 reg = get_in_reg(node, pos);
355 emit_16bit_register(reg);
358 void ia32_emit_dest_register(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, NULL);
365 void ia32_emit_dest_register_size(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, get_ia32_ls_mode(node));
372 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
374 const arch_register_t *reg = get_out_reg(node, pos);
376 emit_register(reg, mode_Bu);
379 void ia32_emit_x87_register(const ir_node *node, int pos)
381 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
385 be_emit_string(attr->x87[pos]->name);
388 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
390 assert(mode_is_int(mode) || mode_is_reference(mode));
391 switch (get_mode_size_bits(mode)) {
392 case 8: be_emit_char('b'); return;
393 case 16: be_emit_char('w'); return;
394 case 32: be_emit_char('l'); return;
395 /* gas docu says q is the suffix but gcc, objdump and icc use ll
397 case 64: be_emit_cstring("ll"); return;
399 panic("Can't output mode_suffix for %+F", mode);
402 void ia32_emit_mode_suffix(const ir_node *node)
404 ir_mode *mode = get_ia32_ls_mode(node);
408 ia32_emit_mode_suffix_mode(mode);
411 void ia32_emit_x87_mode_suffix(const ir_node *node)
415 /* we only need to emit the mode on address mode */
416 if (get_ia32_op_type(node) == ia32_Normal)
419 mode = get_ia32_ls_mode(node);
420 assert(mode != NULL);
422 if (mode_is_float(mode)) {
423 switch (get_mode_size_bits(mode)) {
424 case 32: be_emit_char('s'); return;
425 case 64: be_emit_char('l'); return;
427 case 96: be_emit_char('t'); return;
430 assert(mode_is_int(mode));
431 switch (get_mode_size_bits(mode)) {
432 case 16: be_emit_char('s'); return;
433 case 32: be_emit_char('l'); return;
434 /* gas docu says q is the suffix but gcc, objdump and icc use ll
436 case 64: be_emit_cstring("ll"); return;
439 panic("Can't output mode_suffix for %+F", mode);
442 static char get_xmm_mode_suffix(ir_mode *mode)
444 assert(mode_is_float(mode));
445 switch(get_mode_size_bits(mode)) {
448 default: panic("Invalid XMM mode");
452 void ia32_emit_xmm_mode_suffix(const ir_node *node)
454 ir_mode *mode = get_ia32_ls_mode(node);
455 assert(mode != NULL);
457 be_emit_char(get_xmm_mode_suffix(mode));
460 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
462 ir_mode *mode = get_ia32_ls_mode(node);
463 assert(mode != NULL);
464 be_emit_char(get_xmm_mode_suffix(mode));
467 void ia32_emit_extend_suffix(const ir_node *node)
469 ir_mode *mode = get_ia32_ls_mode(node);
470 if (get_mode_size_bits(mode) == 32)
472 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
473 ia32_emit_mode_suffix_mode(mode);
476 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
478 ir_node *in = get_irn_n(node, pos);
479 if (is_ia32_Immediate(in)) {
480 emit_ia32_Immediate(in);
482 const ir_mode *mode = get_ia32_ls_mode(node);
483 const arch_register_t *reg = get_in_reg(node, pos);
484 emit_register(reg, mode);
489 * Returns the target block for a control flow node.
491 static ir_node *get_cfop_target_block(const ir_node *irn)
493 assert(get_irn_mode(irn) == mode_X);
494 return get_irn_link(irn);
498 * Emits a block label for the given block.
500 static void ia32_emit_block_name(const ir_node *block)
502 if (has_Block_entity(block)) {
503 ir_entity *entity = get_Block_entity(block);
504 be_gas_emit_entity(entity);
506 be_emit_cstring(BLOCK_PREFIX);
507 be_emit_irprintf("%ld", get_irn_node_nr(block));
512 * Emits the target label for a control flow node.
514 static void ia32_emit_cfop_target(const ir_node *node)
516 ir_node *block = get_cfop_target_block(node);
517 ia32_emit_block_name(block);
521 * positive conditions for signed compares
523 static const char *const cmp2condition_s[] = {
524 NULL, /* always false */
531 NULL /* always true */
535 * positive conditions for unsigned compares
537 static const char *const cmp2condition_u[] = {
538 NULL, /* always false */
545 NULL /* always true */
549 * Emit the suffix for a compare instruction.
551 static void ia32_emit_cmp_suffix(int pnc)
555 if (pnc == ia32_pn_Cmp_parity) {
559 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
560 str = cmp2condition_u[pnc & 7];
562 str = cmp2condition_s[pnc & 7];
568 typedef enum ia32_emit_mod_t {
569 EMIT_RESPECT_LS = 1U << 0,
570 EMIT_ALTERNATE_AM = 1U << 1,
575 * Emits address mode.
577 void ia32_emit_am(const ir_node *node)
579 ir_entity *ent = get_ia32_am_sc(node);
580 int offs = get_ia32_am_offs_int(node);
581 ir_node *base = get_irn_n(node, n_ia32_base);
582 int has_base = !is_ia32_NoReg_GP(base);
583 ir_node *index = get_irn_n(node, n_ia32_index);
584 int has_index = !is_ia32_NoReg_GP(index);
586 /* just to be sure... */
587 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
591 const ia32_attr_t *attr = get_ia32_attr_const(node);
592 if (is_ia32_am_sc_sign(node))
594 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
597 /* also handle special case if nothing is set */
598 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
600 be_emit_irprintf("%+d", offs);
602 be_emit_irprintf("%d", offs);
606 if (has_base || has_index) {
611 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
612 emit_register(reg, NULL);
615 /* emit index + scale */
617 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
620 emit_register(reg, NULL);
622 scale = get_ia32_am_scale(node);
624 be_emit_irprintf(",%d", 1 << scale);
632 * fmt parameter output
633 * ---- ---------------------- ---------------------------------------------
635 * %AM <node> address mode of the node
636 * %AR const arch_register_t* address mode of the node or register
637 * %ASx <node> address mode of the node or source register x
638 * %Dx <node> destination register x
639 * %I <node> immediate of the node
640 * %L <node> control flow target of the node
641 * %M <node> mode suffix of the node
642 * %P int condition code
643 * %R const arch_register_t* register
644 * %Sx <node> source register x
645 * %s const char* string
646 * %u unsigned int unsigned int
647 * %d signed int signed int
650 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
651 * * modifier does not prefix immediates with $, but AM with *
652 * l modifier for %lu and %ld
654 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
660 const char *start = fmt;
661 ia32_emit_mod_t mod = 0;
663 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
666 be_emit_string_len(start, fmt - start);
670 be_emit_finish_line_gas(node);
682 mod |= EMIT_ALTERNATE_AM;
687 mod |= EMIT_RESPECT_LS;
704 if (mod & EMIT_ALTERNATE_AM)
711 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
712 if (mod & EMIT_ALTERNATE_AM)
714 if (get_ia32_op_type(node) == ia32_AddrModeS) {
717 emit_register(reg, NULL);
723 if (get_ia32_op_type(node) == ia32_AddrModeS) {
724 if (mod & EMIT_ALTERNATE_AM)
729 assert(get_ia32_op_type(node) == ia32_Normal);
734 default: goto unknown;
741 const arch_register_t *reg;
743 if (*fmt < '0' || '9' <= *fmt)
747 reg = get_out_reg(node, pos);
748 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
753 if (!(mod & EMIT_ALTERNATE_AM))
755 emit_ia32_Immediate_no_prefix(node);
759 ia32_emit_cfop_target(node);
763 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
768 int pnc = va_arg(ap, int);
769 ia32_emit_cmp_suffix(pnc);
774 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
775 emit_register(reg, NULL);
784 if (*fmt < '0' || '9' <= *fmt)
788 in = get_irn_n(node, pos);
789 if (is_ia32_Immediate(in)) {
790 if (!(mod & EMIT_ALTERNATE_AM))
792 emit_ia32_Immediate_no_prefix(in);
794 const arch_register_t *reg;
796 if (mod & EMIT_ALTERNATE_AM)
798 reg = get_in_reg(node, pos);
799 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
805 const char *str = va_arg(ap, const char*);
811 if (mod & EMIT_LONG) {
812 unsigned long num = va_arg(ap, unsigned long);
813 be_emit_irprintf("%lu", num);
815 unsigned num = va_arg(ap, unsigned);
816 be_emit_irprintf("%u", num);
821 if (mod & EMIT_LONG) {
822 long num = va_arg(ap, long);
823 be_emit_irprintf("%ld", num);
825 int num = va_arg(ap, int);
826 be_emit_irprintf("%d", num);
832 panic("unknown format conversion in ia32_emitf()");
840 * Emits registers and/or address mode of a binary operation.
842 void ia32_emit_binop(const ir_node *node)
844 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
845 ia32_emitf(node, "%#S4, %#AS3");
847 ia32_emitf(node, "%#AS4, %#S3");
852 * Emits registers and/or address mode of a binary operation.
854 void ia32_emit_x87_binop(const ir_node *node)
856 switch(get_ia32_op_type(node)) {
859 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
860 const arch_register_t *in1 = x87_attr->x87[0];
861 const arch_register_t *in = x87_attr->x87[1];
862 const arch_register_t *out = x87_attr->x87[2];
866 } else if (out == in) {
871 be_emit_string(arch_register_get_name(in));
872 be_emit_cstring(", %");
873 be_emit_string(arch_register_get_name(out));
881 assert(0 && "unsupported op type");
886 * Emits registers and/or address mode of a unary operation.
888 void ia32_emit_unop(const ir_node *node, int pos)
892 ia32_emitf(node, fmt);
895 static void emit_ia32_IMul(const ir_node *node)
897 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
898 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
900 /* do we need the 3-address form? */
901 if (is_ia32_NoReg_GP(left) ||
902 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
903 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
905 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
910 * walks up a tree of copies/perms/spills/reloads to find the original value
911 * that is moved around
913 static ir_node *find_original_value(ir_node *node)
915 if (irn_visited(node))
918 mark_irn_visited(node);
919 if (be_is_Copy(node)) {
920 return find_original_value(be_get_Copy_op(node));
921 } else if (be_is_CopyKeep(node)) {
922 return find_original_value(be_get_CopyKeep_op(node));
923 } else if (is_Proj(node)) {
924 ir_node *pred = get_Proj_pred(node);
925 if (be_is_Perm(pred)) {
926 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
927 } else if (be_is_MemPerm(pred)) {
928 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
929 } else if (is_ia32_Load(pred)) {
930 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
934 } else if (is_ia32_Store(node)) {
935 return find_original_value(get_irn_n(node, n_ia32_Store_val));
936 } else if (is_Phi(node)) {
938 arity = get_irn_arity(node);
939 for (i = 0; i < arity; ++i) {
940 ir_node *in = get_irn_n(node, i);
941 ir_node *res = find_original_value(in);
952 static int determine_final_pnc(const ir_node *node, int flags_pos,
955 ir_node *flags = get_irn_n(node, flags_pos);
956 const ia32_attr_t *flags_attr;
957 flags = skip_Proj(flags);
959 if (is_ia32_Sahf(flags)) {
960 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
961 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
962 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
963 inc_irg_visited(current_ir_graph);
964 cmp = find_original_value(cmp);
966 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
967 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
970 flags_attr = get_ia32_attr_const(cmp);
971 if (flags_attr->data.ins_permuted)
972 pnc = get_mirrored_pnc(pnc);
973 pnc |= ia32_pn_Cmp_float;
974 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
975 || is_ia32_Fucompi(flags)) {
976 flags_attr = get_ia32_attr_const(flags);
978 if (flags_attr->data.ins_permuted)
979 pnc = get_mirrored_pnc(pnc);
980 pnc |= ia32_pn_Cmp_float;
982 flags_attr = get_ia32_attr_const(flags);
984 if (flags_attr->data.ins_permuted)
985 pnc = get_mirrored_pnc(pnc);
986 if (flags_attr->data.cmp_unsigned)
987 pnc |= ia32_pn_Cmp_unsigned;
993 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
995 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
996 return get_negated_pnc(pnc, mode);
999 void ia32_emit_cmp_suffix_node(const ir_node *node,
1002 const ia32_attr_t *attr = get_ia32_attr_const(node);
1004 pn_Cmp pnc = get_ia32_condcode(node);
1006 pnc = determine_final_pnc(node, flags_pos, pnc);
1007 if (attr->data.ins_permuted)
1008 pnc = ia32_get_negated_pnc(pnc);
1010 ia32_emit_cmp_suffix(pnc);
1014 * Emits an exception label for a given node.
1016 static void ia32_emit_exc_label(const ir_node *node)
1018 be_emit_string(be_gas_insn_label_prefix());
1019 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1023 * Returns the Proj with projection number proj and NOT mode_M
1025 static ir_node *get_proj(const ir_node *node, long proj)
1027 const ir_edge_t *edge;
1030 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1032 foreach_out_edge(node, edge) {
1033 src = get_edge_src_irn(edge);
1035 assert(is_Proj(src) && "Proj expected");
1036 if (get_irn_mode(src) == mode_M)
1039 if (get_Proj_proj(src) == proj)
1045 static int can_be_fallthrough(const ir_node *node)
1047 ir_node *target_block = get_cfop_target_block(node);
1048 ir_node *block = get_nodes_block(node);
1049 return get_prev_block_sched(target_block) == block;
1053 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1055 static void emit_ia32_Jcc(const ir_node *node)
1057 int need_parity_label = 0;
1058 const ir_node *proj_true;
1059 const ir_node *proj_false;
1060 const ir_node *block;
1061 pn_Cmp pnc = get_ia32_condcode(node);
1063 pnc = determine_final_pnc(node, 0, pnc);
1065 /* get both Projs */
1066 proj_true = get_proj(node, pn_ia32_Jcc_true);
1067 assert(proj_true && "Jcc without true Proj");
1069 proj_false = get_proj(node, pn_ia32_Jcc_false);
1070 assert(proj_false && "Jcc without false Proj");
1072 block = get_nodes_block(node);
1074 if (can_be_fallthrough(proj_true)) {
1075 /* exchange both proj's so the second one can be omitted */
1076 const ir_node *t = proj_true;
1078 proj_true = proj_false;
1080 pnc = ia32_get_negated_pnc(pnc);
1083 if (pnc & ia32_pn_Cmp_float) {
1084 /* Some floating point comparisons require a test of the parity flag,
1085 * which indicates that the result is unordered */
1088 ia32_emitf(proj_true, "\tjp %L\n");
1093 ia32_emitf(proj_true, "\tjnp %L\n");
1099 /* we need a local label if the false proj is a fallthrough
1100 * as the falseblock might have no label emitted then */
1101 if (can_be_fallthrough(proj_false)) {
1102 need_parity_label = 1;
1103 ia32_emitf(proj_false, "\tjp 1f\n");
1105 ia32_emitf(proj_false, "\tjp %L\n");
1112 ia32_emitf(proj_true, "\tjp %L\n");
1120 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1123 if (need_parity_label) {
1124 ia32_emitf(NULL, "1:\n");
1127 /* the second Proj might be a fallthrough */
1128 if (can_be_fallthrough(proj_false)) {
1129 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1131 ia32_emitf(proj_false, "\tjmp %L\n");
1135 static void emit_ia32_CMov(const ir_node *node)
1137 const ia32_attr_t *attr = get_ia32_attr_const(node);
1138 int ins_permuted = attr->data.ins_permuted;
1139 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1140 pn_Cmp pnc = get_ia32_condcode(node);
1141 const arch_register_t *in_true;
1142 const arch_register_t *in_false;
1144 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1146 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1147 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1149 /* should be same constraint fullfilled? */
1150 if (out == in_false) {
1151 /* yes -> nothing to do */
1152 } else if (out == in_true) {
1153 const arch_register_t *tmp;
1155 assert(get_ia32_op_type(node) == ia32_Normal);
1157 ins_permuted = !ins_permuted;
1164 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1168 pnc = ia32_get_negated_pnc(pnc);
1170 /* TODO: handling of Nans isn't correct yet */
1172 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1175 /*********************************************************
1178 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1179 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1180 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1181 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1184 *********************************************************/
1186 /* jump table entry (target and corresponding number) */
1187 typedef struct _branch_t {
1192 /* jump table for switch generation */
1193 typedef struct _jmp_tbl_t {
1194 ir_node *defProj; /**< default target */
1195 long min_value; /**< smallest switch case */
1196 long max_value; /**< largest switch case */
1197 long num_branches; /**< number of jumps */
1198 char *label; /**< label of the jump table */
1199 branch_t *branches; /**< jump array */
1203 * Compare two variables of type branch_t. Used to sort all switch cases
1205 static int ia32_cmp_branch_t(const void *a, const void *b)
1207 branch_t *b1 = (branch_t *)a;
1208 branch_t *b2 = (branch_t *)b;
1210 if (b1->value <= b2->value)
1217 * Emits code for a SwitchJmp (creates a jump table if
1218 * possible otherwise a cmp-jmp cascade). Port from
1221 static void emit_ia32_SwitchJmp(const ir_node *node)
1223 unsigned long interval;
1229 const ir_edge_t *edge;
1231 /* fill the table structure */
1232 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1233 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1235 tbl.num_branches = get_irn_n_edges(node) - 1;
1236 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1237 tbl.min_value = INT_MAX;
1238 tbl.max_value = INT_MIN;
1240 default_pn = get_ia32_condcode(node);
1242 /* go over all proj's and collect them */
1243 foreach_out_edge(node, edge) {
1244 proj = get_edge_src_irn(edge);
1245 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1247 pnc = get_Proj_proj(proj);
1249 /* check for default proj */
1250 if (pnc == default_pn) {
1251 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1254 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1255 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1257 /* create branch entry */
1258 tbl.branches[i].target = proj;
1259 tbl.branches[i].value = pnc;
1264 assert(i == tbl.num_branches);
1266 /* sort the branches by their number */
1267 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1269 /* two-complement's magic make this work without overflow */
1270 interval = tbl.max_value - tbl.min_value;
1272 /* emit the table */
1273 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1274 ia32_emitf(tbl.defProj, "\tja %L\n");
1276 if (tbl.num_branches > 1) {
1278 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1280 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1281 ia32_emitf(NULL, "\t.align 4\n");
1282 ia32_emitf(NULL, "%s:\n", tbl.label);
1284 last_value = tbl.branches[0].value;
1285 for (i = 0; i != tbl.num_branches; ++i) {
1286 while (last_value != tbl.branches[i].value) {
1287 ia32_emitf(tbl.defProj, ".long %L\n");
1290 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1293 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1295 /* one jump is enough */
1296 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1306 * Emits code for a unconditional jump.
1308 static void emit_Jmp(const ir_node *node)
1312 /* for now, the code works for scheduled and non-schedules blocks */
1313 block = get_nodes_block(node);
1315 /* we have a block schedule */
1316 if (can_be_fallthrough(node)) {
1317 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1319 ia32_emitf(node, "\tjmp %L\n");
1324 * Emit an inline assembler operand.
1326 * @param node the ia32_ASM node
1327 * @param s points to the operand (a %c)
1329 * @return pointer to the first char in s NOT in the current operand
1331 static const char* emit_asm_operand(const ir_node *node, const char *s)
1333 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1334 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1336 const arch_register_t *reg;
1337 const ia32_asm_reg_t *asm_regs = attr->register_map;
1338 const ia32_asm_reg_t *asm_reg;
1339 const char *reg_name;
1348 /* parse modifiers */
1351 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1376 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1383 sscanf(s, "%d%n", &num, &p);
1385 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1392 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1394 "Error: Custom assembler references invalid input/output (%+F)\n",
1398 asm_reg = & asm_regs[num];
1399 assert(asm_reg->valid);
1402 if (asm_reg->use_input == 0) {
1403 reg = get_out_reg(node, asm_reg->inout_pos);
1405 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1407 /* might be an immediate value */
1408 if (is_ia32_Immediate(pred)) {
1409 emit_ia32_Immediate(pred);
1412 reg = get_in_reg(node, asm_reg->inout_pos);
1416 "Warning: no register assigned for %d asm op (%+F)\n",
1421 if (asm_reg->memory) {
1426 if (modifier != 0) {
1430 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1433 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1436 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1439 panic("Invalid asm op modifier");
1441 be_emit_string(reg_name);
1443 emit_register(reg, asm_reg->mode);
1446 if (asm_reg->memory) {
1454 * Emits code for an ASM pseudo op.
1456 static void emit_ia32_Asm(const ir_node *node)
1458 const void *gen_attr = get_irn_generic_attr_const(node);
1459 const ia32_asm_attr_t *attr
1460 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1461 ident *asm_text = attr->asm_text;
1462 const char *s = get_id_str(asm_text);
1464 ia32_emitf(node, "#APP\t\n");
1471 s = emit_asm_operand(node, s);
1477 ia32_emitf(NULL, "\n#NO_APP\n");
1480 /**********************************
1483 * | | ___ _ __ _ _| |_) |
1484 * | | / _ \| '_ \| | | | _ <
1485 * | |___| (_) | |_) | |_| | |_) |
1486 * \_____\___/| .__/ \__, |____/
1489 **********************************/
1492 * Emit movsb/w instructions to make mov count divideable by 4
1494 static void emit_CopyB_prolog(unsigned size)
1497 ia32_emitf(NULL, "\tmovsb\n");
1499 ia32_emitf(NULL, "\tmovsw\n");
1503 * Emit rep movsd instruction for memcopy.
1505 static void emit_ia32_CopyB(const ir_node *node)
1507 unsigned size = get_ia32_copyb_size(node);
1509 emit_CopyB_prolog(size);
1510 ia32_emitf(node, "\trep movsd\n");
1514 * Emits unrolled memcopy.
1516 static void emit_ia32_CopyB_i(const ir_node *node)
1518 unsigned size = get_ia32_copyb_size(node);
1520 emit_CopyB_prolog(size);
1524 ia32_emitf(NULL, "\tmovsd\n");
1530 /***************************
1534 * | | / _ \| '_ \ \ / /
1535 * | |___| (_) | | | \ V /
1536 * \_____\___/|_| |_|\_/
1538 ***************************/
1541 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1543 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1546 ir_mode *ls_mode = get_ia32_ls_mode(node);
1547 int ls_bits = get_mode_size_bits(ls_mode);
1548 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1550 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1553 static void emit_ia32_Conv_I2FP(const ir_node *node)
1555 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1558 static void emit_ia32_Conv_FP2I(const ir_node *node)
1560 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1563 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1565 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1569 * Emits code for an Int conversion.
1571 static void emit_ia32_Conv_I2I(const ir_node *node)
1573 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1574 int signed_mode = mode_is_signed(smaller_mode);
1575 const char *sign_suffix;
1577 assert(!mode_is_float(smaller_mode));
1579 sign_suffix = signed_mode ? "s" : "z";
1580 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1586 static void emit_ia32_Call(const ir_node *node)
1588 /* Special case: Call must not have its immediates prefixed by $, instead
1589 * address mode is prefixed by *. */
1590 ia32_emitf(node, "\tcall %*AS3\n");
1594 /*******************************************
1597 * | |__ ___ _ __ ___ __| | ___ ___
1598 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1599 * | |_) | __/ | | | (_) | (_| | __/\__ \
1600 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1602 *******************************************/
1605 * Emits code to increase stack pointer.
1607 static void emit_be_IncSP(const ir_node *node)
1609 int offs = be_get_IncSP_offset(node);
1615 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1617 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1621 static inline bool is_unknown_reg(const arch_register_t *reg)
1623 if(reg == &ia32_gp_regs[REG_GP_UKNWN]
1624 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1625 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1632 * Emits code for Copy/CopyKeep.
1634 static void Copy_emitter(const ir_node *node, const ir_node *op)
1636 const arch_register_t *in = arch_get_irn_register(op);
1637 const arch_register_t *out = arch_get_irn_register(node);
1642 if (is_unknown_reg(in))
1644 /* copies of vf nodes aren't real... */
1645 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1648 if (get_irn_mode(node) == mode_E) {
1649 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1651 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1655 static void emit_be_Copy(const ir_node *node)
1657 Copy_emitter(node, be_get_Copy_op(node));
1660 static void emit_be_CopyKeep(const ir_node *node)
1662 Copy_emitter(node, be_get_CopyKeep_op(node));
1666 * Emits code for exchange.
1668 static void emit_be_Perm(const ir_node *node)
1670 const arch_register_t *in0, *in1;
1671 const arch_register_class_t *cls0, *cls1;
1673 in0 = arch_get_irn_register(get_irn_n(node, 0));
1674 in1 = arch_get_irn_register(get_irn_n(node, 1));
1676 cls0 = arch_register_get_class(in0);
1677 cls1 = arch_register_get_class(in1);
1679 assert(cls0 == cls1 && "Register class mismatch at Perm");
1681 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1682 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1683 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1684 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1685 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1686 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1687 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1689 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1692 panic("unexpected register class in be_Perm (%+F)", node);
1697 * Emits code for Constant loading.
1699 static void emit_ia32_Const(const ir_node *node)
1701 ia32_emitf(node, "\tmovl %I, %D0\n");
1705 * Emits code to load the TLS base
1707 static void emit_ia32_LdTls(const ir_node *node)
1709 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1712 /* helper function for emit_ia32_Minus64Bit */
1713 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1715 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1718 /* helper function for emit_ia32_Minus64Bit */
1719 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1721 ia32_emitf(node, "\tnegl %R\n", reg);
1724 /* helper function for emit_ia32_Minus64Bit */
1725 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1727 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1730 /* helper function for emit_ia32_Minus64Bit */
1731 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1733 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1736 /* helper function for emit_ia32_Minus64Bit */
1737 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1739 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1742 /* helper function for emit_ia32_Minus64Bit */
1743 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1745 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1748 static void emit_ia32_Minus64Bit(const ir_node *node)
1750 const arch_register_t *in_lo = get_in_reg(node, 0);
1751 const arch_register_t *in_hi = get_in_reg(node, 1);
1752 const arch_register_t *out_lo = get_out_reg(node, 0);
1753 const arch_register_t *out_hi = get_out_reg(node, 1);
1755 if (out_lo == in_lo) {
1756 if (out_hi != in_hi) {
1757 /* a -> a, b -> d */
1760 /* a -> a, b -> b */
1763 } else if (out_lo == in_hi) {
1764 if (out_hi == in_lo) {
1765 /* a -> b, b -> a */
1766 emit_xchg(node, in_lo, in_hi);
1769 /* a -> b, b -> d */
1770 emit_mov(node, in_hi, out_hi);
1771 emit_mov(node, in_lo, out_lo);
1775 if (out_hi == in_lo) {
1776 /* a -> c, b -> a */
1777 emit_mov(node, in_lo, out_lo);
1779 } else if (out_hi == in_hi) {
1780 /* a -> c, b -> b */
1781 emit_mov(node, in_lo, out_lo);
1784 /* a -> c, b -> d */
1785 emit_mov(node, in_lo, out_lo);
1791 emit_neg( node, out_hi);
1792 emit_neg( node, out_lo);
1793 emit_sbb0(node, out_hi);
1797 emit_zero(node, out_hi);
1798 emit_neg( node, out_lo);
1799 emit_sbb( node, in_hi, out_hi);
1802 static void emit_ia32_GetEIP(const ir_node *node)
1804 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1805 ia32_emitf(NULL, "%s:\n", pic_base_label);
1806 ia32_emitf(node, "\tpopl %D0\n");
1809 static void emit_ia32_ClimbFrame(const ir_node *node)
1811 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1813 ia32_emitf(node, "\tmovl %S0, %D0\n");
1814 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1815 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1816 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1817 ia32_emitf(node, "\tdec %S1\n");
1818 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1821 static void emit_be_Return(const ir_node *node)
1823 unsigned pop = be_Return_get_pop(node);
1825 if (pop > 0 || be_Return_get_emit_pop(node)) {
1826 ia32_emitf(node, "\tret $%u\n", pop);
1828 ia32_emitf(node, "\tret\n");
1832 static void emit_Nothing(const ir_node *node)
1838 /***********************************************************************************
1841 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1842 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1843 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1844 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1846 ***********************************************************************************/
1849 * Enters the emitter functions for handled nodes into the generic
1850 * pointer of an opcode.
1852 static void ia32_register_emitters(void)
1854 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1855 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1856 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1857 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1858 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1859 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1861 /* first clear the generic function pointer for all ops */
1862 clear_irp_opcodes_generic_func();
1864 /* register all emitter functions defined in spec */
1865 ia32_register_spec_emitters();
1867 /* other ia32 emitter functions */
1868 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1873 IA32_EMIT(Conv_FP2FP);
1874 IA32_EMIT(Conv_FP2I);
1875 IA32_EMIT(Conv_I2FP);
1876 IA32_EMIT(Conv_I2I);
1883 IA32_EMIT(Minus64Bit);
1884 IA32_EMIT(SwitchJmp);
1885 IA32_EMIT(ClimbFrame);
1887 /* benode emitter */
1910 typedef void (*emit_func_ptr) (const ir_node *);
1913 * Assign and emit an exception label if the current instruction can fail.
1915 static void ia32_assign_exc_label(ir_node *node)
1917 /* assign a new ID to the instruction */
1918 set_ia32_exc_label_id(node, ++exc_label_id);
1920 ia32_emit_exc_label(node);
1922 be_emit_pad_comment();
1923 be_emit_cstring("/* exception to Block ");
1924 ia32_emit_cfop_target(node);
1925 be_emit_cstring(" */\n");
1926 be_emit_write_line();
1930 * Emits code for a node.
1932 static void ia32_emit_node(ir_node *node)
1934 ir_op *op = get_irn_op(node);
1936 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1938 if (is_ia32_irn(node)) {
1939 if (get_ia32_exc_label(node)) {
1940 /* emit the exception label of this instruction */
1941 ia32_assign_exc_label(node);
1943 if (mark_spill_reload) {
1944 if (is_ia32_is_spill(node)) {
1945 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1947 if (is_ia32_is_reload(node)) {
1948 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1950 if (is_ia32_is_remat(node)) {
1951 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1955 if (op->ops.generic) {
1956 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1958 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1963 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1969 * Emits gas alignment directives
1971 static void ia32_emit_alignment(unsigned align, unsigned skip)
1973 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1977 * Emits gas alignment directives for Labels depended on cpu architecture.
1979 static void ia32_emit_align_label(void)
1981 unsigned align = ia32_cg_config.label_alignment;
1982 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1983 ia32_emit_alignment(align, maximum_skip);
1987 * Test whether a block should be aligned.
1988 * For cpus in the P4/Athlon class it is useful to align jump labels to
1989 * 16 bytes. However we should only do that if the alignment nops before the
1990 * label aren't executed more often than we have jumps to the label.
1992 static int should_align_block(const ir_node *block)
1994 static const double DELTA = .0001;
1995 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1996 ir_node *prev = get_prev_block_sched(block);
1998 double prev_freq = 0; /**< execfreq of the fallthrough block */
1999 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2002 if (exec_freq == NULL)
2004 if (ia32_cg_config.label_alignment_factor <= 0)
2007 block_freq = get_block_execfreq(exec_freq, block);
2008 if (block_freq < DELTA)
2011 n_cfgpreds = get_Block_n_cfgpreds(block);
2012 for(i = 0; i < n_cfgpreds; ++i) {
2013 const ir_node *pred = get_Block_cfgpred_block(block, i);
2014 double pred_freq = get_block_execfreq(exec_freq, pred);
2017 prev_freq += pred_freq;
2019 jmp_freq += pred_freq;
2023 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2026 jmp_freq /= prev_freq;
2028 return jmp_freq > ia32_cg_config.label_alignment_factor;
2032 * Emit the block header for a block.
2034 * @param block the block
2035 * @param prev_block the previous block
2037 static void ia32_emit_block_header(ir_node *block)
2039 ir_graph *irg = current_ir_graph;
2040 int need_label = block_needs_label(block);
2042 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2044 if (block == get_irg_end_block(irg))
2047 if (ia32_cg_config.label_alignment > 0) {
2048 /* align the current block if:
2049 * a) if should be aligned due to its execution frequency
2050 * b) there is no fall-through here
2052 if (should_align_block(block)) {
2053 ia32_emit_align_label();
2055 /* if the predecessor block has no fall-through,
2056 we can always align the label. */
2058 int has_fallthrough = 0;
2060 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2061 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2062 if (can_be_fallthrough(cfg_pred)) {
2063 has_fallthrough = 1;
2068 if (!has_fallthrough)
2069 ia32_emit_align_label();
2074 ia32_emit_block_name(block);
2077 be_emit_pad_comment();
2078 be_emit_cstring(" /* ");
2080 be_emit_cstring("\t/* ");
2081 ia32_emit_block_name(block);
2082 be_emit_cstring(": ");
2085 be_emit_cstring("preds:");
2087 /* emit list of pred blocks in comment */
2088 arity = get_irn_arity(block);
2090 be_emit_cstring(" none");
2092 for (i = 0; i < arity; ++i) {
2093 ir_node *predblock = get_Block_cfgpred_block(block, i);
2094 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2097 if (exec_freq != NULL) {
2098 be_emit_irprintf(", freq: %f",
2099 get_block_execfreq(exec_freq, block));
2101 be_emit_cstring(" */\n");
2102 be_emit_write_line();
2106 * Walks over the nodes in a block connected by scheduling edges
2107 * and emits code for each node.
2109 static void ia32_gen_block(ir_node *block)
2113 ia32_emit_block_header(block);
2115 /* emit the contents of the block */
2116 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2117 sched_foreach(block, node) {
2118 ia32_emit_node(node);
2122 typedef struct exc_entry {
2123 ir_node *exc_instr; /** The instruction that can issue an exception. */
2124 ir_node *block; /** The block to call then. */
2129 * Sets labels for control flow nodes (jump target).
2130 * Links control predecessors to there destination blocks.
2132 static void ia32_gen_labels(ir_node *block, void *data)
2134 exc_entry **exc_list = data;
2138 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2139 pred = get_Block_cfgpred(block, n);
2140 set_irn_link(pred, block);
2142 pred = skip_Proj(pred);
2143 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2148 ARR_APP1(exc_entry, *exc_list, e);
2149 set_irn_link(pred, block);
2155 * Compare two exception_entries.
2157 static int cmp_exc_entry(const void *a, const void *b)
2159 const exc_entry *ea = a;
2160 const exc_entry *eb = b;
2162 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2168 * Main driver. Emits the code for one routine.
2170 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2172 ir_entity *entity = get_irg_entity(irg);
2173 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2178 do_pic = cg->birg->main_env->options->pic;
2180 ia32_register_emitters();
2182 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2184 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2185 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2187 /* we use links to point to target blocks */
2188 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2189 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2191 /* initialize next block links */
2192 n = ARR_LEN(cg->blk_sched);
2193 for (i = 0; i < n; ++i) {
2194 ir_node *block = cg->blk_sched[i];
2195 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2197 set_irn_link(block, prev);
2200 for (i = 0; i < n; ++i) {
2201 ir_node *block = cg->blk_sched[i];
2203 ia32_gen_block(block);
2206 be_gas_emit_function_epilog(entity);
2207 be_dbg_method_end();
2209 be_emit_write_line();
2211 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2213 /* Sort the exception table using the exception label id's.
2214 Those are ascending with ascending addresses. */
2215 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2219 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2220 be_emit_cstring("\t.long ");
2221 ia32_emit_exc_label(exc_list[i].exc_instr);
2223 be_emit_cstring("\t.long ");
2224 ia32_emit_block_name(exc_list[i].block);
2228 DEL_ARR_F(exc_list);
2231 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2232 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2236 /* ==== Experimental binary emitter ==== */
2238 static unsigned char reg_map[N_ia32_gp_REGS];
2240 static void build_reg_map(void)
2242 reg_map[REG_EAX] = 0x0;
2243 reg_map[REG_ECX] = 0x1;
2244 reg_map[REG_EDX] = 0x2;
2245 reg_map[REG_EBX] = 0x3;
2246 reg_map[REG_ESP] = 0x4;
2247 reg_map[REG_EBP] = 0x5;
2248 reg_map[REG_ESI] = 0x6;
2249 reg_map[REG_EDI] = 0x7;
2252 /* Node: The following routines are supposed to append bytes, words, dwords
2253 to the output stream.
2254 Currently the implementation is stupid in that it still creates output
2255 for an "assembler" in the form of .byte, .long
2256 We will change this when enough infrastructure is there to create complete
2257 machine code in memory/object files */
2259 static void bemit8(const unsigned char byte)
2261 be_emit_irprintf("\t.byte 0x%x\n", byte);
2262 be_emit_write_line();
2265 static void bemit16(const unsigned u16)
2267 be_emit_irprintf("\t.word 0x%x\n", u16);
2268 be_emit_write_line();
2271 static void bemit32(const unsigned u32)
2273 be_emit_irprintf("\t.long 0x%x\n", u32);
2274 be_emit_write_line();
2277 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2280 if (entity == NULL) {
2285 /* the final version should remember the position in the bytestream
2286 and patch it with the correct address at linktime... */
2287 be_emit_cstring("\t.long ");
2290 set_entity_backend_marked(entity, 1);
2291 be_gas_emit_entity(entity);
2294 be_emit_cstring("-.");
2298 be_emit_irprintf("%+d", offset);
2301 be_emit_write_line();
2304 /* end emit routines, all emitters following here should only use the functions
2307 static void bemit_modrr(const arch_register_t *op1_dest,
2308 const arch_register_t *op2)
2310 unsigned char modrm = 0xC0;
2311 modrm |= reg_map[op1_dest->index];
2312 modrm |= reg_map[op2->index] << 3;
2316 static void bemit_modru(const arch_register_t *dest, unsigned val)
2319 unsigned char modrm = 0xC0;
2320 modrm |= reg_map[dest->index];
2325 static unsigned get_imm_size(ir_entity *entity, int offset)
2329 if (offset >= -127 && offset < 128) {
2331 } else if (offset >= -32768 && offset < 32767) {
2338 static void bemit_binop_with_imm(const ir_node *node, unsigned opimm8,
2339 unsigned opimm32, unsigned ruval)
2341 const arch_register_t *reg = get_out_reg(node, 0);
2342 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2343 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2344 unsigned size = get_imm_size(attr->symconst, attr->offset);
2349 bemit_modru(reg, ruval);
2350 bemit8(attr->offset);
2355 bemit_modru(reg, ruval);
2356 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2359 panic("invalid imm size?!?");
2362 static void bemit_modsourceam(unsigned dest_reg, const ir_node *node)
2364 ir_entity *ent = get_ia32_am_sc(node);
2365 int offs = get_ia32_am_offs_int(node);
2366 ir_node *base = get_irn_n(node, n_ia32_base);
2367 int has_base = !is_ia32_NoReg_GP(base);
2368 ir_node *index = get_irn_n(node, n_ia32_index);
2369 int has_index = !is_ia32_NoReg_GP(index);
2372 unsigned emitoffs = 0;
2373 bool emitsib = false;
2375 /* set the mod part depending on displacement */
2379 } else if (offs == 0) {
2381 } else if (offs >= -127 && offs <= 128) {
2389 /* determine if we need a SIB byte */
2391 const arch_register_t *reg_index = arch_get_irn_register(index);
2392 assert(reg_index->index != REG_ESP);
2393 sib |= reg_map[reg_index->index] << 3;
2396 const arch_register_t *reg = arch_get_irn_register(base);
2397 sib |= reg_map[reg->index];
2402 int scale = get_ia32_am_scale(node);
2408 /* determine modrm byte */
2411 } else if (has_base) {
2412 const arch_register_t *reg = arch_get_irn_register(base);
2413 /* we are forced to emit a sib when base is ESP */
2414 if (reg->index == REG_ESP) {
2418 /* we are forced to emit a 32bit offset as EBP base without
2419 offset is a special case for displacement without base */
2420 } else if (reg->index == REG_EBP && emitoffs == 0) {
2421 assert( (modrm & 0xC0) == 0);
2425 modrm |= reg_map[reg->index];
2431 modrm |= dest_reg << 3;
2437 /* emit displacement */
2438 if (emitoffs == 8) {
2439 bemit8((unsigned) offs);
2440 } else if (emitoffs == 32) {
2441 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2445 static void bemit_binop(const ir_node *node, unsigned modrr, unsigned am)
2447 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2448 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2450 bemit_modsourceam(reg_map[out->index], node);
2452 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2453 assert(get_ia32_op_type(node) == ia32_Normal);
2455 bemit_modrr(out, op2);
2459 static void bemit_immediate(const ir_node *node, bool relative)
2461 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2462 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2465 static void bemit_copy(const ir_node *copy)
2467 const ir_node *op = be_get_Copy_op(copy);
2468 const arch_register_t *in = arch_get_irn_register(op);
2469 const arch_register_t *out = arch_get_irn_register(copy);
2471 if (in == out || is_unknown_reg(in))
2473 /* copies of vf nodes aren't real... */
2474 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2477 if (get_irn_mode(copy) == mode_E) {
2480 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2482 bemit_modrr(out, in);
2486 static void bemit_xor0(const ir_node *node)
2488 const arch_register_t *out = get_out_reg(node, 0);
2490 bemit_modrr(out, out);
2493 static void bemit_const(const ir_node *node)
2495 const arch_register_t *out = get_out_reg(node, 0);
2496 bemit8(0xB8 + reg_map[out->index]);
2497 bemit_immediate(node, false);
2500 static void bemit_add(const ir_node *node)
2502 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2503 if (is_ia32_Immediate(right)) {
2504 /* TODO: there's a shorter variant with DEST=EAX */
2505 bemit_binop_with_imm(node, 0x83, 0x81, 0);
2507 bemit_binop(node, 0x01, 0x03);
2511 static void bemit_sub(const ir_node *node)
2513 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2514 if (is_ia32_Immediate(right)) {
2515 /* TODO: there's a shorter variant with DEST=EAX */
2516 bemit_binop_with_imm(node, 0x83, 0x81, 5);
2518 bemit_binop(node, 0x29, 0x2B);
2522 static void bemit_xor(const ir_node *node)
2524 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2525 if (is_ia32_Immediate(right)) {
2526 /* TODO: there's a shorter variant with DEST=EAX */
2527 bemit_binop_with_imm(node, 0x83, 0x81, 6);
2529 bemit_binop(node, 0x31, 0x33);
2533 static void bemit_not(const ir_node *node)
2535 const arch_register_t *reg = get_out_reg(node, 0);
2537 bemit_modru(reg, 2);
2540 static void bemit_lea(const ir_node *node)
2542 const arch_register_t *out = get_out_reg(node, 0);
2544 bemit_modsourceam(reg_map[out->index], node);
2547 static void bemit_cltd(const ir_node *node)
2553 static void bemit_load(const ir_node *node)
2555 const arch_register_t *out = get_out_reg(node, 0);
2557 /* TODO: load from constant address to EAX can be encoded
2560 bemit_modsourceam(reg_map[out->index], node);
2563 static void bemit_store(const ir_node *node)
2565 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2567 if (is_ia32_Immediate(value)) {
2569 bemit_modsourceam(0, node);
2570 bemit_immediate(value, false);
2572 /* TODO: store to constant address from EAX can be encoded as
2574 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
2576 bemit_modsourceam(reg_map[in->index], node);
2580 static void bemit_push(const ir_node *node)
2582 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
2584 if (is_ia32_Immediate(value)) {
2585 const ia32_immediate_attr_t *attr
2586 = get_ia32_immediate_attr_const(value);
2587 unsigned size = get_imm_size(attr->symconst, attr->offset);
2588 /* TODO: check for bitsizes different from 32... */
2592 bemit8(attr->offset);
2597 bemit_immediate(value, false);
2602 bemit_modsourceam(6, node);
2606 static void bemit_pop(const ir_node *node)
2608 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
2609 /* TODO: check for AM pop */
2610 bemit8(0x58 + reg_map[reg->index]);
2613 static void bemit_call(const ir_node *node)
2615 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
2617 if (is_ia32_Immediate(proc)) {
2619 bemit_immediate(proc, true);
2621 panic("indirect call NIY");
2625 static void bemit_return(const ir_node *node)
2627 unsigned pop = be_Return_get_pop(node);
2628 if (pop > 0 || be_Return_get_emit_pop(node)) {
2630 assert(pop <= 0xffff);
2637 static void bemit_incsp(const ir_node *node)
2639 const arch_register_t *reg = get_out_reg(node, 0);
2640 int offs = be_get_IncSP_offset(node);
2641 unsigned size = get_imm_size(NULL, offs);
2644 bemit8(size == 8 ? 0x83 : 0x81);
2645 bemit_modru(reg, 5); /* sub */
2651 } else if (offs < 0) {
2652 bemit8(size == 8 ? 0x83 : 0x81);
2653 bemit_modru(reg, 0); /* add */
2663 * The type of a emitter function.
2665 typedef void (*emit_func) (const ir_node *);
2668 * Set a node emitter. Make it a bit more type safe.
2670 static void register_emitter(ir_op *op, emit_func func)
2672 op->ops.generic = (op_func) func;
2675 static void ia32_register_binary_emitters(void)
2677 /* first clear the generic function pointer for all ops */
2678 clear_irp_opcodes_generic_func();
2680 /* benode emitter */
2681 register_emitter(op_be_Copy, bemit_copy);
2682 register_emitter(op_be_Return, bemit_return);
2683 register_emitter(op_be_IncSP, bemit_incsp);
2684 register_emitter(op_ia32_Add, bemit_add);
2685 register_emitter(op_ia32_Call, bemit_call);
2686 register_emitter(op_ia32_Cltd, bemit_cltd);
2687 register_emitter(op_ia32_Sub, bemit_sub);
2688 register_emitter(op_ia32_Xor0, bemit_xor0);
2689 register_emitter(op_ia32_Xor, bemit_xor);
2690 register_emitter(op_ia32_Const, bemit_const);
2691 register_emitter(op_ia32_Lea, bemit_lea);
2692 register_emitter(op_ia32_Load, bemit_load);
2693 register_emitter(op_ia32_Not, bemit_not);
2694 register_emitter(op_ia32_Push, bemit_push);
2695 register_emitter(op_ia32_Pop, bemit_pop);
2696 register_emitter(op_ia32_Store, bemit_store);
2698 /* ignore the following nodes */
2699 register_emitter(op_ia32_ProduceVal, emit_Nothing);
2700 register_emitter(op_be_Barrier, emit_Nothing);
2701 register_emitter(op_be_Keep, emit_Nothing);
2702 register_emitter(op_be_RegParams, emit_Nothing);
2703 register_emitter(op_Phi, emit_Nothing);
2704 register_emitter(op_Start, emit_Nothing);
2707 static void gen_binary_block(ir_node *block)
2711 ia32_emit_block_header(block);
2713 /* emit the contents of the block */
2714 sched_foreach(block, node) {
2715 ia32_emit_node(node);
2719 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2721 ir_entity *entity = get_irg_entity(irg);
2727 ia32_register_binary_emitters();
2729 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2731 /* we use links to point to target blocks */
2732 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2733 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2735 /* initialize next block links */
2736 n = ARR_LEN(cg->blk_sched);
2737 for (i = 0; i < n; ++i) {
2738 ir_node *block = cg->blk_sched[i];
2739 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2741 set_irn_link(block, prev);
2744 for (i = 0; i < n; ++i) {
2745 ir_node *block = cg->blk_sched[i];
2746 gen_binary_block(block);
2749 be_gas_emit_function_epilog(entity);
2750 be_dbg_method_end();
2752 be_emit_write_line();
2754 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2760 void ia32_init_emitter(void)
2762 lc_opt_entry_t *be_grp;
2763 lc_opt_entry_t *ia32_grp;
2765 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2766 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2768 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2772 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");