2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
78 * Returns the register at in position pos.
80 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
83 const arch_register_t *reg = NULL;
85 assert(get_irn_arity(irn) > pos && "Invalid IN position");
87 /* The out register of the operator at position pos is the
88 in register we need. */
89 op = get_irn_n(irn, pos);
91 reg = arch_get_irn_register(arch_env, op);
93 assert(reg && "no in register found");
95 if(reg == &ia32_gp_regs[REG_GP_NOREG])
96 panic("trying to emit noreg for %+F input %d", irn, pos);
98 /* in case of unknown register: just return a valid register */
99 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
100 const arch_register_req_t *req;
102 /* ask for the requirements */
103 req = arch_get_register_req(arch_env, irn, pos);
105 if (arch_register_req_is(req, limited)) {
106 /* in case of limited requirements: get the first allowed register */
107 unsigned idx = rbitset_next(req->limited, 0, 1);
108 reg = arch_register_for_index(req->cls, idx);
110 /* otherwise get first register in class */
111 reg = arch_register_for_index(req->cls, 0);
119 * Returns the register at out position pos.
121 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
124 const arch_register_t *reg = NULL;
126 /* 1st case: irn is not of mode_T, so it has only */
127 /* one OUT register -> good */
128 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
129 /* Proj with the corresponding projnum for the register */
131 if (get_irn_mode(irn) != mode_T) {
133 reg = arch_get_irn_register(arch_env, irn);
134 } else if (is_ia32_irn(irn)) {
135 reg = get_ia32_out_reg(irn, pos);
137 const ir_edge_t *edge;
139 foreach_out_edge(irn, edge) {
140 proj = get_edge_src_irn(edge);
141 assert(is_Proj(proj) && "non-Proj from mode_T node");
142 if (get_Proj_proj(proj) == pos) {
143 reg = arch_get_irn_register(arch_env, proj);
149 assert(reg && "no out register found");
154 * Add a number to a prefix. This number will not be used a second time.
156 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
158 static unsigned long id = 0;
159 snprintf(buf, buflen, "%s%lu", prefix, ++id);
163 /*************************************************************
165 * (_) | | / _| | | | |
166 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
167 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
168 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
169 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
172 *************************************************************/
174 static void emit_8bit_register(const arch_register_t *reg)
176 const char *reg_name = arch_register_get_name(reg);
179 be_emit_char(reg_name[1]);
183 static void emit_16bit_register(const arch_register_t *reg)
185 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
188 be_emit_string(reg_name);
191 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
193 const char *reg_name;
196 int size = get_mode_size_bits(mode);
198 emit_8bit_register(reg);
200 } else if(size == 16) {
201 emit_16bit_register(reg);
204 assert(mode_is_float(mode) || size == 32);
208 reg_name = arch_register_get_name(reg);
211 be_emit_string(reg_name);
214 void ia32_emit_source_register(const ir_node *node, int pos)
216 const arch_register_t *reg = get_in_reg(node, pos);
218 emit_register(reg, NULL);
221 static void emit_ia32_Immediate(const ir_node *node);
223 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
225 const arch_register_t *reg;
226 ir_node *in = get_irn_n(node, pos);
227 if(is_ia32_Immediate(in)) {
228 emit_ia32_Immediate(in);
232 reg = get_in_reg(node, pos);
233 emit_8bit_register(reg);
236 void ia32_emit_dest_register(const ir_node *node, int pos)
238 const arch_register_t *reg = get_out_reg(node, pos);
240 emit_register(reg, NULL);
243 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
245 const arch_register_t *reg = get_out_reg(node, pos);
247 emit_register(reg, mode_Bu);
250 void ia32_emit_x87_register(const ir_node *node, int pos)
252 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
256 be_emit_string(attr->x87[pos]->name);
259 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
261 if(mode_is_float(mode)) {
262 switch(get_mode_size_bits(mode)) {
263 case 32: be_emit_char('s'); return;
264 case 64: be_emit_char('l'); return;
266 case 96: be_emit_char('t'); return;
269 assert(mode_is_int(mode) || mode_is_reference(mode));
270 switch(get_mode_size_bits(mode)) {
271 case 64: be_emit_cstring("ll"); return;
272 /* gas docu says q is the suffix but gcc, objdump and icc use
274 case 32: be_emit_char('l'); return;
275 case 16: be_emit_char('w'); return;
276 case 8: be_emit_char('b'); return;
279 panic("Can't output mode_suffix for %+F\n", mode);
282 void ia32_emit_mode_suffix(const ir_node *node)
284 ir_mode *mode = get_ia32_ls_mode(node);
288 ia32_emit_mode_suffix_mode(mode);
291 void ia32_emit_x87_mode_suffix(const ir_node *node)
293 ir_mode *mode = get_ia32_ls_mode(node);
294 assert(mode != NULL);
295 /* we only need to emit the mode on address mode */
296 if(get_ia32_op_type(node) != ia32_Normal)
297 ia32_emit_mode_suffix_mode(mode);
300 static char get_xmm_mode_suffix(ir_mode *mode)
302 assert(mode_is_float(mode));
303 switch(get_mode_size_bits(mode)) {
314 void ia32_emit_xmm_mode_suffix(const ir_node *node)
316 ir_mode *mode = get_ia32_ls_mode(node);
317 assert(mode != NULL);
319 be_emit_char(get_xmm_mode_suffix(mode));
322 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
324 ir_mode *mode = get_ia32_ls_mode(node);
325 assert(mode != NULL);
326 be_emit_char(get_xmm_mode_suffix(mode));
329 void ia32_emit_extend_suffix(const ir_mode *mode)
331 if(get_mode_size_bits(mode) == 32)
333 if(mode_is_signed(mode)) {
340 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
342 ir_node *in = get_irn_n(node, pos);
343 if(is_ia32_Immediate(in)) {
344 emit_ia32_Immediate(in);
346 const ir_mode *mode = get_ia32_ls_mode(node);
347 const arch_register_t *reg = get_in_reg(node, pos);
348 emit_register(reg, mode);
353 * Emits registers and/or address mode of a binary operation.
355 void ia32_emit_binop(const ir_node *node) {
356 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
357 const ir_mode *mode = get_ia32_ls_mode(node);
358 const arch_register_t *reg_left;
360 switch(get_ia32_op_type(node)) {
362 reg_left = get_in_reg(node, n_ia32_binary_left);
363 if(is_ia32_Immediate(right_op)) {
364 emit_ia32_Immediate(right_op);
365 be_emit_cstring(", ");
366 emit_register(reg_left, mode);
369 const arch_register_t *reg_right
370 = get_in_reg(node, n_ia32_binary_right);
371 emit_register(reg_right, mode);
372 be_emit_cstring(", ");
373 emit_register(reg_left, mode);
377 if(is_ia32_Immediate(right_op)) {
378 emit_ia32_Immediate(right_op);
379 be_emit_cstring(", ");
382 reg_left = get_in_reg(node, n_ia32_binary_left);
384 be_emit_cstring(", ");
385 emit_register(reg_left, mode);
389 panic("DestMode can't be output by %%binop anymore");
392 assert(0 && "unsupported op type");
397 * Emits registers and/or address mode of a binary operation.
399 void ia32_emit_x87_binop(const ir_node *node) {
400 switch(get_ia32_op_type(node)) {
403 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
404 const arch_register_t *in1 = x87_attr->x87[0];
405 const arch_register_t *in2 = x87_attr->x87[1];
406 const arch_register_t *out = x87_attr->x87[2];
407 const arch_register_t *in;
409 in = out ? ((out == in2) ? in1 : in2) : in2;
410 out = out ? out : in1;
413 be_emit_string(arch_register_get_name(in));
414 be_emit_cstring(", %");
415 be_emit_string(arch_register_get_name(out));
423 assert(0 && "unsupported op type");
428 * Emits registers and/or address mode of a unary operation.
430 void ia32_emit_unop(const ir_node *node, int pos) {
433 switch(get_ia32_op_type(node)) {
435 op = get_irn_n(node, pos);
436 if (is_ia32_Immediate(op)) {
437 emit_ia32_Immediate(op);
439 ia32_emit_source_register(node, pos);
447 assert(0 && "unsupported op type");
451 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
455 set_entity_backend_marked(entity, 1);
456 id = get_entity_ld_ident(entity);
459 if (get_entity_owner(entity) == get_tls_type()) {
460 if (get_entity_visibility(entity) == visibility_external_allocated) {
461 be_emit_cstring("@INDNTPOFF");
463 be_emit_cstring("@NTPOFF");
467 if (!no_pic_adjust && do_pic) {
468 /* TODO: only do this when necessary */
470 be_emit_string(pic_base_label);
475 * Emits address mode.
477 void ia32_emit_am(const ir_node *node) {
478 ir_entity *ent = get_ia32_am_sc(node);
479 int offs = get_ia32_am_offs_int(node);
480 ir_node *base = get_irn_n(node, 0);
481 int has_base = !is_ia32_NoReg_GP(base);
482 ir_node *index = get_irn_n(node, 1);
483 int has_index = !is_ia32_NoReg_GP(index);
485 /* just to be sure... */
486 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
490 if (is_ia32_am_sc_sign(node))
492 ia32_emit_entity(ent, 0);
497 be_emit_irprintf("%+d", offs);
499 be_emit_irprintf("%d", offs);
503 if (has_base || has_index) {
508 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
509 emit_register(reg, NULL);
512 /* emit index + scale */
514 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
517 emit_register(reg, NULL);
519 scale = get_ia32_am_scale(node);
521 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
527 /* special case if nothing is set */
528 if(ent == NULL && offs == 0 && !has_base && !has_index) {
533 static void emit_ia32_IMul(const ir_node *node)
535 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
536 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
538 be_emit_cstring("\timul");
539 ia32_emit_mode_suffix(node);
542 ia32_emit_binop(node);
544 /* do we need the 3-address form? */
545 if(is_ia32_NoReg_GP(left) ||
546 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
547 be_emit_cstring(", ");
548 emit_register(out_reg, get_ia32_ls_mode(node));
550 be_emit_finish_line_gas(node);
553 /*************************************************
556 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
557 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
558 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
559 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
561 *************************************************/
564 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
567 * coding of conditions
569 struct cmp2conditon_t {
575 * positive conditions for signed compares
577 static const struct cmp2conditon_t cmp2condition_s[] = {
578 { NULL, pn_Cmp_False }, /* always false */
579 { "e", pn_Cmp_Eq }, /* == */
580 { "l", pn_Cmp_Lt }, /* < */
581 { "le", pn_Cmp_Le }, /* <= */
582 { "g", pn_Cmp_Gt }, /* > */
583 { "ge", pn_Cmp_Ge }, /* >= */
584 { "ne", pn_Cmp_Lg }, /* != */
585 { NULL, pn_Cmp_Leg}, /* always true */
589 * positive conditions for unsigned compares
591 static const struct cmp2conditon_t cmp2condition_u[] = {
592 { NULL, pn_Cmp_False }, /* always false */
593 { "e", pn_Cmp_Eq }, /* == */
594 { "b", pn_Cmp_Lt }, /* < */
595 { "be", pn_Cmp_Le }, /* <= */
596 { "a", pn_Cmp_Gt }, /* > */
597 { "ae", pn_Cmp_Ge }, /* >= */
598 { "ne", pn_Cmp_Lg }, /* != */
599 { NULL, pn_Cmp_Leg }, /* always true */
603 * walks up a tree of copies/perms/spills/reloads to find the original value
604 * that is moved around
606 static ir_node *find_original_value(ir_node *node)
608 inc_irg_visited(current_ir_graph);
610 mark_irn_visited(node);
611 if(be_is_Copy(node)) {
612 node = be_get_Copy_op(node);
613 } else if(be_is_CopyKeep(node)) {
614 node = be_get_CopyKeep_op(node);
615 } else if(is_Proj(node)) {
616 ir_node *pred = get_Proj_pred(node);
617 if(be_is_Perm(pred)) {
618 node = get_irn_n(pred, get_Proj_proj(node));
619 } else if(be_is_MemPerm(pred)) {
620 node = get_irn_n(pred, get_Proj_proj(node) + 1);
621 } else if(is_ia32_Load(pred)) {
622 node = get_irn_n(pred, n_ia32_Load_mem);
626 } else if(is_ia32_Store(node)) {
627 node = get_irn_n(node, n_ia32_Store_val);
628 } else if(is_Phi(node)) {
630 arity = get_irn_arity(node);
631 for(i = 0; i < arity; ++i) {
632 ir_node *in = get_irn_n(node, i);
645 static int determine_final_pnc(const ir_node *node, int flags_pos,
648 ir_node *flags = get_irn_n(node, flags_pos);
649 const ia32_attr_t *flags_attr;
650 flags = skip_Proj(flags);
652 if(is_ia32_Sahf(flags)) {
653 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
654 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
655 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
656 cmp = find_original_value(cmp);
657 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
658 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
661 flags_attr = get_ia32_attr_const(cmp);
662 if(flags_attr->data.ins_permuted)
663 pnc = get_mirrored_pnc(pnc);
664 pnc |= ia32_pn_Cmp_float;
665 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
666 || is_ia32_Fucompi(flags)) {
667 flags_attr = get_ia32_attr_const(flags);
669 if(flags_attr->data.ins_permuted)
670 pnc = get_mirrored_pnc(pnc);
671 pnc |= ia32_pn_Cmp_float;
674 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
675 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
677 flags_attr = get_ia32_attr_const(flags);
679 if(flags_attr->data.ins_permuted)
680 pnc = get_mirrored_pnc(pnc);
681 if(flags_attr->data.cmp_unsigned)
682 pnc |= ia32_pn_Cmp_unsigned;
688 static void ia32_emit_cmp_suffix(int pnc)
692 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
694 assert(cmp2condition_u[pnc].num == pnc);
695 str = cmp2condition_u[pnc].name;
698 assert(cmp2condition_s[pnc].num == pnc);
699 str = cmp2condition_s[pnc].name;
705 void ia32_emit_cmp_suffix_node(const ir_node *node,
708 const ia32_attr_t *attr = get_ia32_attr_const(node);
710 pn_Cmp pnc = get_ia32_condcode(node);
712 pnc = determine_final_pnc(node, flags_pos, pnc);
713 if(attr->data.ins_permuted) {
714 if(pnc & ia32_pn_Cmp_float) {
715 pnc = get_negated_pnc(pnc, mode_F);
717 pnc = get_negated_pnc(pnc, mode_Iu);
721 ia32_emit_cmp_suffix(pnc);
725 * Returns the target block for a control flow node.
727 static ir_node *get_cfop_target_block(const ir_node *irn) {
728 return get_irn_link(irn);
732 * Emits a block label for the given block.
734 static void ia32_emit_block_name(const ir_node *block)
736 if (has_Block_label(block)) {
737 be_emit_string(be_gas_label_prefix());
738 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
740 be_emit_cstring(BLOCK_PREFIX);
741 be_emit_irprintf("%d", get_irn_node_nr(block));
746 * Emits the target label for a control flow node.
748 static void ia32_emit_cfop_target(const ir_node *node)
750 ir_node *block = get_cfop_target_block(node);
752 ia32_emit_block_name(block);
755 /** Return the next block in Block schedule */
756 static ir_node *next_blk_sched(const ir_node *block)
758 return get_irn_link(block);
762 * Returns the Proj with projection number proj and NOT mode_M
764 static ir_node *get_proj(const ir_node *node, long proj) {
765 const ir_edge_t *edge;
768 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
770 foreach_out_edge(node, edge) {
771 src = get_edge_src_irn(edge);
773 assert(is_Proj(src) && "Proj expected");
774 if (get_irn_mode(src) == mode_M)
777 if (get_Proj_proj(src) == proj)
784 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
786 static void emit_ia32_Jcc(const ir_node *node)
788 int need_parity_label = 0;
789 const ir_node *proj_true;
790 const ir_node *proj_false;
791 const ir_node *block;
792 const ir_node *next_block;
793 pn_Cmp pnc = get_ia32_condcode(node);
795 pnc = determine_final_pnc(node, 0, pnc);
798 proj_true = get_proj(node, pn_ia32_Jcc_true);
799 assert(proj_true && "Jcc without true Proj");
801 proj_false = get_proj(node, pn_ia32_Jcc_false);
802 assert(proj_false && "Jcc without false Proj");
804 block = get_nodes_block(node);
805 next_block = next_blk_sched(block);
807 if (get_cfop_target_block(proj_true) == next_block) {
808 /* exchange both proj's so the second one can be omitted */
809 const ir_node *t = proj_true;
811 proj_true = proj_false;
813 if(pnc & ia32_pn_Cmp_float) {
814 pnc = get_negated_pnc(pnc, mode_F);
816 pnc = get_negated_pnc(pnc, mode_Iu);
820 if (pnc & ia32_pn_Cmp_float) {
821 /* Some floating point comparisons require a test of the parity flag,
822 * which indicates that the result is unordered */
825 be_emit_cstring("\tjp ");
826 ia32_emit_cfop_target(proj_true);
827 be_emit_finish_line_gas(proj_true);
832 be_emit_cstring("\tjnp ");
833 ia32_emit_cfop_target(proj_true);
834 be_emit_finish_line_gas(proj_true);
840 /* we need a local label if the false proj is a fallthrough
841 * as the falseblock might have no label emitted then */
842 if (get_cfop_target_block(proj_false) == next_block) {
843 need_parity_label = 1;
844 be_emit_cstring("\tjp 1f");
846 be_emit_cstring("\tjp ");
847 ia32_emit_cfop_target(proj_false);
849 be_emit_finish_line_gas(proj_false);
855 be_emit_cstring("\tjp ");
856 ia32_emit_cfop_target(proj_true);
857 be_emit_finish_line_gas(proj_true);
865 be_emit_cstring("\tj");
866 ia32_emit_cmp_suffix(pnc);
868 ia32_emit_cfop_target(proj_true);
869 be_emit_finish_line_gas(proj_true);
872 if(need_parity_label) {
873 be_emit_cstring("1:");
874 be_emit_write_line();
877 /* the second Proj might be a fallthrough */
878 if (get_cfop_target_block(proj_false) != next_block) {
879 be_emit_cstring("\tjmp ");
880 ia32_emit_cfop_target(proj_false);
881 be_emit_finish_line_gas(proj_false);
883 be_emit_cstring("\t/* fallthrough to ");
884 ia32_emit_cfop_target(proj_false);
885 be_emit_cstring(" */");
886 be_emit_finish_line_gas(proj_false);
890 static void emit_ia32_CMov(const ir_node *node)
892 const ia32_attr_t *attr = get_ia32_attr_const(node);
893 int ins_permuted = attr->data.ins_permuted;
894 const arch_register_t *out = arch_get_irn_register(arch_env, node);
895 pn_Cmp pnc = get_ia32_condcode(node);
896 const arch_register_t *in_true;
897 const arch_register_t *in_false;
899 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
901 in_true = arch_get_irn_register(arch_env,
902 get_irn_n(node, n_ia32_CMov_val_true));
903 in_false = arch_get_irn_register(arch_env,
904 get_irn_n(node, n_ia32_CMov_val_false));
906 /* should be same constraint fullfilled? */
907 if(out == in_false) {
908 /* yes -> nothing to do */
909 } else if(out == in_true) {
910 const arch_register_t *tmp;
912 assert(get_ia32_op_type(node) == ia32_Normal);
914 ins_permuted = !ins_permuted;
921 be_emit_cstring("\tmovl ");
922 emit_register(in_false, NULL);
923 be_emit_cstring(", ");
924 emit_register(out, NULL);
925 be_emit_finish_line_gas(node);
929 if(pnc & ia32_pn_Cmp_float) {
930 pnc = get_negated_pnc(pnc, mode_F);
932 pnc = get_negated_pnc(pnc, mode_Iu);
936 /* TODO: handling of Nans isn't correct yet */
938 be_emit_cstring("\tcmov");
939 ia32_emit_cmp_suffix(pnc);
941 if(get_ia32_op_type(node) == ia32_AddrModeS) {
944 emit_register(in_true, get_ia32_ls_mode(node));
946 be_emit_cstring(", ");
947 emit_register(out, get_ia32_ls_mode(node));
948 be_emit_finish_line_gas(node);
951 /*********************************************************
954 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
955 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
956 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
957 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
960 *********************************************************/
962 /* jump table entry (target and corresponding number) */
963 typedef struct _branch_t {
968 /* jump table for switch generation */
969 typedef struct _jmp_tbl_t {
970 ir_node *defProj; /**< default target */
971 long min_value; /**< smallest switch case */
972 long max_value; /**< largest switch case */
973 long num_branches; /**< number of jumps */
974 char *label; /**< label of the jump table */
975 branch_t *branches; /**< jump array */
979 * Compare two variables of type branch_t. Used to sort all switch cases
981 static int ia32_cmp_branch_t(const void *a, const void *b) {
982 branch_t *b1 = (branch_t *)a;
983 branch_t *b2 = (branch_t *)b;
985 if (b1->value <= b2->value)
992 * Emits code for a SwitchJmp (creates a jump table if
993 * possible otherwise a cmp-jmp cascade). Port from
996 static void emit_ia32_SwitchJmp(const ir_node *node)
998 unsigned long interval;
1004 const ir_edge_t *edge;
1006 /* fill the table structure */
1007 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1008 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1010 tbl.num_branches = get_irn_n_edges(node) - 1;
1011 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1012 tbl.min_value = INT_MAX;
1013 tbl.max_value = INT_MIN;
1015 default_pn = get_ia32_condcode(node);
1017 /* go over all proj's and collect them */
1018 foreach_out_edge(node, edge) {
1019 proj = get_edge_src_irn(edge);
1020 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1022 pnc = get_Proj_proj(proj);
1024 /* check for default proj */
1025 if (pnc == default_pn) {
1026 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1029 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1030 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1032 /* create branch entry */
1033 tbl.branches[i].target = proj;
1034 tbl.branches[i].value = pnc;
1039 assert(i == tbl.num_branches);
1041 /* sort the branches by their number */
1042 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1044 /* two-complement's magic make this work without overflow */
1045 interval = tbl.max_value - tbl.min_value;
1047 /* emit the table */
1048 be_emit_cstring("\tcmpl $");
1049 be_emit_irprintf("%u, ", interval);
1050 ia32_emit_source_register(node, 0);
1051 be_emit_finish_line_gas(node);
1053 be_emit_cstring("\tja ");
1054 ia32_emit_cfop_target(tbl.defProj);
1055 be_emit_finish_line_gas(node);
1057 if (tbl.num_branches > 1) {
1059 be_emit_cstring("\tjmp *");
1060 be_emit_string(tbl.label);
1061 be_emit_cstring("(,");
1062 ia32_emit_source_register(node, 0);
1063 be_emit_cstring(",4)");
1064 be_emit_finish_line_gas(node);
1066 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1067 be_emit_cstring("\t.align 4\n");
1068 be_emit_write_line();
1070 be_emit_string(tbl.label);
1071 be_emit_cstring(":\n");
1072 be_emit_write_line();
1074 be_emit_cstring(".long ");
1075 ia32_emit_cfop_target(tbl.branches[0].target);
1076 be_emit_finish_line_gas(NULL);
1078 last_value = tbl.branches[0].value;
1079 for (i = 1; i < tbl.num_branches; ++i) {
1080 while (++last_value < tbl.branches[i].value) {
1081 be_emit_cstring(".long ");
1082 ia32_emit_cfop_target(tbl.defProj);
1083 be_emit_finish_line_gas(NULL);
1085 be_emit_cstring(".long ");
1086 ia32_emit_cfop_target(tbl.branches[i].target);
1087 be_emit_finish_line_gas(NULL);
1089 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1091 /* one jump is enough */
1092 be_emit_cstring("\tjmp ");
1093 ia32_emit_cfop_target(tbl.branches[0].target);
1094 be_emit_finish_line_gas(node);
1104 * Emits code for a unconditional jump.
1106 static void emit_Jmp(const ir_node *node)
1108 ir_node *block, *next_block;
1110 /* for now, the code works for scheduled and non-schedules blocks */
1111 block = get_nodes_block(node);
1113 /* we have a block schedule */
1114 next_block = next_blk_sched(block);
1115 if (get_cfop_target_block(node) != next_block) {
1116 be_emit_cstring("\tjmp ");
1117 ia32_emit_cfop_target(node);
1119 be_emit_cstring("\t/* fallthrough to ");
1120 ia32_emit_cfop_target(node);
1121 be_emit_cstring(" */");
1123 be_emit_finish_line_gas(node);
1126 static void emit_ia32_Immediate(const ir_node *node)
1128 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1131 if(attr->symconst != NULL) {
1134 ia32_emit_entity(attr->symconst, 0);
1136 if(attr->symconst == NULL || attr->offset != 0) {
1137 if(attr->symconst != NULL) {
1138 be_emit_irprintf("%+d", attr->offset);
1140 be_emit_irprintf("0x%X", attr->offset);
1146 * Emit an inline assembler operand.
1148 * @param node the ia32_ASM node
1149 * @param s points to the operand (a %c)
1151 * @return pointer to the first char in s NOT in the current operand
1153 static const char* emit_asm_operand(const ir_node *node, const char *s)
1155 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1156 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1158 const arch_register_t *reg;
1159 const ia32_asm_reg_t *asm_regs = attr->register_map;
1160 const ia32_asm_reg_t *asm_reg;
1161 const char *reg_name;
1170 /* parse modifiers */
1173 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1197 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1198 "'%c' for asm op\n", node, c);
1204 sscanf(s, "%d%n", &num, &p);
1206 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1213 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1214 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1215 "input/output (%+F)\n", node);
1218 asm_reg = & asm_regs[num];
1219 assert(asm_reg->valid);
1222 if(asm_reg->use_input == 0) {
1223 reg = get_out_reg(node, asm_reg->inout_pos);
1225 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1227 /* might be an immediate value */
1228 if(is_ia32_Immediate(pred)) {
1229 emit_ia32_Immediate(pred);
1232 reg = get_in_reg(node, asm_reg->inout_pos);
1235 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1236 "(%+F)\n", num, node);
1240 if(asm_reg->memory) {
1249 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1252 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1255 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1258 panic("Invalid asm op modifier");
1260 be_emit_string(reg_name);
1262 emit_register(reg, asm_reg->mode);
1265 if(asm_reg->memory) {
1273 * Emits code for an ASM pseudo op.
1275 static void emit_ia32_Asm(const ir_node *node)
1277 const void *gen_attr = get_irn_generic_attr_const(node);
1278 const ia32_asm_attr_t *attr
1279 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1280 ident *asm_text = attr->asm_text;
1281 const char *s = get_id_str(asm_text);
1283 be_emit_cstring("# Begin ASM \t");
1284 be_emit_finish_line_gas(node);
1291 s = emit_asm_operand(node, s);
1300 be_emit_write_line();
1302 be_emit_cstring("# End ASM\n");
1303 be_emit_write_line();
1306 /**********************************
1309 * | | ___ _ __ _ _| |_) |
1310 * | | / _ \| '_ \| | | | _ <
1311 * | |___| (_) | |_) | |_| | |_) |
1312 * \_____\___/| .__/ \__, |____/
1315 **********************************/
1318 * Emit movsb/w instructions to make mov count divideable by 4
1320 static void emit_CopyB_prolog(unsigned size) {
1321 be_emit_cstring("\tcld");
1322 be_emit_finish_line_gas(NULL);
1326 be_emit_cstring("\tmovsb");
1327 be_emit_finish_line_gas(NULL);
1330 be_emit_cstring("\tmovsw");
1331 be_emit_finish_line_gas(NULL);
1334 be_emit_cstring("\tmovsb");
1335 be_emit_finish_line_gas(NULL);
1336 be_emit_cstring("\tmovsw");
1337 be_emit_finish_line_gas(NULL);
1343 * Emit rep movsd instruction for memcopy.
1345 static void emit_ia32_CopyB(const ir_node *node)
1347 unsigned size = get_ia32_copyb_size(node);
1349 emit_CopyB_prolog(size);
1351 be_emit_cstring("\trep movsd");
1352 be_emit_finish_line_gas(node);
1356 * Emits unrolled memcopy.
1358 static void emit_ia32_CopyB_i(const ir_node *node)
1360 unsigned size = get_ia32_copyb_size(node);
1362 emit_CopyB_prolog(size & 0x3);
1366 be_emit_cstring("\tmovsd");
1367 be_emit_finish_line_gas(NULL);
1373 /***************************
1377 * | | / _ \| '_ \ \ / /
1378 * | |___| (_) | | | \ V /
1379 * \_____\___/|_| |_|\_/
1381 ***************************/
1384 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1386 static void emit_ia32_Conv_with_FP(const ir_node *node)
1388 ir_mode *ls_mode = get_ia32_ls_mode(node);
1389 int ls_bits = get_mode_size_bits(ls_mode);
1391 be_emit_cstring("\tcvt");
1393 if(is_ia32_Conv_I2FP(node)) {
1395 be_emit_cstring("si2ss");
1397 be_emit_cstring("si2sd");
1399 } else if(is_ia32_Conv_FP2I(node)) {
1401 be_emit_cstring("ss2si");
1403 be_emit_cstring("sd2si");
1406 assert(is_ia32_Conv_FP2FP(node));
1408 be_emit_cstring("sd2ss");
1410 be_emit_cstring("ss2sd");
1415 switch(get_ia32_op_type(node)) {
1417 ia32_emit_source_register(node, n_ia32_unary_op);
1419 case ia32_AddrModeS:
1423 assert(0 && "unsupported op type for Conv");
1425 be_emit_cstring(", ");
1426 ia32_emit_dest_register(node, 0);
1427 be_emit_finish_line_gas(node);
1430 static void emit_ia32_Conv_I2FP(const ir_node *node)
1432 emit_ia32_Conv_with_FP(node);
1435 static void emit_ia32_Conv_FP2I(const ir_node *node)
1437 emit_ia32_Conv_with_FP(node);
1440 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1442 emit_ia32_Conv_with_FP(node);
1446 * Emits code for an Int conversion.
1448 static void emit_ia32_Conv_I2I(const ir_node *node)
1450 const char *sign_suffix;
1451 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1452 int smaller_bits = get_mode_size_bits(smaller_mode);
1454 const arch_register_t *in_reg, *out_reg;
1456 assert(!mode_is_float(smaller_mode));
1457 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1459 signed_mode = mode_is_signed(smaller_mode);
1460 if(smaller_bits == 32) {
1461 // this should not happen as it's no convert
1465 sign_suffix = signed_mode ? "s" : "z";
1468 out_reg = get_out_reg(node, 0);
1470 switch(get_ia32_op_type(node)) {
1472 in_reg = get_in_reg(node, n_ia32_unary_op);
1474 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1475 out_reg == &ia32_gp_regs[REG_EAX] &&
1479 /* argument and result are both in EAX and */
1480 /* signedness is ok: -> use the smaller cwtl opcode */
1481 be_emit_cstring("\tcwtl");
1483 be_emit_cstring("\tmov");
1484 be_emit_string(sign_suffix);
1485 ia32_emit_mode_suffix_mode(smaller_mode);
1486 be_emit_cstring("l ");
1487 emit_register(in_reg, smaller_mode);
1488 be_emit_cstring(", ");
1489 emit_register(out_reg, NULL);
1492 case ia32_AddrModeS: {
1493 be_emit_cstring("\tmov");
1494 be_emit_string(sign_suffix);
1495 ia32_emit_mode_suffix_mode(smaller_mode);
1496 be_emit_cstring("l ");
1498 be_emit_cstring(", ");
1499 emit_register(out_reg, NULL);
1503 assert(0 && "unsupported op type for Conv");
1505 be_emit_finish_line_gas(node);
1509 /*******************************************
1512 * | |__ ___ _ __ ___ __| | ___ ___
1513 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1514 * | |_) | __/ | | | (_) | (_| | __/\__ \
1515 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1517 *******************************************/
1520 * Emits a backend call
1522 static void emit_be_Call(const ir_node *node)
1524 ir_entity *ent = be_Call_get_entity(node);
1526 be_emit_cstring("\tcall ");
1528 ia32_emit_entity(ent, 1);
1530 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1532 emit_register(reg, NULL);
1534 be_emit_finish_line_gas(node);
1538 * Emits code to increase stack pointer.
1540 static void emit_be_IncSP(const ir_node *node)
1542 int offs = be_get_IncSP_offset(node);
1543 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1549 be_emit_cstring("\tsubl $");
1550 be_emit_irprintf("%u, ", offs);
1551 emit_register(reg, NULL);
1553 be_emit_cstring("\taddl $");
1554 be_emit_irprintf("%u, ", -offs);
1555 emit_register(reg, NULL);
1557 be_emit_finish_line_gas(node);
1561 * Emits code for Copy/CopyKeep.
1563 static void Copy_emitter(const ir_node *node, const ir_node *op)
1565 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1566 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1572 if(is_unknown_reg(in))
1574 /* copies of vf nodes aren't real... */
1575 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1578 mode = get_irn_mode(node);
1579 if (mode == mode_E) {
1580 be_emit_cstring("\tmovsd ");
1581 emit_register(in, NULL);
1582 be_emit_cstring(", ");
1583 emit_register(out, NULL);
1585 be_emit_cstring("\tmovl ");
1586 emit_register(in, NULL);
1587 be_emit_cstring(", ");
1588 emit_register(out, NULL);
1590 be_emit_finish_line_gas(node);
1593 static void emit_be_Copy(const ir_node *node)
1595 Copy_emitter(node, be_get_Copy_op(node));
1598 static void emit_be_CopyKeep(const ir_node *node)
1600 Copy_emitter(node, be_get_CopyKeep_op(node));
1604 * Emits code for exchange.
1606 static void emit_be_Perm(const ir_node *node)
1608 const arch_register_t *in0, *in1;
1609 const arch_register_class_t *cls0, *cls1;
1611 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1612 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1614 cls0 = arch_register_get_class(in0);
1615 cls1 = arch_register_get_class(in1);
1617 assert(cls0 == cls1 && "Register class mismatch at Perm");
1619 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1620 be_emit_cstring("\txchg ");
1621 emit_register(in1, NULL);
1622 be_emit_cstring(", ");
1623 emit_register(in0, NULL);
1624 be_emit_finish_line_gas(node);
1625 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1626 be_emit_cstring("\txorpd ");
1627 emit_register(in1, NULL);
1628 be_emit_cstring(", ");
1629 emit_register(in0, NULL);
1630 be_emit_finish_line_gas(NULL);
1632 be_emit_cstring("\txorpd ");
1633 emit_register(in0, NULL);
1634 be_emit_cstring(", ");
1635 emit_register(in1, NULL);
1636 be_emit_finish_line_gas(NULL);
1638 be_emit_cstring("\txorpd ");
1639 emit_register(in1, NULL);
1640 be_emit_cstring(", ");
1641 emit_register(in0, NULL);
1642 be_emit_finish_line_gas(node);
1643 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1645 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1648 panic("unexpected register class in be_Perm (%+F)\n", node);
1653 * Emits code for Constant loading.
1655 static void emit_ia32_Const(const ir_node *node)
1657 be_emit_cstring("\tmovl ");
1658 emit_ia32_Immediate(node);
1659 be_emit_cstring(", ");
1660 ia32_emit_dest_register(node, 0);
1662 be_emit_finish_line_gas(node);
1666 * Emits code to load the TLS base
1668 static void emit_ia32_LdTls(const ir_node *node)
1670 be_emit_cstring("\tmovl %gs:0, ");
1671 ia32_emit_dest_register(node, 0);
1672 be_emit_finish_line_gas(node);
1675 /* helper function for emit_ia32_Minus64Bit */
1676 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1678 be_emit_cstring("\tmovl ");
1679 emit_register(src, NULL);
1680 be_emit_cstring(", ");
1681 emit_register(dst, NULL);
1682 be_emit_finish_line_gas(node);
1685 /* helper function for emit_ia32_Minus64Bit */
1686 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1688 be_emit_cstring("\tnegl ");
1689 emit_register(reg, NULL);
1690 be_emit_finish_line_gas(node);
1693 /* helper function for emit_ia32_Minus64Bit */
1694 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1696 be_emit_cstring("\tsbbl $0, ");
1697 emit_register(reg, NULL);
1698 be_emit_finish_line_gas(node);
1701 /* helper function for emit_ia32_Minus64Bit */
1702 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1704 be_emit_cstring("\tsbbl ");
1705 emit_register(src, NULL);
1706 be_emit_cstring(", ");
1707 emit_register(dst, NULL);
1708 be_emit_finish_line_gas(node);
1711 /* helper function for emit_ia32_Minus64Bit */
1712 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1714 be_emit_cstring("\txchgl ");
1715 emit_register(src, NULL);
1716 be_emit_cstring(", ");
1717 emit_register(dst, NULL);
1718 be_emit_finish_line_gas(node);
1721 /* helper function for emit_ia32_Minus64Bit */
1722 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1724 be_emit_cstring("\txorl ");
1725 emit_register(reg, NULL);
1726 be_emit_cstring(", ");
1727 emit_register(reg, NULL);
1728 be_emit_finish_line_gas(node);
1731 static void emit_ia32_Minus64Bit(const ir_node *node)
1733 const arch_register_t *in_lo = get_in_reg(node, 0);
1734 const arch_register_t *in_hi = get_in_reg(node, 1);
1735 const arch_register_t *out_lo = get_out_reg(node, 0);
1736 const arch_register_t *out_hi = get_out_reg(node, 1);
1738 if (out_lo == in_lo) {
1739 if (out_hi != in_hi) {
1740 /* a -> a, b -> d */
1743 /* a -> a, b -> b */
1746 } else if (out_lo == in_hi) {
1747 if (out_hi == in_lo) {
1748 /* a -> b, b -> a */
1749 emit_xchg(node, in_lo, in_hi);
1752 /* a -> b, b -> d */
1753 emit_mov(node, in_hi, out_hi);
1754 emit_mov(node, in_lo, out_lo);
1758 if (out_hi == in_lo) {
1759 /* a -> c, b -> a */
1760 emit_mov(node, in_lo, out_lo);
1762 } else if (out_hi == in_hi) {
1763 /* a -> c, b -> b */
1764 emit_mov(node, in_lo, out_lo);
1767 /* a -> c, b -> d */
1768 emit_mov(node, in_lo, out_lo);
1774 emit_neg( node, out_hi);
1775 emit_neg( node, out_lo);
1776 emit_sbb0(node, out_hi);
1780 emit_zero(node, out_hi);
1781 emit_neg( node, out_lo);
1782 emit_sbb( node, in_hi, out_hi);
1785 static void emit_ia32_GetEIP(const ir_node *node)
1787 be_emit_cstring("\tcall ");
1788 be_emit_string(pic_base_label);
1789 be_emit_finish_line_gas(node);
1791 be_emit_string(pic_base_label);
1792 be_emit_cstring(":\n");
1793 be_emit_write_line();
1795 be_emit_cstring("\tpopl ");
1796 ia32_emit_dest_register(node, 0);
1798 be_emit_write_line();
1801 static void emit_be_Return(const ir_node *node)
1804 be_emit_cstring("\tret");
1806 pop = be_Return_get_pop(node);
1807 if (pop > 0 || be_Return_get_emit_pop(node)) {
1808 be_emit_irprintf(" $%d", pop);
1810 be_emit_finish_line_gas(node);
1813 static void emit_Nothing(const ir_node *node)
1819 /***********************************************************************************
1822 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1823 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1824 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1825 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1827 ***********************************************************************************/
1830 * Enters the emitter functions for handled nodes into the generic
1831 * pointer of an opcode.
1833 static void ia32_register_emitters(void) {
1835 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1836 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1837 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1838 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1839 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1840 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1842 /* first clear the generic function pointer for all ops */
1843 clear_irp_opcodes_generic_func();
1845 /* register all emitter functions defined in spec */
1846 ia32_register_spec_emitters();
1848 /* other ia32 emitter functions */
1852 IA32_EMIT(SwitchJmp);
1855 IA32_EMIT(Conv_I2FP);
1856 IA32_EMIT(Conv_FP2I);
1857 IA32_EMIT(Conv_FP2FP);
1858 IA32_EMIT(Conv_I2I);
1859 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1862 IA32_EMIT(Minus64Bit);
1866 /* benode emitter */
1891 typedef void (*emit_func_ptr) (const ir_node *);
1894 * Emits code for a node.
1896 static void ia32_emit_node(const ir_node *node)
1898 ir_op *op = get_irn_op(node);
1900 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1902 if (op->ops.generic) {
1903 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1905 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1910 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1916 * Emits gas alignment directives
1918 static void ia32_emit_alignment(unsigned align, unsigned skip)
1920 be_emit_cstring("\t.p2align ");
1921 be_emit_irprintf("%u,,%u\n", align, skip);
1922 be_emit_write_line();
1926 * Emits gas alignment directives for Labels depended on cpu architecture.
1928 static void ia32_emit_align_label(void)
1930 unsigned align = ia32_cg_config.label_alignment;
1931 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1932 ia32_emit_alignment(align, maximum_skip);
1936 * Test whether a block should be aligned.
1937 * For cpus in the P4/Athlon class it is useful to align jump labels to
1938 * 16 bytes. However we should only do that if the alignment nops before the
1939 * label aren't executed more often than we have jumps to the label.
1941 static int should_align_block(ir_node *block, ir_node *prev)
1943 static const double DELTA = .0001;
1944 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1946 double prev_freq = 0; /**< execfreq of the fallthrough block */
1947 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1950 if(exec_freq == NULL)
1952 if(ia32_cg_config.label_alignment_factor <= 0)
1955 block_freq = get_block_execfreq(exec_freq, block);
1956 if(block_freq < DELTA)
1959 n_cfgpreds = get_Block_n_cfgpreds(block);
1960 for(i = 0; i < n_cfgpreds; ++i) {
1961 ir_node *pred = get_Block_cfgpred_block(block, i);
1962 double pred_freq = get_block_execfreq(exec_freq, pred);
1965 prev_freq += pred_freq;
1967 jmp_freq += pred_freq;
1971 if(prev_freq < DELTA && !(jmp_freq < DELTA))
1974 jmp_freq /= prev_freq;
1976 return jmp_freq > ia32_cg_config.label_alignment_factor;
1980 * Return non-zero, if a instruction in a fall-through.
1982 static int is_fallthrough(ir_node *cfgpred)
1986 if(!is_Proj(cfgpred))
1988 pred = get_Proj_pred(cfgpred);
1989 if(is_ia32_SwitchJmp(pred))
1996 * Emit the block header for a block.
1998 * @param block the block
1999 * @param prev_block the previous block
2001 static void ia32_emit_block_header(ir_node *block, ir_node *prev_block)
2003 ir_graph *irg = current_ir_graph;
2007 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2009 if(block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2012 n_cfgpreds = get_Block_n_cfgpreds(block);
2014 if(n_cfgpreds == 0) {
2016 } else if(n_cfgpreds == 1) {
2017 ir_node *cfgpred = get_Block_cfgpred(block, 0);
2018 if(get_nodes_block(cfgpred) == prev_block && is_fallthrough(cfgpred)) {
2023 if (ia32_cg_config.label_alignment > 0) {
2024 /* align the current block if:
2025 * a) if should be aligned due to its execution frequency
2026 * b) there is no fall-through here
2028 if (should_align_block(block, prev_block)) {
2029 ia32_emit_align_label();
2031 /* if the predecessor block has no fall-through,
2032 we can always align the label. */
2034 ir_node *check_node = NULL;
2036 for (i = n_cfgpreds - 1; i >= 0; --i) {
2037 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2039 if (get_nodes_block(skip_Proj(cfg_pred)) == prev_block) {
2040 check_node = cfg_pred;
2044 if (check_node == NULL || !is_fallthrough(check_node))
2045 ia32_emit_align_label();
2050 ia32_emit_block_name(block);
2053 be_emit_pad_comment();
2054 be_emit_cstring(" /* ");
2056 be_emit_cstring("\t/* ");
2057 ia32_emit_block_name(block);
2058 be_emit_cstring(": ");
2061 be_emit_cstring("preds:");
2063 /* emit list of pred blocks in comment */
2064 arity = get_irn_arity(block);
2065 for (i = 0; i < arity; ++i) {
2066 ir_node *predblock = get_Block_cfgpred_block(block, i);
2067 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2069 if (exec_freq != NULL) {
2070 be_emit_irprintf(" freq: %f",
2071 get_block_execfreq(exec_freq, block));
2073 be_emit_cstring(" */\n");
2074 be_emit_write_line();
2078 * Walks over the nodes in a block connected by scheduling edges
2079 * and emits code for each node.
2081 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2083 const ir_node *node;
2085 ia32_emit_block_header(block, last_block);
2087 /* emit the contents of the block */
2088 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2089 sched_foreach(block, node) {
2090 ia32_emit_node(node);
2096 * Sets labels for control flow nodes (jump target)
2098 static void ia32_gen_labels(ir_node *block, void *data)
2101 int n = get_Block_n_cfgpreds(block);
2104 for (n--; n >= 0; n--) {
2105 pred = get_Block_cfgpred(block, n);
2106 set_irn_link(pred, block);
2111 * Emit an exception label if the current instruction can fail.
2113 void ia32_emit_exc_label(const ir_node *node)
2115 if (get_ia32_exc_label(node)) {
2116 be_emit_irprintf(".EXL%u\n", 0);
2117 be_emit_write_line();
2122 * Main driver. Emits the code for one routine.
2124 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2127 ir_node *last_block = NULL;
2128 ir_entity *entity = get_irg_entity(irg);
2132 isa = (const ia32_isa_t*) cg->arch_env;
2133 arch_env = cg->arch_env;
2134 do_pic = cg->birg->main_env->options->pic;
2136 ia32_register_emitters();
2138 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2140 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2141 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2143 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2145 n = ARR_LEN(cg->blk_sched);
2146 for (i = 0; i < n;) {
2149 block = cg->blk_sched[i];
2151 next_bl = i < n ? cg->blk_sched[i] : NULL;
2153 /* set here the link. the emitter expects to find the next block here */
2154 set_irn_link(block, next_bl);
2155 ia32_gen_block(block, last_block);
2159 be_gas_emit_function_epilog(entity);
2160 be_dbg_method_end();
2162 be_emit_write_line();
2165 void ia32_init_emitter(void)
2167 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");