2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "ia32_emitter.h"
28 #include "gen_ia32_emitter.h"
29 #include "gen_ia32_regalloc_if.h"
30 #include "ia32_nodes_attr.h"
31 #include "ia32_new_nodes.h"
32 #include "ia32_map_regs.h"
33 #include "bearch_ia32_t.h"
35 #define BLOCK_PREFIX(x) ".L" x
37 #define SNPRINTF_BUF_LEN 128
39 /* global arch_env for lc_printf functions */
40 static const arch_env_t *arch_env = NULL;
42 /** by default, we generate assembler code for the Linux gas */
43 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
46 * Switch to a new section
48 void ia32_switch_section(FILE *F, section_t sec) {
49 static section_t curr_sec = NO_SECTION;
50 static const char *text[ASM_MAX][SECTION_MAX] = {
56 ".section\t.tbss,\"awT\",@nobits",
57 ".section\t.ctors,\"aw\",@progbits"
62 ".section .rdata,\"dr\"",
64 ".section\t.tbss,\"awT\",@nobits",
65 ".section\t.ctors,\"aw\",@progbits"
84 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
92 static void ia32_dump_function_object(FILE *F, const char *name)
94 switch (asm_flavour) {
96 fprintf(F, "\t.type\t%s, @function\n", name);
99 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
106 static void ia32_dump_function_size(FILE *F, const char *name)
108 switch (asm_flavour) {
110 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
117 /*************************************************************
119 * (_) | | / _| | | | |
120 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
121 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
122 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
123 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
126 *************************************************************/
128 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
130 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
131 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
132 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
136 * returns true if a node has x87 registers
138 static INLINE int has_x87_register(const ir_node *n) {
139 return is_irn_machine_user(n, 0);
142 /* We always pass the ir_node which is a pointer. */
143 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
144 return lc_arg_type_ptr;
149 * Returns the register at in position pos.
151 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
153 const arch_register_t *reg = NULL;
155 assert(get_irn_arity(irn) > pos && "Invalid IN position");
157 /* The out register of the operator at position pos is the
158 in register we need. */
159 op = get_irn_n(irn, pos);
161 reg = arch_get_irn_register(arch_env, op);
163 assert(reg && "no in register found");
165 /* in case of unknown: just return a register */
166 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
167 reg = &ia32_gp_regs[REG_EAX];
168 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
169 reg = &ia32_xmm_regs[REG_XMM0];
170 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
171 reg = &ia32_vfp_regs[REG_VF0];
177 * Returns the register at out position pos.
179 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
181 const arch_register_t *reg = NULL;
183 /* 1st case: irn is not of mode_T, so it has only */
184 /* one OUT register -> good */
185 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
186 /* Proj with the corresponding projnum for the register */
188 if (get_irn_mode(irn) != mode_T) {
189 reg = arch_get_irn_register(arch_env, irn);
191 else if (is_ia32_irn(irn)) {
192 reg = get_ia32_out_reg(irn, pos);
195 const ir_edge_t *edge;
197 foreach_out_edge(irn, edge) {
198 proj = get_edge_src_irn(edge);
199 assert(is_Proj(proj) && "non-Proj from mode_T node");
200 if (get_Proj_proj(proj) == pos) {
201 reg = arch_get_irn_register(arch_env, proj);
207 assert(reg && "no out register found");
217 * Returns the name of the in register at position pos.
219 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
220 const arch_register_t *reg;
222 if (in_out == IN_REG) {
223 reg = get_in_reg(irn, pos);
225 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
226 /* FIXME: works for binop only */
227 assert(2 <= pos && pos <= 3);
228 reg = get_ia32_attr(irn)->x87[pos - 2];
232 /* destination address mode nodes don't have outputs */
233 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
237 reg = get_out_reg(irn, pos);
238 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
239 reg = get_ia32_attr(irn)->x87[pos + 2];
241 return arch_register_get_name(reg);
245 * Get the register name for a node.
247 static int ia32_get_reg_name(lc_appendable_t *app,
248 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
251 ir_node *irn = arg->v_ptr;
252 int nr = occ->width - 1;
255 return lc_appendable_snadd(app, "(null)", 6);
257 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
259 /* append the stupid % to register names */
260 lc_appendable_chadd(app, '%');
261 return lc_appendable_snadd(app, buf, strlen(buf));
265 * Get the x87 register name for a node.
267 static int ia32_get_x87_name(lc_appendable_t *app,
268 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
271 ir_node *irn = arg->v_ptr;
272 int nr = occ->width - 1;
276 return lc_appendable_snadd(app, "(null)", 6);
278 attr = get_ia32_attr(irn);
279 buf = attr->x87[nr]->name;
280 lc_appendable_chadd(app, '%');
281 return lc_appendable_snadd(app, buf, strlen(buf));
285 * Returns the tarval, offset or scale of an ia32 as a string.
287 static int ia32_const_to_str(lc_appendable_t *app,
288 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
291 ir_node *irn = arg->v_ptr;
294 return lc_arg_append(app, occ, "(null)", 6);
296 if (occ->conversion == 'C') {
297 buf = get_ia32_cnst(irn);
300 buf = get_ia32_am_offs(irn);
303 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
307 * Determines the SSE suffix depending on the mode.
309 static int ia32_get_mode_suffix(lc_appendable_t *app,
310 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
312 ir_node *irn = arg->v_ptr;
313 ir_mode *mode = get_irn_mode(irn);
315 if (mode == mode_T) {
316 mode = get_ia32_res_mode(irn);
318 mode = get_ia32_ls_mode(irn);
322 return lc_arg_append(app, occ, "(null)", 6);
324 if (mode_is_float(mode)) {
325 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
328 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
333 * Return the ia32 printf arg environment.
334 * We use the firm environment with some additional handlers.
336 const lc_arg_env_t *ia32_get_arg_env(void) {
337 static lc_arg_env_t *env = NULL;
339 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
340 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
341 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
342 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
345 /* extend the firm printer */
346 env = firm_get_arg_env();
348 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
349 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
350 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
351 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
352 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
353 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
359 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
360 switch(get_mode_size_bits(mode)) {
362 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
364 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
366 return (char *)arch_register_get_name(reg);
371 * Emits registers and/or address mode of a binary operation.
373 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
374 static char *buf = NULL;
376 /* verify that this function is never called on non-AM supporting operations */
377 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
379 #define PRODUCES_RESULT(n) \
380 (!(is_ia32_St(n) || \
381 is_ia32_Store8Bit(n) || \
382 is_ia32_CondJmp(n) || \
383 is_ia32_xCondJmp(n) || \
384 is_ia32_CmpSet(n) || \
385 is_ia32_xCmpSet(n) || \
386 is_ia32_SwitchJmp(n)))
389 buf = xcalloc(1, SNPRINTF_BUF_LEN);
392 memset(buf, 0, SNPRINTF_BUF_LEN);
395 switch(get_ia32_op_type(n)) {
397 if (is_ia32_ImmConst(n)) {
398 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
400 else if (is_ia32_ImmSymConst(n)) {
401 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
404 const arch_register_t *in1 = get_in_reg(n, 2);
405 const arch_register_t *in2 = get_in_reg(n, 3);
406 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
407 const arch_register_t *in;
410 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
411 out = out ? out : in1;
412 in_name = arch_register_get_name(in);
414 if (is_ia32_emit_cl(n)) {
415 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
419 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
423 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
424 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
425 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
428 if (PRODUCES_RESULT(n)) {
429 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
432 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
437 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
438 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
439 ia32_emit_am(n, env),
440 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
441 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
444 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
445 ir_mode *mode = get_ia32_res_mode(n);
448 mode = mode ? mode : get_ia32_ls_mode(n);
449 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
451 if (is_ia32_emit_cl(n)) {
452 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
456 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
460 assert(0 && "unsupported op type");
463 #undef PRODUCES_RESULT
469 * Returns the xxx PTR string for a given mode
471 * @param mode the mode
472 * @param x87_insn if non-zero returns the string for a x87 instruction
473 * else for a SSE instruction
475 static const char *pointer_size(ir_mode *mode, int x87_insn)
478 switch (get_mode_size_bits(mode)) {
479 case 8: return "BYTE PTR";
480 case 16: return "WORD PTR";
481 case 32: return "DWORD PTR";
487 case 96: return "XWORD PTR";
488 default: return NULL;
495 * Emits registers and/or address mode of a binary operation.
497 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
498 static char *buf = NULL;
500 /* verify that this function is never called on non-AM supporting operations */
501 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
504 buf = xcalloc(1, SNPRINTF_BUF_LEN);
507 memset(buf, 0, SNPRINTF_BUF_LEN);
510 switch(get_ia32_op_type(n)) {
512 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
513 ir_mode *mode = get_ia32_ls_mode(n);
514 const char *p = pointer_size(mode, 1);
515 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
518 ia32_attr_t *attr = get_ia32_attr(n);
519 const arch_register_t *in1 = attr->x87[0];
520 const arch_register_t *in2 = attr->x87[1];
521 const arch_register_t *out = attr->x87[2];
522 const arch_register_t *in;
525 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
526 out = out ? out : in1;
527 in_name = arch_register_get_name(in);
529 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
534 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
537 assert(0 && "unsupported op type");
544 * Emits registers and/or address mode of a unary operation.
546 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
547 static char *buf = NULL;
550 buf = xcalloc(1, SNPRINTF_BUF_LEN);
553 memset(buf, 0, SNPRINTF_BUF_LEN);
556 switch(get_ia32_op_type(n)) {
558 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
559 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
562 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
563 /* MulS and Mulh implicitly multiply by EAX */
564 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
567 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
571 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
575 Mulh is emitted via emit_unop
576 imul [MEM] means EDX:EAX <- EAX * [MEM]
578 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
579 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
582 assert(0 && "unsupported op type");
589 * Emits address mode.
591 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
592 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
596 static struct obstack *obst = NULL;
597 ir_mode *mode = get_ia32_ls_mode(n);
599 if (! is_ia32_Lea(n))
600 assert(mode && "AM node must have ls_mode attribute set.");
603 obst = xcalloc(1, sizeof(*obst));
606 obstack_free(obst, NULL);
609 /* obstack_free with NULL results in an uninitialized obstack */
612 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
614 obstack_printf(obst, "%s ", p);
616 /* emit address mode symconst */
617 if (get_ia32_am_sc(n)) {
618 if (is_ia32_am_sc_sign(n))
619 obstack_printf(obst, "-");
620 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
623 if (am_flav & ia32_B) {
624 obstack_printf(obst, "[");
625 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
629 if (am_flav & ia32_I) {
631 obstack_printf(obst, "+");
634 obstack_printf(obst, "[");
637 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
639 if (am_flav & ia32_S) {
640 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
646 if (am_flav & ia32_O) {
647 s = get_ia32_am_offs(n);
650 /* omit explicit + if there was no base or index */
652 obstack_printf(obst, "[");
657 obstack_printf(obst, s);
663 obstack_printf(obst, "] ");
665 obstack_1grow(obst, '\0');
666 s = obstack_finish(obst);
674 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
676 static char buf[SNPRINTF_BUF_LEN];
677 ir_mode *mode = get_ia32_ls_mode(irn);
678 const char *adr = get_ia32_cnst(irn);
679 const char *pref = pointer_size(mode, has_x87_register(irn));
681 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
686 * Formated print of commands and comments.
688 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
690 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
693 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
695 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
701 * Add a number to a prefix. This number will not be used a second time.
703 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
704 static unsigned long id = 0;
705 snprintf(buf, buflen, "%s%lu", prefix, ++id);
711 /*************************************************
714 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
715 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
716 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
717 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
719 *************************************************/
722 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
725 * coding of conditions
727 struct cmp2conditon_t {
733 * positive conditions for signed compares
735 static const struct cmp2conditon_t cmp2condition_s[] = {
736 { NULL, pn_Cmp_False }, /* always false */
737 { "e", pn_Cmp_Eq }, /* == */
738 { "l", pn_Cmp_Lt }, /* < */
739 { "le", pn_Cmp_Le }, /* <= */
740 { "g", pn_Cmp_Gt }, /* > */
741 { "ge", pn_Cmp_Ge }, /* >= */
742 { "ne", pn_Cmp_Lg }, /* != */
743 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
744 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
745 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
746 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
747 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
748 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
749 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
750 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
751 { NULL, pn_Cmp_True }, /* always true */
755 * positive conditions for unsigned compares
757 static const struct cmp2conditon_t cmp2condition_u[] = {
758 { NULL, pn_Cmp_False }, /* always false */
759 { "e", pn_Cmp_Eq }, /* == */
760 { "b", pn_Cmp_Lt }, /* < */
761 { "be", pn_Cmp_Le }, /* <= */
762 { "a", pn_Cmp_Gt }, /* > */
763 { "ae", pn_Cmp_Ge }, /* >= */
764 { "ne", pn_Cmp_Lg }, /* != */
765 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
766 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
767 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
768 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
769 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
770 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
771 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
772 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
773 { NULL, pn_Cmp_True }, /* always true */
777 * returns the condition code
779 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
781 assert(cmp2condition_s[cmp_code].num == cmp_code);
782 assert(cmp2condition_u[cmp_code].num == cmp_code);
784 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
788 * Returns the target block for a control flow node.
790 static ir_node *get_cfop_target_block(const ir_node *irn) {
791 return get_irn_link(irn);
795 * Returns the target label for a control flow node.
797 static char *get_cfop_target(const ir_node *irn, char *buf) {
798 ir_node *bl = get_cfop_target_block(irn);
800 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
804 /** Return the next block in Block schedule */
805 static ir_node *next_blk_sched(const ir_node *block) {
806 return get_irn_link(block);
810 * Returns the Proj with projection number proj and NOT mode_M
812 static ir_node *get_proj(const ir_node *irn, long proj) {
813 const ir_edge_t *edge;
816 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
818 foreach_out_edge(irn, edge) {
819 src = get_edge_src_irn(edge);
821 assert(is_Proj(src) && "Proj expected");
822 if (get_irn_mode(src) == mode_M)
825 if (get_Proj_proj(src) == proj)
832 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
834 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
835 const ir_node *proj_true;
836 const ir_node *proj_false;
837 const ir_node *block;
838 const ir_node *next_block;
839 char buf[SNPRINTF_BUF_LEN];
840 char cmd_buf[SNPRINTF_BUF_LEN];
841 char cmnt_buf[SNPRINTF_BUF_LEN];
846 /* get both Proj's */
847 proj_true = get_proj(irn, pn_Cond_true);
848 assert(proj_true && "CondJmp without true Proj");
850 proj_false = get_proj(irn, pn_Cond_false);
851 assert(proj_false && "CondJmp without false Proj");
853 pnc = get_ia32_pncode(irn);
855 /* for now, the code works for scheduled and non-schedules blocks */
856 block = get_nodes_block(irn);
858 /* we have a block schedule */
859 next_block = next_blk_sched(block);
861 if (get_cfop_target_block(proj_true) == next_block) {
862 /* exchange both proj's so the second one can be omitted */
863 const ir_node *t = proj_true;
864 proj_true = proj_false;
868 pnc = get_negated_pnc(pnc, mode);
871 /* the first Proj must always be created */
872 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
873 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
874 get_cmp_suffix(pnc, is_unsigned),
875 get_cfop_target(proj_true, buf));
876 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
877 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
880 /* the second Proj might be a fallthrough */
881 if (get_cfop_target_block(proj_false) != next_block) {
882 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
883 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
887 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
893 * Emits code for conditional jump.
895 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
897 char cmd_buf[SNPRINTF_BUF_LEN];
898 char cmnt_buf[SNPRINTF_BUF_LEN];
900 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
901 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
903 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
907 * Emits code for conditional jump with two variables.
909 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
910 CondJmp_emitter(irn, env);
914 * Emits code for conditional test and jump.
916 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
918 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
921 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
922 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
923 char cmd_buf[SNPRINTF_BUF_LEN];
924 char cmnt_buf[SNPRINTF_BUF_LEN];
927 op2 = arch_register_get_name(get_in_reg(irn, 1));
929 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
930 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
933 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
939 * Emits code for conditional test and jump with two variables.
941 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
942 TestJmp_emitter(irn, env);
945 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
947 char cmd_buf[SNPRINTF_BUF_LEN];
948 char cmnt_buf[SNPRINTF_BUF_LEN];
950 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
951 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
953 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
956 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
958 char cmd_buf[SNPRINTF_BUF_LEN];
959 char cmnt_buf[SNPRINTF_BUF_LEN];
961 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
962 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
964 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
968 * Emits code for conditional SSE floating point jump with two variables.
970 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
972 char cmd_buf[SNPRINTF_BUF_LEN];
973 char cmnt_buf[SNPRINTF_BUF_LEN];
975 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
976 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
978 finish_CondJmp(F, irn, mode_F);
983 * Emits code for conditional x87 floating point jump with two variables.
985 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
987 char cmd_buf[SNPRINTF_BUF_LEN];
988 char cmnt_buf[SNPRINTF_BUF_LEN];
989 ia32_attr_t *attr = get_ia32_attr(irn);
990 const char *reg = attr->x87[1]->name;
991 const char *instr = "fcom";
994 switch (get_ia32_irn_opcode(irn)) {
995 case iro_ia32_fcomrJmp:
997 case iro_ia32_fcomJmp:
1001 case iro_ia32_fcomrpJmp:
1003 case iro_ia32_fcompJmp:
1006 case iro_ia32_fcomrppJmp:
1008 case iro_ia32_fcomppJmp:
1015 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1017 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1018 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1020 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1021 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1023 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1024 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1027 /* the compare flags must be evaluated using carry , ie unsigned */
1028 finish_CondJmp(F, irn, mode_Iu);
1031 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1033 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1034 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1035 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1036 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1037 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1038 int idx_left = 2 - is_PsiCondCMov;
1039 int idx_right = 3 - is_PsiCondCMov;
1041 char cmd_buf[SNPRINTF_BUF_LEN];
1042 char cmnt_buf[SNPRINTF_BUF_LEN];
1043 const arch_register_t *in1, *in2, *out;
1045 out = arch_get_irn_register(env->arch_env, irn);
1046 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1047 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1049 /* we have to emit the cmp first, because the destination register */
1050 /* could be one of the compare registers */
1051 if (is_ia32_CmpCMov(irn)) {
1052 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1054 else if (is_ia32_xCmpCMov(irn)) {
1055 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1057 else if (is_PsiCondCMov) {
1058 /* omit compare because flags are already set by And/Or */
1059 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1062 assert(0 && "unsupported CMov");
1064 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1067 if (REGS_ARE_EQUAL(out, in2)) {
1068 /* best case: default in == out -> do nothing */
1070 else if (REGS_ARE_EQUAL(out, in1)) {
1071 /* true in == out -> need complement compare and exchange true and default in */
1072 ir_node *t = get_irn_n(irn, idx_left);
1073 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1074 set_irn_n(irn, idx_right, t);
1076 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1080 /* out is different from in: need copy default -> out */
1082 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1084 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1086 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1091 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1093 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1095 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1099 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1100 CMov_emitter(irn, env);
1103 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1104 CMov_emitter(irn, env);
1107 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1108 CMov_emitter(irn, env);
1111 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1113 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1114 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1115 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1116 const char *reg8bit;
1118 char cmd_buf[SNPRINTF_BUF_LEN];
1119 char cmnt_buf[SNPRINTF_BUF_LEN];
1120 const arch_register_t *out;
1122 out = arch_get_irn_register(env->arch_env, irn);
1123 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1125 if (is_ia32_CmpSet(irn)) {
1126 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1128 else if (is_ia32_xCmpSet(irn)) {
1129 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1131 else if (is_ia32_PsiCondSet(irn)) {
1132 /* omit compare because flags are already set by And/Or */
1133 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1136 assert(0 && "unsupported Set");
1138 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1141 /* use mov to clear target because it doesn't affect the eflags */
1142 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1143 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1146 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1147 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1151 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1152 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1155 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1156 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1159 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1160 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1163 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1165 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1167 long pnc = get_ia32_pncode(irn);
1168 long unord = pnc & pn_Cmp_Uo;
1169 char cmd_buf[SNPRINTF_BUF_LEN];
1170 char cmnt_buf[SNPRINTF_BUF_LEN];
1173 case pn_Cmp_Leg: /* odered */
1176 case pn_Cmp_Uo: /* unordered */
1180 case pn_Cmp_Eq: /* == */
1184 case pn_Cmp_Lt: /* < */
1188 case pn_Cmp_Le: /* <= */
1192 case pn_Cmp_Gt: /* > */
1196 case pn_Cmp_Ge: /* >= */
1200 case pn_Cmp_Lg: /* != */
1205 assert(sse_pnc >= 0 && "unsupported compare");
1207 if (unord && sse_pnc != 3) {
1209 We need a separate compare against unordered.
1210 Quick and Dirty solution:
1211 - get some memory on stack
1215 - and result and stored result
1218 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1219 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1221 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1222 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1224 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1225 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1229 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1230 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1233 if (unord && sse_pnc != 3) {
1234 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1235 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1237 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1238 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1243 /*********************************************************
1246 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1247 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1248 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1249 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1252 *********************************************************/
1254 /* jump table entry (target and corresponding number) */
1255 typedef struct _branch_t {
1260 /* jump table for switch generation */
1261 typedef struct _jmp_tbl_t {
1262 ir_node *defProj; /**< default target */
1263 int min_value; /**< smallest switch case */
1264 int max_value; /**< largest switch case */
1265 int num_branches; /**< number of jumps */
1266 char *label; /**< label of the jump table */
1267 branch_t *branches; /**< jump array */
1271 * Compare two variables of type branch_t. Used to sort all switch cases
1273 static int ia32_cmp_branch_t(const void *a, const void *b) {
1274 branch_t *b1 = (branch_t *)a;
1275 branch_t *b2 = (branch_t *)b;
1277 if (b1->value <= b2->value)
1284 * Emits code for a SwitchJmp (creates a jump table if
1285 * possible otherwise a cmp-jmp cascade). Port from
1288 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1289 unsigned long interval;
1290 char buf[SNPRINTF_BUF_LEN];
1291 int last_value, i, pn;
1294 const ir_edge_t *edge;
1295 const lc_arg_env_t *env = ia32_get_arg_env();
1296 FILE *F = emit_env->out;
1297 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1299 /* fill the table structure */
1300 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1301 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1303 tbl.num_branches = get_irn_n_edges(irn);
1304 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1305 tbl.min_value = INT_MAX;
1306 tbl.max_value = INT_MIN;
1309 /* go over all proj's and collect them */
1310 foreach_out_edge(irn, edge) {
1311 proj = get_edge_src_irn(edge);
1312 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1314 pn = get_Proj_proj(proj);
1316 /* create branch entry */
1317 tbl.branches[i].target = proj;
1318 tbl.branches[i].value = pn;
1320 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1321 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1323 /* check for default proj */
1324 if (pn == get_ia32_pncode(irn)) {
1325 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1332 /* sort the branches by their number */
1333 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1335 /* two-complement's magic make this work without overflow */
1336 interval = tbl.max_value - tbl.min_value;
1338 /* emit the table */
1339 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1340 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1343 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1344 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1347 if (tbl.num_branches > 1) {
1350 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1351 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1354 ia32_switch_section(F, SECTION_RODATA);
1355 fprintf(F, "\t.align 4\n");
1357 fprintf(F, "%s:\n", tbl.label);
1359 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1360 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1363 last_value = tbl.branches[0].value;
1364 for (i = 1; i < tbl.num_branches; ++i) {
1365 while (++last_value < tbl.branches[i].value) {
1366 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1367 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1370 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1371 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1374 ia32_switch_section(F, SECTION_TEXT);
1377 /* one jump is enough */
1378 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1379 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1390 * Emits code for a unconditional jump.
1392 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1393 ir_node *block, *next_bl;
1395 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1397 /* for now, the code works for scheduled and non-schedules blocks */
1398 block = get_nodes_block(irn);
1400 /* we have a block schedule */
1401 next_bl = next_blk_sched(block);
1402 if (get_cfop_target_block(irn) != next_bl) {
1403 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1404 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1408 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1413 /****************************
1416 * _ __ _ __ ___ _ ___
1417 * | '_ \| '__/ _ \| |/ __|
1418 * | |_) | | | (_) | |\__ \
1419 * | .__/|_| \___/| ||___/
1422 ****************************/
1425 * Emits code for a proj -> node
1427 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1428 ir_node *pred = get_Proj_pred(irn);
1430 if (get_irn_op(pred) == op_Start) {
1431 switch(get_Proj_proj(irn)) {
1432 case pn_Start_X_initial_exec:
1441 /**********************************
1444 * | | ___ _ __ _ _| |_) |
1445 * | | / _ \| '_ \| | | | _ <
1446 * | |___| (_) | |_) | |_| | |_) |
1447 * \_____\___/| .__/ \__, |____/
1450 **********************************/
1453 * Emit movsb/w instructions to make mov count divideable by 4
1455 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1456 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1458 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1460 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1461 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1466 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1467 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1471 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1472 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1476 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1477 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1479 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1480 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1488 * Emit rep movsd instruction for memcopy.
1490 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1491 FILE *F = emit_env->out;
1492 tarval *tv = get_ia32_Immop_tarval(irn);
1493 int rem = get_tarval_long(tv);
1494 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1496 emit_CopyB_prolog(F, irn, rem);
1498 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1499 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1504 * Emits unrolled memcopy.
1506 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1507 tarval *tv = get_ia32_Immop_tarval(irn);
1508 int size = get_tarval_long(tv);
1509 FILE *F = emit_env->out;
1510 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1512 emit_CopyB_prolog(F, irn, size & 0x3);
1516 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1517 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1524 /***************************
1528 * | | / _ \| '_ \ \ / /
1529 * | |___| (_) | | | \ V /
1530 * \_____\___/|_| |_|\_/
1532 ***************************/
1535 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1537 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1538 FILE *F = emit_env->out;
1539 const lc_arg_env_t *env = ia32_get_arg_env();
1540 ir_mode *src_mode = get_ia32_src_mode(irn);
1541 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1542 char *from, *to, buf[64];
1543 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1545 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1546 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1548 switch(get_ia32_op_type(irn)) {
1550 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1552 case ia32_AddrModeS:
1553 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1556 assert(0 && "unsupported op type for Conv");
1559 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1560 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1564 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1565 emit_ia32_Conv_with_FP(irn, emit_env);
1568 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1569 emit_ia32_Conv_with_FP(irn, emit_env);
1572 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1573 emit_ia32_Conv_with_FP(irn, emit_env);
1577 * Emits code for an Int conversion.
1579 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1580 FILE *F = emit_env->out;
1581 const lc_arg_env_t *env = ia32_get_arg_env();
1582 char *move_cmd = "movzx";
1583 char *conv_cmd = NULL;
1584 ir_mode *src_mode = get_ia32_src_mode(irn);
1585 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1587 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1588 const arch_register_t *in_reg, *out_reg;
1590 n = get_mode_size_bits(src_mode);
1591 m = get_mode_size_bits(tgt_mode);
1593 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1595 if (n == 8 || m == 8)
1597 else if (n == 16 || m == 16)
1600 printf("%d -> %d unsupported\n", n, m);
1601 assert(0 && "unsupported Conv_I2I");
1605 switch(get_ia32_op_type(irn)) {
1607 in_reg = get_in_reg(irn, 2);
1608 out_reg = get_out_reg(irn, 0);
1610 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1611 REGS_ARE_EQUAL(out_reg, in_reg) &&
1612 mode_is_signed(n < m ? src_mode : tgt_mode))
1614 /* argument and result are both in EAX and */
1615 /* signedness is ok: -> use converts */
1616 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1618 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1619 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1621 /* argument and result are in the same register */
1622 /* and signedness is ok: -> use and with mask */
1623 int mask = (1 << (n < m ? n : m)) - 1;
1624 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1627 /* use move w/o sign extension */
1628 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1629 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1633 case ia32_AddrModeS:
1634 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1635 move_cmd, irn, ia32_emit_am(irn, emit_env));
1638 assert(0 && "unsupported op type for Conv");
1641 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1642 irn, n, src_mode, m, tgt_mode);
1648 * Emits code for an 8Bit Int conversion.
1650 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1651 emit_ia32_Conv_I2I(irn, emit_env);
1655 /*******************************************
1658 * | |__ ___ _ __ ___ __| | ___ ___
1659 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1660 * | |_) | __/ | | | (_) | (_| | __/\__ \
1661 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1663 *******************************************/
1666 * Emits a backend call
1668 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1669 FILE *F = emit_env->out;
1670 entity *ent = be_Call_get_entity(irn);
1671 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1674 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1677 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1680 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1686 * Emits code to increase stack pointer.
1688 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1689 FILE *F = emit_env->out;
1690 int offs = be_get_IncSP_offset(irn);
1691 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1695 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1697 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1698 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1701 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1702 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1709 * Emits code to set stack pointer.
1711 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1712 FILE *F = emit_env->out;
1713 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1715 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1716 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1721 * Emits code for Copy/CopyKeep.
1723 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1724 FILE *F = emit_env->out;
1725 const arch_env_t *aenv = emit_env->arch_env;
1726 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1728 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1729 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1732 if (mode_is_float(get_irn_mode(irn)))
1733 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1735 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1736 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1740 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1741 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1744 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1745 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1749 * Emits code for exchange.
1751 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1752 FILE *F = emit_env->out;
1753 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1754 const arch_register_t *in1, *in2;
1755 const arch_register_class_t *cls1, *cls2;
1757 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1758 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1760 cls1 = arch_register_get_class(in1);
1761 cls2 = arch_register_get_class(in2);
1763 assert(cls1 == cls2 && "Register class mismatch at Perm");
1765 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1766 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1768 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1769 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1770 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1772 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1776 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1781 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1786 * Emits code for Constant loading.
1788 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1790 char cmd_buf[256], cmnt_buf[256];
1791 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1793 if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
1794 const char *instr = "xor";
1795 if (env->isa->opt_arch == arch_pentium_4) {
1796 /* P4 prefers sub r, r, others xor r, r */
1799 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1800 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1803 if (get_ia32_op_type(n) == ia32_SymConst) {
1804 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1805 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1808 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1809 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1812 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1816 * Emits code to increase stack pointer.
1818 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1819 FILE *F = emit_env->out;
1820 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1822 if (is_ia32_ImmConst(irn)) {
1823 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1825 else if (is_ia32_ImmSymConst(irn)) {
1826 if (get_ia32_op_type(irn) == ia32_Normal)
1827 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1828 else /* source address mode */
1829 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1832 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1834 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1840 * Emits code to load the TLS base
1842 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1843 FILE *F = emit_env->out;
1844 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1846 switch (asm_flavour) {
1848 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1851 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1854 assert(0 && "unsupported TLS");
1857 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1862 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1864 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1866 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1869 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1872 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1876 /***********************************************************************************
1879 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1880 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1881 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1882 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1884 ***********************************************************************************/
1887 * Enters the emitter functions for handled nodes into the generic
1888 * pointer of an opcode.
1890 static void ia32_register_emitters(void) {
1892 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1893 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1894 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1895 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1896 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1897 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1899 /* first clear the generic function pointer for all ops */
1900 clear_irp_opcodes_generic_func();
1902 /* register all emitter functions defined in spec */
1903 ia32_register_spec_emitters();
1905 /* other ia32 emitter functions */
1911 IA32_EMIT(PsiCondCMov);
1913 IA32_EMIT(PsiCondSet);
1914 IA32_EMIT(SwitchJmp);
1917 IA32_EMIT(Conv_I2FP);
1918 IA32_EMIT(Conv_FP2I);
1919 IA32_EMIT(Conv_FP2FP);
1920 IA32_EMIT(Conv_I2I);
1921 IA32_EMIT(Conv_I2I8Bit);
1927 IA32_EMIT(xCmpCMov);
1928 IA32_EMIT(xCondJmp);
1929 IA32_EMIT2(fcomJmp, x87CondJmp);
1930 IA32_EMIT2(fcompJmp, x87CondJmp);
1931 IA32_EMIT2(fcomppJmp, x87CondJmp);
1932 IA32_EMIT2(fcomrJmp, x87CondJmp);
1933 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1934 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1936 /* benode emitter */
1963 * Emits code for a node.
1965 static void ia32_emit_node(const ir_node *irn, void *env) {
1966 ia32_emit_env_t *emit_env = env;
1967 ir_op *op = get_irn_op(irn);
1968 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
1970 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
1972 if (op->ops.generic) {
1973 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
1977 emit_Nothing(irn, env);
1978 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
1983 * Emits gas alignment directives
1985 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
1986 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
1990 * Emits gas alignment directives for Functions depended on cpu architecture.
1992 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
1993 unsigned align; unsigned maximum_skip;
2008 maximum_skip = (1 << align) - 1;
2009 ia32_emit_alignment(F, align, maximum_skip);
2013 * Emits gas alignment directives for Labels depended on cpu architecture.
2015 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2016 unsigned align; unsigned maximum_skip;
2031 maximum_skip = (1 << align) - 1;
2032 ia32_emit_alignment(F, align, maximum_skip);
2036 * Walks over the nodes in a block connected by scheduling edges
2037 * and emits code for each node.
2039 static void ia32_gen_block(ir_node *block, void *env) {
2040 ia32_emit_env_t *emit_env = env;
2042 int need_label = block != get_irg_start_block(get_irn_irg(block));
2043 FILE *F = emit_env->out;
2045 if (! is_Block(block))
2048 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2049 /* if the extended block scheduler is used, only leader blocks need
2051 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2055 char cmd_buf[SNPRINTF_BUF_LEN];
2058 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2060 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2061 get_irn_node_nr(block));
2062 fprintf(F, "%-43s ", cmd_buf);
2064 /* emit list of pred blocks in comment */
2065 fprintf(F, "/* preds:");
2067 arity = get_irn_arity(block);
2068 for(i = 0; i < arity; ++i) {
2069 ir_node *predblock = get_Block_cfgpred_block(block, i);
2070 fprintf(F, " %ld", get_irn_node_nr(predblock));
2072 fprintf(F, " */\n");
2075 /* emit the contents of the block */
2076 sched_foreach(block, irn) {
2077 ia32_emit_node(irn, env);
2082 * Emits code for function start.
2084 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
2085 entity *irg_ent = get_irg_entity(irg);
2086 const char *irg_name = get_entity_ld_name(irg_ent);
2089 ia32_switch_section(F, SECTION_TEXT);
2090 ia32_emit_align_func(F, cpu);
2091 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2092 fprintf(F, ".globl %s\n", irg_name);
2094 ia32_dump_function_object(F, irg_name);
2095 fprintf(F, "%s:\n", irg_name);
2099 * Emits code for function end
2101 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
2102 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2104 ia32_dump_function_size(F, irg_name);
2110 * Sets labels for control flow nodes (jump target)
2111 * TODO: Jump optimization
2113 static void ia32_gen_labels(ir_node *block, void *env) {
2115 int n = get_Block_n_cfgpreds(block);
2117 for (n--; n >= 0; n--) {
2118 pred = get_Block_cfgpred(block, n);
2119 set_irn_link(pred, block);
2124 * Main driver. Emits the code for one routine.
2126 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2127 ia32_emit_env_t emit_env;
2131 emit_env.arch_env = cg->arch_env;
2133 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2134 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2136 /* set the global arch_env (needed by print hooks) */
2137 arch_env = cg->arch_env;
2139 ia32_register_emitters();
2141 ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
2142 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2144 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2145 int i, n = ARR_LEN(cg->blk_sched);
2147 for (i = 0; i < n;) {
2150 block = cg->blk_sched[i];
2152 next_bl = i < n ? cg->blk_sched[i] : NULL;
2154 /* set here the link. the emitter expects to find the next block here */
2155 set_irn_link(block, next_bl);
2156 ia32_gen_block(block, &emit_env);
2160 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2161 in the block schedule. As this number should NEVER be equal the next block,
2162 we does not need a clear block link here. */
2163 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2166 ia32_emit_func_epilog(F, irg);