2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
43 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../benode.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
73 static char pic_base_label[128];
74 static ir_label_t exc_label_id;
75 static int mark_spill_reload = 0;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 /** Checks if the current block is a fall-through target. */
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
99 * returns non-zero if the given block needs a label
100 * because of being a jump-target (and not a fall-through)
102 static int block_needs_label(const ir_node *block)
105 int n_cfgpreds = get_Block_n_cfgpreds(block);
107 if (has_Block_entity(block))
110 if (n_cfgpreds == 0) {
112 } else if (n_cfgpreds == 1) {
113 ir_node *cfgpred = get_Block_cfgpred(block, 0);
114 ir_node *cfgpred_block = get_nodes_block(cfgpred);
116 if (get_prev_block_sched(block) == cfgpred_block
117 && is_fallthrough(cfgpred)) {
126 * Returns the register at in position pos.
128 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
131 const arch_register_t *reg = NULL;
133 assert(get_irn_arity(irn) > pos && "Invalid IN position");
135 /* The out register of the operator at position pos is the
136 in register we need. */
137 op = get_irn_n(irn, pos);
139 reg = arch_get_irn_register(op);
141 assert(reg && "no in register found");
143 if (reg == &ia32_gp_regs[REG_GP_NOREG])
144 panic("trying to emit noreg for %+F input %d", irn, pos);
146 /* in case of unknown register: just return a valid register */
147 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
148 const arch_register_req_t *req = arch_get_register_req(irn, pos);
150 if (arch_register_req_is(req, limited)) {
151 /* in case of limited requirements: get the first allowed register */
152 unsigned idx = rbitset_next(req->limited, 0, 1);
153 reg = arch_register_for_index(req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%lu", prefix, ++id);
208 /*************************************************************
210 * (_) | | / _| | | | |
211 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
212 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
213 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
214 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
217 *************************************************************/
220 * Emit the name of the 8bit low register
222 static void emit_8bit_register(const arch_register_t *reg)
224 const char *reg_name = arch_register_get_name(reg);
227 be_emit_char(reg_name[1]);
232 * Emit the name of the 8bit high register
234 static void emit_8bit_register_high(const arch_register_t *reg)
236 const char *reg_name = arch_register_get_name(reg);
239 be_emit_char(reg_name[1]);
243 static void emit_16bit_register(const arch_register_t *reg)
245 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
248 be_emit_string(reg_name);
252 * emit a register, possible shortened by a mode
254 * @param reg the register
255 * @param mode the mode of the register or NULL for full register
257 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
259 const char *reg_name;
262 int size = get_mode_size_bits(mode);
264 case 8: emit_8bit_register(reg); return;
265 case 16: emit_16bit_register(reg); return;
267 assert(mode_is_float(mode) || size == 32);
270 reg_name = arch_register_get_name(reg);
273 be_emit_string(reg_name);
276 void ia32_emit_source_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_in_reg(node, pos);
280 emit_register(reg, NULL);
283 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
285 set_entity_backend_marked(entity, 1);
286 be_gas_emit_entity(entity);
288 if (get_entity_owner(entity) == get_tls_type()) {
289 if (get_entity_visibility(entity) == visibility_external_allocated) {
290 be_emit_cstring("@INDNTPOFF");
292 be_emit_cstring("@NTPOFF");
296 if (do_pic && !no_pic_adjust) {
298 be_emit_string(pic_base_label);
302 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
304 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
306 if (attr->symconst != NULL) {
309 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
311 if (attr->symconst == NULL || attr->offset != 0) {
312 if (attr->symconst != NULL) {
313 be_emit_irprintf("%+d", attr->offset);
315 be_emit_irprintf("0x%X", attr->offset);
320 static void emit_ia32_Immediate(const ir_node *node)
323 emit_ia32_Immediate_no_prefix(node);
326 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
328 const arch_register_t *reg;
329 const ir_node *in = get_irn_n(node, pos);
330 if (is_ia32_Immediate(in)) {
331 emit_ia32_Immediate(in);
335 reg = get_in_reg(node, pos);
336 emit_8bit_register(reg);
339 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
341 const arch_register_t *reg = get_in_reg(node, pos);
342 emit_8bit_register_high(reg);
345 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
347 const arch_register_t *reg;
348 const ir_node *in = get_irn_n(node, pos);
349 if (is_ia32_Immediate(in)) {
350 emit_ia32_Immediate(in);
354 reg = get_in_reg(node, pos);
355 emit_16bit_register(reg);
358 void ia32_emit_dest_register(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, NULL);
365 void ia32_emit_dest_register_size(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, get_ia32_ls_mode(node));
372 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
374 const arch_register_t *reg = get_out_reg(node, pos);
376 emit_register(reg, mode_Bu);
379 void ia32_emit_x87_register(const ir_node *node, int pos)
381 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
385 be_emit_string(attr->x87[pos]->name);
388 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
390 assert(mode_is_int(mode) || mode_is_reference(mode));
391 switch (get_mode_size_bits(mode)) {
392 case 8: be_emit_char('b'); return;
393 case 16: be_emit_char('w'); return;
394 case 32: be_emit_char('l'); return;
395 /* gas docu says q is the suffix but gcc, objdump and icc use ll
397 case 64: be_emit_cstring("ll"); return;
399 panic("Can't output mode_suffix for %+F", mode);
402 void ia32_emit_mode_suffix(const ir_node *node)
404 ir_mode *mode = get_ia32_ls_mode(node);
408 ia32_emit_mode_suffix_mode(mode);
411 void ia32_emit_x87_mode_suffix(const ir_node *node)
415 /* we only need to emit the mode on address mode */
416 if (get_ia32_op_type(node) == ia32_Normal)
419 mode = get_ia32_ls_mode(node);
420 assert(mode != NULL);
422 if (mode_is_float(mode)) {
423 switch (get_mode_size_bits(mode)) {
424 case 32: be_emit_char('s'); return;
425 case 64: be_emit_char('l'); return;
427 case 96: be_emit_char('t'); return;
430 assert(mode_is_int(mode));
431 switch (get_mode_size_bits(mode)) {
432 case 16: be_emit_char('s'); return;
433 case 32: be_emit_char('l'); return;
434 /* gas docu says q is the suffix but gcc, objdump and icc use ll
436 case 64: be_emit_cstring("ll"); return;
439 panic("Can't output mode_suffix for %+F", mode);
442 static char get_xmm_mode_suffix(ir_mode *mode)
444 assert(mode_is_float(mode));
445 switch(get_mode_size_bits(mode)) {
448 default: panic("Invalid XMM mode");
452 void ia32_emit_xmm_mode_suffix(const ir_node *node)
454 ir_mode *mode = get_ia32_ls_mode(node);
455 assert(mode != NULL);
457 be_emit_char(get_xmm_mode_suffix(mode));
460 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
462 ir_mode *mode = get_ia32_ls_mode(node);
463 assert(mode != NULL);
464 be_emit_char(get_xmm_mode_suffix(mode));
467 void ia32_emit_extend_suffix(const ir_node *node)
469 ir_mode *mode = get_ia32_ls_mode(node);
470 if (get_mode_size_bits(mode) == 32)
472 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
473 ia32_emit_mode_suffix_mode(mode);
476 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
478 ir_node *in = get_irn_n(node, pos);
479 if (is_ia32_Immediate(in)) {
480 emit_ia32_Immediate(in);
482 const ir_mode *mode = get_ia32_ls_mode(node);
483 const arch_register_t *reg = get_in_reg(node, pos);
484 emit_register(reg, mode);
489 * Returns the target block for a control flow node.
491 static ir_node *get_cfop_target_block(const ir_node *irn)
493 assert(get_irn_mode(irn) == mode_X);
494 return get_irn_link(irn);
498 * Emits a block label for the given block.
500 static void ia32_emit_block_name(const ir_node *block)
502 if (has_Block_entity(block)) {
503 ir_entity *entity = get_Block_entity(block);
504 be_gas_emit_entity(entity);
506 be_emit_cstring(BLOCK_PREFIX);
507 be_emit_irprintf("%ld", get_irn_node_nr(block));
512 * Emits the target label for a control flow node.
514 static void ia32_emit_cfop_target(const ir_node *node)
516 ir_node *block = get_cfop_target_block(node);
517 ia32_emit_block_name(block);
521 * positive conditions for signed compares
523 static const char *const cmp2condition_s[] = {
524 NULL, /* always false */
531 NULL /* always true */
535 * positive conditions for unsigned compares
537 static const char *const cmp2condition_u[] = {
538 NULL, /* always false */
545 NULL /* always true */
549 * Emit the suffix for a compare instruction.
551 static void ia32_emit_cmp_suffix(int pnc)
555 if (pnc == ia32_pn_Cmp_parity) {
559 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
560 str = cmp2condition_u[pnc & 7];
562 str = cmp2condition_s[pnc & 7];
568 typedef enum ia32_emit_mod_t {
569 EMIT_RESPECT_LS = 1U << 0,
570 EMIT_ALTERNATE_AM = 1U << 1,
575 * Emits address mode.
577 void ia32_emit_am(const ir_node *node)
579 ir_entity *ent = get_ia32_am_sc(node);
580 int offs = get_ia32_am_offs_int(node);
581 ir_node *base = get_irn_n(node, n_ia32_base);
582 int has_base = !is_ia32_NoReg_GP(base);
583 ir_node *index = get_irn_n(node, n_ia32_index);
584 int has_index = !is_ia32_NoReg_GP(index);
586 /* just to be sure... */
587 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
591 const ia32_attr_t *attr = get_ia32_attr_const(node);
592 if (is_ia32_am_sc_sign(node))
594 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
597 /* also handle special case if nothing is set */
598 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
600 be_emit_irprintf("%+d", offs);
602 be_emit_irprintf("%d", offs);
606 if (has_base || has_index) {
611 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
612 emit_register(reg, NULL);
615 /* emit index + scale */
617 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
620 emit_register(reg, NULL);
622 scale = get_ia32_am_scale(node);
624 be_emit_irprintf(",%d", 1 << scale);
632 * fmt parameter output
633 * ---- ---------------------- ---------------------------------------------
635 * %AM <node> address mode of the node
636 * %AR const arch_register_t* address mode of the node or register
637 * %ASx <node> address mode of the node or source register x
638 * %Dx <node> destination register x
639 * %I <node> immediate of the node
640 * %L <node> control flow target of the node
641 * %M <node> mode suffix of the node
642 * %P int condition code
643 * %R const arch_register_t* register
644 * %Sx <node> source register x
645 * %s const char* string
646 * %u unsigned int unsigned int
647 * %d signed int signed int
650 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
651 * * modifier does not prefix immediates with $, but AM with *
652 * l modifier for %lu and %ld
654 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
660 const char *start = fmt;
661 ia32_emit_mod_t mod = 0;
663 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
666 be_emit_string_len(start, fmt - start);
670 be_emit_finish_line_gas(node);
682 mod |= EMIT_ALTERNATE_AM;
687 mod |= EMIT_RESPECT_LS;
704 if (mod & EMIT_ALTERNATE_AM)
711 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
712 if (mod & EMIT_ALTERNATE_AM)
714 if (get_ia32_op_type(node) == ia32_AddrModeS) {
717 emit_register(reg, NULL);
723 if (get_ia32_op_type(node) == ia32_AddrModeS) {
724 if (mod & EMIT_ALTERNATE_AM)
729 assert(get_ia32_op_type(node) == ia32_Normal);
734 default: goto unknown;
741 const arch_register_t *reg;
743 if (*fmt < '0' || '9' <= *fmt)
747 reg = get_out_reg(node, pos);
748 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
753 if (!(mod & EMIT_ALTERNATE_AM))
755 emit_ia32_Immediate_no_prefix(node);
759 ia32_emit_cfop_target(node);
763 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
768 int pnc = va_arg(ap, int);
769 ia32_emit_cmp_suffix(pnc);
774 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
775 emit_register(reg, NULL);
784 if (*fmt < '0' || '9' <= *fmt)
788 in = get_irn_n(node, pos);
789 if (is_ia32_Immediate(in)) {
790 if (!(mod & EMIT_ALTERNATE_AM))
792 emit_ia32_Immediate_no_prefix(in);
794 const arch_register_t *reg;
796 if (mod & EMIT_ALTERNATE_AM)
798 reg = get_in_reg(node, pos);
799 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
805 const char *str = va_arg(ap, const char*);
811 if (mod & EMIT_LONG) {
812 unsigned long num = va_arg(ap, unsigned long);
813 be_emit_irprintf("%lu", num);
815 unsigned num = va_arg(ap, unsigned);
816 be_emit_irprintf("%u", num);
821 if (mod & EMIT_LONG) {
822 long num = va_arg(ap, long);
823 be_emit_irprintf("%ld", num);
825 int num = va_arg(ap, int);
826 be_emit_irprintf("%d", num);
832 panic("unknown format conversion in ia32_emitf()");
840 * Emits registers and/or address mode of a binary operation.
842 void ia32_emit_binop(const ir_node *node)
844 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
845 ia32_emitf(node, "%#S4, %#AS3");
847 ia32_emitf(node, "%#AS4, %#S3");
852 * Emits registers and/or address mode of a binary operation.
854 void ia32_emit_x87_binop(const ir_node *node)
856 switch(get_ia32_op_type(node)) {
859 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
860 const arch_register_t *in1 = x87_attr->x87[0];
861 const arch_register_t *in = x87_attr->x87[1];
862 const arch_register_t *out = x87_attr->x87[2];
866 } else if (out == in) {
871 be_emit_string(arch_register_get_name(in));
872 be_emit_cstring(", %");
873 be_emit_string(arch_register_get_name(out));
881 assert(0 && "unsupported op type");
886 * Emits registers and/or address mode of a unary operation.
888 void ia32_emit_unop(const ir_node *node, int pos)
892 ia32_emitf(node, fmt);
895 static void emit_ia32_IMul(const ir_node *node)
897 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
898 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
900 /* do we need the 3-address form? */
901 if (is_ia32_NoReg_GP(left) ||
902 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
903 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
905 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
910 * walks up a tree of copies/perms/spills/reloads to find the original value
911 * that is moved around
913 static ir_node *find_original_value(ir_node *node)
915 if (irn_visited(node))
918 mark_irn_visited(node);
919 if (be_is_Copy(node)) {
920 return find_original_value(be_get_Copy_op(node));
921 } else if (be_is_CopyKeep(node)) {
922 return find_original_value(be_get_CopyKeep_op(node));
923 } else if (is_Proj(node)) {
924 ir_node *pred = get_Proj_pred(node);
925 if (be_is_Perm(pred)) {
926 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
927 } else if (be_is_MemPerm(pred)) {
928 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
929 } else if (is_ia32_Load(pred)) {
930 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
934 } else if (is_ia32_Store(node)) {
935 return find_original_value(get_irn_n(node, n_ia32_Store_val));
936 } else if (is_Phi(node)) {
938 arity = get_irn_arity(node);
939 for (i = 0; i < arity; ++i) {
940 ir_node *in = get_irn_n(node, i);
941 ir_node *res = find_original_value(in);
952 static int determine_final_pnc(const ir_node *node, int flags_pos,
955 ir_node *flags = get_irn_n(node, flags_pos);
956 const ia32_attr_t *flags_attr;
957 flags = skip_Proj(flags);
959 if (is_ia32_Sahf(flags)) {
960 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
961 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
962 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
963 inc_irg_visited(current_ir_graph);
964 cmp = find_original_value(cmp);
966 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
967 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
970 flags_attr = get_ia32_attr_const(cmp);
971 if (flags_attr->data.ins_permuted)
972 pnc = get_mirrored_pnc(pnc);
973 pnc |= ia32_pn_Cmp_float;
974 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
975 || is_ia32_Fucompi(flags)) {
976 flags_attr = get_ia32_attr_const(flags);
978 if (flags_attr->data.ins_permuted)
979 pnc = get_mirrored_pnc(pnc);
980 pnc |= ia32_pn_Cmp_float;
982 flags_attr = get_ia32_attr_const(flags);
984 if (flags_attr->data.ins_permuted)
985 pnc = get_mirrored_pnc(pnc);
986 if (flags_attr->data.cmp_unsigned)
987 pnc |= ia32_pn_Cmp_unsigned;
993 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
995 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
996 return get_negated_pnc(pnc, mode);
999 void ia32_emit_cmp_suffix_node(const ir_node *node,
1002 const ia32_attr_t *attr = get_ia32_attr_const(node);
1004 pn_Cmp pnc = get_ia32_condcode(node);
1006 pnc = determine_final_pnc(node, flags_pos, pnc);
1007 if (attr->data.ins_permuted)
1008 pnc = ia32_get_negated_pnc(pnc);
1010 ia32_emit_cmp_suffix(pnc);
1014 * Emits an exception label for a given node.
1016 static void ia32_emit_exc_label(const ir_node *node)
1018 be_emit_string(be_gas_insn_label_prefix());
1019 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1023 * Returns the Proj with projection number proj and NOT mode_M
1025 static ir_node *get_proj(const ir_node *node, long proj)
1027 const ir_edge_t *edge;
1030 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1032 foreach_out_edge(node, edge) {
1033 src = get_edge_src_irn(edge);
1035 assert(is_Proj(src) && "Proj expected");
1036 if (get_irn_mode(src) == mode_M)
1039 if (get_Proj_proj(src) == proj)
1045 static int can_be_fallthrough(const ir_node *node)
1047 ir_node *target_block = get_cfop_target_block(node);
1048 ir_node *block = get_nodes_block(node);
1049 return get_prev_block_sched(target_block) == block;
1053 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1055 static void emit_ia32_Jcc(const ir_node *node)
1057 int need_parity_label = 0;
1058 const ir_node *proj_true;
1059 const ir_node *proj_false;
1060 const ir_node *block;
1061 pn_Cmp pnc = get_ia32_condcode(node);
1063 pnc = determine_final_pnc(node, 0, pnc);
1065 /* get both Projs */
1066 proj_true = get_proj(node, pn_ia32_Jcc_true);
1067 assert(proj_true && "Jcc without true Proj");
1069 proj_false = get_proj(node, pn_ia32_Jcc_false);
1070 assert(proj_false && "Jcc without false Proj");
1072 block = get_nodes_block(node);
1074 if (can_be_fallthrough(proj_true)) {
1075 /* exchange both proj's so the second one can be omitted */
1076 const ir_node *t = proj_true;
1078 proj_true = proj_false;
1080 pnc = ia32_get_negated_pnc(pnc);
1083 if (pnc & ia32_pn_Cmp_float) {
1084 /* Some floating point comparisons require a test of the parity flag,
1085 * which indicates that the result is unordered */
1088 ia32_emitf(proj_true, "\tjp %L\n");
1093 ia32_emitf(proj_true, "\tjnp %L\n");
1099 /* we need a local label if the false proj is a fallthrough
1100 * as the falseblock might have no label emitted then */
1101 if (can_be_fallthrough(proj_false)) {
1102 need_parity_label = 1;
1103 ia32_emitf(proj_false, "\tjp 1f\n");
1105 ia32_emitf(proj_false, "\tjp %L\n");
1112 ia32_emitf(proj_true, "\tjp %L\n");
1120 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1123 if (need_parity_label) {
1124 ia32_emitf(NULL, "1:\n");
1127 /* the second Proj might be a fallthrough */
1128 if (can_be_fallthrough(proj_false)) {
1129 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1131 ia32_emitf(proj_false, "\tjmp %L\n");
1135 static void emit_ia32_CMov(const ir_node *node)
1137 const ia32_attr_t *attr = get_ia32_attr_const(node);
1138 int ins_permuted = attr->data.ins_permuted;
1139 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1140 pn_Cmp pnc = get_ia32_condcode(node);
1141 const arch_register_t *in_true;
1142 const arch_register_t *in_false;
1144 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1146 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1147 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1149 /* should be same constraint fullfilled? */
1150 if (out == in_false) {
1151 /* yes -> nothing to do */
1152 } else if (out == in_true) {
1153 const arch_register_t *tmp;
1155 assert(get_ia32_op_type(node) == ia32_Normal);
1157 ins_permuted = !ins_permuted;
1164 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1168 pnc = ia32_get_negated_pnc(pnc);
1170 /* TODO: handling of Nans isn't correct yet */
1172 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1175 /*********************************************************
1178 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1179 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1180 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1181 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1184 *********************************************************/
1186 /* jump table entry (target and corresponding number) */
1187 typedef struct _branch_t {
1192 /* jump table for switch generation */
1193 typedef struct _jmp_tbl_t {
1194 ir_node *defProj; /**< default target */
1195 long min_value; /**< smallest switch case */
1196 long max_value; /**< largest switch case */
1197 long num_branches; /**< number of jumps */
1198 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1199 branch_t *branches; /**< jump array */
1203 * Compare two variables of type branch_t. Used to sort all switch cases
1205 static int ia32_cmp_branch_t(const void *a, const void *b)
1207 branch_t *b1 = (branch_t *)a;
1208 branch_t *b2 = (branch_t *)b;
1210 if (b1->value <= b2->value)
1217 * Emits code for a SwitchJmp (creates a jump table if
1218 * possible otherwise a cmp-jmp cascade). Port from
1221 static void emit_ia32_SwitchJmp(const ir_node *node)
1223 unsigned long interval;
1229 const ir_edge_t *edge;
1231 /* fill the table structure */
1232 get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1234 tbl.num_branches = get_irn_n_edges(node) - 1;
1235 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1236 tbl.min_value = INT_MAX;
1237 tbl.max_value = INT_MIN;
1239 default_pn = get_ia32_condcode(node);
1241 /* go over all proj's and collect them */
1242 foreach_out_edge(node, edge) {
1243 proj = get_edge_src_irn(edge);
1244 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1246 pnc = get_Proj_proj(proj);
1248 /* check for default proj */
1249 if (pnc == default_pn) {
1250 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1253 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1254 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1256 /* create branch entry */
1257 tbl.branches[i].target = proj;
1258 tbl.branches[i].value = pnc;
1263 assert(i == tbl.num_branches);
1265 /* sort the branches by their number */
1266 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1268 /* two-complement's magic make this work without overflow */
1269 interval = tbl.max_value - tbl.min_value;
1271 /* emit the table */
1272 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1273 ia32_emitf(tbl.defProj, "\tja %L\n");
1275 if (tbl.num_branches > 1) {
1277 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1279 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1280 ia32_emitf(NULL, "\t.align 4\n");
1281 ia32_emitf(NULL, "%s:\n", tbl.label);
1283 last_value = tbl.branches[0].value;
1284 for (i = 0; i != tbl.num_branches; ++i) {
1285 while (last_value != tbl.branches[i].value) {
1286 ia32_emitf(tbl.defProj, ".long %L\n");
1289 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1292 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1294 /* one jump is enough */
1295 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1302 * Emits code for a unconditional jump.
1304 static void emit_ia32_Jmp(const ir_node *node)
1308 /* for now, the code works for scheduled and non-schedules blocks */
1309 block = get_nodes_block(node);
1311 /* we have a block schedule */
1312 if (can_be_fallthrough(node)) {
1313 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1315 ia32_emitf(node, "\tjmp %L\n");
1320 * Emit an inline assembler operand.
1322 * @param node the ia32_ASM node
1323 * @param s points to the operand (a %c)
1325 * @return pointer to the first char in s NOT in the current operand
1327 static const char* emit_asm_operand(const ir_node *node, const char *s)
1329 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1330 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1332 const arch_register_t *reg;
1333 const ia32_asm_reg_t *asm_regs = attr->register_map;
1334 const ia32_asm_reg_t *asm_reg;
1335 const char *reg_name;
1344 /* parse modifiers */
1347 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1372 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1379 sscanf(s, "%d%n", &num, &p);
1381 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1388 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1390 "Error: Custom assembler references invalid input/output (%+F)\n",
1394 asm_reg = & asm_regs[num];
1395 assert(asm_reg->valid);
1398 if (asm_reg->use_input == 0) {
1399 reg = get_out_reg(node, asm_reg->inout_pos);
1401 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1403 /* might be an immediate value */
1404 if (is_ia32_Immediate(pred)) {
1405 emit_ia32_Immediate(pred);
1408 reg = get_in_reg(node, asm_reg->inout_pos);
1412 "Warning: no register assigned for %d asm op (%+F)\n",
1417 if (asm_reg->memory) {
1422 if (modifier != 0) {
1426 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1429 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1432 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1435 panic("Invalid asm op modifier");
1437 be_emit_string(reg_name);
1439 emit_register(reg, asm_reg->mode);
1442 if (asm_reg->memory) {
1450 * Emits code for an ASM pseudo op.
1452 static void emit_ia32_Asm(const ir_node *node)
1454 const void *gen_attr = get_irn_generic_attr_const(node);
1455 const ia32_asm_attr_t *attr
1456 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1457 ident *asm_text = attr->asm_text;
1458 const char *s = get_id_str(asm_text);
1460 ia32_emitf(node, "#APP\t\n");
1467 s = emit_asm_operand(node, s);
1473 ia32_emitf(NULL, "\n#NO_APP\n");
1476 /**********************************
1479 * | | ___ _ __ _ _| |_) |
1480 * | | / _ \| '_ \| | | | _ <
1481 * | |___| (_) | |_) | |_| | |_) |
1482 * \_____\___/| .__/ \__, |____/
1485 **********************************/
1488 * Emit movsb/w instructions to make mov count divideable by 4
1490 static void emit_CopyB_prolog(unsigned size)
1493 ia32_emitf(NULL, "\tmovsb\n");
1495 ia32_emitf(NULL, "\tmovsw\n");
1499 * Emit rep movsd instruction for memcopy.
1501 static void emit_ia32_CopyB(const ir_node *node)
1503 unsigned size = get_ia32_copyb_size(node);
1505 emit_CopyB_prolog(size);
1506 ia32_emitf(node, "\trep movsd\n");
1510 * Emits unrolled memcopy.
1512 static void emit_ia32_CopyB_i(const ir_node *node)
1514 unsigned size = get_ia32_copyb_size(node);
1516 emit_CopyB_prolog(size);
1520 ia32_emitf(NULL, "\tmovsd\n");
1526 /***************************
1530 * | | / _ \| '_ \ \ / /
1531 * | |___| (_) | | | \ V /
1532 * \_____\___/|_| |_|\_/
1534 ***************************/
1537 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1539 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1542 ir_mode *ls_mode = get_ia32_ls_mode(node);
1543 int ls_bits = get_mode_size_bits(ls_mode);
1544 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1546 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1549 static void emit_ia32_Conv_I2FP(const ir_node *node)
1551 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1554 static void emit_ia32_Conv_FP2I(const ir_node *node)
1556 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1559 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1561 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1565 * Emits code for an Int conversion.
1567 static void emit_ia32_Conv_I2I(const ir_node *node)
1569 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1570 int signed_mode = mode_is_signed(smaller_mode);
1571 const char *sign_suffix;
1573 assert(!mode_is_float(smaller_mode));
1575 sign_suffix = signed_mode ? "s" : "z";
1576 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1582 static void emit_ia32_Call(const ir_node *node)
1584 /* Special case: Call must not have its immediates prefixed by $, instead
1585 * address mode is prefixed by *. */
1586 ia32_emitf(node, "\tcall %*AS3\n");
1590 /*******************************************
1593 * | |__ ___ _ __ ___ __| | ___ ___
1594 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1595 * | |_) | __/ | | | (_) | (_| | __/\__ \
1596 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1598 *******************************************/
1601 * Emits code to increase stack pointer.
1603 static void emit_be_IncSP(const ir_node *node)
1605 int offs = be_get_IncSP_offset(node);
1611 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1613 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1617 static inline bool is_unknown_reg(const arch_register_t *reg)
1619 if(reg == &ia32_gp_regs[REG_GP_UKNWN]
1620 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1621 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1628 * Emits code for Copy/CopyKeep.
1630 static void Copy_emitter(const ir_node *node, const ir_node *op)
1632 const arch_register_t *in = arch_get_irn_register(op);
1633 const arch_register_t *out = arch_get_irn_register(node);
1638 if (is_unknown_reg(in))
1640 /* copies of vf nodes aren't real... */
1641 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1644 if (get_irn_mode(node) == mode_E) {
1645 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1647 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1651 static void emit_be_Copy(const ir_node *node)
1653 Copy_emitter(node, be_get_Copy_op(node));
1656 static void emit_be_CopyKeep(const ir_node *node)
1658 Copy_emitter(node, be_get_CopyKeep_op(node));
1662 * Emits code for exchange.
1664 static void emit_be_Perm(const ir_node *node)
1666 const arch_register_t *in0, *in1;
1667 const arch_register_class_t *cls0, *cls1;
1669 in0 = arch_get_irn_register(get_irn_n(node, 0));
1670 in1 = arch_get_irn_register(get_irn_n(node, 1));
1672 cls0 = arch_register_get_class(in0);
1673 cls1 = arch_register_get_class(in1);
1675 assert(cls0 == cls1 && "Register class mismatch at Perm");
1677 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1678 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1679 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1680 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1681 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1682 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1683 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1685 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1688 panic("unexpected register class in be_Perm (%+F)", node);
1693 * Emits code for Constant loading.
1695 static void emit_ia32_Const(const ir_node *node)
1697 ia32_emitf(node, "\tmovl %I, %D0\n");
1701 * Emits code to load the TLS base
1703 static void emit_ia32_LdTls(const ir_node *node)
1705 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1708 /* helper function for emit_ia32_Minus64Bit */
1709 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1711 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1714 /* helper function for emit_ia32_Minus64Bit */
1715 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1717 ia32_emitf(node, "\tnegl %R\n", reg);
1720 /* helper function for emit_ia32_Minus64Bit */
1721 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1723 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1726 /* helper function for emit_ia32_Minus64Bit */
1727 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1729 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1732 /* helper function for emit_ia32_Minus64Bit */
1733 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1735 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1738 /* helper function for emit_ia32_Minus64Bit */
1739 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1741 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1744 static void emit_ia32_Minus64Bit(const ir_node *node)
1746 const arch_register_t *in_lo = get_in_reg(node, 0);
1747 const arch_register_t *in_hi = get_in_reg(node, 1);
1748 const arch_register_t *out_lo = get_out_reg(node, 0);
1749 const arch_register_t *out_hi = get_out_reg(node, 1);
1751 if (out_lo == in_lo) {
1752 if (out_hi != in_hi) {
1753 /* a -> a, b -> d */
1756 /* a -> a, b -> b */
1759 } else if (out_lo == in_hi) {
1760 if (out_hi == in_lo) {
1761 /* a -> b, b -> a */
1762 emit_xchg(node, in_lo, in_hi);
1765 /* a -> b, b -> d */
1766 emit_mov(node, in_hi, out_hi);
1767 emit_mov(node, in_lo, out_lo);
1771 if (out_hi == in_lo) {
1772 /* a -> c, b -> a */
1773 emit_mov(node, in_lo, out_lo);
1775 } else if (out_hi == in_hi) {
1776 /* a -> c, b -> b */
1777 emit_mov(node, in_lo, out_lo);
1780 /* a -> c, b -> d */
1781 emit_mov(node, in_lo, out_lo);
1787 emit_neg( node, out_hi);
1788 emit_neg( node, out_lo);
1789 emit_sbb0(node, out_hi);
1793 emit_zero(node, out_hi);
1794 emit_neg( node, out_lo);
1795 emit_sbb( node, in_hi, out_hi);
1798 static void emit_ia32_GetEIP(const ir_node *node)
1800 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1801 ia32_emitf(NULL, "%s:\n", pic_base_label);
1802 ia32_emitf(node, "\tpopl %D0\n");
1805 static void emit_ia32_ClimbFrame(const ir_node *node)
1807 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1809 ia32_emitf(node, "\tmovl %S0, %D0\n");
1810 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1811 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1812 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1813 ia32_emitf(node, "\tdec %S1\n");
1814 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1817 static void emit_be_Return(const ir_node *node)
1819 unsigned pop = be_Return_get_pop(node);
1821 if (pop > 0 || be_Return_get_emit_pop(node)) {
1822 ia32_emitf(node, "\tret $%u\n", pop);
1824 ia32_emitf(node, "\tret\n");
1828 static void emit_Nothing(const ir_node *node)
1834 /***********************************************************************************
1837 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1838 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1839 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1840 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1842 ***********************************************************************************/
1845 * Enters the emitter functions for handled nodes into the generic
1846 * pointer of an opcode.
1848 static void ia32_register_emitters(void)
1850 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1851 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1852 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1853 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1854 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1855 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1857 /* first clear the generic function pointer for all ops */
1858 clear_irp_opcodes_generic_func();
1860 /* register all emitter functions defined in spec */
1861 ia32_register_spec_emitters();
1863 /* other ia32 emitter functions */
1864 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1869 IA32_EMIT(Conv_FP2FP);
1870 IA32_EMIT(Conv_FP2I);
1871 IA32_EMIT(Conv_I2FP);
1872 IA32_EMIT(Conv_I2I);
1879 IA32_EMIT(Minus64Bit);
1880 IA32_EMIT(SwitchJmp);
1881 IA32_EMIT(ClimbFrame);
1884 /* benode emitter */
1905 typedef void (*emit_func_ptr) (const ir_node *);
1908 * Assign and emit an exception label if the current instruction can fail.
1910 static void ia32_assign_exc_label(ir_node *node)
1912 /* assign a new ID to the instruction */
1913 set_ia32_exc_label_id(node, ++exc_label_id);
1915 ia32_emit_exc_label(node);
1917 be_emit_pad_comment();
1918 be_emit_cstring("/* exception to Block ");
1919 ia32_emit_cfop_target(node);
1920 be_emit_cstring(" */\n");
1921 be_emit_write_line();
1925 * Emits code for a node.
1927 static void ia32_emit_node(ir_node *node)
1929 ir_op *op = get_irn_op(node);
1931 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1933 if (is_ia32_irn(node)) {
1934 if (get_ia32_exc_label(node)) {
1935 /* emit the exception label of this instruction */
1936 ia32_assign_exc_label(node);
1938 if (mark_spill_reload) {
1939 if (is_ia32_is_spill(node)) {
1940 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1942 if (is_ia32_is_reload(node)) {
1943 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1945 if (is_ia32_is_remat(node)) {
1946 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1950 if (op->ops.generic) {
1951 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1953 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1958 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1964 * Emits gas alignment directives
1966 static void ia32_emit_alignment(unsigned align, unsigned skip)
1968 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1972 * Emits gas alignment directives for Labels depended on cpu architecture.
1974 static void ia32_emit_align_label(void)
1976 unsigned align = ia32_cg_config.label_alignment;
1977 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1978 ia32_emit_alignment(align, maximum_skip);
1982 * Test whether a block should be aligned.
1983 * For cpus in the P4/Athlon class it is useful to align jump labels to
1984 * 16 bytes. However we should only do that if the alignment nops before the
1985 * label aren't executed more often than we have jumps to the label.
1987 static int should_align_block(const ir_node *block)
1989 static const double DELTA = .0001;
1990 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1991 ir_node *prev = get_prev_block_sched(block);
1993 double prev_freq = 0; /**< execfreq of the fallthrough block */
1994 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1997 if (exec_freq == NULL)
1999 if (ia32_cg_config.label_alignment_factor <= 0)
2002 block_freq = get_block_execfreq(exec_freq, block);
2003 if (block_freq < DELTA)
2006 n_cfgpreds = get_Block_n_cfgpreds(block);
2007 for(i = 0; i < n_cfgpreds; ++i) {
2008 const ir_node *pred = get_Block_cfgpred_block(block, i);
2009 double pred_freq = get_block_execfreq(exec_freq, pred);
2012 prev_freq += pred_freq;
2014 jmp_freq += pred_freq;
2018 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2021 jmp_freq /= prev_freq;
2023 return jmp_freq > ia32_cg_config.label_alignment_factor;
2027 * Emit the block header for a block.
2029 * @param block the block
2030 * @param prev_block the previous block
2032 static void ia32_emit_block_header(ir_node *block)
2034 ir_graph *irg = current_ir_graph;
2035 int need_label = block_needs_label(block);
2037 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2039 if (block == get_irg_end_block(irg))
2042 if (ia32_cg_config.label_alignment > 0) {
2043 /* align the current block if:
2044 * a) if should be aligned due to its execution frequency
2045 * b) there is no fall-through here
2047 if (should_align_block(block)) {
2048 ia32_emit_align_label();
2050 /* if the predecessor block has no fall-through,
2051 we can always align the label. */
2053 int has_fallthrough = 0;
2055 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2056 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2057 if (can_be_fallthrough(cfg_pred)) {
2058 has_fallthrough = 1;
2063 if (!has_fallthrough)
2064 ia32_emit_align_label();
2069 ia32_emit_block_name(block);
2072 be_emit_pad_comment();
2073 be_emit_cstring(" /* ");
2075 be_emit_cstring("\t/* ");
2076 ia32_emit_block_name(block);
2077 be_emit_cstring(": ");
2080 be_emit_cstring("preds:");
2082 /* emit list of pred blocks in comment */
2083 arity = get_irn_arity(block);
2085 be_emit_cstring(" none");
2087 for (i = 0; i < arity; ++i) {
2088 ir_node *predblock = get_Block_cfgpred_block(block, i);
2089 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2092 if (exec_freq != NULL) {
2093 be_emit_irprintf(", freq: %f",
2094 get_block_execfreq(exec_freq, block));
2096 be_emit_cstring(" */\n");
2097 be_emit_write_line();
2101 * Walks over the nodes in a block connected by scheduling edges
2102 * and emits code for each node.
2104 static void ia32_gen_block(ir_node *block)
2108 ia32_emit_block_header(block);
2110 /* emit the contents of the block */
2111 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2112 sched_foreach(block, node) {
2113 ia32_emit_node(node);
2117 typedef struct exc_entry {
2118 ir_node *exc_instr; /** The instruction that can issue an exception. */
2119 ir_node *block; /** The block to call then. */
2124 * Sets labels for control flow nodes (jump target).
2125 * Links control predecessors to there destination blocks.
2127 static void ia32_gen_labels(ir_node *block, void *data)
2129 exc_entry **exc_list = data;
2133 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2134 pred = get_Block_cfgpred(block, n);
2135 set_irn_link(pred, block);
2137 pred = skip_Proj(pred);
2138 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2143 ARR_APP1(exc_entry, *exc_list, e);
2144 set_irn_link(pred, block);
2150 * Compare two exception_entries.
2152 static int cmp_exc_entry(const void *a, const void *b)
2154 const exc_entry *ea = a;
2155 const exc_entry *eb = b;
2157 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2163 * Main driver. Emits the code for one routine.
2165 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2167 ir_entity *entity = get_irg_entity(irg);
2168 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2173 do_pic = cg->birg->main_env->options->pic;
2175 ia32_register_emitters();
2177 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2179 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2180 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2182 /* we use links to point to target blocks */
2183 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2184 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2186 /* initialize next block links */
2187 n = ARR_LEN(cg->blk_sched);
2188 for (i = 0; i < n; ++i) {
2189 ir_node *block = cg->blk_sched[i];
2190 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2192 set_irn_link(block, prev);
2195 for (i = 0; i < n; ++i) {
2196 ir_node *block = cg->blk_sched[i];
2198 ia32_gen_block(block);
2201 be_gas_emit_function_epilog(entity);
2202 be_dbg_method_end();
2204 be_emit_write_line();
2206 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2208 /* Sort the exception table using the exception label id's.
2209 Those are ascending with ascending addresses. */
2210 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2214 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2215 be_emit_cstring("\t.long ");
2216 ia32_emit_exc_label(exc_list[i].exc_instr);
2218 be_emit_cstring("\t.long ");
2219 ia32_emit_block_name(exc_list[i].block);
2223 DEL_ARR_F(exc_list);
2226 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2227 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2231 /* ==== Experimental binary emitter ==== */
2233 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2234 static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2235 static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2236 static unsigned char pnc_map_signed[8];
2237 static unsigned char pnc_map_unsigned[8];
2239 static void build_reg_map(void)
2241 reg_gp_map[REG_EAX] = 0x0;
2242 reg_gp_map[REG_ECX] = 0x1;
2243 reg_gp_map[REG_EDX] = 0x2;
2244 reg_gp_map[REG_EBX] = 0x3;
2245 reg_gp_map[REG_ESP] = 0x4;
2246 reg_gp_map[REG_EBP] = 0x5;
2247 reg_gp_map[REG_ESI] = 0x6;
2248 reg_gp_map[REG_EDI] = 0x7;
2250 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2251 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2252 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2253 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2254 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2255 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2257 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2258 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2259 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2260 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2261 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2262 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2265 static unsigned char pnc2cc(int pnc)
2268 if (pnc == ia32_pn_Cmp_parity) {
2270 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2271 cc = pnc_map_unsigned[pnc & 0x07];
2273 cc = pnc_map_signed[pnc & 0x07];
2279 /** Sign extension bit values for binops */
2281 UNSIGNED_IMM = 0, /**< unsigned immediate */
2282 SIGNEXT_IMM = 2, /**< sign extended immediate */
2285 /** The mod encoding of the ModR/M */
2287 MOD_IND = 0x00, /**< [reg1] */
2288 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2289 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2290 MOD_REG = 0xC0 /**< reg1 */
2293 /** create R/M encoding for ModR/M */
2294 #define ENC_RM(x) (x)
2295 /** create REG encoding for ModR/M */
2296 #define ENC_REG(x) ((x) << 3)
2298 /** create encoding for a SIB byte */
2299 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2301 /* Node: The following routines are supposed to append bytes, words, dwords
2302 to the output stream.
2303 Currently the implementation is stupid in that it still creates output
2304 for an "assembler" in the form of .byte, .long
2305 We will change this when enough infrastructure is there to create complete
2306 machine code in memory/object files */
2308 static void bemit8(const unsigned char byte)
2310 be_emit_irprintf("\t.byte 0x%x\n", byte);
2311 be_emit_write_line();
2314 static void bemit16(const unsigned short u16)
2316 be_emit_irprintf("\t.word 0x%x\n", u16);
2317 be_emit_write_line();
2320 static void bemit32(const unsigned u32)
2322 be_emit_irprintf("\t.long 0x%x\n", u32);
2323 be_emit_write_line();
2327 * Emit address of an entity. If @p is_relative is true then a relative
2328 * offset from behind the address to the entity is created.
2330 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2333 if (entity == NULL) {
2342 /* the final version should remember the position in the bytestream
2343 and patch it with the correct address at linktime... */
2344 be_emit_cstring("\t.long ");
2347 set_entity_backend_marked(entity, 1);
2348 be_gas_emit_entity(entity);
2351 be_emit_cstring("-.");
2355 be_emit_irprintf("%+d", offset);
2358 be_emit_write_line();
2361 static void bemit_jmp_destination(const ir_node *dest_block)
2363 be_emit_cstring("\t.long ");
2364 ia32_emit_block_name(dest_block);
2365 be_emit_cstring(" - . - 4\n");
2366 be_emit_write_line();
2369 /* end emit routines, all emitters following here should only use the functions
2372 /** Create a ModR/M byte for src1,src2 registers */
2373 static void bemit_modrr(const arch_register_t *src1,
2374 const arch_register_t *src2)
2376 unsigned char modrm = MOD_REG;
2377 modrm |= ENC_RM(reg_gp_map[src1->index]);
2378 modrm |= ENC_REG(reg_gp_map[src2->index]);
2382 /** Create a ModR/M byte for one register and extension */
2383 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2385 unsigned char modrm = MOD_REG;
2387 modrm |= ENC_RM(reg_gp_map[reg->index]);
2388 modrm |= ENC_REG(ext);
2393 * Calculate the size of an signed immediate in bytes.
2395 * @param offset an offset
2397 static unsigned get_signed_imm_size(int offset)
2399 if (-128 <= offset && offset < 128) {
2401 } else if (-32768 <= offset && offset < 32768) {
2409 * Emit an address mode.
2411 * @param reg content of the reg field: either a register index or an opcode extension
2412 * @param node the node
2414 static void bemit_mod_am(unsigned reg, const ir_node *node)
2416 ir_entity *ent = get_ia32_am_sc(node);
2417 int offs = get_ia32_am_offs_int(node);
2418 ir_node *base = get_irn_n(node, n_ia32_base);
2419 int has_base = !is_ia32_NoReg_GP(base);
2420 ir_node *index = get_irn_n(node, n_ia32_index);
2421 int has_index = !is_ia32_NoReg_GP(index);
2424 unsigned emitoffs = 0;
2425 bool emitsib = false;
2428 /* set the mod part depending on displacement */
2430 modrm |= MOD_IND_WORD_OFS;
2432 } else if (offs == 0) {
2435 } else if (-128 <= offs && offs < 128) {
2436 modrm |= MOD_IND_BYTE_OFS;
2439 modrm |= MOD_IND_WORD_OFS;
2444 const arch_register_t *base_reg = arch_get_irn_register(base);
2445 base_enc = reg_gp_map[base_reg->index];
2447 /* Use the EBP encoding + MOD_IND if NO base register. There is
2448 * always a 32bit offset present in this case. */
2454 /* Determine if we need a SIB byte. */
2456 const arch_register_t *reg_index = arch_get_irn_register(index);
2457 int scale = get_ia32_am_scale(node);
2459 /* R/M set to ESP means SIB in 32bit mode. */
2460 modrm |= ENC_RM(0x04);
2461 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2463 } else if (base_enc == 0x04) {
2464 /* for the above reason we are forced to emit a SIB when base is ESP.
2465 * Only the base is used, index must be ESP too, which means no index.
2467 modrm |= ENC_RM(0x04);
2468 sib = ENC_SIB(0, 0x04, 0x04);
2471 modrm |= ENC_RM(base_enc);
2474 /* We are forced to emit an 8bit offset as EBP base without offset is a
2475 * special case for SIB without base register. */
2476 if (base_enc == 0x05 && emitoffs == 0) {
2477 modrm |= MOD_IND_BYTE_OFS;
2481 modrm |= ENC_REG(reg);
2487 /* emit displacement */
2488 if (emitoffs == 8) {
2489 bemit8((unsigned) offs);
2490 } else if (emitoffs == 32) {
2491 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2496 * Emit a binop with a immediate operand.
2498 * @param node the node to emit
2499 * @param opcode_eax the opcode for the op eax, imm variant
2500 * @param opcode the opcode for the reg, imm variant
2501 * @param ruval the opcode extension for opcode
2503 static void bemit_binop_with_imm(
2504 const ir_node *node,
2505 unsigned char opcode_ax,
2506 unsigned char opcode, unsigned char ruval)
2508 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2509 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2510 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2513 /* Some instructions (test) have no short form with 32bit value + 8bit
2515 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2518 /* check for sign extension */
2519 size = get_signed_imm_size(attr->offset);
2524 bemit8(opcode | SIGNEXT_IMM);
2525 /* cmp has this special mode */
2526 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2527 bemit_mod_am(ruval, node);
2529 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2530 bemit_modru(reg, ruval);
2532 bemit8((unsigned char)attr->offset);
2536 /* check for eax variant: this variant is shorter for 32bit immediates only */
2537 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2539 bemit_mod_am(ruval, node);
2541 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2542 if (reg->index == REG_EAX) {
2546 bemit_modru(reg, ruval);
2549 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2552 panic("invalid imm size?!?");
2558 static void bemit_binop_2(const ir_node *node, unsigned code)
2560 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2562 if (get_ia32_op_type(node) == ia32_Normal) {
2563 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2564 bemit_modrr(op2, out);
2566 bemit_mod_am(reg_gp_map[out->index], node);
2573 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2575 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2576 if (is_ia32_Immediate(right)) {
2577 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2579 bemit_binop_2(node, opcodes[0]);
2586 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2589 if (get_ia32_op_type(node) == ia32_Normal) {
2590 const arch_register_t *in = get_in_reg(node, input);
2591 bemit_modru(in, ext);
2593 bemit_mod_am(ext, node);
2597 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2599 const arch_register_t *out = get_out_reg(node, 0);
2600 bemit_unop(node, code, reg_gp_map[out->index], input);
2603 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2605 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2608 bemit8(size == 8 ? code : code + 1);
2609 bemit_mod_am(ext, node);
2612 static void bemit_immediate(const ir_node *node, bool relative)
2614 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2615 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2618 static void bemit_copy(const ir_node *copy)
2620 const arch_register_t *in = get_in_reg(copy, 0);
2621 const arch_register_t *out = get_out_reg(copy, 0);
2623 if (in == out || is_unknown_reg(in))
2625 /* copies of vf nodes aren't real... */
2626 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2629 if (get_irn_mode(copy) == mode_E) {
2632 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2634 bemit_modrr(in, out);
2638 static void bemit_perm(const ir_node *node)
2640 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2641 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2642 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2644 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2646 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2647 if (in0->index == REG_EAX) {
2648 bemit8(0x90 + reg_gp_map[in1->index]);
2649 } else if (in1->index == REG_EAX) {
2650 bemit8(0x90 + reg_gp_map[in0->index]);
2653 bemit_modrr(in0, in1);
2655 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2656 panic("unimplemented"); // TODO implement
2657 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2658 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2659 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2660 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2662 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2665 panic("unexpected register class in be_Perm (%+F)", node);
2669 static void bemit_xor0(const ir_node *node)
2671 const arch_register_t *out = get_out_reg(node, 0);
2673 bemit_modrr(out, out);
2676 static void bemit_mov_const(const ir_node *node)
2678 const arch_register_t *out = get_out_reg(node, 0);
2679 bemit8(0xB8 + reg_gp_map[out->index]);
2680 bemit_immediate(node, false);
2684 * Creates a function for a Binop with 3 possible encodings.
2686 #define BINOP(op, op0, op1, op2, op2_ext) \
2687 static void bemit_ ## op(const ir_node *node) { \
2688 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2689 bemit_binop(node, op ## _codes); \
2692 /* insn def eax,imm imm */
2693 BINOP(add, 0x03, 0x05, 0x81, 0)
2694 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2695 BINOP(adc, 0x13, 0x15, 0x81, 2)
2696 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2697 BINOP(and, 0x23, 0x25, 0x81, 4)
2698 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2699 BINOP(xor, 0x33, 0x35, 0x81, 6)
2700 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2702 #define BINOPMEM(op, ext) \
2703 static void bemit_##op(const ir_node *node) \
2705 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2708 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2709 if (is_ia32_Immediate(val)) { \
2710 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2711 int offset = attr->offset; \
2712 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2714 bemit_mod_am(ext, node); \
2718 bemit_mod_am(ext, node); \
2722 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2726 bemit8(ext << 3 | 1); \
2727 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2731 static void bemit_##op##8bit(const ir_node *node) \
2733 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2734 if (is_ia32_Immediate(val)) { \
2736 bemit_mod_am(ext, node); \
2737 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2740 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2752 * Creates a function for an Unop with code /ext encoding.
2754 #define UNOP(op, code, ext, input) \
2755 static void bemit_ ## op(const ir_node *node) { \
2756 bemit_unop(node, code, ext, input); \
2759 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2760 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2761 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2762 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2763 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2764 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2766 /* TODO: am support for IJmp */
2767 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2769 #define SHIFT(op, ext) \
2770 static void bemit_##op(const ir_node *node) \
2772 const arch_register_t *out = get_out_reg(node, 0); \
2773 ir_node *count = get_irn_n(node, 1); \
2774 if (is_ia32_Immediate(count)) { \
2775 int offset = get_ia32_immediate_attr_const(count)->offset; \
2776 if (offset == 1) { \
2778 bemit_modru(out, ext); \
2781 bemit_modru(out, ext); \
2786 bemit_modru(out, ext); \
2790 static void bemit_##op##mem(const ir_node *node) \
2792 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2795 ir_node *count = get_irn_n(node, 1); \
2796 if (is_ia32_Immediate(count)) { \
2797 int offset = get_ia32_immediate_attr_const(count)->offset; \
2798 if (offset == 1) { \
2799 bemit8(size == 1 ? 0xD0 : 0xD1); \
2800 bemit_mod_am(ext, node); \
2802 bemit8(size == 1 ? 0xC0 : 0xC1); \
2803 bemit_mod_am(ext, node); \
2807 bemit8(size == 1 ? 0xD2 : 0xD3); \
2808 bemit_mod_am(ext, node); \
2818 static void bemit_shld(const ir_node *node)
2820 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2821 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2822 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2824 if (is_ia32_Immediate(count)) {
2826 bemit_modrr(out, in);
2827 bemit8(get_ia32_immediate_attr_const(count)->offset);
2830 bemit_modrr(out, in);
2834 static void bemit_shrd(const ir_node *node)
2836 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2837 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2838 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2840 if (is_ia32_Immediate(count)) {
2842 bemit_modrr(out, in);
2843 bemit8(get_ia32_immediate_attr_const(count)->offset);
2846 bemit_modrr(out, in);
2850 static void bemit_cmov(const ir_node *node)
2852 const ia32_attr_t *attr = get_ia32_attr_const(node);
2853 int ins_permuted = attr->data.ins_permuted;
2854 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2855 pn_Cmp pnc = get_ia32_condcode(node);
2856 const arch_register_t *in_true;
2857 const arch_register_t *in_false;
2859 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
2861 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
2862 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
2864 /* should be same constraint fullfilled? */
2865 if (out == in_false) {
2866 /* yes -> nothing to do */
2867 } else if (out == in_true) {
2868 assert(get_ia32_op_type(node) == ia32_Normal);
2869 ins_permuted = !ins_permuted;
2873 bemit8(0x8B); // mov %in_false, %out
2874 bemit_modrr(in_false, out);
2878 pnc = ia32_get_negated_pnc(pnc);
2880 /* TODO: handling of Nans isn't correct yet */
2883 bemit8(0x40 + pnc2cc(pnc));
2884 if (get_ia32_op_type(node) == ia32_Normal) {
2885 bemit_modrr(in_true, out);
2887 bemit_mod_am(reg_gp_map[out->index], node);
2891 static void bemit_cmp(const ir_node *node)
2893 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2899 right = get_irn_n(node, n_ia32_binary_right);
2900 if (is_ia32_Immediate(right)) {
2901 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2902 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2903 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2906 if (attr->symconst != NULL) {
2909 /* check for sign extension */
2910 size = get_signed_imm_size(attr->offset);
2915 bemit8(0x81 | SIGNEXT_IMM);
2916 /* cmp has this special mode */
2917 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2918 bemit_mod_am(7, node);
2920 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2921 bemit_modru(reg, 7);
2923 bemit8((unsigned char)attr->offset);
2927 /* check for eax variant: this variant is shorter for 32bit immediates only */
2928 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2930 bemit_mod_am(7, node);
2932 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2933 if (reg->index == REG_EAX) {
2937 bemit_modru(reg, 7);
2940 if (ls_size == 16) {
2941 bemit16(attr->offset);
2943 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2947 panic("invalid imm size?!?");
2949 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2951 if (get_ia32_op_type(node) == ia32_Normal) {
2952 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2953 bemit_modrr(op2, out);
2955 bemit_mod_am(reg_gp_map[out->index], node);
2960 static void bemit_cmp8bit(const ir_node *node)
2962 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2963 if (is_ia32_Immediate(right)) {
2964 if (get_ia32_op_type(node) == ia32_Normal) {
2965 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2966 if (out->index == REG_EAX) {
2970 bemit_modru(out, 7);
2974 bemit_mod_am(7, node);
2976 bemit8(get_ia32_immediate_attr_const(right)->offset);
2979 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2980 if (get_ia32_op_type(node) == ia32_Normal) {
2981 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2982 bemit_modrr(out, in);
2984 bemit_mod_am(reg_gp_map[out->index], node);
2989 static void bemit_test8bit(const ir_node *node)
2991 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2992 if (is_ia32_Immediate(right)) {
2993 if (get_ia32_op_type(node) == ia32_Normal) {
2994 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2995 if (out->index == REG_EAX) {
2999 bemit_modru(out, 0);
3003 bemit_mod_am(0, node);
3005 bemit8(get_ia32_immediate_attr_const(right)->offset);
3008 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3009 if (get_ia32_op_type(node) == ia32_Normal) {
3010 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3011 bemit_modrr(out, in);
3013 bemit_mod_am(reg_gp_map[out->index], node);
3018 static void bemit_imul(const ir_node *node)
3020 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3021 /* Do we need the immediate form? */
3022 if (is_ia32_Immediate(right)) {
3023 int imm = get_ia32_immediate_attr_const(right)->offset;
3024 if (get_signed_imm_size(imm) == 1) {
3025 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3028 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3033 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3037 static void bemit_dec(const ir_node *node)
3039 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3040 bemit8(0x48 + reg_gp_map[out->index]);
3043 static void bemit_inc(const ir_node *node)
3045 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3046 bemit8(0x40 + reg_gp_map[out->index]);
3049 #define UNOPMEM(op, code, ext) \
3050 static void bemit_##op(const ir_node *node) \
3052 bemit_unop_mem(node, code, ext); \
3055 UNOPMEM(notmem, 0xF6, 2)
3056 UNOPMEM(negmem, 0xF6, 3)
3057 UNOPMEM(incmem, 0xFE, 0)
3058 UNOPMEM(decmem, 0xFE, 1)
3060 static void bemit_set(const ir_node *node)
3066 pnc = get_ia32_condcode(node);
3067 pnc = determine_final_pnc(node, n_ia32_Set_eflags, pnc);
3068 if (get_ia32_attr_const(node)->data.ins_permuted)
3069 pnc = ia32_get_negated_pnc(pnc);
3071 bemit8(0x90 + pnc2cc(pnc));
3072 bemit_modru(get_out_reg(node, pn_ia32_Set_res), 2);
3075 static void bemit_ldtls(const ir_node *node)
3077 const arch_register_t *out = get_out_reg(node, 0);
3079 bemit8(0x65); // gs:
3080 if (out->index == REG_EAX) {
3081 bemit8(0xA1); // movl 0, %eax
3083 bemit8(0x8B); // movl 0, %reg
3084 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3092 static void bemit_lea(const ir_node *node)
3094 const arch_register_t *out = get_out_reg(node, 0);
3096 bemit_mod_am(reg_gp_map[out->index], node);
3100 * Emit a single opcode.
3102 #define EMIT_SINGLEOP(op, code) \
3103 static void bemit_ ## op(const ir_node *node) { \
3108 //EMIT_SINGLEOP(daa, 0x27)
3109 //EMIT_SINGLEOP(das, 0x2F)
3110 //EMIT_SINGLEOP(aaa, 0x37)
3111 //EMIT_SINGLEOP(aas, 0x3F)
3112 //EMIT_SINGLEOP(nop, 0x90)
3113 EMIT_SINGLEOP(cwtl, 0x98)
3114 EMIT_SINGLEOP(cltd, 0x99)
3115 //EMIT_SINGLEOP(fwait, 0x9B)
3116 EMIT_SINGLEOP(sahf, 0x9E)
3117 //EMIT_SINGLEOP(popf, 0x9D)
3118 EMIT_SINGLEOP(leave, 0xC9)
3119 EMIT_SINGLEOP(int3, 0xCC)
3120 //EMIT_SINGLEOP(iret, 0xCF)
3121 //EMIT_SINGLEOP(xlat, 0xD7)
3122 //EMIT_SINGLEOP(lock, 0xF0)
3123 EMIT_SINGLEOP(rep, 0xF3)
3124 //EMIT_SINGLEOP(halt, 0xF4)
3125 EMIT_SINGLEOP(cmc, 0xF5)
3126 EMIT_SINGLEOP(stc, 0xF9)
3127 //EMIT_SINGLEOP(cli, 0xFA)
3128 //EMIT_SINGLEOP(sti, 0xFB)
3129 //EMIT_SINGLEOP(std, 0xFD)
3132 * Emits a MOV out, [MEM].
3134 static void bemit_load(const ir_node *node)
3136 const arch_register_t *out = get_out_reg(node, 0);
3138 if (out->index == REG_EAX) {
3139 ir_node *base = get_irn_n(node, n_ia32_base);
3140 int has_base = !is_ia32_NoReg_GP(base);
3141 ir_node *index = get_irn_n(node, n_ia32_index);
3142 int has_index = !is_ia32_NoReg_GP(index);
3143 if (!has_base && !has_index) {
3144 ir_entity *ent = get_ia32_am_sc(node);
3145 int offs = get_ia32_am_offs_int(node);
3146 /* load from constant address to EAX can be encoded
3149 bemit_entity(ent, 0, offs, false);
3154 bemit_mod_am(reg_gp_map[out->index], node);
3158 * Emits a MOV [mem], in.
3160 static void bemit_store(const ir_node *node)
3162 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3163 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3165 if (is_ia32_Immediate(value)) {
3168 bemit_mod_am(0, node);
3169 bemit8(get_ia32_immediate_attr_const(value)->offset);
3170 } else if (size == 16) {
3173 bemit_mod_am(0, node);
3174 bemit16(get_ia32_immediate_attr_const(value)->offset);
3177 bemit_mod_am(0, node);
3178 bemit_immediate(value, false);
3181 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3183 if (in->index == REG_EAX) {
3184 ir_node *base = get_irn_n(node, n_ia32_base);
3185 int has_base = !is_ia32_NoReg_GP(base);
3186 ir_node *index = get_irn_n(node, n_ia32_index);
3187 int has_index = !is_ia32_NoReg_GP(index);
3188 if (!has_base && !has_index) {
3189 ir_entity *ent = get_ia32_am_sc(node);
3190 int offs = get_ia32_am_offs_int(node);
3191 /* store to constant address from EAX can be encoded as
3192 * 0xA2/0xA3 [offset]*/
3200 bemit_entity(ent, 0, offs, false);
3212 bemit_mod_am(reg_gp_map[in->index], node);
3216 static void bemit_conv_i2i(const ir_node *node)
3218 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3227 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3228 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3229 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3235 static void bemit_push(const ir_node *node)
3237 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3239 if (is_ia32_Immediate(value)) {
3240 const ia32_immediate_attr_t *attr
3241 = get_ia32_immediate_attr_const(value);
3242 unsigned size = get_signed_imm_size(attr->offset);
3248 bemit8((unsigned char)attr->offset);
3253 bemit_immediate(value, false);
3256 } else if (is_ia32_NoReg_GP(value)) {
3258 bemit_mod_am(6, node);
3260 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3261 bemit8(0x50 + reg_gp_map[reg->index]);
3268 static void bemit_pop(const ir_node *node)
3270 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3271 bemit8(0x58 + reg_gp_map[reg->index]);
3274 static void bemit_popmem(const ir_node *node)
3277 bemit_mod_am(0, node);
3280 static void bemit_call(const ir_node *node)
3282 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3284 if (is_ia32_Immediate(proc)) {
3286 bemit_immediate(proc, true);
3288 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3292 static void bemit_jmp(const ir_node *dest_block)
3295 bemit_jmp_destination(dest_block);
3298 static void bemit_jump(const ir_node *node)
3300 if (can_be_fallthrough(node))
3303 bemit_jmp(get_cfop_target_block(node));
3306 static void bemit_jcc(int pnc, const ir_node *dest_block)
3308 unsigned char cc = pnc2cc(pnc);
3311 bemit_jmp_destination(dest_block);
3314 static void bemit_jp(bool odd, const ir_node *dest_block)
3318 bemit_jmp_destination(dest_block);
3321 static void bemit_ia32_jcc(const ir_node *node)
3323 int pnc = get_ia32_condcode(node);
3324 const ir_node *proj_true;
3325 const ir_node *proj_false;
3326 const ir_node *dest_true;
3327 const ir_node *dest_false;
3328 const ir_node *block;
3330 pnc = determine_final_pnc(node, 0, pnc);
3332 /* get both Projs */
3333 proj_true = get_proj(node, pn_ia32_Jcc_true);
3334 assert(proj_true && "Jcc without true Proj");
3336 proj_false = get_proj(node, pn_ia32_Jcc_false);
3337 assert(proj_false && "Jcc without false Proj");
3339 block = get_nodes_block(node);
3341 if (can_be_fallthrough(proj_true)) {
3342 /* exchange both proj's so the second one can be omitted */
3343 const ir_node *t = proj_true;
3345 proj_true = proj_false;
3347 pnc = ia32_get_negated_pnc(pnc);
3350 dest_true = get_cfop_target_block(proj_true);
3351 dest_false = get_cfop_target_block(proj_false);
3353 if (pnc & ia32_pn_Cmp_float) {
3354 /* Some floating point comparisons require a test of the parity flag,
3355 * which indicates that the result is unordered */
3358 bemit_jp(false, dest_true);
3363 bemit_jp(true, dest_true);
3369 /* we need a local label if the false proj is a fallthrough
3370 * as the falseblock might have no label emitted then */
3371 if (can_be_fallthrough(proj_false)) {
3373 bemit8(0x06); // jp + 6
3375 bemit_jp(false, dest_false);
3382 bemit_jp(false, dest_true);
3390 bemit_jcc(pnc, dest_true);
3393 /* the second Proj might be a fallthrough */
3394 if (can_be_fallthrough(proj_false)) {
3395 /* it's a fallthrough */
3397 bemit_jmp(dest_false);
3404 static void bemit_return(const ir_node *node)
3406 unsigned pop = be_Return_get_pop(node);
3407 if (pop > 0 || be_Return_get_emit_pop(node)) {
3409 assert(pop <= 0xffff);
3416 static void bemit_subsp(const ir_node *node)
3418 const arch_register_t *out;
3421 /* mov %esp, %out */
3423 out = get_out_reg(node, 1);
3424 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3427 static void bemit_incsp(const ir_node *node)
3430 const arch_register_t *reg;
3434 offs = be_get_IncSP_offset(node);
3445 size = get_signed_imm_size(offs);
3446 bemit8(size == 1 ? 0x83 : 0x81);
3448 reg = get_out_reg(node, 0);
3449 bemit_modru(reg, ext);
3458 static void bemit_copybi(const ir_node *node)
3460 unsigned size = get_ia32_copyb_size(node);
3462 bemit8(0xA4); // movsb
3465 bemit8(0xA5); // movsw
3469 bemit8(0xA5); // movsl
3473 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3475 if (get_ia32_op_type(node) == ia32_Normal) {
3476 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3477 const arch_register_t *in1 = x87_attr->x87[0];
3478 const arch_register_t *in = x87_attr->x87[1];
3479 const arch_register_t *out = x87_attr->x87[2];
3483 } else if (out == in) {
3487 if (out->index == 0) {
3489 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3492 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3495 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3500 bemit_mod_am(code, node);
3504 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3506 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3507 const arch_register_t *out = x87_attr->x87[2];
3509 bemit8(code + out->index);
3512 static void bemit_fabs(const ir_node *node)
3520 static void bemit_fadd(const ir_node *node)
3522 bemit_fbinop(node, 0, 0);
3525 static void bemit_faddp(const ir_node *node)
3527 bemit_fbinopp(node, 0xC0);
3530 static void bemit_fchs(const ir_node *node)
3538 static void bemit_fdiv(const ir_node *node)
3540 bemit_fbinop(node, 6, 7);
3543 static void bemit_fdivp(const ir_node *node)
3545 bemit_fbinopp(node, 0xF8);
3548 static void bemit_fdivr(const ir_node *node)
3550 bemit_fbinop(node, 7, 6);
3553 static void bemit_fdivrp(const ir_node *node)
3555 bemit_fbinopp(node, 0xF0);
3558 static void bemit_fild(const ir_node *node)
3560 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3562 bemit8(0xDF); // filds
3563 bemit_mod_am(0, node);
3567 bemit8(0xDB); // fildl
3568 bemit_mod_am(0, node);
3572 bemit8(0xDF); // fildll
3573 bemit_mod_am(5, node);
3577 panic("invalid mode size");
3581 static void bemit_fist(const ir_node *node)
3583 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3585 bemit8(0xDF); // fists
3589 bemit8(0xDB); // fistl
3593 panic("invalid mode size");
3595 bemit_mod_am(2, node);
3598 static void bemit_fistp(const ir_node *node)
3600 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3602 bemit8(0xDF); // fistps
3603 bemit_mod_am(3, node);
3607 bemit8(0xDB); // fistpl
3608 bemit_mod_am(3, node);
3612 bemit8(0xDF); // fistpll
3613 bemit_mod_am(7, node);
3617 panic("invalid mode size");
3621 static void bemit_fld(const ir_node *node)
3623 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3625 bemit8(0xD9); // flds
3626 bemit_mod_am(0, node);
3630 bemit8(0xDD); // fldl
3631 bemit_mod_am(0, node);
3636 bemit8(0xDB); // fldt
3637 bemit_mod_am(5, node);
3641 panic("invalid mode size");
3645 static void bemit_fld1(const ir_node *node)
3649 bemit8(0xE8); // fld1
3652 static void bemit_fldcw(const ir_node *node)
3654 bemit8(0xD9); // fldcw
3655 bemit_mod_am(5, node);
3658 static void bemit_fldz(const ir_node *node)
3662 bemit8(0xEE); // fldz
3665 static void bemit_fmul(const ir_node *node)
3667 bemit_fbinop(node, 1, 1);
3670 static void bemit_fmulp(const ir_node *node)
3672 bemit_fbinopp(node, 0xC8);
3675 static void bemit_fpop(const ir_node *node)
3677 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3679 bemit8(0xD8 + attr->x87[0]->index);
3682 static void bemit_fpush(const ir_node *node)
3684 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3686 bemit8(0xC0 + attr->x87[0]->index);
3689 static void bemit_fpushcopy(const ir_node *node)
3691 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3693 bemit8(0xC0 + attr->x87[0]->index);
3696 static void bemit_fst(const ir_node *node)
3698 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3700 bemit8(0xD9); // fsts
3704 bemit8(0xDD); // fstl
3708 panic("invalid mode size");
3710 bemit_mod_am(2, node);
3713 static void bemit_fstp(const ir_node *node)
3715 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3717 bemit8(0xD9); // fstps
3718 bemit_mod_am(3, node);
3722 bemit8(0xDD); // fstpl
3723 bemit_mod_am(3, node);
3728 bemit8(0xDB); // fstpt
3729 bemit_mod_am(7, node);
3733 panic("invalid mode size");
3737 static void bemit_fsub(const ir_node *node)
3739 bemit_fbinop(node, 4, 5);
3742 static void bemit_fsubp(const ir_node *node)
3744 bemit_fbinopp(node, 0xE8);
3747 static void bemit_fsubr(const ir_node *node)
3749 bemit_fbinop(node, 5, 4);
3752 static void bemit_fsubrp(const ir_node *node)
3754 bemit_fbinopp(node, 0xE0);
3757 static void bemit_fnstcw(const ir_node *node)
3759 bemit8(0xD9); // fnstcw
3760 bemit_mod_am(7, node);
3763 static void bemit_fnstsw(void)
3765 bemit8(0xDF); // fnstsw %ax
3769 static void bemit_ftstfnstsw(const ir_node *node)
3773 bemit8(0xD9); // ftst
3778 static void bemit_fucomi(const ir_node *node)
3780 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3781 bemit8(0xDB); // fucomi
3782 bemit8(0xE8 + attr->x87[1]->index);
3785 static void bemit_fucomip(const ir_node *node)
3787 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3788 bemit8(0xDF); // fucomip
3789 bemit8(0xE8 + attr->x87[1]->index);
3792 static void bemit_fucomfnstsw(const ir_node *node)
3794 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3795 bemit8(0xDD); // fucom
3796 bemit8(0xE0 + attr->x87[1]->index);
3800 static void bemit_fucompfnstsw(const ir_node *node)
3802 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3803 bemit8(0xDD); // fucomp
3804 bemit8(0xE8 + attr->x87[1]->index);
3808 static void bemit_fucomppfnstsw(const ir_node *node)
3812 bemit8(0xDA); // fucompp
3817 static void bemit_fxch(const ir_node *node)
3819 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3821 bemit8(0xC8 + attr->x87[0]->index);
3825 * The type of a emitter function.
3827 typedef void (*emit_func) (const ir_node *);
3830 * Set a node emitter. Make it a bit more type safe.
3832 static void register_emitter(ir_op *op, emit_func func)
3834 op->ops.generic = (op_func) func;
3837 static void ia32_register_binary_emitters(void)
3839 /* first clear the generic function pointer for all ops */
3840 clear_irp_opcodes_generic_func();
3842 /* benode emitter */
3843 register_emitter(op_be_Copy, bemit_copy);
3844 register_emitter(op_be_CopyKeep, bemit_copy);
3845 register_emitter(op_be_IncSP, bemit_incsp);
3846 register_emitter(op_be_Perm, bemit_perm);
3847 register_emitter(op_be_Return, bemit_return);
3848 register_emitter(op_ia32_Adc, bemit_adc);
3849 register_emitter(op_ia32_Add, bemit_add);
3850 register_emitter(op_ia32_AddMem, bemit_addmem);
3851 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3852 register_emitter(op_ia32_And, bemit_and);
3853 register_emitter(op_ia32_AndMem, bemit_andmem);
3854 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3855 register_emitter(op_ia32_Breakpoint, bemit_int3);
3856 register_emitter(op_ia32_CMov, bemit_cmov);
3857 register_emitter(op_ia32_Call, bemit_call);
3858 register_emitter(op_ia32_Cltd, bemit_cltd);
3859 register_emitter(op_ia32_Cmc, bemit_cmc);
3860 register_emitter(op_ia32_Cmp, bemit_cmp);
3861 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3862 register_emitter(op_ia32_Const, bemit_mov_const);
3863 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3864 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3865 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3866 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3867 register_emitter(op_ia32_Dec, bemit_dec);
3868 register_emitter(op_ia32_DecMem, bemit_decmem);
3869 register_emitter(op_ia32_Div, bemit_div);
3870 register_emitter(op_ia32_FldCW, bemit_fldcw);
3871 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3872 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3873 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3874 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3875 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3876 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3877 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3878 register_emitter(op_ia32_IDiv, bemit_idiv);
3879 register_emitter(op_ia32_IJmp, bemit_ijmp);
3880 register_emitter(op_ia32_IMul, bemit_imul);
3881 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3882 register_emitter(op_ia32_Inc, bemit_inc);
3883 register_emitter(op_ia32_IncMem, bemit_incmem);
3884 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3885 register_emitter(op_ia32_Jmp, bemit_jump);
3886 register_emitter(op_ia32_LdTls, bemit_ldtls);
3887 register_emitter(op_ia32_Lea, bemit_lea);
3888 register_emitter(op_ia32_Leave, bemit_leave);
3889 register_emitter(op_ia32_Load, bemit_load);
3890 register_emitter(op_ia32_Mul, bemit_mul);
3891 register_emitter(op_ia32_Neg, bemit_neg);
3892 register_emitter(op_ia32_NegMem, bemit_negmem);
3893 register_emitter(op_ia32_Not, bemit_not);
3894 register_emitter(op_ia32_NotMem, bemit_notmem);
3895 register_emitter(op_ia32_Or, bemit_or);
3896 register_emitter(op_ia32_OrMem, bemit_ormem);
3897 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3898 register_emitter(op_ia32_Pop, bemit_pop);
3899 register_emitter(op_ia32_PopEbp, bemit_pop);
3900 register_emitter(op_ia32_PopMem, bemit_popmem);
3901 register_emitter(op_ia32_Push, bemit_push);
3902 register_emitter(op_ia32_RepPrefix, bemit_rep);
3903 register_emitter(op_ia32_Rol, bemit_rol);
3904 register_emitter(op_ia32_RolMem, bemit_rolmem);
3905 register_emitter(op_ia32_Ror, bemit_ror);
3906 register_emitter(op_ia32_RorMem, bemit_rormem);
3907 register_emitter(op_ia32_Sahf, bemit_sahf);
3908 register_emitter(op_ia32_Sar, bemit_sar);
3909 register_emitter(op_ia32_SarMem, bemit_sarmem);
3910 register_emitter(op_ia32_Sbb, bemit_sbb);
3911 register_emitter(op_ia32_Set, bemit_set);
3912 register_emitter(op_ia32_Shl, bemit_shl);
3913 register_emitter(op_ia32_ShlD, bemit_shld);
3914 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3915 register_emitter(op_ia32_Shr, bemit_shr);
3916 register_emitter(op_ia32_ShrD, bemit_shrd);
3917 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3918 register_emitter(op_ia32_Stc, bemit_stc);
3919 register_emitter(op_ia32_Store, bemit_store);
3920 register_emitter(op_ia32_Store8Bit, bemit_store);
3921 register_emitter(op_ia32_Sub, bemit_sub);
3922 register_emitter(op_ia32_SubMem, bemit_submem);
3923 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3924 register_emitter(op_ia32_SubSP, bemit_subsp);
3925 register_emitter(op_ia32_Test, bemit_test);
3926 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3927 register_emitter(op_ia32_Xor, bemit_xor);
3928 register_emitter(op_ia32_Xor0, bemit_xor0);
3929 register_emitter(op_ia32_XorMem, bemit_xormem);
3930 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3931 register_emitter(op_ia32_fabs, bemit_fabs);
3932 register_emitter(op_ia32_fadd, bemit_fadd);
3933 register_emitter(op_ia32_faddp, bemit_faddp);
3934 register_emitter(op_ia32_fchs, bemit_fchs);
3935 register_emitter(op_ia32_fdiv, bemit_fdiv);
3936 register_emitter(op_ia32_fdivp, bemit_fdivp);
3937 register_emitter(op_ia32_fdivr, bemit_fdivr);
3938 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3939 register_emitter(op_ia32_fild, bemit_fild);
3940 register_emitter(op_ia32_fist, bemit_fist);
3941 register_emitter(op_ia32_fistp, bemit_fistp);
3942 register_emitter(op_ia32_fld, bemit_fld);
3943 register_emitter(op_ia32_fld1, bemit_fld1);
3944 register_emitter(op_ia32_fldz, bemit_fldz);
3945 register_emitter(op_ia32_fmul, bemit_fmul);
3946 register_emitter(op_ia32_fmulp, bemit_fmulp);
3947 register_emitter(op_ia32_fpop, bemit_fpop);
3948 register_emitter(op_ia32_fpush, bemit_fpush);
3949 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3950 register_emitter(op_ia32_fst, bemit_fst);
3951 register_emitter(op_ia32_fstp, bemit_fstp);
3952 register_emitter(op_ia32_fsub, bemit_fsub);
3953 register_emitter(op_ia32_fsubp, bemit_fsubp);
3954 register_emitter(op_ia32_fsubr, bemit_fsubr);
3955 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3956 register_emitter(op_ia32_fxch, bemit_fxch);
3958 /* ignore the following nodes */
3959 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3960 register_emitter(op_be_Barrier, emit_Nothing);
3961 register_emitter(op_be_Keep, emit_Nothing);
3962 register_emitter(op_be_Start, emit_Nothing);
3963 register_emitter(op_Phi, emit_Nothing);
3964 register_emitter(op_Start, emit_Nothing);
3967 static void gen_binary_block(ir_node *block)
3971 ia32_emit_block_header(block);
3973 /* emit the contents of the block */
3974 sched_foreach(block, node) {
3975 ia32_emit_node(node);
3979 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
3981 ir_entity *entity = get_irg_entity(irg);
3987 ia32_register_binary_emitters();
3989 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
3991 /* we use links to point to target blocks */
3992 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3993 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3995 /* initialize next block links */
3996 n = ARR_LEN(cg->blk_sched);
3997 for (i = 0; i < n; ++i) {
3998 ir_node *block = cg->blk_sched[i];
3999 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4001 set_irn_link(block, prev);
4004 for (i = 0; i < n; ++i) {
4005 ir_node *block = cg->blk_sched[i];
4006 gen_binary_block(block);
4009 be_gas_emit_function_epilog(entity);
4010 be_dbg_method_end();
4012 be_emit_write_line();
4014 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4020 void ia32_init_emitter(void)
4022 lc_opt_entry_t *be_grp;
4023 lc_opt_entry_t *ia32_grp;
4025 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4026 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4028 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4032 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");