2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
27 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
35 * pnc_Leg => NP (ordered)
57 #include "iredges_t.h"
61 #include "raw_bitset.h"
65 #include "../besched.h"
66 #include "../benode.h"
68 #include "../be_dbgout.h"
69 #include "../beemitter.h"
70 #include "../begnuas.h"
72 #include "../be_dbgout.h"
74 #include "ia32_emitter.h"
75 #include "ia32_common_transform.h"
76 #include "gen_ia32_emitter.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "ia32_nodes_attr.h"
79 #include "ia32_new_nodes.h"
80 #include "ia32_architecture.h"
81 #include "bearch_ia32_t.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
85 #define SNPRINTF_BUF_LEN 128
87 static const ia32_isa_t *isa;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_registers[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
210 * Emit the name of the 8bit low register
212 static void emit_8bit_register(const arch_register_t *reg)
214 const char *reg_name = arch_register_get_name(reg);
215 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
216 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
219 be_emit_char(reg_name[1]); /* get the basic name of the register */
224 * Emit the name of the 8bit high register
226 static void emit_8bit_register_high(const arch_register_t *reg)
228 const char *reg_name = arch_register_get_name(reg);
229 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
230 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
233 be_emit_char(reg_name[1]); /* get the basic name of the register */
237 static void emit_16bit_register(const arch_register_t *reg)
239 const char *reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
246 * emit a register, possible shortened by a mode
248 * @param reg the register
249 * @param mode the mode of the register or NULL for full register
251 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
253 const char *reg_name;
256 int size = get_mode_size_bits(mode);
258 case 8: emit_8bit_register(reg); return;
259 case 16: emit_16bit_register(reg); return;
261 assert(mode_is_float(mode) || size == 32);
264 reg_name = arch_register_get_name(reg);
267 be_emit_string(reg_name);
270 void ia32_emit_source_register(const ir_node *node, int pos)
272 const arch_register_t *reg = get_in_reg(node, pos);
274 emit_register(reg, NULL);
277 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
279 be_gas_emit_entity(entity);
281 if (get_entity_owner(entity) == get_tls_type()) {
282 if (get_entity_visibility(entity) == ir_visibility_external) {
283 be_emit_cstring("@INDNTPOFF");
285 be_emit_cstring("@NTPOFF");
289 if (do_pic && !no_pic_adjust) {
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const arch_register_t *reg = get_in_reg(node, pos);
335 emit_8bit_register_high(reg);
338 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
340 const arch_register_t *reg;
341 const ir_node *in = get_irn_n(node, pos);
342 if (is_ia32_Immediate(in)) {
343 emit_ia32_Immediate(in);
347 reg = get_in_reg(node, pos);
348 emit_16bit_register(reg);
351 void ia32_emit_dest_register(const ir_node *node, int pos)
353 const arch_register_t *reg = get_out_reg(node, pos);
355 emit_register(reg, NULL);
358 void ia32_emit_dest_register_size(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, get_ia32_ls_mode(node));
365 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, mode_Bu);
372 void ia32_emit_x87_register(const ir_node *node, int pos)
374 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
378 be_emit_string(attr->x87[pos]->name);
381 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
383 assert(mode_is_int(mode) || mode_is_reference(mode));
384 switch (get_mode_size_bits(mode)) {
385 case 8: be_emit_char('b'); return;
386 case 16: be_emit_char('w'); return;
387 case 32: be_emit_char('l'); return;
388 /* gas docu says q is the suffix but gcc, objdump and icc use ll
390 case 64: be_emit_cstring("ll"); return;
392 panic("Can't output mode_suffix for %+F", mode);
395 void ia32_emit_mode_suffix(const ir_node *node)
397 ir_mode *mode = get_ia32_ls_mode(node);
401 ia32_emit_mode_suffix_mode(mode);
404 void ia32_emit_x87_mode_suffix(const ir_node *node)
408 /* we only need to emit the mode on address mode */
409 if (get_ia32_op_type(node) == ia32_Normal)
412 mode = get_ia32_ls_mode(node);
413 assert(mode != NULL);
415 if (mode_is_float(mode)) {
416 switch (get_mode_size_bits(mode)) {
417 case 32: be_emit_char('s'); return;
418 case 64: be_emit_char('l'); return;
419 /* long doubles have different sizes due to alignment on different
423 case 128: be_emit_char('t'); return;
426 assert(mode_is_int(mode) || mode_is_reference(mode));
427 switch (get_mode_size_bits(mode)) {
428 case 16: be_emit_char('s'); return;
429 case 32: be_emit_char('l'); return;
430 /* gas docu says q is the suffix but gcc, objdump and icc use ll
432 case 64: be_emit_cstring("ll"); return;
435 panic("Can't output mode_suffix for %+F", mode);
438 static char get_xmm_mode_suffix(ir_mode *mode)
440 assert(mode_is_float(mode));
441 switch (get_mode_size_bits(mode)) {
444 default: panic("Invalid XMM mode");
448 void ia32_emit_xmm_mode_suffix(const ir_node *node)
450 ir_mode *mode = get_ia32_ls_mode(node);
451 assert(mode != NULL);
453 be_emit_char(get_xmm_mode_suffix(mode));
456 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
458 ir_mode *mode = get_ia32_ls_mode(node);
459 assert(mode != NULL);
460 be_emit_char(get_xmm_mode_suffix(mode));
463 void ia32_emit_extend_suffix(const ir_node *node)
465 ir_mode *mode = get_ia32_ls_mode(node);
466 if (get_mode_size_bits(mode) == 32)
468 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
469 ia32_emit_mode_suffix_mode(mode);
472 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
474 ir_node *in = get_irn_n(node, pos);
475 if (is_ia32_Immediate(in)) {
476 emit_ia32_Immediate(in);
478 const ir_mode *mode = get_ia32_ls_mode(node);
479 const arch_register_t *reg = get_in_reg(node, pos);
480 emit_register(reg, mode);
485 * Returns the target block for a control flow node.
487 static ir_node *get_cfop_target_block(const ir_node *irn)
489 assert(get_irn_mode(irn) == mode_X);
490 return (ir_node*)get_irn_link(irn);
494 * Emits the target label for a control flow node.
496 static void ia32_emit_cfop_target(const ir_node *node)
498 ir_node *block = get_cfop_target_block(node);
499 be_gas_emit_block_name(block);
503 * Emit the suffix for a compare instruction.
505 static void ia32_emit_condition_code(ia32_condition_code_t cc)
508 case ia32_cc_overflow: be_emit_cstring("o"); return;
509 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
510 case ia32_cc_float_below:
511 case ia32_cc_float_unordered_below:
512 case ia32_cc_below: be_emit_cstring("b"); return;
513 case ia32_cc_float_above_equal:
514 case ia32_cc_float_unordered_above_equal:
515 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
516 case ia32_cc_float_equal:
517 case ia32_cc_equal: be_emit_cstring("e"); return;
518 case ia32_cc_float_not_equal:
519 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
520 case ia32_cc_float_below_equal:
521 case ia32_cc_float_unordered_below_equal:
522 case ia32_cc_below_equal: be_emit_cstring("be"); return;
523 case ia32_cc_float_above:
524 case ia32_cc_float_unordered_above:
525 case ia32_cc_above: be_emit_cstring("a"); return;
526 case ia32_cc_sign: be_emit_cstring("s"); return;
527 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
528 case ia32_cc_parity: be_emit_cstring("p"); return;
529 case ia32_cc_not_parity: be_emit_cstring("np"); return;
530 case ia32_cc_less: be_emit_cstring("l"); return;
531 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
532 case ia32_cc_less_equal: be_emit_cstring("le"); return;
533 case ia32_cc_greater: be_emit_cstring("g"); return;
534 case ia32_cc_float_parity_cases:
535 case ia32_cc_additional_float_cases:
538 panic("Invalid ia32 condition code");
541 typedef enum ia32_emit_mod_t {
543 EMIT_RESPECT_LS = 1U << 0,
544 EMIT_ALTERNATE_AM = 1U << 1,
546 EMIT_HIGH_REG = 1U << 3,
547 EMIT_LOW_REG = 1U << 4
549 ENUM_BITSET(ia32_emit_mod_t)
552 * Emits address mode.
554 void ia32_emit_am(const ir_node *node)
556 ir_entity *ent = get_ia32_am_sc(node);
557 int offs = get_ia32_am_offs_int(node);
558 ir_node *base = get_irn_n(node, n_ia32_base);
559 int has_base = !is_ia32_NoReg_GP(base);
560 ir_node *index = get_irn_n(node, n_ia32_index);
561 int has_index = !is_ia32_NoReg_GP(index);
563 /* just to be sure... */
564 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
568 const ia32_attr_t *attr = get_ia32_attr_const(node);
569 if (is_ia32_am_sc_sign(node))
571 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
574 /* also handle special case if nothing is set */
575 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
577 be_emit_irprintf("%+d", offs);
579 be_emit_irprintf("%d", offs);
583 if (has_base || has_index) {
588 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
589 emit_register(reg, NULL);
592 /* emit index + scale */
594 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
597 emit_register(reg, NULL);
599 scale = get_ia32_am_scale(node);
601 be_emit_irprintf(",%d", 1 << scale);
609 * fmt parameter output
610 * ---- ---------------------- ---------------------------------------------
612 * %AM <node> address mode of the node
613 * %AR const arch_register_t* address mode of the node or register
614 * %ASx <node> address mode of the node or source register x
615 * %Dx <node> destination register x
616 * %I <node> immediate of the node
617 * %L <node> control flow target of the node
618 * %M <node> mode suffix of the node
619 * %P int condition code
620 * %R const arch_register_t* register
621 * %Sx <node> source register x
622 * %s const char* string
623 * %u unsigned int unsigned int
624 * %d signed int signed int
627 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
628 * * modifier does not prefix immediates with $, but AM with *
629 * l modifier for %lu and %ld
630 * > modifier to output high 8bit register (ah, bh)
631 * < modifier to output low 8bit register (al, bl)
633 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
639 const char *start = fmt;
640 ia32_emit_mod_t mod = EMIT_NONE;
642 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
645 be_emit_string_len(start, fmt - start);
649 be_emit_finish_line_gas(node);
662 case '*': mod |= EMIT_ALTERNATE_AM; break;
663 case '#': mod |= EMIT_RESPECT_LS; break;
664 case 'l': mod |= EMIT_LONG; break;
665 case '>': mod |= EMIT_HIGH_REG; break;
666 case '<': mod |= EMIT_LOW_REG; break;
683 if (mod & EMIT_ALTERNATE_AM)
689 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
690 if (get_ia32_op_type(node) == ia32_AddrModeS) {
693 if (mod & EMIT_ALTERNATE_AM)
695 emit_register(reg, NULL);
701 if (get_ia32_op_type(node) == ia32_AddrModeS) {
705 assert(get_ia32_op_type(node) == ia32_Normal);
710 default: goto unknown;
717 const arch_register_t *reg;
719 if (*fmt < '0' || '9' <= *fmt)
723 reg = get_out_reg(node, pos);
724 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
729 if (!(mod & EMIT_ALTERNATE_AM))
731 emit_ia32_Immediate_no_prefix(node);
735 ia32_emit_cfop_target(node);
739 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
744 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
745 ia32_emit_condition_code(cc);
750 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
751 if (mod & EMIT_HIGH_REG) {
752 emit_8bit_register_high(reg);
753 } else if (mod & EMIT_LOW_REG) {
754 emit_8bit_register(reg);
756 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
766 if (*fmt < '0' || '9' <= *fmt)
770 in = get_irn_n(node, pos);
771 if (is_ia32_Immediate(in)) {
772 if (!(mod & EMIT_ALTERNATE_AM))
774 emit_ia32_Immediate_no_prefix(in);
776 const arch_register_t *reg;
778 if (mod & EMIT_ALTERNATE_AM)
780 reg = get_in_reg(node, pos);
781 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
787 const char *str = va_arg(ap, const char*);
793 if (mod & EMIT_LONG) {
794 unsigned long num = va_arg(ap, unsigned long);
795 be_emit_irprintf("%lu", num);
797 unsigned num = va_arg(ap, unsigned);
798 be_emit_irprintf("%u", num);
803 if (mod & EMIT_LONG) {
804 long num = va_arg(ap, long);
805 be_emit_irprintf("%ld", num);
807 int num = va_arg(ap, int);
808 be_emit_irprintf("%d", num);
814 panic("unknown format conversion in ia32_emitf()");
822 * Emits registers and/or address mode of a binary operation.
824 void ia32_emit_binop(const ir_node *node)
826 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
827 ia32_emitf(node, "%#S4, %#AS3");
829 ia32_emitf(node, "%#AS4, %#S3");
834 * Emits registers and/or address mode of a binary operation.
836 void ia32_emit_x87_binop(const ir_node *node)
838 switch (get_ia32_op_type(node)) {
841 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
842 const arch_register_t *in1 = x87_attr->x87[0];
843 const arch_register_t *in = x87_attr->x87[1];
844 const arch_register_t *out = x87_attr->x87[2];
848 } else if (out == in) {
853 be_emit_string(arch_register_get_name(in));
854 be_emit_cstring(", %");
855 be_emit_string(arch_register_get_name(out));
863 assert(0 && "unsupported op type");
868 * Emits registers and/or address mode of a unary operation.
870 void ia32_emit_unop(const ir_node *node, int pos)
874 ia32_emitf(node, fmt);
877 static void emit_ia32_IMul(const ir_node *node)
879 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
880 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
882 /* do we need the 3-address form? */
883 if (is_ia32_NoReg_GP(left) ||
884 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
885 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
887 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
892 * walks up a tree of copies/perms/spills/reloads to find the original value
893 * that is moved around
895 static ir_node *find_original_value(ir_node *node)
897 if (irn_visited(node))
900 mark_irn_visited(node);
901 if (be_is_Copy(node)) {
902 return find_original_value(be_get_Copy_op(node));
903 } else if (be_is_CopyKeep(node)) {
904 return find_original_value(be_get_CopyKeep_op(node));
905 } else if (is_Proj(node)) {
906 ir_node *pred = get_Proj_pred(node);
907 if (be_is_Perm(pred)) {
908 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
909 } else if (be_is_MemPerm(pred)) {
910 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
911 } else if (is_ia32_Load(pred)) {
912 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
916 } else if (is_ia32_Store(node)) {
917 return find_original_value(get_irn_n(node, n_ia32_Store_val));
918 } else if (is_Phi(node)) {
920 arity = get_irn_arity(node);
921 for (i = 0; i < arity; ++i) {
922 ir_node *in = get_irn_n(node, i);
923 ir_node *res = find_original_value(in);
934 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
936 ir_node *flags = get_irn_n(node, flags_pos);
937 const ia32_attr_t *flags_attr;
938 flags = skip_Proj(flags);
940 if (is_ia32_Sahf(flags)) {
941 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
942 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
943 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
944 inc_irg_visited(current_ir_graph);
945 cmp = find_original_value(cmp);
947 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
948 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
951 flags_attr = get_ia32_attr_const(cmp);
953 flags_attr = get_ia32_attr_const(flags);
956 if (flags_attr->data.ins_permuted)
957 cc = ia32_invert_condition_code(cc);
961 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
963 ia32_condition_code_t cc = get_ia32_condcode(node);
964 cc = determine_final_cc(node, flags_pos, cc);
966 ia32_emit_condition_code(cc);
970 * Emits an exception label for a given node.
972 static void ia32_emit_exc_label(const ir_node *node)
974 be_emit_string(be_gas_insn_label_prefix());
975 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
979 * Returns the Proj with projection number proj and NOT mode_M
981 static ir_node *get_proj(const ir_node *node, long proj)
983 const ir_edge_t *edge;
986 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
988 foreach_out_edge(node, edge) {
989 src = get_edge_src_irn(edge);
991 assert(is_Proj(src) && "Proj expected");
992 if (get_irn_mode(src) == mode_M)
995 if (get_Proj_proj(src) == proj)
1001 static int can_be_fallthrough(const ir_node *node)
1003 ir_node *target_block = get_cfop_target_block(node);
1004 ir_node *block = get_nodes_block(node);
1005 return get_prev_block_sched(target_block) == block;
1009 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1011 static void emit_ia32_Jcc(const ir_node *node)
1013 int need_parity_label = 0;
1014 ia32_condition_code_t cc = get_ia32_condcode(node);
1015 const ir_node *proj_true;
1016 const ir_node *proj_false;
1018 cc = determine_final_cc(node, 0, cc);
1020 /* get both Projs */
1021 proj_true = get_proj(node, pn_ia32_Jcc_true);
1022 assert(proj_true && "Jcc without true Proj");
1024 proj_false = get_proj(node, pn_ia32_Jcc_false);
1025 assert(proj_false && "Jcc without false Proj");
1027 if (can_be_fallthrough(proj_true)) {
1028 /* exchange both proj's so the second one can be omitted */
1029 const ir_node *t = proj_true;
1031 proj_true = proj_false;
1033 cc = ia32_negate_condition_code(cc);
1036 if (cc & ia32_cc_float_parity_cases) {
1037 /* Some floating point comparisons require a test of the parity flag,
1038 * which indicates that the result is unordered */
1039 if (cc & ia32_cc_negated) {
1040 ia32_emitf(proj_true, "\tjp %L\n");
1042 /* we need a local label if the false proj is a fallthrough
1043 * as the falseblock might have no label emitted then */
1044 if (can_be_fallthrough(proj_false)) {
1045 need_parity_label = 1;
1046 ia32_emitf(proj_false, "\tjp 1f\n");
1048 ia32_emitf(proj_false, "\tjp %L\n");
1052 ia32_emitf(proj_true, "\tj%P %L\n", cc);
1053 if (need_parity_label) {
1054 ia32_emitf(NULL, "1:\n");
1057 /* the second Proj might be a fallthrough */
1058 if (can_be_fallthrough(proj_false)) {
1059 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1061 ia32_emitf(proj_false, "\tjmp %L\n");
1066 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1069 static void emit_ia32_Setcc(const ir_node *node)
1071 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1073 ia32_condition_code_t cc = get_ia32_condcode(node);
1074 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1075 if (cc & ia32_cc_float_parity_cases) {
1076 if (cc & ia32_cc_negated) {
1077 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1078 ia32_emitf(node, "\tsetp %>R\n", dreg);
1079 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1081 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1082 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1083 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1086 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1090 static void emit_ia32_CMovcc(const ir_node *node)
1092 const ia32_attr_t *attr = get_ia32_attr_const(node);
1093 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1094 ia32_condition_code_t cc = get_ia32_condcode(node);
1095 const arch_register_t *in_true;
1096 const arch_register_t *in_false;
1098 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1099 /* although you can't set ins_permuted in the constructor it might still
1100 * be set by memory operand folding
1101 * Permuting inputs of a cmov means the condition is negated!
1103 if (attr->data.ins_permuted)
1104 cc = ia32_negate_condition_code(cc);
1106 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1107 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1109 /* should be same constraint fullfilled? */
1110 if (out == in_false) {
1111 /* yes -> nothing to do */
1112 } else if (out == in_true) {
1113 const arch_register_t *tmp;
1115 assert(get_ia32_op_type(node) == ia32_Normal);
1117 cc = ia32_negate_condition_code(cc);
1124 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1127 if (cc & ia32_cc_float_parity_cases) {
1128 panic("CMov with floatingpoint compare/parity not supported yet");
1131 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1135 /* jump table entry (target and corresponding number) */
1136 typedef struct branch_t {
1141 /* jump table for switch generation */
1142 typedef struct jmp_tbl_t {
1143 ir_node *defProj; /**< default target */
1144 long min_value; /**< smallest switch case */
1145 long max_value; /**< largest switch case */
1146 long num_branches; /**< number of jumps */
1147 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1148 branch_t *branches; /**< jump array */
1152 * Compare two variables of type branch_t. Used to sort all switch cases
1154 static int ia32_cmp_branch_t(const void *a, const void *b)
1156 branch_t *b1 = (branch_t *)a;
1157 branch_t *b2 = (branch_t *)b;
1159 if (b1->value <= b2->value)
1165 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1168 long default_pn = get_ia32_default_pn(node);
1170 const ir_edge_t *edge;
1172 /* fill the table structure */
1173 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1174 tbl->defProj = NULL;
1175 tbl->num_branches = get_irn_n_edges(node) - 1;
1176 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1177 tbl->min_value = LONG_MAX;
1178 tbl->max_value = LONG_MIN;
1181 /* go over all proj's and collect them */
1182 foreach_out_edge(node, edge) {
1184 proj = get_edge_src_irn(edge);
1185 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1187 pn = get_Proj_proj(proj);
1189 /* check for default proj */
1190 if (pn == default_pn) {
1191 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1192 tbl->defProj = proj;
1194 tbl->min_value = pn < tbl->min_value ? pn : tbl->min_value;
1195 tbl->max_value = pn > tbl->max_value ? pn : tbl->max_value;
1197 /* create branch entry */
1198 tbl->branches[i].target = proj;
1199 tbl->branches[i].value = pn;
1204 assert(i == tbl->num_branches);
1206 /* sort the branches by their number */
1207 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1211 * Emits code for a SwitchJmp (creates a jump table if
1212 * possible otherwise a cmp-jmp cascade). Port from
1215 static void emit_ia32_SwitchJmp(const ir_node *node)
1217 unsigned long interval;
1221 /* fill the table structure */
1222 generate_jump_table(&tbl, node);
1224 /* two-complement's magic make this work without overflow */
1225 interval = tbl.max_value - tbl.min_value;
1227 /* emit the table */
1228 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1229 ia32_emitf(tbl.defProj, "\tja %L\n");
1231 if (tbl.num_branches > 1) {
1233 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1235 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1236 ia32_emitf(NULL, "\t.align 4\n");
1237 ia32_emitf(NULL, "%s:\n", tbl.label);
1239 last_value = tbl.branches[0].value;
1240 for (i = 0; i != tbl.num_branches; ++i) {
1241 while (last_value != tbl.branches[i].value) {
1242 ia32_emitf(tbl.defProj, ".long %L\n");
1245 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1248 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1250 /* one jump is enough */
1251 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1258 * Emits code for a unconditional jump.
1260 static void emit_ia32_Jmp(const ir_node *node)
1264 /* for now, the code works for scheduled and non-schedules blocks */
1265 block = get_nodes_block(node);
1267 /* we have a block schedule */
1268 if (can_be_fallthrough(node)) {
1269 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1271 ia32_emitf(node, "\tjmp %L\n");
1276 * Emit an inline assembler operand.
1278 * @param node the ia32_ASM node
1279 * @param s points to the operand (a %c)
1281 * @return pointer to the first char in s NOT in the current operand
1283 static const char* emit_asm_operand(const ir_node *node, const char *s)
1285 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1286 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1288 const arch_register_t *reg;
1289 const ia32_asm_reg_t *asm_regs = attr->register_map;
1290 const ia32_asm_reg_t *asm_reg;
1299 /* parse modifiers */
1302 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1327 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1334 if (sscanf(s, "%d%n", &num, &p) != 1) {
1335 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1342 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1344 "Error: Custom assembler references invalid input/output (%+F)\n",
1348 asm_reg = & asm_regs[num];
1349 assert(asm_reg->valid);
1352 if (asm_reg->use_input == 0) {
1353 reg = get_out_reg(node, asm_reg->inout_pos);
1355 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1357 /* might be an immediate value */
1358 if (is_ia32_Immediate(pred)) {
1359 emit_ia32_Immediate(pred);
1362 reg = get_in_reg(node, asm_reg->inout_pos);
1366 "Warning: no register assigned for %d asm op (%+F)\n",
1371 if (asm_reg->memory) {
1376 if (modifier != 0) {
1379 emit_8bit_register(reg);
1382 emit_8bit_register_high(reg);
1385 emit_16bit_register(reg);
1388 panic("Invalid asm op modifier");
1391 emit_register(reg, asm_reg->mode);
1394 if (asm_reg->memory) {
1402 * Emits code for an ASM pseudo op.
1404 static void emit_ia32_Asm(const ir_node *node)
1406 const void *gen_attr = get_irn_generic_attr_const(node);
1407 const ia32_asm_attr_t *attr
1408 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1409 ident *asm_text = attr->asm_text;
1410 const char *s = get_id_str(asm_text);
1412 ia32_emitf(node, "#APP\t\n");
1419 s = emit_asm_operand(node, s);
1425 ia32_emitf(NULL, "\n#NO_APP\n");
1430 * Emit movsb/w instructions to make mov count divideable by 4
1432 static void emit_CopyB_prolog(unsigned size)
1435 ia32_emitf(NULL, "\tmovsb\n");
1437 ia32_emitf(NULL, "\tmovsw\n");
1441 * Emit rep movsd instruction for memcopy.
1443 static void emit_ia32_CopyB(const ir_node *node)
1445 unsigned size = get_ia32_copyb_size(node);
1447 emit_CopyB_prolog(size);
1448 ia32_emitf(node, "\trep movsd\n");
1452 * Emits unrolled memcopy.
1454 static void emit_ia32_CopyB_i(const ir_node *node)
1456 unsigned size = get_ia32_copyb_size(node);
1458 emit_CopyB_prolog(size);
1462 ia32_emitf(NULL, "\tmovsd\n");
1468 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1470 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1473 ir_mode *ls_mode = get_ia32_ls_mode(node);
1474 int ls_bits = get_mode_size_bits(ls_mode);
1475 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1477 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1480 static void emit_ia32_Conv_I2FP(const ir_node *node)
1482 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1485 static void emit_ia32_Conv_FP2I(const ir_node *node)
1487 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1490 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1492 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1496 * Emits code for an Int conversion.
1498 static void emit_ia32_Conv_I2I(const ir_node *node)
1500 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1501 int signed_mode = mode_is_signed(smaller_mode);
1502 const char *sign_suffix;
1504 assert(!mode_is_float(smaller_mode));
1506 sign_suffix = signed_mode ? "s" : "z";
1507 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1513 static void emit_ia32_Call(const ir_node *node)
1515 /* Special case: Call must not have its immediates prefixed by $, instead
1516 * address mode is prefixed by *. */
1517 ia32_emitf(node, "\tcall %*AS3\n");
1522 * Emits code to increase stack pointer.
1524 static void emit_be_IncSP(const ir_node *node)
1526 int offs = be_get_IncSP_offset(node);
1532 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1534 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1539 * Emits code for Copy/CopyKeep.
1541 static void Copy_emitter(const ir_node *node, const ir_node *op)
1543 const arch_register_t *in = arch_get_irn_register(op);
1544 const arch_register_t *out = arch_get_irn_register(node);
1549 /* copies of vf nodes aren't real... */
1550 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1553 if (get_irn_mode(node) == mode_E) {
1554 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1556 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1560 static void emit_be_Copy(const ir_node *node)
1562 Copy_emitter(node, be_get_Copy_op(node));
1565 static void emit_be_CopyKeep(const ir_node *node)
1567 Copy_emitter(node, be_get_CopyKeep_op(node));
1571 * Emits code for exchange.
1573 static void emit_be_Perm(const ir_node *node)
1575 const arch_register_t *in0, *in1;
1576 const arch_register_class_t *cls0, *cls1;
1578 in0 = arch_get_irn_register(get_irn_n(node, 0));
1579 in1 = arch_get_irn_register(get_irn_n(node, 1));
1581 cls0 = arch_register_get_class(in0);
1582 cls1 = arch_register_get_class(in1);
1584 assert(cls0 == cls1 && "Register class mismatch at Perm");
1586 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1587 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1588 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1589 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1590 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1591 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1592 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1594 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1597 panic("unexpected register class in be_Perm (%+F)", node);
1602 * Emits code for Constant loading.
1604 static void emit_ia32_Const(const ir_node *node)
1606 ia32_emitf(node, "\tmovl %I, %D0\n");
1610 * Emits code to load the TLS base
1612 static void emit_ia32_LdTls(const ir_node *node)
1614 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1617 /* helper function for emit_ia32_Minus64Bit */
1618 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1620 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1623 /* helper function for emit_ia32_Minus64Bit */
1624 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1626 ia32_emitf(node, "\tnegl %R\n", reg);
1629 /* helper function for emit_ia32_Minus64Bit */
1630 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1632 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1635 /* helper function for emit_ia32_Minus64Bit */
1636 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1638 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1641 /* helper function for emit_ia32_Minus64Bit */
1642 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1644 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1647 /* helper function for emit_ia32_Minus64Bit */
1648 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1650 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1653 static void emit_ia32_Minus64Bit(const ir_node *node)
1655 const arch_register_t *in_lo = get_in_reg(node, 0);
1656 const arch_register_t *in_hi = get_in_reg(node, 1);
1657 const arch_register_t *out_lo = get_out_reg(node, 0);
1658 const arch_register_t *out_hi = get_out_reg(node, 1);
1660 if (out_lo == in_lo) {
1661 if (out_hi != in_hi) {
1662 /* a -> a, b -> d */
1665 /* a -> a, b -> b */
1668 } else if (out_lo == in_hi) {
1669 if (out_hi == in_lo) {
1670 /* a -> b, b -> a */
1671 emit_xchg(node, in_lo, in_hi);
1674 /* a -> b, b -> d */
1675 emit_mov(node, in_hi, out_hi);
1676 emit_mov(node, in_lo, out_lo);
1680 if (out_hi == in_lo) {
1681 /* a -> c, b -> a */
1682 emit_mov(node, in_lo, out_lo);
1684 } else if (out_hi == in_hi) {
1685 /* a -> c, b -> b */
1686 emit_mov(node, in_lo, out_lo);
1689 /* a -> c, b -> d */
1690 emit_mov(node, in_lo, out_lo);
1696 emit_neg( node, out_hi);
1697 emit_neg( node, out_lo);
1698 emit_sbb0(node, out_hi);
1702 emit_zero(node, out_hi);
1703 emit_neg( node, out_lo);
1704 emit_sbb( node, in_hi, out_hi);
1707 static void emit_ia32_GetEIP(const ir_node *node)
1709 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1710 ia32_emitf(NULL, "%s:\n", pic_base_label);
1711 ia32_emitf(node, "\tpopl %D0\n");
1714 static void emit_ia32_ClimbFrame(const ir_node *node)
1716 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1718 ia32_emitf(node, "\tmovl %S0, %D0\n");
1719 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1720 be_gas_emit_block_name(node);
1721 be_emit_cstring(":\n");
1722 be_emit_write_line();
1723 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1724 ia32_emitf(node, "\tdec %S1\n");
1725 be_emit_cstring("\tjnz ");
1726 be_gas_emit_block_name(node);
1727 be_emit_finish_line_gas(node);
1730 static void emit_be_Return(const ir_node *node)
1732 unsigned pop = be_Return_get_pop(node);
1734 if (pop > 0 || be_Return_get_emit_pop(node)) {
1735 ia32_emitf(node, "\tret $%u\n", pop);
1737 ia32_emitf(node, "\tret\n");
1741 static void emit_Nothing(const ir_node *node)
1748 * Enters the emitter functions for handled nodes into the generic
1749 * pointer of an opcode.
1751 static void ia32_register_emitters(void)
1753 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1754 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1755 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1756 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1757 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1758 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1760 /* first clear the generic function pointer for all ops */
1761 clear_irp_opcodes_generic_func();
1763 /* register all emitter functions defined in spec */
1764 ia32_register_spec_emitters();
1766 /* other ia32 emitter functions */
1767 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1772 IA32_EMIT(Conv_FP2FP);
1773 IA32_EMIT(Conv_FP2I);
1774 IA32_EMIT(Conv_I2FP);
1775 IA32_EMIT(Conv_I2I);
1783 IA32_EMIT(Minus64Bit);
1784 IA32_EMIT(SwitchJmp);
1785 IA32_EMIT(ClimbFrame);
1788 /* benode emitter */
1808 typedef void (*emit_func_ptr) (const ir_node *);
1811 * Assign and emit an exception label if the current instruction can fail.
1813 static void ia32_assign_exc_label(ir_node *node)
1815 /* assign a new ID to the instruction */
1816 set_ia32_exc_label_id(node, ++exc_label_id);
1818 ia32_emit_exc_label(node);
1820 be_emit_pad_comment();
1821 be_emit_cstring("/* exception to Block ");
1822 ia32_emit_cfop_target(node);
1823 be_emit_cstring(" */\n");
1824 be_emit_write_line();
1828 * Emits code for a node.
1830 static void ia32_emit_node(ir_node *node)
1832 ir_op *op = get_irn_op(node);
1834 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1836 if (is_ia32_irn(node)) {
1837 if (get_ia32_exc_label(node)) {
1838 /* emit the exception label of this instruction */
1839 ia32_assign_exc_label(node);
1841 if (mark_spill_reload) {
1842 if (is_ia32_is_spill(node)) {
1843 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1845 if (is_ia32_is_reload(node)) {
1846 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1848 if (is_ia32_is_remat(node)) {
1849 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1853 if (op->ops.generic) {
1854 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1856 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1861 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1867 * Emits gas alignment directives
1869 static void ia32_emit_alignment(unsigned align, unsigned skip)
1871 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1875 * Emits gas alignment directives for Labels depended on cpu architecture.
1877 static void ia32_emit_align_label(void)
1879 unsigned align = ia32_cg_config.label_alignment;
1880 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1881 ia32_emit_alignment(align, maximum_skip);
1885 * Test whether a block should be aligned.
1886 * For cpus in the P4/Athlon class it is useful to align jump labels to
1887 * 16 bytes. However we should only do that if the alignment nops before the
1888 * label aren't executed more often than we have jumps to the label.
1890 static int should_align_block(const ir_node *block)
1892 static const double DELTA = .0001;
1893 ir_graph *irg = get_irn_irg(block);
1894 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1895 ir_node *prev = get_prev_block_sched(block);
1897 double prev_freq = 0; /**< execfreq of the fallthrough block */
1898 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1901 if (exec_freq == NULL)
1903 if (ia32_cg_config.label_alignment_factor <= 0)
1906 block_freq = get_block_execfreq(exec_freq, block);
1907 if (block_freq < DELTA)
1910 n_cfgpreds = get_Block_n_cfgpreds(block);
1911 for (i = 0; i < n_cfgpreds; ++i) {
1912 const ir_node *pred = get_Block_cfgpred_block(block, i);
1913 double pred_freq = get_block_execfreq(exec_freq, pred);
1916 prev_freq += pred_freq;
1918 jmp_freq += pred_freq;
1922 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1925 jmp_freq /= prev_freq;
1927 return jmp_freq > ia32_cg_config.label_alignment_factor;
1931 * Emit the block header for a block.
1933 * @param block the block
1934 * @param prev_block the previous block
1936 static void ia32_emit_block_header(ir_node *block)
1938 ir_graph *irg = current_ir_graph;
1939 int need_label = block_needs_label(block);
1941 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1943 if (block == get_irg_end_block(irg))
1946 if (ia32_cg_config.label_alignment > 0) {
1947 /* align the current block if:
1948 * a) if should be aligned due to its execution frequency
1949 * b) there is no fall-through here
1951 if (should_align_block(block)) {
1952 ia32_emit_align_label();
1954 /* if the predecessor block has no fall-through,
1955 we can always align the label. */
1957 int has_fallthrough = 0;
1959 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1960 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1961 if (can_be_fallthrough(cfg_pred)) {
1962 has_fallthrough = 1;
1967 if (!has_fallthrough)
1968 ia32_emit_align_label();
1973 be_gas_emit_block_name(block);
1976 be_emit_pad_comment();
1977 be_emit_cstring(" /* ");
1979 be_emit_cstring("\t/* ");
1980 be_gas_emit_block_name(block);
1981 be_emit_cstring(": ");
1984 be_emit_cstring("preds:");
1986 /* emit list of pred blocks in comment */
1987 arity = get_irn_arity(block);
1989 be_emit_cstring(" none");
1991 for (i = 0; i < arity; ++i) {
1992 ir_node *predblock = get_Block_cfgpred_block(block, i);
1993 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1996 if (exec_freq != NULL) {
1997 be_emit_irprintf(", freq: %f",
1998 get_block_execfreq(exec_freq, block));
2000 be_emit_cstring(" */\n");
2001 be_emit_write_line();
2005 * Walks over the nodes in a block connected by scheduling edges
2006 * and emits code for each node.
2008 static void ia32_gen_block(ir_node *block)
2012 ia32_emit_block_header(block);
2014 /* emit the contents of the block */
2015 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2016 sched_foreach(block, node) {
2017 ia32_emit_node(node);
2021 typedef struct exc_entry {
2022 ir_node *exc_instr; /** The instruction that can issue an exception. */
2023 ir_node *block; /** The block to call then. */
2028 * Sets labels for control flow nodes (jump target).
2029 * Links control predecessors to there destination blocks.
2031 static void ia32_gen_labels(ir_node *block, void *data)
2033 exc_entry **exc_list = (exc_entry**)data;
2037 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2038 pred = get_Block_cfgpred(block, n);
2039 set_irn_link(pred, block);
2041 pred = skip_Proj(pred);
2042 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2047 ARR_APP1(exc_entry, *exc_list, e);
2048 set_irn_link(pred, block);
2054 * Compare two exception_entries.
2056 static int cmp_exc_entry(const void *a, const void *b)
2058 const exc_entry *ea = (const exc_entry*)a;
2059 const exc_entry *eb = (const exc_entry*)b;
2061 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2067 * Main driver. Emits the code for one routine.
2069 void ia32_gen_routine(ir_graph *irg)
2071 ir_entity *entity = get_irg_entity(irg);
2072 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2073 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2074 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
2075 ir_node **blk_sched = irg_data->blk_sched;
2078 isa = (ia32_isa_t*) arch_env;
2079 do_pic = be_get_irg_options(irg)->pic;
2081 be_gas_elf_type_char = '@';
2083 ia32_register_emitters();
2085 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2087 be_dbg_method_begin(entity);
2088 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2090 /* we use links to point to target blocks */
2091 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2092 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2094 /* initialize next block links */
2095 n = ARR_LEN(blk_sched);
2096 for (i = 0; i < n; ++i) {
2097 ir_node *block = blk_sched[i];
2098 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
2100 set_irn_link(block, prev);
2103 for (i = 0; i < n; ++i) {
2104 ir_node *block = blk_sched[i];
2106 ia32_gen_block(block);
2109 be_gas_emit_function_epilog(entity);
2110 be_dbg_method_end();
2112 be_emit_write_line();
2114 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2116 /* Sort the exception table using the exception label id's.
2117 Those are ascending with ascending addresses. */
2118 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2122 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2123 be_emit_cstring("\t.long ");
2124 ia32_emit_exc_label(exc_list[i].exc_instr);
2126 be_emit_cstring("\t.long ");
2127 be_gas_emit_block_name(exc_list[i].block);
2131 DEL_ARR_F(exc_list);
2134 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2135 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2139 /* ==== Experimental binary emitter ==== */
2141 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2142 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2143 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2145 static void build_reg_map(void)
2147 reg_gp_map[REG_GP_EAX] = 0x0;
2148 reg_gp_map[REG_GP_ECX] = 0x1;
2149 reg_gp_map[REG_GP_EDX] = 0x2;
2150 reg_gp_map[REG_GP_EBX] = 0x3;
2151 reg_gp_map[REG_GP_ESP] = 0x4;
2152 reg_gp_map[REG_GP_EBP] = 0x5;
2153 reg_gp_map[REG_GP_ESI] = 0x6;
2154 reg_gp_map[REG_GP_EDI] = 0x7;
2157 /** Returns the encoding for a pnc field. */
2158 static unsigned char pnc2cc(ia32_condition_code_t cc)
2163 /** Sign extension bit values for binops */
2165 UNSIGNED_IMM = 0, /**< unsigned immediate */
2166 SIGNEXT_IMM = 2, /**< sign extended immediate */
2169 /** The mod encoding of the ModR/M */
2171 MOD_IND = 0x00, /**< [reg1] */
2172 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2173 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2174 MOD_REG = 0xC0 /**< reg1 */
2177 /** create R/M encoding for ModR/M */
2178 #define ENC_RM(x) (x)
2179 /** create REG encoding for ModR/M */
2180 #define ENC_REG(x) ((x) << 3)
2182 /** create encoding for a SIB byte */
2183 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2185 /* Node: The following routines are supposed to append bytes, words, dwords
2186 to the output stream.
2187 Currently the implementation is stupid in that it still creates output
2188 for an "assembler" in the form of .byte, .long
2189 We will change this when enough infrastructure is there to create complete
2190 machine code in memory/object files */
2192 static void bemit8(const unsigned char byte)
2194 be_emit_irprintf("\t.byte 0x%x\n", byte);
2195 be_emit_write_line();
2198 static void bemit16(const unsigned short u16)
2200 be_emit_irprintf("\t.word 0x%x\n", u16);
2201 be_emit_write_line();
2204 static void bemit32(const unsigned u32)
2206 be_emit_irprintf("\t.long 0x%x\n", u32);
2207 be_emit_write_line();
2211 * Emit address of an entity. If @p is_relative is true then a relative
2212 * offset from behind the address to the entity is created.
2214 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2217 if (entity == NULL) {
2222 /* the final version should remember the position in the bytestream
2223 and patch it with the correct address at linktime... */
2224 be_emit_cstring("\t.long ");
2227 be_gas_emit_entity(entity);
2229 if (get_entity_owner(entity) == get_tls_type()) {
2230 if (get_entity_visibility(entity) == ir_visibility_external) {
2231 be_emit_cstring("@INDNTPOFF");
2233 be_emit_cstring("@NTPOFF");
2238 be_emit_cstring("-.");
2243 be_emit_irprintf("%+d", offset);
2246 be_emit_write_line();
2249 static void bemit_jmp_destination(const ir_node *dest_block)
2251 be_emit_cstring("\t.long ");
2252 be_gas_emit_block_name(dest_block);
2253 be_emit_cstring(" - . - 4\n");
2254 be_emit_write_line();
2257 /* end emit routines, all emitters following here should only use the functions
2260 typedef enum reg_modifier {
2265 /** Create a ModR/M byte for src1,src2 registers */
2266 static void bemit_modrr(const arch_register_t *src1,
2267 const arch_register_t *src2)
2269 unsigned char modrm = MOD_REG;
2270 modrm |= ENC_RM(reg_gp_map[src1->index]);
2271 modrm |= ENC_REG(reg_gp_map[src2->index]);
2275 /** Create a ModR/M8 byte for src1,src2 registers */
2276 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2277 reg_modifier_t high_part2, const arch_register_t *src2)
2279 unsigned char modrm = MOD_REG;
2280 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2281 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2285 /** Create a ModR/M byte for one register and extension */
2286 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2288 unsigned char modrm = MOD_REG;
2290 modrm |= ENC_RM(reg_gp_map[reg->index]);
2291 modrm |= ENC_REG(ext);
2295 /** Create a ModR/M8 byte for one register */
2296 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2298 unsigned char modrm = MOD_REG;
2299 assert(reg_gp_map[reg->index] < 4);
2300 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2306 * Calculate the size of an signed immediate in bytes.
2308 * @param offset an offset
2310 static unsigned get_signed_imm_size(int offset)
2312 if (-128 <= offset && offset < 128) {
2314 } else if (-32768 <= offset && offset < 32768) {
2322 * Emit an address mode.
2324 * @param reg content of the reg field: either a register index or an opcode extension
2325 * @param node the node
2327 static void bemit_mod_am(unsigned reg, const ir_node *node)
2329 ir_entity *ent = get_ia32_am_sc(node);
2330 int offs = get_ia32_am_offs_int(node);
2331 ir_node *base = get_irn_n(node, n_ia32_base);
2332 int has_base = !is_ia32_NoReg_GP(base);
2333 ir_node *index = get_irn_n(node, n_ia32_index);
2334 int has_index = !is_ia32_NoReg_GP(index);
2337 unsigned emitoffs = 0;
2338 bool emitsib = false;
2341 /* set the mod part depending on displacement */
2343 modrm |= MOD_IND_WORD_OFS;
2345 } else if (offs == 0) {
2348 } else if (-128 <= offs && offs < 128) {
2349 modrm |= MOD_IND_BYTE_OFS;
2352 modrm |= MOD_IND_WORD_OFS;
2357 const arch_register_t *base_reg = arch_get_irn_register(base);
2358 base_enc = reg_gp_map[base_reg->index];
2360 /* Use the EBP encoding + MOD_IND if NO base register. There is
2361 * always a 32bit offset present in this case. */
2367 /* Determine if we need a SIB byte. */
2369 const arch_register_t *reg_index = arch_get_irn_register(index);
2370 int scale = get_ia32_am_scale(node);
2372 /* R/M set to ESP means SIB in 32bit mode. */
2373 modrm |= ENC_RM(0x04);
2374 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2376 } else if (base_enc == 0x04) {
2377 /* for the above reason we are forced to emit a SIB when base is ESP.
2378 * Only the base is used, index must be ESP too, which means no index.
2380 modrm |= ENC_RM(0x04);
2381 sib = ENC_SIB(0, 0x04, 0x04);
2384 modrm |= ENC_RM(base_enc);
2387 /* We are forced to emit an 8bit offset as EBP base without offset is a
2388 * special case for SIB without base register. */
2389 if (base_enc == 0x05 && emitoffs == 0) {
2390 modrm |= MOD_IND_BYTE_OFS;
2394 modrm |= ENC_REG(reg);
2400 /* emit displacement */
2401 if (emitoffs == 8) {
2402 bemit8((unsigned) offs);
2403 } else if (emitoffs == 32) {
2404 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2409 * Emit a binop with a immediate operand.
2411 * @param node the node to emit
2412 * @param opcode_eax the opcode for the op eax, imm variant
2413 * @param opcode the opcode for the reg, imm variant
2414 * @param ruval the opcode extension for opcode
2416 static void bemit_binop_with_imm(
2417 const ir_node *node,
2418 unsigned char opcode_ax,
2419 unsigned char opcode, unsigned char ruval)
2421 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2422 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2423 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2426 /* Some instructions (test) have no short form with 32bit value + 8bit
2428 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2431 /* check for sign extension */
2432 size = get_signed_imm_size(attr->offset);
2437 bemit8(opcode | SIGNEXT_IMM);
2438 /* cmp has this special mode */
2439 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2440 bemit_mod_am(ruval, node);
2442 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2443 bemit_modru(reg, ruval);
2445 bemit8((unsigned char)attr->offset);
2449 /* check for eax variant: this variant is shorter for 32bit immediates only */
2450 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2452 bemit_mod_am(ruval, node);
2454 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2455 if (reg->index == REG_GP_EAX) {
2459 bemit_modru(reg, ruval);
2462 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2465 panic("invalid imm size?!?");
2471 static void bemit_binop_2(const ir_node *node, unsigned code)
2473 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2475 if (get_ia32_op_type(node) == ia32_Normal) {
2476 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2477 bemit_modrr(op2, out);
2479 bemit_mod_am(reg_gp_map[out->index], node);
2486 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2488 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2489 if (is_ia32_Immediate(right)) {
2490 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2492 bemit_binop_2(node, opcodes[0]);
2499 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2502 if (get_ia32_op_type(node) == ia32_Normal) {
2503 const arch_register_t *in = get_in_reg(node, input);
2504 bemit_modru(in, ext);
2506 bemit_mod_am(ext, node);
2510 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2512 const arch_register_t *out = get_out_reg(node, 0);
2513 bemit_unop(node, code, reg_gp_map[out->index], input);
2516 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2518 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2521 bemit8(size == 8 ? code : code + 1);
2522 bemit_mod_am(ext, node);
2525 static void bemit_immediate(const ir_node *node, bool relative)
2527 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2528 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2531 static void bemit_copy(const ir_node *copy)
2533 const arch_register_t *in = get_in_reg(copy, 0);
2534 const arch_register_t *out = get_out_reg(copy, 0);
2538 /* copies of vf nodes aren't real... */
2539 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2542 if (get_irn_mode(copy) == mode_E) {
2545 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2547 bemit_modrr(in, out);
2551 static void bemit_perm(const ir_node *node)
2553 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2554 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2555 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2557 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2559 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2560 if (in0->index == REG_GP_EAX) {
2561 bemit8(0x90 + reg_gp_map[in1->index]);
2562 } else if (in1->index == REG_GP_EAX) {
2563 bemit8(0x90 + reg_gp_map[in0->index]);
2566 bemit_modrr(in0, in1);
2568 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2569 panic("unimplemented"); // TODO implement
2570 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2571 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2572 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2573 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2575 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2578 panic("unexpected register class in be_Perm (%+F)", node);
2582 static void bemit_xor0(const ir_node *node)
2584 const arch_register_t *out = get_out_reg(node, 0);
2586 bemit_modrr(out, out);
2589 static void bemit_mov_const(const ir_node *node)
2591 const arch_register_t *out = get_out_reg(node, 0);
2592 bemit8(0xB8 + reg_gp_map[out->index]);
2593 bemit_immediate(node, false);
2597 * Creates a function for a Binop with 3 possible encodings.
2599 #define BINOP(op, op0, op1, op2, op2_ext) \
2600 static void bemit_ ## op(const ir_node *node) { \
2601 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2602 bemit_binop(node, op ## _codes); \
2605 /* insn def eax,imm imm */
2606 BINOP(add, 0x03, 0x05, 0x81, 0)
2607 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2608 BINOP(adc, 0x13, 0x15, 0x81, 2)
2609 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2610 BINOP(and, 0x23, 0x25, 0x81, 4)
2611 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2612 BINOP(xor, 0x33, 0x35, 0x81, 6)
2613 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2615 #define BINOPMEM(op, ext) \
2616 static void bemit_##op(const ir_node *node) \
2619 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2622 val = get_irn_n(node, n_ia32_unary_op); \
2623 if (is_ia32_Immediate(val)) { \
2624 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2625 int offset = attr->offset; \
2626 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2628 bemit_mod_am(ext, node); \
2632 bemit_mod_am(ext, node); \
2636 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2640 bemit8(ext << 3 | 1); \
2641 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2645 static void bemit_##op##8bit(const ir_node *node) \
2647 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2648 if (is_ia32_Immediate(val)) { \
2650 bemit_mod_am(ext, node); \
2651 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2654 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2666 * Creates a function for an Unop with code /ext encoding.
2668 #define UNOP(op, code, ext, input) \
2669 static void bemit_ ## op(const ir_node *node) { \
2670 bemit_unop(node, code, ext, input); \
2673 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2674 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2675 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2676 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2677 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2678 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2680 /* TODO: am support for IJmp */
2681 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2683 #define SHIFT(op, ext) \
2684 static void bemit_##op(const ir_node *node) \
2686 const arch_register_t *out = get_out_reg(node, 0); \
2687 ir_node *count = get_irn_n(node, 1); \
2688 if (is_ia32_Immediate(count)) { \
2689 int offset = get_ia32_immediate_attr_const(count)->offset; \
2690 if (offset == 1) { \
2692 bemit_modru(out, ext); \
2695 bemit_modru(out, ext); \
2700 bemit_modru(out, ext); \
2704 static void bemit_##op##mem(const ir_node *node) \
2707 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2710 count = get_irn_n(node, 1); \
2711 if (is_ia32_Immediate(count)) { \
2712 int offset = get_ia32_immediate_attr_const(count)->offset; \
2713 if (offset == 1) { \
2714 bemit8(size == 8 ? 0xD0 : 0xD1); \
2715 bemit_mod_am(ext, node); \
2717 bemit8(size == 8 ? 0xC0 : 0xC1); \
2718 bemit_mod_am(ext, node); \
2722 bemit8(size == 8 ? 0xD2 : 0xD3); \
2723 bemit_mod_am(ext, node); \
2733 static void bemit_shld(const ir_node *node)
2735 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2736 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2737 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2739 if (is_ia32_Immediate(count)) {
2741 bemit_modrr(out, in);
2742 bemit8(get_ia32_immediate_attr_const(count)->offset);
2745 bemit_modrr(out, in);
2749 static void bemit_shrd(const ir_node *node)
2751 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2752 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2753 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2755 if (is_ia32_Immediate(count)) {
2757 bemit_modrr(out, in);
2758 bemit8(get_ia32_immediate_attr_const(count)->offset);
2761 bemit_modrr(out, in);
2766 * binary emitter for setcc.
2768 static void bemit_setcc(const ir_node *node)
2770 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2772 ia32_condition_code_t cc = get_ia32_condcode(node);
2773 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2774 if (cc & ia32_cc_float_parity_cases) {
2775 if (cc & ia32_cc_negated) {
2778 bemit8(0x90 | pnc2cc(cc));
2779 bemit_modrm8(REG_LOW, dreg);
2784 bemit_modrm8(REG_HIGH, dreg);
2786 /* orb %>dreg, %<dreg */
2788 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2792 bemit8(0x90 | pnc2cc(cc));
2793 bemit_modrm8(REG_LOW, dreg);
2798 bemit_modrm8(REG_HIGH, dreg);
2800 /* andb %>dreg, %<dreg */
2802 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2807 bemit8(0x90 | pnc2cc(cc));
2808 bemit_modrm8(REG_LOW, dreg);
2812 static void bemit_cmovcc(const ir_node *node)
2814 const ia32_attr_t *attr = get_ia32_attr_const(node);
2815 int ins_permuted = attr->data.ins_permuted;
2816 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2817 ia32_condition_code_t cc = get_ia32_condcode(node);
2818 const arch_register_t *in_true;
2819 const arch_register_t *in_false;
2821 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2823 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2824 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2826 /* should be same constraint fullfilled? */
2827 if (out == in_false) {
2828 /* yes -> nothing to do */
2829 } else if (out == in_true) {
2830 assert(get_ia32_op_type(node) == ia32_Normal);
2831 ins_permuted = !ins_permuted;
2835 bemit8(0x8B); // mov %in_false, %out
2836 bemit_modrr(in_false, out);
2840 cc = ia32_negate_condition_code(cc);
2842 if (cc & ia32_cc_float_parity_cases)
2843 panic("cmov can't handle parity float cases");
2846 bemit8(0x40 | pnc2cc(cc));
2847 if (get_ia32_op_type(node) == ia32_Normal) {
2848 bemit_modrr(in_true, out);
2850 bemit_mod_am(reg_gp_map[out->index], node);
2854 static void bemit_cmp(const ir_node *node)
2856 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2862 right = get_irn_n(node, n_ia32_binary_right);
2863 if (is_ia32_Immediate(right)) {
2864 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2865 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2866 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2869 if (attr->symconst != NULL) {
2872 /* check for sign extension */
2873 size = get_signed_imm_size(attr->offset);
2878 bemit8(0x81 | SIGNEXT_IMM);
2879 /* cmp has this special mode */
2880 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2881 bemit_mod_am(7, node);
2883 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2884 bemit_modru(reg, 7);
2886 bemit8((unsigned char)attr->offset);
2890 /* check for eax variant: this variant is shorter for 32bit immediates only */
2891 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2893 bemit_mod_am(7, node);
2895 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2896 if (reg->index == REG_GP_EAX) {
2900 bemit_modru(reg, 7);
2903 if (ls_size == 16) {
2904 bemit16(attr->offset);
2906 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2910 panic("invalid imm size?!?");
2912 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2914 if (get_ia32_op_type(node) == ia32_Normal) {
2915 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2916 bemit_modrr(op2, out);
2918 bemit_mod_am(reg_gp_map[out->index], node);
2923 static void bemit_cmp8bit(const ir_node *node)
2925 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2926 if (is_ia32_Immediate(right)) {
2927 if (get_ia32_op_type(node) == ia32_Normal) {
2928 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2929 if (out->index == REG_GP_EAX) {
2933 bemit_modru(out, 7);
2937 bemit_mod_am(7, node);
2939 bemit8(get_ia32_immediate_attr_const(right)->offset);
2941 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2943 if (get_ia32_op_type(node) == ia32_Normal) {
2944 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2945 bemit_modrr(out, in);
2947 bemit_mod_am(reg_gp_map[out->index], node);
2952 static void bemit_test8bit(const ir_node *node)
2954 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2955 if (is_ia32_Immediate(right)) {
2956 if (get_ia32_op_type(node) == ia32_Normal) {
2957 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2958 if (out->index == REG_GP_EAX) {
2962 bemit_modru(out, 0);
2966 bemit_mod_am(0, node);
2968 bemit8(get_ia32_immediate_attr_const(right)->offset);
2970 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2972 if (get_ia32_op_type(node) == ia32_Normal) {
2973 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
2974 bemit_modrr(out, in);
2976 bemit_mod_am(reg_gp_map[out->index], node);
2981 static void bemit_imul(const ir_node *node)
2983 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2984 /* Do we need the immediate form? */
2985 if (is_ia32_Immediate(right)) {
2986 int imm = get_ia32_immediate_attr_const(right)->offset;
2987 if (get_signed_imm_size(imm) == 1) {
2988 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2991 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2996 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3000 static void bemit_dec(const ir_node *node)
3002 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3003 bemit8(0x48 + reg_gp_map[out->index]);
3006 static void bemit_inc(const ir_node *node)
3008 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3009 bemit8(0x40 + reg_gp_map[out->index]);
3012 #define UNOPMEM(op, code, ext) \
3013 static void bemit_##op(const ir_node *node) \
3015 bemit_unop_mem(node, code, ext); \
3018 UNOPMEM(notmem, 0xF6, 2)
3019 UNOPMEM(negmem, 0xF6, 3)
3020 UNOPMEM(incmem, 0xFE, 0)
3021 UNOPMEM(decmem, 0xFE, 1)
3023 static void bemit_ldtls(const ir_node *node)
3025 const arch_register_t *out = get_out_reg(node, 0);
3027 bemit8(0x65); // gs:
3028 if (out->index == REG_GP_EAX) {
3029 bemit8(0xA1); // movl 0, %eax
3031 bemit8(0x8B); // movl 0, %reg
3032 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3040 static void bemit_lea(const ir_node *node)
3042 const arch_register_t *out = get_out_reg(node, 0);
3044 bemit_mod_am(reg_gp_map[out->index], node);
3047 /* helper function for bemit_minus64bit */
3048 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3050 bemit8(0x8B); // movl %src, %dst
3051 bemit_modrr(src, dst);
3054 /* helper function for bemit_minus64bit */
3055 static void bemit_helper_neg(const arch_register_t *reg)
3057 bemit8(0xF7); // negl %reg
3058 bemit_modru(reg, 3);
3061 /* helper function for bemit_minus64bit */
3062 static void bemit_helper_sbb0(const arch_register_t *reg)
3064 bemit8(0x83); // sbbl $0, %reg
3065 bemit_modru(reg, 3);
3069 /* helper function for bemit_minus64bit */
3070 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3072 bemit8(0x1B); // sbbl %src, %dst
3073 bemit_modrr(src, dst);
3076 /* helper function for bemit_minus64bit */
3077 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3079 if (src->index == REG_GP_EAX) {
3080 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3081 } else if (dst->index == REG_GP_EAX) {
3082 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3084 bemit8(0x87); // xchgl %src, %dst
3085 bemit_modrr(src, dst);
3089 /* helper function for bemit_minus64bit */
3090 static void bemit_helper_zero(const arch_register_t *reg)
3092 bemit8(0x33); // xorl %reg, %reg
3093 bemit_modrr(reg, reg);
3096 static void bemit_minus64bit(const ir_node *node)
3098 const arch_register_t *in_lo = get_in_reg(node, 0);
3099 const arch_register_t *in_hi = get_in_reg(node, 1);
3100 const arch_register_t *out_lo = get_out_reg(node, 0);
3101 const arch_register_t *out_hi = get_out_reg(node, 1);
3103 if (out_lo == in_lo) {
3104 if (out_hi != in_hi) {
3105 /* a -> a, b -> d */
3108 /* a -> a, b -> b */
3111 } else if (out_lo == in_hi) {
3112 if (out_hi == in_lo) {
3113 /* a -> b, b -> a */
3114 bemit_helper_xchg(in_lo, in_hi);
3117 /* a -> b, b -> d */
3118 bemit_helper_mov(in_hi, out_hi);
3119 bemit_helper_mov(in_lo, out_lo);
3123 if (out_hi == in_lo) {
3124 /* a -> c, b -> a */
3125 bemit_helper_mov(in_lo, out_lo);
3127 } else if (out_hi == in_hi) {
3128 /* a -> c, b -> b */
3129 bemit_helper_mov(in_lo, out_lo);
3132 /* a -> c, b -> d */
3133 bemit_helper_mov(in_lo, out_lo);
3139 bemit_helper_neg( out_hi);
3140 bemit_helper_neg( out_lo);
3141 bemit_helper_sbb0(out_hi);
3145 bemit_helper_zero(out_hi);
3146 bemit_helper_neg( out_lo);
3147 bemit_helper_sbb( in_hi, out_hi);
3151 * Emit a single opcode.
3153 #define EMIT_SINGLEOP(op, code) \
3154 static void bemit_ ## op(const ir_node *node) { \
3159 //EMIT_SINGLEOP(daa, 0x27)
3160 //EMIT_SINGLEOP(das, 0x2F)
3161 //EMIT_SINGLEOP(aaa, 0x37)
3162 //EMIT_SINGLEOP(aas, 0x3F)
3163 //EMIT_SINGLEOP(nop, 0x90)
3164 EMIT_SINGLEOP(cwtl, 0x98)
3165 EMIT_SINGLEOP(cltd, 0x99)
3166 //EMIT_SINGLEOP(fwait, 0x9B)
3167 EMIT_SINGLEOP(sahf, 0x9E)
3168 //EMIT_SINGLEOP(popf, 0x9D)
3169 EMIT_SINGLEOP(leave, 0xC9)
3170 EMIT_SINGLEOP(int3, 0xCC)
3171 //EMIT_SINGLEOP(iret, 0xCF)
3172 //EMIT_SINGLEOP(xlat, 0xD7)
3173 //EMIT_SINGLEOP(lock, 0xF0)
3174 EMIT_SINGLEOP(rep, 0xF3)
3175 //EMIT_SINGLEOP(halt, 0xF4)
3176 EMIT_SINGLEOP(cmc, 0xF5)
3177 EMIT_SINGLEOP(stc, 0xF9)
3178 //EMIT_SINGLEOP(cli, 0xFA)
3179 //EMIT_SINGLEOP(sti, 0xFB)
3180 //EMIT_SINGLEOP(std, 0xFD)
3183 * Emits a MOV out, [MEM].
3185 static void bemit_load(const ir_node *node)
3187 const arch_register_t *out = get_out_reg(node, 0);
3189 if (out->index == REG_GP_EAX) {
3190 ir_node *base = get_irn_n(node, n_ia32_base);
3191 int has_base = !is_ia32_NoReg_GP(base);
3192 ir_node *index = get_irn_n(node, n_ia32_index);
3193 int has_index = !is_ia32_NoReg_GP(index);
3194 if (!has_base && !has_index) {
3195 ir_entity *ent = get_ia32_am_sc(node);
3196 int offs = get_ia32_am_offs_int(node);
3197 /* load from constant address to EAX can be encoded
3200 bemit_entity(ent, 0, offs, false);
3205 bemit_mod_am(reg_gp_map[out->index], node);
3209 * Emits a MOV [mem], in.
3211 static void bemit_store(const ir_node *node)
3213 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3214 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3216 if (is_ia32_Immediate(value)) {
3219 bemit_mod_am(0, node);
3220 bemit8(get_ia32_immediate_attr_const(value)->offset);
3221 } else if (size == 16) {
3224 bemit_mod_am(0, node);
3225 bemit16(get_ia32_immediate_attr_const(value)->offset);
3228 bemit_mod_am(0, node);
3229 bemit_immediate(value, false);
3232 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3234 if (in->index == REG_GP_EAX) {
3235 ir_node *base = get_irn_n(node, n_ia32_base);
3236 int has_base = !is_ia32_NoReg_GP(base);
3237 ir_node *index = get_irn_n(node, n_ia32_index);
3238 int has_index = !is_ia32_NoReg_GP(index);
3239 if (!has_base && !has_index) {
3240 ir_entity *ent = get_ia32_am_sc(node);
3241 int offs = get_ia32_am_offs_int(node);
3242 /* store to constant address from EAX can be encoded as
3243 * 0xA2/0xA3 [offset]*/
3251 bemit_entity(ent, 0, offs, false);
3263 bemit_mod_am(reg_gp_map[in->index], node);
3267 static void bemit_conv_i2i(const ir_node *node)
3269 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3278 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3279 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3280 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3286 static void bemit_push(const ir_node *node)
3288 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3290 if (is_ia32_Immediate(value)) {
3291 const ia32_immediate_attr_t *attr
3292 = get_ia32_immediate_attr_const(value);
3293 unsigned size = get_signed_imm_size(attr->offset);
3299 bemit8((unsigned char)attr->offset);
3304 bemit_immediate(value, false);
3307 } else if (is_ia32_NoReg_GP(value)) {
3309 bemit_mod_am(6, node);
3311 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3312 bemit8(0x50 + reg_gp_map[reg->index]);
3319 static void bemit_pop(const ir_node *node)
3321 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3322 bemit8(0x58 + reg_gp_map[reg->index]);
3325 static void bemit_popmem(const ir_node *node)
3328 bemit_mod_am(0, node);
3331 static void bemit_call(const ir_node *node)
3333 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3335 if (is_ia32_Immediate(proc)) {
3337 bemit_immediate(proc, true);
3339 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3343 static void bemit_jmp(const ir_node *dest_block)
3346 bemit_jmp_destination(dest_block);
3349 static void bemit_jump(const ir_node *node)
3351 if (can_be_fallthrough(node))
3354 bemit_jmp(get_cfop_target_block(node));
3357 static void bemit_jcc(int pnc, const ir_node *dest_block)
3359 unsigned char cc = pnc2cc(pnc);
3362 bemit_jmp_destination(dest_block);
3365 static void bemit_jp(bool odd, const ir_node *dest_block)
3369 bemit_jmp_destination(dest_block);
3372 static void bemit_ia32_jcc(const ir_node *node)
3374 ia32_condition_code_t cc = get_ia32_condcode(node);
3375 const ir_node *proj_true;
3376 const ir_node *proj_false;
3377 const ir_node *dest_true;
3378 const ir_node *dest_false;
3379 const ir_node *block;
3381 cc = determine_final_cc(node, 0, cc);
3383 /* get both Projs */
3384 proj_true = get_proj(node, pn_ia32_Jcc_true);
3385 assert(proj_true && "Jcc without true Proj");
3387 proj_false = get_proj(node, pn_ia32_Jcc_false);
3388 assert(proj_false && "Jcc without false Proj");
3390 block = get_nodes_block(node);
3392 if (can_be_fallthrough(proj_true)) {
3393 /* exchange both proj's so the second one can be omitted */
3394 const ir_node *t = proj_true;
3396 proj_true = proj_false;
3398 cc = ia32_negate_condition_code(cc);
3401 dest_true = get_cfop_target_block(proj_true);
3402 dest_false = get_cfop_target_block(proj_false);
3404 if (cc & ia32_cc_float_parity_cases) {
3405 /* Some floating point comparisons require a test of the parity flag,
3406 * which indicates that the result is unordered */
3407 if (cc & ia32_cc_negated) {
3408 bemit_jp(false, dest_true);
3410 /* we need a local label if the false proj is a fallthrough
3411 * as the falseblock might have no label emitted then */
3412 if (can_be_fallthrough(proj_false)) {
3414 bemit8(0x06); // jp + 6
3416 bemit_jp(false, dest_false);
3420 bemit_jcc(cc, dest_true);
3422 /* the second Proj might be a fallthrough */
3423 if (can_be_fallthrough(proj_false)) {
3424 /* it's a fallthrough */
3426 bemit_jmp(dest_false);
3430 static void bemit_switchjmp(const ir_node *node)
3432 unsigned long interval;
3436 const arch_register_t *in;
3438 /* fill the table structure */
3439 generate_jump_table(&tbl, node);
3441 /* two-complement's magic make this work without overflow */
3442 interval = tbl.max_value - tbl.min_value;
3444 in = get_in_reg(node, 0);
3445 /* emit the table */
3446 if (get_signed_imm_size(interval) == 1) {
3447 bemit8(0x83); // cmpl $imm8, %in
3451 bemit8(0x81); // cmpl $imm32, %in
3455 bemit8(0x0F); // ja tbl.defProj
3457 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3459 if (tbl.num_branches > 1) {
3461 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3462 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3463 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3464 be_emit_irprintf("\t.long %s\n", tbl.label);
3466 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3467 be_emit_cstring(".align 4\n");
3468 be_emit_irprintf("%s:\n", tbl.label);
3470 last_value = tbl.branches[0].value;
3471 for (i = 0; i != tbl.num_branches; ++i) {
3472 while (last_value != tbl.branches[i].value) {
3473 ia32_emitf(tbl.defProj, ".long %L\n");
3476 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3479 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3481 /* one jump is enough */
3482 panic("switch only has one case");
3483 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3486 be_emit_write_line();
3494 static void bemit_return(const ir_node *node)
3496 unsigned pop = be_Return_get_pop(node);
3497 if (pop > 0 || be_Return_get_emit_pop(node)) {
3499 assert(pop <= 0xffff);
3506 static void bemit_subsp(const ir_node *node)
3508 const arch_register_t *out;
3511 /* mov %esp, %out */
3513 out = get_out_reg(node, 1);
3514 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3517 static void bemit_incsp(const ir_node *node)
3520 const arch_register_t *reg;
3524 offs = be_get_IncSP_offset(node);
3535 size = get_signed_imm_size(offs);
3536 bemit8(size == 1 ? 0x83 : 0x81);
3538 reg = get_out_reg(node, 0);
3539 bemit_modru(reg, ext);
3548 static void bemit_copybi(const ir_node *node)
3550 unsigned size = get_ia32_copyb_size(node);
3552 bemit8(0xA4); // movsb
3555 bemit8(0xA5); // movsw
3559 bemit8(0xA5); // movsl
3563 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3565 if (get_ia32_op_type(node) == ia32_Normal) {
3566 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3567 const arch_register_t *in1 = x87_attr->x87[0];
3568 const arch_register_t *in = x87_attr->x87[1];
3569 const arch_register_t *out = x87_attr->x87[2];
3573 } else if (out == in) {
3577 if (out->index == 0) {
3579 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3582 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3585 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3590 bemit_mod_am(code, node);
3594 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3596 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3597 const arch_register_t *out = x87_attr->x87[2];
3599 bemit8(code + out->index);
3602 static void bemit_fabs(const ir_node *node)
3610 static void bemit_fadd(const ir_node *node)
3612 bemit_fbinop(node, 0, 0);
3615 static void bemit_faddp(const ir_node *node)
3617 bemit_fbinopp(node, 0xC0);
3620 static void bemit_fchs(const ir_node *node)
3628 static void bemit_fdiv(const ir_node *node)
3630 bemit_fbinop(node, 6, 7);
3633 static void bemit_fdivp(const ir_node *node)
3635 bemit_fbinopp(node, 0xF8);
3638 static void bemit_fdivr(const ir_node *node)
3640 bemit_fbinop(node, 7, 6);
3643 static void bemit_fdivrp(const ir_node *node)
3645 bemit_fbinopp(node, 0xF0);
3648 static void bemit_fild(const ir_node *node)
3650 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3652 bemit8(0xDF); // filds
3653 bemit_mod_am(0, node);
3657 bemit8(0xDB); // fildl
3658 bemit_mod_am(0, node);
3662 bemit8(0xDF); // fildll
3663 bemit_mod_am(5, node);
3667 panic("invalid mode size");
3671 static void bemit_fist(const ir_node *node)
3673 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3675 bemit8(0xDF); // fists
3679 bemit8(0xDB); // fistl
3683 panic("invalid mode size");
3685 bemit_mod_am(2, node);
3688 static void bemit_fistp(const ir_node *node)
3690 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3692 bemit8(0xDF); // fistps
3693 bemit_mod_am(3, node);
3697 bemit8(0xDB); // fistpl
3698 bemit_mod_am(3, node);
3702 bemit8(0xDF); // fistpll
3703 bemit_mod_am(7, node);
3707 panic("invalid mode size");
3711 static void bemit_fld(const ir_node *node)
3713 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3715 bemit8(0xD9); // flds
3716 bemit_mod_am(0, node);
3720 bemit8(0xDD); // fldl
3721 bemit_mod_am(0, node);
3726 bemit8(0xDB); // fldt
3727 bemit_mod_am(5, node);
3731 panic("invalid mode size");
3735 static void bemit_fld1(const ir_node *node)
3739 bemit8(0xE8); // fld1
3742 static void bemit_fldcw(const ir_node *node)
3744 bemit8(0xD9); // fldcw
3745 bemit_mod_am(5, node);
3748 static void bemit_fldz(const ir_node *node)
3752 bemit8(0xEE); // fldz
3755 static void bemit_fmul(const ir_node *node)
3757 bemit_fbinop(node, 1, 1);
3760 static void bemit_fmulp(const ir_node *node)
3762 bemit_fbinopp(node, 0xC8);
3765 static void bemit_fpop(const ir_node *node)
3767 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3769 bemit8(0xD8 + attr->x87[0]->index);
3772 static void bemit_fpush(const ir_node *node)
3774 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3776 bemit8(0xC0 + attr->x87[0]->index);
3779 static void bemit_fpushcopy(const ir_node *node)
3781 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3783 bemit8(0xC0 + attr->x87[0]->index);
3786 static void bemit_fst(const ir_node *node)
3788 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3790 bemit8(0xD9); // fsts
3794 bemit8(0xDD); // fstl
3798 panic("invalid mode size");
3800 bemit_mod_am(2, node);
3803 static void bemit_fstp(const ir_node *node)
3805 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3807 bemit8(0xD9); // fstps
3808 bemit_mod_am(3, node);
3812 bemit8(0xDD); // fstpl
3813 bemit_mod_am(3, node);
3818 bemit8(0xDB); // fstpt
3819 bemit_mod_am(7, node);
3823 panic("invalid mode size");
3827 static void bemit_fsub(const ir_node *node)
3829 bemit_fbinop(node, 4, 5);
3832 static void bemit_fsubp(const ir_node *node)
3834 bemit_fbinopp(node, 0xE8);
3837 static void bemit_fsubr(const ir_node *node)
3839 bemit_fbinop(node, 5, 4);
3842 static void bemit_fsubrp(const ir_node *node)
3844 bemit_fbinopp(node, 0xE0);
3847 static void bemit_fnstcw(const ir_node *node)
3849 bemit8(0xD9); // fnstcw
3850 bemit_mod_am(7, node);
3853 static void bemit_fnstsw(void)
3855 bemit8(0xDF); // fnstsw %ax
3859 static void bemit_ftstfnstsw(const ir_node *node)
3863 bemit8(0xD9); // ftst
3868 static void bemit_fucomi(const ir_node *node)
3870 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3871 bemit8(0xDB); // fucomi
3872 bemit8(0xE8 + attr->x87[1]->index);
3875 static void bemit_fucomip(const ir_node *node)
3877 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3878 bemit8(0xDF); // fucomip
3879 bemit8(0xE8 + attr->x87[1]->index);
3882 static void bemit_fucomfnstsw(const ir_node *node)
3884 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3885 bemit8(0xDD); // fucom
3886 bemit8(0xE0 + attr->x87[1]->index);
3890 static void bemit_fucompfnstsw(const ir_node *node)
3892 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3893 bemit8(0xDD); // fucomp
3894 bemit8(0xE8 + attr->x87[1]->index);
3898 static void bemit_fucomppfnstsw(const ir_node *node)
3902 bemit8(0xDA); // fucompp
3907 static void bemit_fxch(const ir_node *node)
3909 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3911 bemit8(0xC8 + attr->x87[0]->index);
3915 * The type of a emitter function.
3917 typedef void (*emit_func) (const ir_node *);
3920 * Set a node emitter. Make it a bit more type safe.
3922 static void register_emitter(ir_op *op, emit_func func)
3924 op->ops.generic = (op_func) func;
3927 static void ia32_register_binary_emitters(void)
3929 /* first clear the generic function pointer for all ops */
3930 clear_irp_opcodes_generic_func();
3932 /* benode emitter */
3933 register_emitter(op_be_Copy, bemit_copy);
3934 register_emitter(op_be_CopyKeep, bemit_copy);
3935 register_emitter(op_be_IncSP, bemit_incsp);
3936 register_emitter(op_be_Perm, bemit_perm);
3937 register_emitter(op_be_Return, bemit_return);
3938 register_emitter(op_ia32_Adc, bemit_adc);
3939 register_emitter(op_ia32_Add, bemit_add);
3940 register_emitter(op_ia32_AddMem, bemit_addmem);
3941 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3942 register_emitter(op_ia32_And, bemit_and);
3943 register_emitter(op_ia32_AndMem, bemit_andmem);
3944 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3945 register_emitter(op_ia32_Breakpoint, bemit_int3);
3946 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3947 register_emitter(op_ia32_Call, bemit_call);
3948 register_emitter(op_ia32_Cltd, bemit_cltd);
3949 register_emitter(op_ia32_Cmc, bemit_cmc);
3950 register_emitter(op_ia32_Cmp, bemit_cmp);
3951 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3952 register_emitter(op_ia32_Const, bemit_mov_const);
3953 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3954 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3955 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3956 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3957 register_emitter(op_ia32_Dec, bemit_dec);
3958 register_emitter(op_ia32_DecMem, bemit_decmem);
3959 register_emitter(op_ia32_Div, bemit_div);
3960 register_emitter(op_ia32_FldCW, bemit_fldcw);
3961 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3962 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3963 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3964 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3965 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3966 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3967 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3968 register_emitter(op_ia32_IDiv, bemit_idiv);
3969 register_emitter(op_ia32_IJmp, bemit_ijmp);
3970 register_emitter(op_ia32_IMul, bemit_imul);
3971 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3972 register_emitter(op_ia32_Inc, bemit_inc);
3973 register_emitter(op_ia32_IncMem, bemit_incmem);
3974 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3975 register_emitter(op_ia32_Jmp, bemit_jump);
3976 register_emitter(op_ia32_LdTls, bemit_ldtls);
3977 register_emitter(op_ia32_Lea, bemit_lea);
3978 register_emitter(op_ia32_Leave, bemit_leave);
3979 register_emitter(op_ia32_Load, bemit_load);
3980 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3981 register_emitter(op_ia32_Mul, bemit_mul);
3982 register_emitter(op_ia32_Neg, bemit_neg);
3983 register_emitter(op_ia32_NegMem, bemit_negmem);
3984 register_emitter(op_ia32_Not, bemit_not);
3985 register_emitter(op_ia32_NotMem, bemit_notmem);
3986 register_emitter(op_ia32_Or, bemit_or);
3987 register_emitter(op_ia32_OrMem, bemit_ormem);
3988 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3989 register_emitter(op_ia32_Pop, bemit_pop);
3990 register_emitter(op_ia32_PopEbp, bemit_pop);
3991 register_emitter(op_ia32_PopMem, bemit_popmem);
3992 register_emitter(op_ia32_Push, bemit_push);
3993 register_emitter(op_ia32_RepPrefix, bemit_rep);
3994 register_emitter(op_ia32_Rol, bemit_rol);
3995 register_emitter(op_ia32_RolMem, bemit_rolmem);
3996 register_emitter(op_ia32_Ror, bemit_ror);
3997 register_emitter(op_ia32_RorMem, bemit_rormem);
3998 register_emitter(op_ia32_Sahf, bemit_sahf);
3999 register_emitter(op_ia32_Sar, bemit_sar);
4000 register_emitter(op_ia32_SarMem, bemit_sarmem);
4001 register_emitter(op_ia32_Sbb, bemit_sbb);
4002 register_emitter(op_ia32_Setcc, bemit_setcc);
4003 register_emitter(op_ia32_Shl, bemit_shl);
4004 register_emitter(op_ia32_ShlD, bemit_shld);
4005 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4006 register_emitter(op_ia32_Shr, bemit_shr);
4007 register_emitter(op_ia32_ShrD, bemit_shrd);
4008 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4009 register_emitter(op_ia32_Stc, bemit_stc);
4010 register_emitter(op_ia32_Store, bemit_store);
4011 register_emitter(op_ia32_Store8Bit, bemit_store);
4012 register_emitter(op_ia32_Sub, bemit_sub);
4013 register_emitter(op_ia32_SubMem, bemit_submem);
4014 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4015 register_emitter(op_ia32_SubSP, bemit_subsp);
4016 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4017 register_emitter(op_ia32_Test, bemit_test);
4018 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4019 register_emitter(op_ia32_Xor, bemit_xor);
4020 register_emitter(op_ia32_Xor0, bemit_xor0);
4021 register_emitter(op_ia32_XorMem, bemit_xormem);
4022 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4023 register_emitter(op_ia32_fabs, bemit_fabs);
4024 register_emitter(op_ia32_fadd, bemit_fadd);
4025 register_emitter(op_ia32_faddp, bemit_faddp);
4026 register_emitter(op_ia32_fchs, bemit_fchs);
4027 register_emitter(op_ia32_fdiv, bemit_fdiv);
4028 register_emitter(op_ia32_fdivp, bemit_fdivp);
4029 register_emitter(op_ia32_fdivr, bemit_fdivr);
4030 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4031 register_emitter(op_ia32_fild, bemit_fild);
4032 register_emitter(op_ia32_fist, bemit_fist);
4033 register_emitter(op_ia32_fistp, bemit_fistp);
4034 register_emitter(op_ia32_fld, bemit_fld);
4035 register_emitter(op_ia32_fld1, bemit_fld1);
4036 register_emitter(op_ia32_fldz, bemit_fldz);
4037 register_emitter(op_ia32_fmul, bemit_fmul);
4038 register_emitter(op_ia32_fmulp, bemit_fmulp);
4039 register_emitter(op_ia32_fpop, bemit_fpop);
4040 register_emitter(op_ia32_fpush, bemit_fpush);
4041 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4042 register_emitter(op_ia32_fst, bemit_fst);
4043 register_emitter(op_ia32_fstp, bemit_fstp);
4044 register_emitter(op_ia32_fsub, bemit_fsub);
4045 register_emitter(op_ia32_fsubp, bemit_fsubp);
4046 register_emitter(op_ia32_fsubr, bemit_fsubr);
4047 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4048 register_emitter(op_ia32_fxch, bemit_fxch);
4050 /* ignore the following nodes */
4051 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4052 register_emitter(op_be_Keep, emit_Nothing);
4053 register_emitter(op_be_Start, emit_Nothing);
4054 register_emitter(op_Phi, emit_Nothing);
4055 register_emitter(op_Start, emit_Nothing);
4058 static void gen_binary_block(ir_node *block)
4062 ia32_emit_block_header(block);
4064 /* emit the contents of the block */
4065 sched_foreach(block, node) {
4066 ia32_emit_node(node);
4070 void ia32_gen_binary_routine(ir_graph *irg)
4072 ir_entity *entity = get_irg_entity(irg);
4073 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
4074 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4075 ir_node **blk_sched = irg_data->blk_sched;
4078 isa = (ia32_isa_t*) arch_env;
4080 ia32_register_binary_emitters();
4082 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4084 /* we use links to point to target blocks */
4085 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4086 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4088 /* initialize next block links */
4089 n = ARR_LEN(blk_sched);
4090 for (i = 0; i < n; ++i) {
4091 ir_node *block = blk_sched[i];
4092 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
4094 set_irn_link(block, prev);
4097 for (i = 0; i < n; ++i) {
4098 ir_node *block = blk_sched[i];
4099 gen_binary_block(block);
4102 be_gas_emit_function_epilog(entity);
4103 be_dbg_method_end();
4105 be_emit_write_line();
4107 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4111 void ia32_init_emitter(void)
4113 lc_opt_entry_t *be_grp;
4114 lc_opt_entry_t *ia32_grp;
4116 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4117 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4119 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4123 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");