2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 if(reg == &ia32_gp_regs[REG_GP_NOREG])
90 panic("trying to emit noreg");
92 /* in case of unknown register: just return a valid register */
93 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
94 const arch_register_req_t *req;
96 /* ask for the requirements */
97 req = arch_get_register_req(arch_env, irn, pos);
99 if (arch_register_req_is(req, limited)) {
100 /* in case of limited requirements: get the first allowed register */
101 unsigned idx = rbitset_next(req->limited, 0, 1);
102 reg = arch_register_for_index(req->cls, idx);
104 /* otherwise get first register in class */
105 reg = arch_register_for_index(req->cls, 0);
113 * Returns the register at out position pos.
116 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
119 const arch_env_t *arch_env = env->arch_env;
121 const arch_register_t *reg = NULL;
123 /* 1st case: irn is not of mode_T, so it has only */
124 /* one OUT register -> good */
125 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
126 /* Proj with the corresponding projnum for the register */
128 if (get_irn_mode(irn) != mode_T) {
129 reg = arch_get_irn_register(arch_env, irn);
130 } else if (is_ia32_irn(irn)) {
131 reg = get_ia32_out_reg(irn, pos);
133 const ir_edge_t *edge;
135 foreach_out_edge(irn, edge) {
136 proj = get_edge_src_irn(edge);
137 assert(is_Proj(proj) && "non-Proj from mode_T node");
138 if (get_Proj_proj(proj) == pos) {
139 reg = arch_get_irn_register(arch_env, proj);
145 assert(reg && "no out register found");
150 * Determine the gnu assembler suffix that indicates a mode
153 char get_mode_suffix(const ir_mode *mode) {
154 if(mode_is_float(mode)) {
155 switch(get_mode_size_bits(mode)) {
165 assert(mode_is_int(mode) || mode_is_reference(mode));
166 switch(get_mode_size_bits(mode)) {
177 panic("Can't output mode_suffix for %+F\n", mode);
181 int produces_result(const ir_node *node) {
183 !is_ia32_CmpSet(node) &&
184 !is_ia32_CondJmp(node) &&
186 !is_ia32_SwitchJmp(node) &&
187 !is_ia32_TestJmp(node) &&
188 !is_ia32_xCmpSet(node) &&
189 !is_ia32_xCondJmp(node) &&
190 !is_ia32_CmpCMov(node) &&
191 !is_ia32_TestCMov(node) &&
192 !is_ia32_CmpSet(node) && /* this is correct, the Cmp has no result */
193 !is_ia32_TestSet(node);
197 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
198 const arch_register_t *reg) {
199 switch(get_mode_size_bits(mode)) {
201 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
203 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
205 return (char *)arch_register_get_name(reg);
210 * Add a number to a prefix. This number will not be used a second time.
213 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
214 static unsigned long id = 0;
215 snprintf(buf, buflen, "%s%lu", prefix, ++id);
219 /*************************************************************
221 * (_) | | / _| | | | |
222 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
223 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
224 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
225 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
228 *************************************************************/
230 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
231 // be_emit_env_t* so we cheat a bit...
232 #define be_emit_char(env,c) be_emit_char(env->emit,c)
233 #define be_emit_string(env,s) be_emit_string(env->emit,s)
234 #undef be_emit_cstring
235 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
236 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
237 #define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
238 #define be_emit_write_line(env) be_emit_write_line(env->emit)
239 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
240 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
242 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
244 const arch_register_t *reg = get_in_reg(env, node, pos);
245 const char *reg_name = arch_register_get_name(reg);
247 assert(pos < get_irn_arity(node));
249 be_emit_char(env, '%');
250 be_emit_string(env, reg_name);
253 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
254 const arch_register_t *reg = get_out_reg(env, node, pos);
255 const char *reg_name = arch_register_get_name(reg);
257 be_emit_char(env, '%');
258 be_emit_string(env, reg_name);
261 static void ia32_emit_register(ia32_emit_env_t *env, const arch_register_t *reg)
263 const char *reg_name = arch_register_get_name(reg);
265 be_emit_char(env, '%');
266 be_emit_string(env, reg_name);
269 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
271 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
274 be_emit_char(env, '%');
275 be_emit_string(env, attr->x87[pos]->name);
278 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
284 be_emit_char(env, '$');
286 switch(get_ia32_immop_type(node)) {
288 tv = get_ia32_Immop_tarval(node);
289 be_emit_tarval(env, tv);
291 case ia32_ImmSymConst:
292 ent = get_ia32_Immop_symconst(node);
293 set_entity_backend_marked(ent, 1);
294 id = get_entity_ld_ident(ent);
295 be_emit_ident(env, id);
302 be_emit_string(env, "BAD");
307 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
309 be_emit_char(env, get_mode_suffix(mode));
312 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
314 ir_mode *mode = get_ia32_ls_mode(node);
318 ia32_emit_mode_suffix_mode(env, mode);
321 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
323 ir_mode *mode = get_ia32_ls_mode(node);
325 ia32_emit_mode_suffix_mode(env, mode);
329 char get_xmm_mode_suffix(ir_mode *mode)
331 assert(mode_is_float(mode));
332 switch(get_mode_size_bits(mode)) {
343 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
345 ir_mode *mode = get_ia32_ls_mode(node);
346 assert(mode != NULL);
347 be_emit_char(env, 's');
348 be_emit_char(env, get_xmm_mode_suffix(mode));
351 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
353 ir_mode *mode = get_ia32_ls_mode(node);
354 assert(mode != NULL);
355 be_emit_char(env, get_xmm_mode_suffix(mode));
358 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
360 if(get_mode_size_bits(mode) == 32)
362 if(mode_is_signed(mode)) {
363 be_emit_char(env, 's');
365 be_emit_char(env, 'z');
370 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
372 switch (be_gas_flavour) {
373 case GAS_FLAVOUR_NORMAL:
374 be_emit_cstring(env, "\t.type\t");
375 be_emit_string(env, name);
376 be_emit_cstring(env, ", @function\n");
377 be_emit_write_line(env);
379 case GAS_FLAVOUR_MINGW:
380 be_emit_cstring(env, "\t.def\t");
381 be_emit_string(env, name);
382 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
383 be_emit_write_line(env);
391 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
393 switch (be_gas_flavour) {
394 case GAS_FLAVOUR_NORMAL:
395 be_emit_cstring(env, "\t.size\t");
396 be_emit_string(env, name);
397 be_emit_cstring(env, ", .-");
398 be_emit_string(env, name);
399 be_emit_char(env, '\n');
400 be_emit_write_line(env);
409 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node);
412 * Emits registers and/or address mode of a binary operation.
414 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
416 const ir_node *right_op = get_irn_n(node, 3);
418 switch(get_ia32_op_type(node)) {
420 if(is_ia32_Immediate(right_op)) {
421 emit_ia32_Immediate(env, right_op);
422 be_emit_cstring(env, ", ");
423 ia32_emit_source_register(env, node, 2);
425 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
426 ia32_emit_immediate(env, node);
427 be_emit_cstring(env, ", ");
428 ia32_emit_source_register(env, node, 2);
430 const arch_register_t *in1 = get_in_reg(env, node, 2);
431 const arch_register_t *in2 = get_in_reg(env, node, 3);
432 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
433 const arch_register_t *in;
436 in = out ? ((out == in2) ? in1 : in2) : in2;
437 out = out ? out : in1;
438 in_name = arch_register_get_name(in);
440 if (is_ia32_emit_cl(node)) {
441 assert(in == &ia32_gp_regs[REG_ECX]);
445 be_emit_char(env, '%');
446 be_emit_string(env, in_name);
447 be_emit_cstring(env, ", %");
448 be_emit_string(env, arch_register_get_name(out));
452 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
453 assert(!produces_result(node) &&
454 "Source AM with Const must not produce result");
455 ia32_emit_immediate(env, node);
456 be_emit_cstring(env, ", ");
457 ia32_emit_am(env, node);
458 } else if(is_ia32_Immediate(right_op)) {
459 assert(!produces_result(node) &&
460 "Source AM with Const must not produce result");
462 emit_ia32_Immediate(env, right_op);
463 be_emit_cstring(env, ", ");
464 ia32_emit_am(env, node);
465 } else if (produces_result(node)) {
466 ia32_emit_am(env, node);
467 be_emit_cstring(env, ", ");
468 ia32_emit_dest_register(env, node, 0);
470 ia32_emit_am(env, node);
471 be_emit_cstring(env, ", ");
472 ia32_emit_source_register(env, node, 2);
476 right_pos = get_irn_arity(node) >= 5 ? 3 : 2;
477 right_op = get_irn_n(node, right_pos);
478 if(is_ia32_Immediate(right_op)) {
479 emit_ia32_Immediate(env, right_op);
480 be_emit_cstring(env, ", ");
481 ia32_emit_am(env, node);
483 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
484 ia32_emit_immediate(env, node);
485 be_emit_cstring(env, ", ");
486 ia32_emit_am(env, node);
488 const arch_register_t *in1 = get_in_reg(env, node, right_pos);
489 ir_mode *mode = get_ia32_ls_mode(node);
492 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
494 if (is_ia32_emit_cl(node)) {
495 assert(in1 == &ia32_gp_regs[REG_ECX]);
499 be_emit_char(env, '%');
500 be_emit_string(env, in_name);
501 be_emit_cstring(env, ", ");
502 ia32_emit_am(env, node);
506 assert(0 && "unsupported op type");
511 * Emits registers and/or address mode of a binary operation.
513 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
514 switch(get_ia32_op_type(node)) {
516 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
517 // should not happen...
520 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
521 const arch_register_t *in1 = x87_attr->x87[0];
522 const arch_register_t *in2 = x87_attr->x87[1];
523 const arch_register_t *out = x87_attr->x87[2];
524 const arch_register_t *in;
526 in = out ? ((out == in2) ? in1 : in2) : in2;
527 out = out ? out : in1;
529 be_emit_char(env, '%');
530 be_emit_string(env, arch_register_get_name(in));
531 be_emit_cstring(env, ", %");
532 be_emit_string(env, arch_register_get_name(out));
537 ia32_emit_am(env, node);
540 assert(0 && "unsupported op type");
544 void ia32_emit_am_or_dest_register(ia32_emit_env_t *env, const ir_node *node,
546 if(get_ia32_op_type(node) == ia32_Normal) {
547 ia32_emit_dest_register(env, node, pos);
549 assert(get_ia32_op_type(node) == ia32_AddrModeD);
550 ia32_emit_am(env, node);
555 * Emits registers and/or address mode of a unary operation.
557 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node, int pos) {
560 switch(get_ia32_op_type(node)) {
562 op = get_irn_n(node, pos);
563 if (is_ia32_Immediate(op)) {
564 emit_ia32_Immediate(env, op);
565 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
566 ia32_emit_immediate(env, node);
568 ia32_emit_source_register(env, node, pos);
573 ia32_emit_am(env, node);
576 assert(0 && "unsupported op type");
581 * Emits address mode.
583 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
584 ir_entity *ent = get_ia32_am_sc(node);
585 int offs = get_ia32_am_offs_int(node);
586 ir_node *base = get_irn_n(node, 0);
587 int has_base = !is_ia32_NoReg_GP(base);
588 ir_node *index = get_irn_n(node, 1);
589 int has_index = !is_ia32_NoReg_GP(index);
591 /* just to be sure... */
592 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
598 set_entity_backend_marked(ent, 1);
599 id = get_entity_ld_ident(ent);
600 if (is_ia32_am_sc_sign(node))
601 be_emit_char(env, '-');
602 be_emit_ident(env, id);
604 if(get_entity_owner(ent) == get_tls_type()) {
605 if (get_entity_visibility(ent) == visibility_external_allocated) {
606 be_emit_cstring(env, "@INDNTPOFF");
608 be_emit_cstring(env, "@NTPOFF");
615 be_emit_irprintf(env->emit, "%+d", offs);
617 be_emit_irprintf(env->emit, "%d", offs);
621 if (has_base || has_index) {
622 be_emit_char(env, '(');
626 ia32_emit_source_register(env, node, 0);
629 /* emit index + scale */
632 be_emit_char(env, ',');
633 ia32_emit_source_register(env, node, 1);
635 scale = get_ia32_am_scale(node);
637 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
640 be_emit_char(env, ')');
644 /*************************************************
647 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
648 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
649 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
650 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
652 *************************************************/
655 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
658 * coding of conditions
660 struct cmp2conditon_t {
666 * positive conditions for signed compares
669 const struct cmp2conditon_t cmp2condition_s[] = {
670 { NULL, pn_Cmp_False }, /* always false */
671 { "e", pn_Cmp_Eq }, /* == */
672 { "l", pn_Cmp_Lt }, /* < */
673 { "le", pn_Cmp_Le }, /* <= */
674 { "g", pn_Cmp_Gt }, /* > */
675 { "ge", pn_Cmp_Ge }, /* >= */
676 { "ne", pn_Cmp_Lg }, /* != */
677 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
681 * positive conditions for unsigned compares
684 const struct cmp2conditon_t cmp2condition_u[] = {
685 { NULL, pn_Cmp_False }, /* always false */
686 { "e", pn_Cmp_Eq }, /* == */
687 { "b", pn_Cmp_Lt }, /* < */
688 { "be", pn_Cmp_Le }, /* <= */
689 { "a", pn_Cmp_Gt }, /* > */
690 { "ae", pn_Cmp_Ge }, /* >= */
691 { "ne", pn_Cmp_Lg }, /* != */
692 { NULL, pn_Cmp_True }, /* always true */
696 * returns the condition code
699 const char *get_cmp_suffix(pn_Cmp cmp_code)
701 assert( (cmp2condition_s[cmp_code & 7].num) == (cmp_code & 7));
702 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
704 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
705 return cmp2condition_u[cmp_code & 7].name;
707 return cmp2condition_s[cmp_code & 7].name;
711 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
713 be_emit_string(env, get_cmp_suffix(pnc));
718 * Returns the target block for a control flow node.
721 ir_node *get_cfop_target_block(const ir_node *irn) {
722 return get_irn_link(irn);
726 * Emits a block label for the given block.
729 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
731 be_emit_cstring(env, BLOCK_PREFIX);
732 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
736 * Emits the target label for a control flow node.
739 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
740 ir_node *block = get_cfop_target_block(node);
742 ia32_emit_block_name(env, block);
745 /** Return the next block in Block schedule */
746 static ir_node *next_blk_sched(const ir_node *block) {
747 return get_irn_link(block);
751 * Returns the Proj with projection number proj and NOT mode_M
754 ir_node *get_proj(const ir_node *node, long proj) {
755 const ir_edge_t *edge;
758 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
760 foreach_out_edge(node, edge) {
761 src = get_edge_src_irn(edge);
763 assert(is_Proj(src) && "Proj expected");
764 if (get_irn_mode(src) == mode_M)
767 if (get_Proj_proj(src) == proj)
774 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
777 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
779 const ir_node *proj_true;
780 const ir_node *proj_false;
781 const ir_node *block;
782 const ir_node *next_block;
785 /* get both Proj's */
786 proj_true = get_proj(node, pn_Cond_true);
787 assert(proj_true && "CondJmp without true Proj");
789 proj_false = get_proj(node, pn_Cond_false);
790 assert(proj_false && "CondJmp without false Proj");
792 /* for now, the code works for scheduled and non-schedules blocks */
793 block = get_nodes_block(node);
795 /* we have a block schedule */
796 next_block = next_blk_sched(block);
798 if (get_cfop_target_block(proj_true) == next_block) {
799 /* exchange both proj's so the second one can be omitted */
800 const ir_node *t = proj_true;
802 proj_true = proj_false;
805 pnc = get_negated_pnc(pnc, mode);
808 /* in case of unordered compare, check for parity */
809 if (pnc & pn_Cmp_Uo) {
810 be_emit_cstring(env, "\tjp ");
811 ia32_emit_cfop_target(env, proj_true);
812 be_emit_finish_line_gas(env, proj_true);
815 be_emit_cstring(env, "\tj");
816 ia32_emit_cmp_suffix(env, pnc | ia32_pn_Cmp_Unsigned);
817 be_emit_char(env, ' ');
818 ia32_emit_cfop_target(env, proj_true);
819 be_emit_finish_line_gas(env, proj_true);
821 /* the second Proj might be a fallthrough */
822 if (get_cfop_target_block(proj_false) != next_block) {
823 be_emit_cstring(env, "\tjmp ");
824 ia32_emit_cfop_target(env, proj_false);
825 be_emit_finish_line_gas(env, proj_false);
827 be_emit_cstring(env, "\t/* fallthrough to ");
828 ia32_emit_cfop_target(env, proj_false);
829 be_emit_cstring(env, " */");
830 be_emit_finish_line_gas(env, proj_false);
835 * Emits code for conditional jump.
838 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
839 be_emit_cstring(env, "\tcmp");
840 ia32_emit_mode_suffix(env, node);
841 be_emit_char(env, ' ');
842 ia32_emit_binop(env, node);
843 be_emit_finish_line_gas(env, node);
845 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
849 * Emits code for conditional jump with two variables.
852 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
853 CondJmp_emitter(env, node);
857 * Emits code for conditional test and jump.
860 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
861 be_emit_cstring(env, "\ttest");
862 ia32_emit_mode_suffix(env, node);
863 be_emit_char(env, ' ');
865 ia32_emit_binop(env, node);
866 be_emit_finish_line_gas(env, node);
868 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
872 * Emits code for conditional test and jump with two variables.
875 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
876 TestJmp_emitter(env, node);
880 * Emits code for conditional SSE floating point jump with two variables.
883 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
884 be_emit_cstring(env, "\tucomi");
885 ia32_emit_xmm_mode_suffix(env, node);
886 be_emit_char(env, ' ');
887 ia32_emit_binop(env, node);
888 be_emit_finish_line_gas(env, node);
890 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
894 * Emits code for conditional x87 floating point jump with two variables.
897 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
898 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
899 const char *reg = x87_attr->x87[1]->name;
900 long pnc = get_ia32_pncode(node);
902 switch (get_ia32_irn_opcode(node)) {
903 case iro_ia32_fcomrJmp:
904 pnc = get_inversed_pnc(pnc);
905 reg = x87_attr->x87[0]->name;
906 case iro_ia32_fcomJmp:
908 be_emit_cstring(env, "\tfucom ");
910 case iro_ia32_fcomrpJmp:
911 pnc = get_inversed_pnc(pnc);
912 reg = x87_attr->x87[0]->name;
913 case iro_ia32_fcompJmp:
914 be_emit_cstring(env, "\tfucomp ");
916 case iro_ia32_fcomrppJmp:
917 pnc = get_inversed_pnc(pnc);
918 case iro_ia32_fcomppJmp:
919 be_emit_cstring(env, "\tfucompp ");
925 be_emit_char(env, '%');
926 be_emit_string(env, reg);
928 be_emit_finish_line_gas(env, node);
930 be_emit_cstring(env, "\tfnstsw %ax");
931 be_emit_finish_line_gas(env, node);
932 be_emit_cstring(env, "\tsahf");
933 be_emit_finish_line_gas(env, node);
935 finish_CondJmp(env, node, mode_E, pnc);
939 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
941 const arch_register_t *in1, *in2, *out;
942 long pnc = get_ia32_pncode(node);
944 out = arch_get_irn_register(env->arch_env, node);
946 /* we have to emit the cmp first, because the destination register */
947 /* could be one of the compare registers */
948 if (is_ia32_xCmpCMov(node)) {
949 be_emit_cstring(env, "\tucomis");
950 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
951 be_emit_char(env, ' ');
952 ia32_emit_source_register(env, node, 1);
953 be_emit_cstring(env, ", ");
954 ia32_emit_source_register(env, node, 0);
956 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 2));
957 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 3));
959 if (is_ia32_CmpCMov(node)) {
960 be_emit_cstring(env, "\tcmp ");
962 assert(is_ia32_TestCMov(node));
963 be_emit_cstring(env, "\ttest ");
965 ia32_emit_binop(env, node);
967 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 5));
968 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 6));
970 be_emit_finish_line_gas(env, node);
973 /* best case: default in == out -> do nothing */
974 } else if(in2 == &ia32_gp_regs[REG_GP_UKNWN]) {
975 /* also nothign to do for unknown regs */
976 } else if (out == in1) {
977 const arch_register_t *t;
978 /* true in == out -> need complement compare and exchange true and
983 pnc = get_negated_pnc(pnc, get_irn_mode(node));
985 /* out is different from both ins: need copy default -> out */
986 be_emit_cstring(env, "\tmovl ");
987 ia32_emit_register(env, in2);
988 be_emit_cstring(env, ", ");
989 ia32_emit_register(env, out);
990 be_emit_finish_line_gas(env, node);
993 be_emit_cstring(env, "\tcmov");
994 ia32_emit_cmp_suffix(env, pnc );
995 be_emit_cstring(env, "l ");
996 ia32_emit_register(env, in1);
997 be_emit_cstring(env, ", ");
998 ia32_emit_register(env, out);
1000 be_emit_finish_line_gas(env, node);
1004 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
1006 CMov_emitter(env, node);
1010 void emit_ia32_TestCMov(ia32_emit_env_t *env, const ir_node *node)
1012 CMov_emitter(env, node);
1016 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
1018 CMov_emitter(env, node);
1022 void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
1024 long pnc = get_ia32_pncode(node);
1025 const char *reg8bit;
1026 const arch_register_t *out;
1028 out = arch_get_irn_register(env->arch_env, node);
1029 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1031 if(is_ia32_xCmpSet(node)) {
1032 be_emit_cstring(env, "\tucomis");
1033 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1034 be_emit_char(env, ' ');
1035 ia32_emit_binop(env, node);
1037 if (is_ia32_CmpSet(node)) {
1038 be_emit_cstring(env, "\tcmp ");
1040 assert(is_ia32_TestSet(node));
1041 be_emit_cstring(env, "\ttest ");
1043 ia32_emit_binop(env, node);
1045 be_emit_finish_line_gas(env, node);
1047 /* use mov to clear target because it doesn't affect the eflags */
1048 be_emit_cstring(env, "\tmovl $0, %");
1049 be_emit_string(env, arch_register_get_name(out));
1050 be_emit_finish_line_gas(env, node);
1052 be_emit_cstring(env, "\tset");
1053 ia32_emit_cmp_suffix(env, pnc);
1054 be_emit_cstring(env, " %");
1055 be_emit_string(env, reg8bit);
1056 be_emit_finish_line_gas(env, node);
1060 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1061 Set_emitter(env, node);
1065 void emit_ia32_TestSet(ia32_emit_env_t *env, const ir_node *node) {
1066 Set_emitter(env, node);
1070 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1071 Set_emitter(env, node);
1075 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1077 long pnc = get_ia32_pncode(node);
1078 long unord = pnc & pn_Cmp_Uo;
1080 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1083 case pn_Cmp_Leg: /* odered */
1086 case pn_Cmp_Uo: /* unordered */
1090 case pn_Cmp_Eq: /* == */
1094 case pn_Cmp_Lt: /* < */
1098 case pn_Cmp_Le: /* <= */
1102 case pn_Cmp_Gt: /* > */
1106 case pn_Cmp_Ge: /* >= */
1110 case pn_Cmp_Lg: /* != */
1115 assert(sse_pnc >= 0 && "unsupported compare");
1117 if (unord && sse_pnc != 3) {
1119 We need a separate compare against unordered.
1120 Quick and Dirty solution:
1121 - get some memory on stack
1125 - and result and stored result
1128 be_emit_cstring(env, "\tsubl $8, %esp");
1129 be_emit_finish_line_gas(env, node);
1131 be_emit_cstring(env, "\tcmpsd $3, ");
1132 ia32_emit_binop(env, node);
1133 be_emit_finish_line_gas(env, node);
1135 be_emit_cstring(env, "\tmovsd ");
1136 ia32_emit_dest_register(env, node, 0);
1137 be_emit_cstring(env, ", (%esp)");
1138 be_emit_finish_line_gas(env, node);
1141 be_emit_cstring(env, "\tcmpsd ");
1142 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1143 ia32_emit_binop(env, node);
1144 be_emit_finish_line_gas(env, node);
1146 if (unord && sse_pnc != 3) {
1147 be_emit_cstring(env, "\tandpd (%esp), ");
1148 ia32_emit_dest_register(env, node, 0);
1149 be_emit_finish_line_gas(env, node);
1151 be_emit_cstring(env, "\taddl $8, %esp");
1152 be_emit_finish_line_gas(env, node);
1156 /*********************************************************
1159 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1160 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1161 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1162 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1165 *********************************************************/
1167 /* jump table entry (target and corresponding number) */
1168 typedef struct _branch_t {
1173 /* jump table for switch generation */
1174 typedef struct _jmp_tbl_t {
1175 ir_node *defProj; /**< default target */
1176 long min_value; /**< smallest switch case */
1177 long max_value; /**< largest switch case */
1178 long num_branches; /**< number of jumps */
1179 char *label; /**< label of the jump table */
1180 branch_t *branches; /**< jump array */
1184 * Compare two variables of type branch_t. Used to sort all switch cases
1187 int ia32_cmp_branch_t(const void *a, const void *b) {
1188 branch_t *b1 = (branch_t *)a;
1189 branch_t *b2 = (branch_t *)b;
1191 if (b1->value <= b2->value)
1198 * Emits code for a SwitchJmp (creates a jump table if
1199 * possible otherwise a cmp-jmp cascade). Port from
1203 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1204 unsigned long interval;
1209 const ir_edge_t *edge;
1211 /* fill the table structure */
1212 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1213 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1215 tbl.num_branches = get_irn_n_edges(node);
1216 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1217 tbl.min_value = INT_MAX;
1218 tbl.max_value = INT_MIN;
1221 /* go over all proj's and collect them */
1222 foreach_out_edge(node, edge) {
1223 proj = get_edge_src_irn(edge);
1224 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1226 pnc = get_Proj_proj(proj);
1228 /* create branch entry */
1229 tbl.branches[i].target = proj;
1230 tbl.branches[i].value = pnc;
1232 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1233 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1235 /* check for default proj */
1236 if (pnc == get_ia32_pncode(node)) {
1237 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1244 /* sort the branches by their number */
1245 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1247 /* two-complement's magic make this work without overflow */
1248 interval = tbl.max_value - tbl.min_value;
1250 /* emit the table */
1251 be_emit_cstring(env, "\tcmpl $");
1252 be_emit_irprintf(env->emit, "%u, ", interval);
1253 ia32_emit_source_register(env, node, 0);
1254 be_emit_finish_line_gas(env, node);
1256 be_emit_cstring(env, "\tja ");
1257 ia32_emit_cfop_target(env, tbl.defProj);
1258 be_emit_finish_line_gas(env, node);
1260 if (tbl.num_branches > 1) {
1262 be_emit_cstring(env, "\tjmp *");
1263 be_emit_string(env, tbl.label);
1264 be_emit_cstring(env, "(,");
1265 ia32_emit_source_register(env, node, 0);
1266 be_emit_cstring(env, ",4)");
1267 be_emit_finish_line_gas(env, node);
1269 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1270 be_emit_cstring(env, "\t.align 4\n");
1271 be_emit_write_line(env);
1273 be_emit_string(env, tbl.label);
1274 be_emit_cstring(env, ":\n");
1275 be_emit_write_line(env);
1277 be_emit_cstring(env, ".long ");
1278 ia32_emit_cfop_target(env, tbl.branches[0].target);
1279 be_emit_finish_line_gas(env, NULL);
1281 last_value = tbl.branches[0].value;
1282 for (i = 1; i < tbl.num_branches; ++i) {
1283 while (++last_value < tbl.branches[i].value) {
1284 be_emit_cstring(env, ".long ");
1285 ia32_emit_cfop_target(env, tbl.defProj);
1286 be_emit_finish_line_gas(env, NULL);
1288 be_emit_cstring(env, ".long ");
1289 ia32_emit_cfop_target(env, tbl.branches[i].target);
1290 be_emit_finish_line_gas(env, NULL);
1292 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1294 /* one jump is enough */
1295 be_emit_cstring(env, "\tjmp ");
1296 ia32_emit_cfop_target(env, tbl.branches[0].target);
1297 be_emit_finish_line_gas(env, node);
1307 * Emits code for a unconditional jump.
1310 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1311 ir_node *block, *next_block;
1313 /* for now, the code works for scheduled and non-schedules blocks */
1314 block = get_nodes_block(node);
1316 /* we have a block schedule */
1317 next_block = next_blk_sched(block);
1318 if (get_cfop_target_block(node) != next_block) {
1319 be_emit_cstring(env, "\tjmp ");
1320 ia32_emit_cfop_target(env, node);
1322 be_emit_cstring(env, "\t/* fallthrough to ");
1323 ia32_emit_cfop_target(env, node);
1324 be_emit_cstring(env, " */");
1326 be_emit_finish_line_gas(env, node);
1330 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
1332 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1334 be_emit_char(env, '$');
1335 if(attr->symconst != NULL) {
1336 ident *id = get_entity_ld_ident(attr->symconst);
1338 if(attr->attr.data.am_sc_sign)
1339 be_emit_char(env, '-');
1340 be_emit_ident(env, id);
1342 if(attr->symconst == NULL || attr->offset != 0) {
1343 if(attr->symconst != NULL)
1344 be_emit_char(env, '+');
1345 be_emit_irprintf(env->emit, "%d", attr->offset);
1350 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1353 const arch_register_t *reg;
1354 const char *reg_name;
1358 const ia32_attr_t *attr;
1365 /* parse modifiers */
1368 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1369 be_emit_char(env, '%');
1372 be_emit_char(env, '%');
1392 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1393 "'%c' for asm op\n", node, c);
1399 sscanf(s, "%d%n", &num, &p);
1401 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1409 attr = get_ia32_attr_const(node);
1410 n_outs = ARR_LEN(attr->slots);
1412 reg = get_out_reg(env, node, num);
1415 int in = num - n_outs;
1416 if(in >= get_irn_arity(node)) {
1417 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1418 "op (%+F)\n", num, node);
1421 pred = get_irn_n(node, in);
1422 /* might be an immediate value */
1423 if(is_ia32_Immediate(pred)) {
1424 emit_ia32_Immediate(env, pred);
1427 reg = get_in_reg(env, node, in);
1430 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1431 "(%+F)\n", num, node);
1436 be_emit_char(env, '%');
1439 reg_name = arch_register_get_name(reg);
1442 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1445 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
1448 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1451 panic("Invalid asm op modifier");
1453 be_emit_string(env, reg_name);
1459 * Emits code for an ASM pseudo op.
1462 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1464 const void *gen_attr = get_irn_generic_attr_const(node);
1465 const ia32_asm_attr_t *attr
1466 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1467 ident *asm_text = attr->asm_text;
1468 const char *s = get_id_str(asm_text);
1470 be_emit_cstring(env, "# Begin ASM \t");
1471 be_emit_finish_line_gas(env, node);
1474 be_emit_char(env, '\t');
1478 s = emit_asm_operand(env, node, s);
1481 be_emit_char(env, *s);
1486 be_emit_char(env, '\n');
1487 be_emit_write_line(env);
1489 be_emit_cstring(env, "# End ASM\n");
1490 be_emit_write_line(env);
1493 /**********************************
1496 * | | ___ _ __ _ _| |_) |
1497 * | | / _ \| '_ \| | | | _ <
1498 * | |___| (_) | |_) | |_| | |_) |
1499 * \_____\___/| .__/ \__, |____/
1502 **********************************/
1505 * Emit movsb/w instructions to make mov count divideable by 4
1508 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1509 be_emit_cstring(env, "\tcld");
1510 be_emit_finish_line_gas(env, NULL);
1514 be_emit_cstring(env, "\tmovsb");
1515 be_emit_finish_line_gas(env, NULL);
1518 be_emit_cstring(env, "\tmovsw");
1519 be_emit_finish_line_gas(env, NULL);
1522 be_emit_cstring(env, "\tmovsb");
1523 be_emit_finish_line_gas(env, NULL);
1524 be_emit_cstring(env, "\tmovsw");
1525 be_emit_finish_line_gas(env, NULL);
1531 * Emit rep movsd instruction for memcopy.
1534 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1535 tarval *tv = get_ia32_Immop_tarval(node);
1536 int rem = get_tarval_long(tv);
1538 emit_CopyB_prolog(env, rem);
1540 be_emit_cstring(env, "\trep movsd");
1541 be_emit_finish_line_gas(env, node);
1545 * Emits unrolled memcopy.
1548 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1549 tarval *tv = get_ia32_Immop_tarval(node);
1550 int size = get_tarval_long(tv);
1552 emit_CopyB_prolog(env, size & 0x3);
1556 be_emit_cstring(env, "\tmovsd");
1557 be_emit_finish_line_gas(env, NULL);
1563 /***************************
1567 * | | / _ \| '_ \ \ / /
1568 * | |___| (_) | | | \ V /
1569 * \_____\___/|_| |_|\_/
1571 ***************************/
1574 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1577 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1578 ir_mode *ls_mode = get_ia32_ls_mode(node);
1579 int ls_bits = get_mode_size_bits(ls_mode);
1581 be_emit_cstring(env, "\tcvt");
1583 if(is_ia32_Conv_I2FP(node)) {
1585 be_emit_cstring(env, "si2ss");
1587 be_emit_cstring(env, "si2sd");
1589 } else if(is_ia32_Conv_FP2I(node)) {
1591 be_emit_cstring(env, "ss2si");
1593 be_emit_cstring(env, "sd2si");
1596 assert(is_ia32_Conv_FP2FP(node));
1598 be_emit_cstring(env, "sd2ss");
1600 be_emit_cstring(env, "ss2sd");
1603 be_emit_char(env, ' ');
1605 switch(get_ia32_op_type(node)) {
1607 ia32_emit_source_register(env, node, 2);
1608 be_emit_cstring(env, ", ");
1609 ia32_emit_dest_register(env, node, 0);
1611 case ia32_AddrModeS:
1612 ia32_emit_dest_register(env, node, 0);
1613 be_emit_cstring(env, ", ");
1614 ia32_emit_am(env, node);
1617 assert(0 && "unsupported op type for Conv");
1619 be_emit_finish_line_gas(env, node);
1623 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1624 emit_ia32_Conv_with_FP(env, node);
1628 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1629 emit_ia32_Conv_with_FP(env, node);
1633 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1634 emit_ia32_Conv_with_FP(env, node);
1638 * Emits code for an Int conversion.
1641 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1642 const char *sign_suffix;
1643 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1644 int smaller_bits = get_mode_size_bits(smaller_mode);
1646 const arch_register_t *in_reg, *out_reg;
1648 assert(!mode_is_float(smaller_mode));
1649 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1651 signed_mode = mode_is_signed(smaller_mode);
1652 if(smaller_bits == 32) {
1653 // this should not happen as it's no convert
1657 sign_suffix = signed_mode ? "s" : "z";
1660 switch(get_ia32_op_type(node)) {
1662 in_reg = get_in_reg(env, node, 2);
1663 out_reg = get_out_reg(env, node, 0);
1665 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1666 out_reg == &ia32_gp_regs[REG_EAX] &&
1670 /* argument and result are both in EAX and */
1671 /* signedness is ok: -> use the smaller cwtl opcode */
1672 be_emit_cstring(env, "\tcwtl");
1674 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1676 be_emit_cstring(env, "\tmov");
1677 be_emit_string(env, sign_suffix);
1678 ia32_emit_mode_suffix_mode(env, smaller_mode);
1679 be_emit_cstring(env, "l %");
1680 be_emit_string(env, sreg);
1681 be_emit_cstring(env, ", ");
1682 ia32_emit_dest_register(env, node, 0);
1685 case ia32_AddrModeS: {
1686 be_emit_cstring(env, "\tmov");
1687 be_emit_string(env, sign_suffix);
1688 ia32_emit_mode_suffix_mode(env, smaller_mode);
1689 be_emit_cstring(env, "l %");
1690 ia32_emit_am(env, node);
1691 be_emit_cstring(env, ", ");
1692 ia32_emit_dest_register(env, node, 0);
1696 assert(0 && "unsupported op type for Conv");
1698 be_emit_finish_line_gas(env, node);
1702 * Emits code for an 8Bit Int conversion.
1704 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1705 emit_ia32_Conv_I2I(env, node);
1709 /*******************************************
1712 * | |__ ___ _ __ ___ __| | ___ ___
1713 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1714 * | |_) | __/ | | | (_) | (_| | __/\__ \
1715 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1717 *******************************************/
1720 * Emits a backend call
1723 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1724 ir_entity *ent = be_Call_get_entity(node);
1726 be_emit_cstring(env, "\tcall ");
1728 set_entity_backend_marked(ent, 1);
1729 be_emit_string(env, get_entity_ld_name(ent));
1731 be_emit_char(env, '*');
1732 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1734 be_emit_finish_line_gas(env, node);
1738 * Emits code to increase stack pointer.
1741 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1742 int offs = be_get_IncSP_offset(node);
1748 be_emit_cstring(env, "\tsubl $");
1749 be_emit_irprintf(env->emit, "%u, ", offs);
1750 ia32_emit_source_register(env, node, 0);
1752 be_emit_cstring(env, "\taddl $");
1753 be_emit_irprintf(env->emit, "%u, ", -offs);
1754 ia32_emit_source_register(env, node, 0);
1756 be_emit_finish_line_gas(env, node);
1760 * Emits code to set stack pointer.
1763 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1764 be_emit_cstring(env, "\tmovl ");
1765 ia32_emit_source_register(env, node, 2);
1766 be_emit_cstring(env, ", ");
1767 ia32_emit_dest_register(env, node, 0);
1768 be_emit_finish_line_gas(env, node);
1772 * Emits code for Copy/CopyKeep.
1775 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1777 const arch_env_t *arch_env = env->arch_env;
1778 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1779 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1785 if(is_unknown_reg(in))
1787 /* copies of vf nodes aren't real... */
1788 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1791 mode = get_irn_mode(node);
1792 if (mode == mode_E) {
1793 be_emit_cstring(env, "\tmovsd ");
1794 ia32_emit_register(env, in);
1795 be_emit_cstring(env, ", ");
1796 ia32_emit_register(env, out);
1798 be_emit_cstring(env, "\tmovl ");
1799 ia32_emit_register(env, in);
1800 be_emit_cstring(env, ", ");
1801 ia32_emit_register(env, out);
1803 be_emit_finish_line_gas(env, node);
1807 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1808 Copy_emitter(env, node, be_get_Copy_op(node));
1812 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1813 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1817 * Emits code for exchange.
1820 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1821 const arch_register_t *in1, *in2;
1822 const arch_register_class_t *cls1, *cls2;
1824 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1825 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1827 cls1 = arch_register_get_class(in1);
1828 cls2 = arch_register_get_class(in2);
1830 assert(cls1 == cls2 && "Register class mismatch at Perm");
1832 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1833 be_emit_cstring(env, "\txchg ");
1834 ia32_emit_source_register(env, node, 1);
1835 be_emit_cstring(env, ", ");
1836 ia32_emit_source_register(env, node, 0);
1837 be_emit_finish_line_gas(env, node);
1838 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1839 be_emit_cstring(env, "\txorpd ");
1840 ia32_emit_source_register(env, node, 1);
1841 be_emit_cstring(env, ", ");
1842 ia32_emit_source_register(env, node, 0);
1843 be_emit_finish_line_gas(env, NULL);
1845 be_emit_cstring(env, "\txorpd ");
1846 ia32_emit_source_register(env, node, 0);
1847 be_emit_cstring(env, ", ");
1848 ia32_emit_source_register(env, node, 1);
1849 be_emit_finish_line_gas(env, NULL);
1851 be_emit_cstring(env, "\txorpd ");
1852 ia32_emit_source_register(env, node, 1);
1853 be_emit_cstring(env, ", ");
1854 ia32_emit_source_register(env, node, 0);
1855 be_emit_finish_line_gas(env, node);
1856 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1858 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1864 * Emits code for Constant loading.
1867 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1868 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1870 if (imm_tp == ia32_ImmSymConst) {
1871 be_emit_cstring(env, "\tmovl ");
1872 ia32_emit_immediate(env, node);
1873 be_emit_cstring(env, ", ");
1874 ia32_emit_dest_register(env, node, 0);
1876 tarval *tv = get_ia32_Immop_tarval(node);
1877 assert(get_irn_mode(node) == mode_Iu);
1878 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1879 if (tarval_is_null(tv)) {
1880 if (env->isa->opt_arch == arch_pentium_4) {
1881 /* P4 prefers sub r, r, others xor r, r */
1882 be_emit_cstring(env, "\tsubl ");
1884 be_emit_cstring(env, "\txorl ");
1886 ia32_emit_dest_register(env, node, 0);
1887 be_emit_cstring(env, ", ");
1888 ia32_emit_dest_register(env, node, 0);
1890 be_emit_cstring(env, "\tmovl ");
1891 ia32_emit_immediate(env, node);
1892 be_emit_cstring(env, ", ");
1893 ia32_emit_dest_register(env, node, 0);
1896 be_emit_finish_line_gas(env, node);
1900 * Emits code to load the TLS base
1903 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1904 be_emit_cstring(env, "\tmovl %gs:0, ");
1905 ia32_emit_dest_register(env, node, 0);
1906 be_emit_finish_line_gas(env, node);
1910 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
1912 be_emit_cstring(env, "\tret");
1913 be_emit_finish_line_gas(env, node);
1917 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
1924 /***********************************************************************************
1927 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1928 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1929 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1930 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1932 ***********************************************************************************/
1935 * Enters the emitter functions for handled nodes into the generic
1936 * pointer of an opcode.
1939 void ia32_register_emitters(void) {
1941 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1942 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1943 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1944 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1945 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1946 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1948 /* first clear the generic function pointer for all ops */
1949 clear_irp_opcodes_generic_func();
1951 /* register all emitter functions defined in spec */
1952 ia32_register_spec_emitters();
1954 /* other ia32 emitter functions */
1959 IA32_EMIT(TestCMov);
1962 IA32_EMIT(SwitchJmp);
1965 IA32_EMIT(Conv_I2FP);
1966 IA32_EMIT(Conv_FP2I);
1967 IA32_EMIT(Conv_FP2FP);
1968 IA32_EMIT(Conv_I2I);
1969 IA32_EMIT(Conv_I2I8Bit);
1974 IA32_EMIT(xCmpCMov);
1975 IA32_EMIT(xCondJmp);
1976 IA32_EMIT2(fcomJmp, x87CondJmp);
1977 IA32_EMIT2(fcompJmp, x87CondJmp);
1978 IA32_EMIT2(fcomppJmp, x87CondJmp);
1979 IA32_EMIT2(fcomrJmp, x87CondJmp);
1980 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1981 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1983 /* benode emitter */
2009 static const char *last_name = NULL;
2010 static unsigned last_line = -1;
2011 static unsigned num = -1;
2014 * Emit the debug support for node node.
2017 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
2018 dbg_info *db = get_irn_dbg_info(node);
2020 const char *fname = be_retrieve_dbg_info(db, &lineno);
2022 if (! env->cg->birg->main_env->options->stabs_debug_support)
2026 if (last_name != fname) {
2028 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2031 if (last_line != lineno) {
2034 snprintf(name, sizeof(name), ".LM%u", ++num);
2036 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2037 be_emit_string(env, name);
2038 be_emit_cstring(env, ":\n");
2039 be_emit_write_line(env);
2044 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2047 * Emits code for a node.
2050 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2051 ir_op *op = get_irn_op(node);
2053 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2055 if (op->ops.generic) {
2056 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2057 ia32_emit_dbg(env, node);
2058 (*func) (env, node);
2060 emit_Nothing(env, node);
2061 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
2067 * Emits gas alignment directives
2070 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2071 be_emit_cstring(env, "\t.p2align ");
2072 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2073 be_emit_write_line(env);
2077 * Emits gas alignment directives for Functions depended on cpu architecture.
2080 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2082 unsigned maximum_skip;
2097 maximum_skip = (1 << align) - 1;
2098 ia32_emit_alignment(env, align, maximum_skip);
2102 * Emits gas alignment directives for Labels depended on cpu architecture.
2105 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2106 unsigned align; unsigned maximum_skip;
2121 maximum_skip = (1 << align) - 1;
2122 ia32_emit_alignment(env, align, maximum_skip);
2126 * Test wether a block should be aligned.
2127 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2128 * 16 bytes. However we should only do that if the alignment nops before the
2129 * label aren't executed more often than we have jumps to the label.
2132 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2133 static const double DELTA = .0001;
2134 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2136 double prev_freq = 0; /**< execfreq of the fallthrough block */
2137 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2138 cpu_support cpu = env->isa->opt_arch;
2141 if(exec_freq == NULL)
2143 if(cpu == arch_i386 || cpu == arch_i486)
2146 block_freq = get_block_execfreq(exec_freq, block);
2147 if(block_freq < DELTA)
2150 n_cfgpreds = get_Block_n_cfgpreds(block);
2151 for(i = 0; i < n_cfgpreds; ++i) {
2152 ir_node *pred = get_Block_cfgpred_block(block, i);
2153 double pred_freq = get_block_execfreq(exec_freq, pred);
2156 prev_freq += pred_freq;
2158 jmp_freq += pred_freq;
2162 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2165 jmp_freq /= prev_freq;
2169 case arch_athlon_64:
2171 return jmp_freq > 3;
2173 return jmp_freq > 2;
2178 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2183 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2186 n_cfgpreds = get_Block_n_cfgpreds(block);
2187 if (n_cfgpreds == 0) {
2189 } else if (n_cfgpreds == 1) {
2190 ir_node *pred = get_Block_cfgpred(block, 0);
2191 ir_node *pred_block = get_nodes_block(pred);
2193 /* we don't need labels for fallthrough blocks, however switch-jmps
2194 * are no fallthroughs */
2195 if(pred_block == prev &&
2196 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2205 if (should_align_block(env, block, prev)) {
2207 ia32_emit_align_label(env, env->isa->opt_arch);
2211 ia32_emit_block_name(env, block);
2212 be_emit_char(env, ':');
2214 be_emit_pad_comment(env);
2215 be_emit_cstring(env, " /* preds:");
2217 /* emit list of pred blocks in comment */
2218 arity = get_irn_arity(block);
2219 for (i = 0; i < arity; ++i) {
2220 ir_node *predblock = get_Block_cfgpred_block(block, i);
2221 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2224 be_emit_cstring(env, "\t/* ");
2225 ia32_emit_block_name(env, block);
2226 be_emit_cstring(env, ": ");
2228 if (exec_freq != NULL) {
2229 be_emit_irprintf(env->emit, " freq: %f",
2230 get_block_execfreq(exec_freq, block));
2232 be_emit_cstring(env, " */\n");
2233 be_emit_write_line(env);
2237 * Walks over the nodes in a block connected by scheduling edges
2238 * and emits code for each node.
2241 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2243 const ir_node *node;
2245 ia32_emit_block_header(env, block, last_block);
2247 /* emit the contents of the block */
2248 ia32_emit_dbg(env, block);
2249 sched_foreach(block, node) {
2250 ia32_emit_node(env, node);
2255 * Emits code for function start.
2258 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2259 ir_entity *irg_ent = get_irg_entity(irg);
2260 const char *irg_name = get_entity_ld_name(irg_ent);
2261 cpu_support cpu = env->isa->opt_arch;
2262 const be_irg_t *birg = env->cg->birg;
2264 be_emit_write_line(env);
2265 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2266 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2267 ia32_emit_align_func(env, cpu);
2268 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2269 be_emit_cstring(env, ".global ");
2270 be_emit_string(env, irg_name);
2271 be_emit_char(env, '\n');
2272 be_emit_write_line(env);
2274 ia32_emit_function_object(env, irg_name);
2275 be_emit_string(env, irg_name);
2276 be_emit_cstring(env, ":\n");
2277 be_emit_write_line(env);
2281 * Emits code for function end
2284 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2285 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2286 const be_irg_t *birg = env->cg->birg;
2288 ia32_emit_function_size(env, irg_name);
2289 be_dbg_method_end(birg->main_env->db_handle);
2290 be_emit_char(env, '\n');
2291 be_emit_write_line(env);
2296 * Sets labels for control flow nodes (jump target)
2299 void ia32_gen_labels(ir_node *block, void *data)
2302 int n = get_Block_n_cfgpreds(block);
2305 for (n--; n >= 0; n--) {
2306 pred = get_Block_cfgpred(block, n);
2307 set_irn_link(pred, block);
2312 * Emit an exception label if the current instruction can fail.
2314 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2315 if (get_ia32_exc_label(node)) {
2316 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2317 be_emit_write_line(env);
2322 * Main driver. Emits the code for one routine.
2324 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2325 ia32_emit_env_t env;
2327 ir_node *last_block = NULL;
2330 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2331 env.emit = &env.isa->emit;
2332 env.arch_env = cg->arch_env;
2335 ia32_register_emitters();
2337 ia32_emit_func_prolog(&env, irg);
2338 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2340 n = ARR_LEN(cg->blk_sched);
2341 for (i = 0; i < n;) {
2344 block = cg->blk_sched[i];
2346 next_bl = i < n ? cg->blk_sched[i] : NULL;
2348 /* set here the link. the emitter expects to find the next block here */
2349 set_irn_link(block, next_bl);
2350 ia32_gen_block(&env, block, last_block);
2354 ia32_emit_func_epilog(&env, irg);
2357 void ia32_init_emitter(void)
2359 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");