2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
27 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
35 * pnc_Leg => NP (ordered)
57 #include "iredges_t.h"
61 #include "raw_bitset.h"
65 #include "../besched.h"
66 #include "../benode.h"
68 #include "../be_dbgout.h"
69 #include "../beemitter.h"
70 #include "../begnuas.h"
72 #include "../be_dbgout.h"
74 #include "ia32_emitter.h"
75 #include "ia32_common_transform.h"
76 #include "gen_ia32_emitter.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "ia32_nodes_attr.h"
79 #include "ia32_new_nodes.h"
80 #include "ia32_architecture.h"
81 #include "bearch_ia32_t.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
85 #define SNPRINTF_BUF_LEN 128
87 static const ia32_isa_t *isa;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_registers[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
210 * Emit the name of the 8bit low register
212 static void emit_8bit_register(const arch_register_t *reg)
214 const char *reg_name = arch_register_get_name(reg);
215 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
216 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
219 be_emit_char(reg_name[1]); /* get the basic name of the register */
224 * Emit the name of the 8bit high register
226 static void emit_8bit_register_high(const arch_register_t *reg)
228 const char *reg_name = arch_register_get_name(reg);
229 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
230 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
233 be_emit_char(reg_name[1]); /* get the basic name of the register */
237 static void emit_16bit_register(const arch_register_t *reg)
239 const char *reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
246 * emit a register, possible shortened by a mode
248 * @param reg the register
249 * @param mode the mode of the register or NULL for full register
251 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
253 const char *reg_name;
256 int size = get_mode_size_bits(mode);
258 case 8: emit_8bit_register(reg); return;
259 case 16: emit_16bit_register(reg); return;
261 assert(mode_is_float(mode) || size == 32);
264 reg_name = arch_register_get_name(reg);
267 be_emit_string(reg_name);
270 void ia32_emit_source_register(const ir_node *node, int pos)
272 const arch_register_t *reg = get_in_reg(node, pos);
274 emit_register(reg, NULL);
277 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
279 be_gas_emit_entity(entity);
281 if (get_entity_owner(entity) == get_tls_type()) {
282 if (get_entity_visibility(entity) == ir_visibility_external) {
283 be_emit_cstring("@INDNTPOFF");
285 be_emit_cstring("@NTPOFF");
289 if (do_pic && !no_pic_adjust) {
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const arch_register_t *reg = get_in_reg(node, pos);
335 emit_8bit_register_high(reg);
338 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
340 const arch_register_t *reg;
341 const ir_node *in = get_irn_n(node, pos);
342 if (is_ia32_Immediate(in)) {
343 emit_ia32_Immediate(in);
347 reg = get_in_reg(node, pos);
348 emit_16bit_register(reg);
351 void ia32_emit_dest_register(const ir_node *node, int pos)
353 const arch_register_t *reg = get_out_reg(node, pos);
355 emit_register(reg, NULL);
358 void ia32_emit_dest_register_size(const ir_node *node, int pos)
360 const arch_register_t *reg = get_out_reg(node, pos);
362 emit_register(reg, get_ia32_ls_mode(node));
365 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
367 const arch_register_t *reg = get_out_reg(node, pos);
369 emit_register(reg, mode_Bu);
372 void ia32_emit_x87_register(const ir_node *node, int pos)
374 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
378 be_emit_string(attr->x87[pos]->name);
381 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
383 assert(mode_is_int(mode) || mode_is_reference(mode));
384 switch (get_mode_size_bits(mode)) {
385 case 8: be_emit_char('b'); return;
386 case 16: be_emit_char('w'); return;
387 case 32: be_emit_char('l'); return;
388 /* gas docu says q is the suffix but gcc, objdump and icc use ll
390 case 64: be_emit_cstring("ll"); return;
392 panic("Can't output mode_suffix for %+F", mode);
395 void ia32_emit_mode_suffix(const ir_node *node)
397 ir_mode *mode = get_ia32_ls_mode(node);
401 ia32_emit_mode_suffix_mode(mode);
404 void ia32_emit_x87_mode_suffix(const ir_node *node)
408 /* we only need to emit the mode on address mode */
409 if (get_ia32_op_type(node) == ia32_Normal)
412 mode = get_ia32_ls_mode(node);
413 assert(mode != NULL);
415 if (mode_is_float(mode)) {
416 switch (get_mode_size_bits(mode)) {
417 case 32: be_emit_char('s'); return;
418 case 64: be_emit_char('l'); return;
419 /* long doubles have different sizes due to alignment on different
423 case 128: be_emit_char('t'); return;
426 assert(mode_is_int(mode) || mode_is_reference(mode));
427 switch (get_mode_size_bits(mode)) {
428 case 16: be_emit_char('s'); return;
429 case 32: be_emit_char('l'); return;
430 /* gas docu says q is the suffix but gcc, objdump and icc use ll
432 case 64: be_emit_cstring("ll"); return;
435 panic("Can't output mode_suffix for %+F", mode);
438 static char get_xmm_mode_suffix(ir_mode *mode)
440 assert(mode_is_float(mode));
441 switch (get_mode_size_bits(mode)) {
444 default: panic("Invalid XMM mode");
448 void ia32_emit_xmm_mode_suffix(const ir_node *node)
450 ir_mode *mode = get_ia32_ls_mode(node);
451 assert(mode != NULL);
453 be_emit_char(get_xmm_mode_suffix(mode));
456 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
458 ir_mode *mode = get_ia32_ls_mode(node);
459 assert(mode != NULL);
460 be_emit_char(get_xmm_mode_suffix(mode));
463 void ia32_emit_extend_suffix(const ir_node *node)
465 ir_mode *mode = get_ia32_ls_mode(node);
466 if (get_mode_size_bits(mode) == 32)
468 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
469 ia32_emit_mode_suffix_mode(mode);
472 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
474 ir_node *in = get_irn_n(node, pos);
475 if (is_ia32_Immediate(in)) {
476 emit_ia32_Immediate(in);
478 const ir_mode *mode = get_ia32_ls_mode(node);
479 const arch_register_t *reg = get_in_reg(node, pos);
480 emit_register(reg, mode);
485 * Returns the target block for a control flow node.
487 static ir_node *get_cfop_target_block(const ir_node *irn)
489 assert(get_irn_mode(irn) == mode_X);
490 return (ir_node*)get_irn_link(irn);
494 * Emits the target label for a control flow node.
496 static void ia32_emit_cfop_target(const ir_node *node)
498 ir_node *block = get_cfop_target_block(node);
499 be_gas_emit_block_name(block);
503 * Emit the suffix for a compare instruction.
505 static void ia32_emit_condition_code(ia32_condition_code_t cc)
508 case ia32_cc_overflow: be_emit_cstring("o"); return;
509 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
510 case ia32_cc_float_below:
511 case ia32_cc_float_unordered_below:
512 case ia32_cc_below: be_emit_cstring("b"); return;
513 case ia32_cc_float_above_equal:
514 case ia32_cc_float_unordered_above_equal:
515 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
516 case ia32_cc_float_equal:
517 case ia32_cc_equal: be_emit_cstring("e"); return;
518 case ia32_cc_float_not_equal:
519 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
520 case ia32_cc_float_below_equal:
521 case ia32_cc_float_unordered_below_equal:
522 case ia32_cc_below_equal: be_emit_cstring("be"); return;
523 case ia32_cc_float_above:
524 case ia32_cc_float_unordered_above:
525 case ia32_cc_above: be_emit_cstring("a"); return;
526 case ia32_cc_sign: be_emit_cstring("s"); return;
527 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
528 case ia32_cc_parity: be_emit_cstring("p"); return;
529 case ia32_cc_not_parity: be_emit_cstring("np"); return;
530 case ia32_cc_less: be_emit_cstring("l"); return;
531 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
532 case ia32_cc_less_equal: be_emit_cstring("le"); return;
533 case ia32_cc_greater: be_emit_cstring("g"); return;
534 case ia32_cc_float_parity_cases:
535 case ia32_cc_additional_float_cases:
538 panic("Invalid ia32 condition code");
541 typedef enum ia32_emit_mod_t {
543 EMIT_RESPECT_LS = 1U << 0,
544 EMIT_ALTERNATE_AM = 1U << 1,
546 EMIT_HIGH_REG = 1U << 3,
547 EMIT_LOW_REG = 1U << 4
549 ENUM_BITSET(ia32_emit_mod_t)
552 * Emits address mode.
554 void ia32_emit_am(const ir_node *node)
556 ir_entity *ent = get_ia32_am_sc(node);
557 int offs = get_ia32_am_offs_int(node);
558 ir_node *base = get_irn_n(node, n_ia32_base);
559 int has_base = !is_ia32_NoReg_GP(base);
560 ir_node *idx = get_irn_n(node, n_ia32_index);
561 int has_index = !is_ia32_NoReg_GP(idx);
563 /* just to be sure... */
564 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
566 if (get_ia32_am_tls_segment(node))
567 be_emit_cstring("%gs:");
571 const ia32_attr_t *attr = get_ia32_attr_const(node);
572 if (is_ia32_am_sc_sign(node))
574 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
577 /* also handle special case if nothing is set */
578 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
580 be_emit_irprintf("%+d", offs);
582 be_emit_irprintf("%d", offs);
586 if (has_base || has_index) {
591 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
592 emit_register(reg, NULL);
595 /* emit index + scale */
597 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
600 emit_register(reg, NULL);
602 scale = get_ia32_am_scale(node);
604 be_emit_irprintf(",%d", 1 << scale);
612 * fmt parameter output
613 * ---- ---------------------- ---------------------------------------------
615 * %AM <node> address mode of the node
616 * %AR const arch_register_t* address mode of the node or register
617 * %ASx <node> address mode of the node or source register x
618 * %Dx <node> destination register x
619 * %I <node> immediate of the node
620 * %L <node> control flow target of the node
621 * %M <node> mode suffix of the node
622 * %P int condition code
623 * %R const arch_register_t* register
624 * %Sx <node> source register x
625 * %s const char* string
626 * %u unsigned int unsigned int
627 * %d signed int signed int
630 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
631 * * modifier does not prefix immediates with $, but AM with *
632 * l modifier for %lu and %ld
633 * > modifier to output high 8bit register (ah, bh)
634 * < modifier to output low 8bit register (al, bl)
636 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
642 const char *start = fmt;
643 ia32_emit_mod_t mod = EMIT_NONE;
645 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
648 be_emit_string_len(start, fmt - start);
652 be_emit_finish_line_gas(node);
665 case '*': mod |= EMIT_ALTERNATE_AM; break;
666 case '#': mod |= EMIT_RESPECT_LS; break;
667 case 'l': mod |= EMIT_LONG; break;
668 case '>': mod |= EMIT_HIGH_REG; break;
669 case '<': mod |= EMIT_LOW_REG; break;
678 arch_register_t const *reg;
689 if (mod & EMIT_ALTERNATE_AM)
695 reg = va_arg(ap, const arch_register_t*);
696 if (get_ia32_op_type(node) == ia32_AddrModeS) {
703 if (get_ia32_op_type(node) == ia32_AddrModeS) {
707 assert(get_ia32_op_type(node) == ia32_Normal);
711 default: goto unknown;
717 if (*fmt < '0' || '9' <= *fmt)
719 reg = get_out_reg(node, *fmt++ - '0');
725 if (!(mod & EMIT_ALTERNATE_AM))
727 emit_ia32_Immediate_no_prefix(imm);
731 ia32_emit_cfop_target(node);
735 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
739 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
740 ia32_emit_condition_code(cc);
745 reg = va_arg(ap, const arch_register_t*);
747 if (mod & EMIT_ALTERNATE_AM)
749 if (mod & EMIT_HIGH_REG) {
750 emit_8bit_register_high(reg);
751 } else if (mod & EMIT_LOW_REG) {
752 emit_8bit_register(reg);
754 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
762 if (*fmt < '0' || '9' <= *fmt)
766 imm = get_irn_n(node, pos);
767 if (is_ia32_Immediate(imm)) {
770 reg = get_in_reg(node, pos);
776 const char *str = va_arg(ap, const char*);
782 if (mod & EMIT_LONG) {
783 unsigned long num = va_arg(ap, unsigned long);
784 be_emit_irprintf("%lu", num);
786 unsigned num = va_arg(ap, unsigned);
787 be_emit_irprintf("%u", num);
792 if (mod & EMIT_LONG) {
793 long num = va_arg(ap, long);
794 be_emit_irprintf("%ld", num);
796 int num = va_arg(ap, int);
797 be_emit_irprintf("%d", num);
803 panic("unknown format conversion in ia32_emitf()");
811 * Emits registers and/or address mode of a binary operation.
813 void ia32_emit_binop(const ir_node *node)
815 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
816 ia32_emitf(node, "%#S4, %#AS3");
818 ia32_emitf(node, "%#AS4, %#S3");
823 * Emits registers and/or address mode of a binary operation.
825 void ia32_emit_x87_binop(const ir_node *node)
827 switch (get_ia32_op_type(node)) {
830 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
831 const arch_register_t *in1 = x87_attr->x87[0];
832 const arch_register_t *in = x87_attr->x87[1];
833 const arch_register_t *out = x87_attr->x87[2];
837 } else if (out == in) {
842 be_emit_string(arch_register_get_name(in));
843 be_emit_cstring(", %");
844 be_emit_string(arch_register_get_name(out));
852 assert(0 && "unsupported op type");
857 * Emits registers and/or address mode of a unary operation.
859 void ia32_emit_unop(const ir_node *node, int pos)
863 ia32_emitf(node, fmt);
866 static void emit_ia32_IMul(const ir_node *node)
868 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
869 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
871 /* do we need the 3-address form? */
872 if (is_ia32_NoReg_GP(left) ||
873 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
874 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
876 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
881 * walks up a tree of copies/perms/spills/reloads to find the original value
882 * that is moved around
884 static ir_node *find_original_value(ir_node *node)
886 if (irn_visited(node))
889 mark_irn_visited(node);
890 if (be_is_Copy(node)) {
891 return find_original_value(be_get_Copy_op(node));
892 } else if (be_is_CopyKeep(node)) {
893 return find_original_value(be_get_CopyKeep_op(node));
894 } else if (is_Proj(node)) {
895 ir_node *pred = get_Proj_pred(node);
896 if (be_is_Perm(pred)) {
897 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
898 } else if (be_is_MemPerm(pred)) {
899 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
900 } else if (is_ia32_Load(pred)) {
901 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
902 } else if (is_ia32_Store(pred)) {
903 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
907 } else if (is_Phi(node)) {
909 arity = get_irn_arity(node);
910 for (i = 0; i < arity; ++i) {
911 ir_node *in = get_irn_n(node, i);
912 ir_node *res = find_original_value(in);
923 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
925 ir_node *flags = get_irn_n(node, flags_pos);
926 const ia32_attr_t *flags_attr;
927 flags = skip_Proj(flags);
929 if (is_ia32_Sahf(flags)) {
930 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
931 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
932 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
933 inc_irg_visited(current_ir_graph);
934 cmp = find_original_value(cmp);
936 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
937 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
940 flags_attr = get_ia32_attr_const(cmp);
942 flags_attr = get_ia32_attr_const(flags);
945 if (flags_attr->data.ins_permuted)
946 cc = ia32_invert_condition_code(cc);
950 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
952 ia32_condition_code_t cc = get_ia32_condcode(node);
953 cc = determine_final_cc(node, flags_pos, cc);
955 ia32_emit_condition_code(cc);
959 * Emits an exception label for a given node.
961 static void ia32_emit_exc_label(const ir_node *node)
963 be_emit_string(be_gas_insn_label_prefix());
964 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
968 * Returns the Proj with projection number proj and NOT mode_M
970 static ir_node *get_proj(const ir_node *node, long proj)
972 const ir_edge_t *edge;
975 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
977 foreach_out_edge(node, edge) {
978 src = get_edge_src_irn(edge);
980 assert(is_Proj(src) && "Proj expected");
981 if (get_irn_mode(src) == mode_M)
984 if (get_Proj_proj(src) == proj)
990 static int can_be_fallthrough(const ir_node *node)
992 ir_node *target_block = get_cfop_target_block(node);
993 ir_node *block = get_nodes_block(node);
994 return get_prev_block_sched(target_block) == block;
998 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1000 static void emit_ia32_Jcc(const ir_node *node)
1002 int need_parity_label = 0;
1003 ia32_condition_code_t cc = get_ia32_condcode(node);
1004 const ir_node *proj_true;
1005 const ir_node *proj_false;
1007 cc = determine_final_cc(node, 0, cc);
1009 /* get both Projs */
1010 proj_true = get_proj(node, pn_ia32_Jcc_true);
1011 assert(proj_true && "Jcc without true Proj");
1013 proj_false = get_proj(node, pn_ia32_Jcc_false);
1014 assert(proj_false && "Jcc without false Proj");
1016 if (can_be_fallthrough(proj_true)) {
1017 /* exchange both proj's so the second one can be omitted */
1018 const ir_node *t = proj_true;
1020 proj_true = proj_false;
1022 cc = ia32_negate_condition_code(cc);
1025 if (cc & ia32_cc_float_parity_cases) {
1026 /* Some floating point comparisons require a test of the parity flag,
1027 * which indicates that the result is unordered */
1028 if (cc & ia32_cc_negated) {
1029 ia32_emitf(proj_true, "\tjp %L\n");
1031 /* we need a local label if the false proj is a fallthrough
1032 * as the falseblock might have no label emitted then */
1033 if (can_be_fallthrough(proj_false)) {
1034 need_parity_label = 1;
1035 ia32_emitf(proj_false, "\tjp 1f\n");
1037 ia32_emitf(proj_false, "\tjp %L\n");
1041 ia32_emitf(proj_true, "\tj%P %L\n", cc);
1042 if (need_parity_label) {
1043 ia32_emitf(NULL, "1:\n");
1046 /* the second Proj might be a fallthrough */
1047 if (can_be_fallthrough(proj_false)) {
1048 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1050 ia32_emitf(proj_false, "\tjmp %L\n");
1055 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1058 static void emit_ia32_Setcc(const ir_node *node)
1060 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1062 ia32_condition_code_t cc = get_ia32_condcode(node);
1063 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1064 if (cc & ia32_cc_float_parity_cases) {
1065 if (cc & ia32_cc_negated) {
1066 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1067 ia32_emitf(node, "\tsetp %>R\n", dreg);
1068 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1070 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1071 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1072 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1075 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1079 static void emit_ia32_CMovcc(const ir_node *node)
1081 const ia32_attr_t *attr = get_ia32_attr_const(node);
1082 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1083 ia32_condition_code_t cc = get_ia32_condcode(node);
1084 const arch_register_t *in_true;
1085 const arch_register_t *in_false;
1087 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1088 /* although you can't set ins_permuted in the constructor it might still
1089 * be set by memory operand folding
1090 * Permuting inputs of a cmov means the condition is negated!
1092 if (attr->data.ins_permuted)
1093 cc = ia32_negate_condition_code(cc);
1095 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1096 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1098 /* should be same constraint fullfilled? */
1099 if (out == in_false) {
1100 /* yes -> nothing to do */
1101 } else if (out == in_true) {
1102 const arch_register_t *tmp;
1104 assert(get_ia32_op_type(node) == ia32_Normal);
1106 cc = ia32_negate_condition_code(cc);
1113 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1116 if (cc & ia32_cc_float_parity_cases) {
1117 panic("CMov with floatingpoint compare/parity not supported yet");
1120 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1124 * Emits code for a SwitchJmp
1126 static void emit_ia32_SwitchJmp(const ir_node *node)
1128 ir_entity *jump_table = get_ia32_am_sc(node);
1129 long default_pn = get_ia32_default_pn(node);
1131 ia32_emitf(node, "\tjmp %*AM\n");
1132 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
1136 * Emits code for a unconditional jump.
1138 static void emit_ia32_Jmp(const ir_node *node)
1140 /* we have a block schedule */
1141 if (can_be_fallthrough(node)) {
1142 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1144 ia32_emitf(node, "\tjmp %L\n");
1149 * Emit an inline assembler operand.
1151 * @param node the ia32_ASM node
1152 * @param s points to the operand (a %c)
1154 * @return pointer to the first char in s NOT in the current operand
1156 static const char* emit_asm_operand(const ir_node *node, const char *s)
1158 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1159 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1161 const arch_register_t *reg;
1162 const ia32_asm_reg_t *asm_regs = attr->register_map;
1163 const ia32_asm_reg_t *asm_reg;
1172 /* parse modifiers */
1175 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1200 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1207 if (sscanf(s, "%d%n", &num, &p) != 1) {
1208 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1215 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1217 "Error: Custom assembler references invalid input/output (%+F)\n",
1221 asm_reg = & asm_regs[num];
1222 assert(asm_reg->valid);
1225 if (asm_reg->use_input == 0) {
1226 reg = get_out_reg(node, asm_reg->inout_pos);
1228 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1230 /* might be an immediate value */
1231 if (is_ia32_Immediate(pred)) {
1232 emit_ia32_Immediate(pred);
1235 reg = get_in_reg(node, asm_reg->inout_pos);
1239 "Warning: no register assigned for %d asm op (%+F)\n",
1244 if (asm_reg->memory) {
1249 if (modifier != 0) {
1252 emit_8bit_register(reg);
1255 emit_8bit_register_high(reg);
1258 emit_16bit_register(reg);
1261 panic("Invalid asm op modifier");
1264 emit_register(reg, asm_reg->mode);
1267 if (asm_reg->memory) {
1275 * Emits code for an ASM pseudo op.
1277 static void emit_ia32_Asm(const ir_node *node)
1279 const void *gen_attr = get_irn_generic_attr_const(node);
1280 const ia32_asm_attr_t *attr
1281 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1282 ident *asm_text = attr->asm_text;
1283 const char *s = get_id_str(asm_text);
1285 ia32_emitf(node, "#APP\t\n");
1292 s = emit_asm_operand(node, s);
1298 ia32_emitf(NULL, "\n#NO_APP\n");
1303 * Emit movsb/w instructions to make mov count divideable by 4
1305 static void emit_CopyB_prolog(unsigned size)
1308 ia32_emitf(NULL, "\tmovsb\n");
1310 ia32_emitf(NULL, "\tmovsw\n");
1314 * Emit rep movsd instruction for memcopy.
1316 static void emit_ia32_CopyB(const ir_node *node)
1318 unsigned size = get_ia32_copyb_size(node);
1320 emit_CopyB_prolog(size);
1321 ia32_emitf(node, "\trep movsd\n");
1325 * Emits unrolled memcopy.
1327 static void emit_ia32_CopyB_i(const ir_node *node)
1329 unsigned size = get_ia32_copyb_size(node);
1331 emit_CopyB_prolog(size);
1335 ia32_emitf(NULL, "\tmovsd\n");
1341 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1343 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1346 ir_mode *ls_mode = get_ia32_ls_mode(node);
1347 int ls_bits = get_mode_size_bits(ls_mode);
1348 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1350 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1353 static void emit_ia32_Conv_I2FP(const ir_node *node)
1355 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1358 static void emit_ia32_Conv_FP2I(const ir_node *node)
1360 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1363 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1365 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1369 * Emits code for an Int conversion.
1371 static void emit_ia32_Conv_I2I(const ir_node *node)
1373 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1374 int signed_mode = mode_is_signed(smaller_mode);
1375 const char *sign_suffix;
1377 assert(!mode_is_float(smaller_mode));
1379 sign_suffix = signed_mode ? "s" : "z";
1380 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1386 static void emit_ia32_Call(const ir_node *node)
1388 /* Special case: Call must not have its immediates prefixed by $, instead
1389 * address mode is prefixed by *. */
1390 ia32_emitf(node, "\tcall %*AS3\n");
1395 * Emits code to increase stack pointer.
1397 static void emit_be_IncSP(const ir_node *node)
1399 int offs = be_get_IncSP_offset(node);
1405 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1407 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1412 * Emits code for Copy/CopyKeep.
1414 static void Copy_emitter(const ir_node *node, const ir_node *op)
1416 const arch_register_t *in = arch_get_irn_register(op);
1417 const arch_register_t *out = arch_get_irn_register(node);
1422 /* copies of vf nodes aren't real... */
1423 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1426 if (get_irn_mode(node) == mode_E) {
1427 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1429 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1433 static void emit_be_Copy(const ir_node *node)
1435 Copy_emitter(node, be_get_Copy_op(node));
1438 static void emit_be_CopyKeep(const ir_node *node)
1440 Copy_emitter(node, be_get_CopyKeep_op(node));
1444 * Emits code for exchange.
1446 static void emit_be_Perm(const ir_node *node)
1448 const arch_register_t *in0, *in1;
1449 const arch_register_class_t *cls0, *cls1;
1451 in0 = arch_get_irn_register(get_irn_n(node, 0));
1452 in1 = arch_get_irn_register(get_irn_n(node, 1));
1454 cls0 = arch_register_get_class(in0);
1455 cls1 = arch_register_get_class(in1);
1457 assert(cls0 == cls1 && "Register class mismatch at Perm");
1459 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1460 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1461 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1462 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1463 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1464 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1465 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1467 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1470 panic("unexpected register class in be_Perm (%+F)", node);
1475 * Emits code for Constant loading.
1477 static void emit_ia32_Const(const ir_node *node)
1479 ia32_emitf(node, "\tmovl %I, %D0\n");
1482 /* helper function for emit_ia32_Minus64Bit */
1483 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1485 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1488 /* helper function for emit_ia32_Minus64Bit */
1489 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1491 ia32_emitf(node, "\tnegl %R\n", reg);
1494 /* helper function for emit_ia32_Minus64Bit */
1495 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1497 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1500 /* helper function for emit_ia32_Minus64Bit */
1501 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1503 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1506 /* helper function for emit_ia32_Minus64Bit */
1507 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1509 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1512 /* helper function for emit_ia32_Minus64Bit */
1513 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1515 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1518 static void emit_ia32_Minus64Bit(const ir_node *node)
1520 const arch_register_t *in_lo = get_in_reg(node, 0);
1521 const arch_register_t *in_hi = get_in_reg(node, 1);
1522 const arch_register_t *out_lo = get_out_reg(node, 0);
1523 const arch_register_t *out_hi = get_out_reg(node, 1);
1525 if (out_lo == in_lo) {
1526 if (out_hi != in_hi) {
1527 /* a -> a, b -> d */
1530 /* a -> a, b -> b */
1533 } else if (out_lo == in_hi) {
1534 if (out_hi == in_lo) {
1535 /* a -> b, b -> a */
1536 emit_xchg(node, in_lo, in_hi);
1539 /* a -> b, b -> d */
1540 emit_mov(node, in_hi, out_hi);
1541 emit_mov(node, in_lo, out_lo);
1545 if (out_hi == in_lo) {
1546 /* a -> c, b -> a */
1547 emit_mov(node, in_lo, out_lo);
1549 } else if (out_hi == in_hi) {
1550 /* a -> c, b -> b */
1551 emit_mov(node, in_lo, out_lo);
1554 /* a -> c, b -> d */
1555 emit_mov(node, in_lo, out_lo);
1561 emit_neg( node, out_hi);
1562 emit_neg( node, out_lo);
1563 emit_sbb0(node, out_hi);
1567 emit_zero(node, out_hi);
1568 emit_neg( node, out_lo);
1569 emit_sbb( node, in_hi, out_hi);
1572 static void emit_ia32_GetEIP(const ir_node *node)
1574 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1575 ia32_emitf(NULL, "%s:\n", pic_base_label);
1576 ia32_emitf(node, "\tpopl %D0\n");
1579 static void emit_ia32_ClimbFrame(const ir_node *node)
1581 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1583 ia32_emitf(node, "\tmovl %S0, %D0\n");
1584 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1585 be_gas_emit_block_name(node);
1586 be_emit_cstring(":\n");
1587 be_emit_write_line();
1588 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1589 ia32_emitf(node, "\tdec %S1\n");
1590 be_emit_cstring("\tjnz ");
1591 be_gas_emit_block_name(node);
1592 be_emit_finish_line_gas(node);
1595 static void emit_be_Return(const ir_node *node)
1597 unsigned pop = be_Return_get_pop(node);
1599 if (pop > 0 || be_Return_get_emit_pop(node)) {
1600 ia32_emitf(node, "\tret $%u\n", pop);
1602 ia32_emitf(node, "\tret\n");
1606 static void emit_Nothing(const ir_node *node)
1613 * Enters the emitter functions for handled nodes into the generic
1614 * pointer of an opcode.
1616 static void ia32_register_emitters(void)
1618 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1619 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1620 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1621 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1622 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1623 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1625 /* first clear the generic function pointer for all ops */
1626 clear_irp_opcodes_generic_func();
1628 /* register all emitter functions defined in spec */
1629 ia32_register_spec_emitters();
1631 /* other ia32 emitter functions */
1632 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1637 IA32_EMIT(Conv_FP2FP);
1638 IA32_EMIT(Conv_FP2I);
1639 IA32_EMIT(Conv_I2FP);
1640 IA32_EMIT(Conv_I2I);
1647 IA32_EMIT(Minus64Bit);
1648 IA32_EMIT(SwitchJmp);
1649 IA32_EMIT(ClimbFrame);
1652 /* benode emitter */
1672 typedef void (*emit_func_ptr) (const ir_node *);
1675 * Assign and emit an exception label if the current instruction can fail.
1677 static void ia32_assign_exc_label(ir_node *node)
1679 /* assign a new ID to the instruction */
1680 set_ia32_exc_label_id(node, ++exc_label_id);
1682 ia32_emit_exc_label(node);
1684 be_emit_pad_comment();
1685 be_emit_cstring("/* exception to Block ");
1686 ia32_emit_cfop_target(node);
1687 be_emit_cstring(" */\n");
1688 be_emit_write_line();
1692 * Emits code for a node.
1694 static void ia32_emit_node(ir_node *node)
1696 ir_op *op = get_irn_op(node);
1698 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1700 if (is_ia32_irn(node)) {
1701 if (get_ia32_exc_label(node)) {
1702 /* emit the exception label of this instruction */
1703 ia32_assign_exc_label(node);
1705 if (mark_spill_reload) {
1706 if (is_ia32_is_spill(node)) {
1707 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1709 if (is_ia32_is_reload(node)) {
1710 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1712 if (is_ia32_is_remat(node)) {
1713 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1717 if (op->ops.generic) {
1718 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1720 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1725 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1731 * Emits gas alignment directives
1733 static void ia32_emit_alignment(unsigned align, unsigned skip)
1735 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1739 * Emits gas alignment directives for Labels depended on cpu architecture.
1741 static void ia32_emit_align_label(void)
1743 unsigned align = ia32_cg_config.label_alignment;
1744 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1745 ia32_emit_alignment(align, maximum_skip);
1749 * Test whether a block should be aligned.
1750 * For cpus in the P4/Athlon class it is useful to align jump labels to
1751 * 16 bytes. However we should only do that if the alignment nops before the
1752 * label aren't executed more often than we have jumps to the label.
1754 static int should_align_block(const ir_node *block)
1756 static const double DELTA = .0001;
1757 ir_graph *irg = get_irn_irg(block);
1758 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1759 ir_node *prev = get_prev_block_sched(block);
1761 double prev_freq = 0; /**< execfreq of the fallthrough block */
1762 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1765 if (exec_freq == NULL)
1767 if (ia32_cg_config.label_alignment_factor <= 0)
1770 block_freq = get_block_execfreq(exec_freq, block);
1771 if (block_freq < DELTA)
1774 n_cfgpreds = get_Block_n_cfgpreds(block);
1775 for (i = 0; i < n_cfgpreds; ++i) {
1776 const ir_node *pred = get_Block_cfgpred_block(block, i);
1777 double pred_freq = get_block_execfreq(exec_freq, pred);
1780 prev_freq += pred_freq;
1782 jmp_freq += pred_freq;
1786 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1789 jmp_freq /= prev_freq;
1791 return jmp_freq > ia32_cg_config.label_alignment_factor;
1795 * Emit the block header for a block.
1797 * @param block the block
1798 * @param prev_block the previous block
1800 static void ia32_emit_block_header(ir_node *block)
1802 ir_graph *irg = current_ir_graph;
1803 int need_label = block_needs_label(block);
1804 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1807 if (block == get_irg_end_block(irg))
1810 if (ia32_cg_config.label_alignment > 0) {
1811 /* align the current block if:
1812 * a) if should be aligned due to its execution frequency
1813 * b) there is no fall-through here
1815 if (should_align_block(block)) {
1816 ia32_emit_align_label();
1818 /* if the predecessor block has no fall-through,
1819 we can always align the label. */
1821 int has_fallthrough = 0;
1823 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1824 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1825 if (can_be_fallthrough(cfg_pred)) {
1826 has_fallthrough = 1;
1831 if (!has_fallthrough)
1832 ia32_emit_align_label();
1837 be_gas_emit_block_name(block);
1840 be_emit_pad_comment();
1841 be_emit_cstring(" /* ");
1843 be_emit_cstring("\t/* ");
1844 be_gas_emit_block_name(block);
1845 be_emit_cstring(": ");
1848 be_emit_cstring("preds:");
1850 /* emit list of pred blocks in comment */
1851 arity = get_irn_arity(block);
1853 be_emit_cstring(" none");
1856 for (i = 0; i < arity; ++i) {
1857 ir_node *predblock = get_Block_cfgpred_block(block, i);
1858 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1861 if (exec_freq != NULL) {
1862 be_emit_irprintf(", freq: %f",
1863 get_block_execfreq(exec_freq, block));
1865 be_emit_cstring(" */\n");
1866 be_emit_write_line();
1870 * Walks over the nodes in a block connected by scheduling edges
1871 * and emits code for each node.
1873 static void ia32_gen_block(ir_node *block)
1877 ia32_emit_block_header(block);
1879 /* emit the contents of the block */
1880 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1881 sched_foreach(block, node) {
1882 ia32_emit_node(node);
1886 typedef struct exc_entry {
1887 ir_node *exc_instr; /** The instruction that can issue an exception. */
1888 ir_node *block; /** The block to call then. */
1893 * Sets labels for control flow nodes (jump target).
1894 * Links control predecessors to there destination blocks.
1896 static void ia32_gen_labels(ir_node *block, void *data)
1898 exc_entry **exc_list = (exc_entry**)data;
1902 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1903 pred = get_Block_cfgpred(block, n);
1904 set_irn_link(pred, block);
1906 pred = skip_Proj(pred);
1907 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1912 ARR_APP1(exc_entry, *exc_list, e);
1913 set_irn_link(pred, block);
1919 * Compare two exception_entries.
1921 static int cmp_exc_entry(const void *a, const void *b)
1923 const exc_entry *ea = (const exc_entry*)a;
1924 const exc_entry *eb = (const exc_entry*)b;
1926 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1932 * Main driver. Emits the code for one routine.
1934 void ia32_gen_routine(ir_graph *irg)
1936 ir_entity *entity = get_irg_entity(irg);
1937 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1938 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1939 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1940 ir_node **blk_sched = irg_data->blk_sched;
1943 isa = (ia32_isa_t*) arch_env;
1944 do_pic = be_get_irg_options(irg)->pic;
1946 be_gas_elf_type_char = '@';
1948 ia32_register_emitters();
1950 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1952 be_dbg_method_begin(entity);
1953 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
1955 /* we use links to point to target blocks */
1956 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1957 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1959 /* initialize next block links */
1960 n = ARR_LEN(blk_sched);
1961 for (i = 0; i < n; ++i) {
1962 ir_node *block = blk_sched[i];
1963 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1965 set_irn_link(block, prev);
1968 for (i = 0; i < n; ++i) {
1969 ir_node *block = blk_sched[i];
1971 ia32_gen_block(block);
1974 be_gas_emit_function_epilog(entity);
1975 be_dbg_method_end();
1977 be_emit_write_line();
1979 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1981 /* Sort the exception table using the exception label id's.
1982 Those are ascending with ascending addresses. */
1983 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1987 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1988 be_emit_cstring("\t.long ");
1989 ia32_emit_exc_label(exc_list[e].exc_instr);
1991 be_emit_cstring("\t.long ");
1992 be_gas_emit_block_name(exc_list[e].block);
1996 DEL_ARR_F(exc_list);
1999 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2000 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2004 /* ==== Experimental binary emitter ==== */
2006 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2007 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2008 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2010 static void build_reg_map(void)
2012 reg_gp_map[REG_GP_EAX] = 0x0;
2013 reg_gp_map[REG_GP_ECX] = 0x1;
2014 reg_gp_map[REG_GP_EDX] = 0x2;
2015 reg_gp_map[REG_GP_EBX] = 0x3;
2016 reg_gp_map[REG_GP_ESP] = 0x4;
2017 reg_gp_map[REG_GP_EBP] = 0x5;
2018 reg_gp_map[REG_GP_ESI] = 0x6;
2019 reg_gp_map[REG_GP_EDI] = 0x7;
2022 /** Returns the encoding for a pnc field. */
2023 static unsigned char pnc2cc(ia32_condition_code_t cc)
2028 /** Sign extension bit values for binops */
2030 UNSIGNED_IMM = 0, /**< unsigned immediate */
2031 SIGNEXT_IMM = 2, /**< sign extended immediate */
2034 /** The mod encoding of the ModR/M */
2036 MOD_IND = 0x00, /**< [reg1] */
2037 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2038 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2039 MOD_REG = 0xC0 /**< reg1 */
2042 /** create R/M encoding for ModR/M */
2043 #define ENC_RM(x) (x)
2044 /** create REG encoding for ModR/M */
2045 #define ENC_REG(x) ((x) << 3)
2047 /** create encoding for a SIB byte */
2048 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2050 /* Node: The following routines are supposed to append bytes, words, dwords
2051 to the output stream.
2052 Currently the implementation is stupid in that it still creates output
2053 for an "assembler" in the form of .byte, .long
2054 We will change this when enough infrastructure is there to create complete
2055 machine code in memory/object files */
2057 static void bemit8(const unsigned char byte)
2059 be_emit_irprintf("\t.byte 0x%x\n", byte);
2060 be_emit_write_line();
2063 static void bemit16(const unsigned short u16)
2065 be_emit_irprintf("\t.word 0x%x\n", u16);
2066 be_emit_write_line();
2069 static void bemit32(const unsigned u32)
2071 be_emit_irprintf("\t.long 0x%x\n", u32);
2072 be_emit_write_line();
2076 * Emit address of an entity. If @p is_relative is true then a relative
2077 * offset from behind the address to the entity is created.
2079 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2082 if (entity == NULL) {
2087 /* the final version should remember the position in the bytestream
2088 and patch it with the correct address at linktime... */
2089 be_emit_cstring("\t.long ");
2092 be_gas_emit_entity(entity);
2094 if (get_entity_owner(entity) == get_tls_type()) {
2095 if (get_entity_visibility(entity) == ir_visibility_external) {
2096 be_emit_cstring("@INDNTPOFF");
2098 be_emit_cstring("@NTPOFF");
2103 be_emit_cstring("-.");
2108 be_emit_irprintf("%+d", offset);
2111 be_emit_write_line();
2114 static void bemit_jmp_destination(const ir_node *dest_block)
2116 be_emit_cstring("\t.long ");
2117 be_gas_emit_block_name(dest_block);
2118 be_emit_cstring(" - . - 4\n");
2119 be_emit_write_line();
2122 /* end emit routines, all emitters following here should only use the functions
2125 typedef enum reg_modifier {
2130 /** Create a ModR/M byte for src1,src2 registers */
2131 static void bemit_modrr(const arch_register_t *src1,
2132 const arch_register_t *src2)
2134 unsigned char modrm = MOD_REG;
2135 modrm |= ENC_RM(reg_gp_map[src1->index]);
2136 modrm |= ENC_REG(reg_gp_map[src2->index]);
2140 /** Create a ModR/M8 byte for src1,src2 registers */
2141 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2142 reg_modifier_t high_part2, const arch_register_t *src2)
2144 unsigned char modrm = MOD_REG;
2145 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2146 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2150 /** Create a ModR/M byte for one register and extension */
2151 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2153 unsigned char modrm = MOD_REG;
2155 modrm |= ENC_RM(reg_gp_map[reg->index]);
2156 modrm |= ENC_REG(ext);
2160 /** Create a ModR/M8 byte for one register */
2161 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2163 unsigned char modrm = MOD_REG;
2164 assert(reg_gp_map[reg->index] < 4);
2165 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2171 * Calculate the size of an signed immediate in bytes.
2173 * @param offset an offset
2175 static unsigned get_signed_imm_size(int offset)
2177 if (-128 <= offset && offset < 128) {
2179 } else if (-32768 <= offset && offset < 32768) {
2187 * Emit an address mode.
2189 * @param reg content of the reg field: either a register index or an opcode extension
2190 * @param node the node
2192 static void bemit_mod_am(unsigned reg, const ir_node *node)
2194 ir_entity *ent = get_ia32_am_sc(node);
2195 int offs = get_ia32_am_offs_int(node);
2196 ir_node *base = get_irn_n(node, n_ia32_base);
2197 int has_base = !is_ia32_NoReg_GP(base);
2198 ir_node *idx = get_irn_n(node, n_ia32_index);
2199 int has_index = !is_ia32_NoReg_GP(idx);
2202 unsigned emitoffs = 0;
2203 bool emitsib = false;
2206 /* set the mod part depending on displacement */
2208 modrm |= MOD_IND_WORD_OFS;
2210 } else if (offs == 0) {
2213 } else if (-128 <= offs && offs < 128) {
2214 modrm |= MOD_IND_BYTE_OFS;
2217 modrm |= MOD_IND_WORD_OFS;
2222 const arch_register_t *base_reg = arch_get_irn_register(base);
2223 base_enc = reg_gp_map[base_reg->index];
2225 /* Use the EBP encoding + MOD_IND if NO base register. There is
2226 * always a 32bit offset present in this case. */
2232 /* Determine if we need a SIB byte. */
2234 const arch_register_t *reg_index = arch_get_irn_register(idx);
2235 int scale = get_ia32_am_scale(node);
2237 /* R/M set to ESP means SIB in 32bit mode. */
2238 modrm |= ENC_RM(0x04);
2239 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2241 } else if (base_enc == 0x04) {
2242 /* for the above reason we are forced to emit a SIB when base is ESP.
2243 * Only the base is used, index must be ESP too, which means no index.
2245 modrm |= ENC_RM(0x04);
2246 sib = ENC_SIB(0, 0x04, 0x04);
2249 modrm |= ENC_RM(base_enc);
2252 /* We are forced to emit an 8bit offset as EBP base without offset is a
2253 * special case for SIB without base register. */
2254 if (base_enc == 0x05 && emitoffs == 0) {
2255 modrm |= MOD_IND_BYTE_OFS;
2259 modrm |= ENC_REG(reg);
2265 /* emit displacement */
2266 if (emitoffs == 8) {
2267 bemit8((unsigned) offs);
2268 } else if (emitoffs == 32) {
2269 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2274 * Emit a binop with a immediate operand.
2276 * @param node the node to emit
2277 * @param opcode_eax the opcode for the op eax, imm variant
2278 * @param opcode the opcode for the reg, imm variant
2279 * @param ruval the opcode extension for opcode
2281 static void bemit_binop_with_imm(
2282 const ir_node *node,
2283 unsigned char opcode_ax,
2284 unsigned char opcode, unsigned char ruval)
2286 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2287 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2288 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2291 /* Some instructions (test) have no short form with 32bit value + 8bit
2293 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2296 /* check for sign extension */
2297 size = get_signed_imm_size(attr->offset);
2302 bemit8(opcode | SIGNEXT_IMM);
2303 /* cmp has this special mode */
2304 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2305 bemit_mod_am(ruval, node);
2307 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2308 bemit_modru(reg, ruval);
2310 bemit8((unsigned char)attr->offset);
2314 /* check for eax variant: this variant is shorter for 32bit immediates only */
2315 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2317 bemit_mod_am(ruval, node);
2319 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2320 if (reg->index == REG_GP_EAX) {
2324 bemit_modru(reg, ruval);
2327 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2330 panic("invalid imm size?!?");
2336 static void bemit_binop_2(const ir_node *node, unsigned code)
2338 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2340 if (get_ia32_op_type(node) == ia32_Normal) {
2341 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2342 bemit_modrr(op2, out);
2344 bemit_mod_am(reg_gp_map[out->index], node);
2351 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2353 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2354 if (is_ia32_Immediate(right)) {
2355 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2357 bemit_binop_2(node, opcodes[0]);
2364 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2367 if (get_ia32_op_type(node) == ia32_Normal) {
2368 const arch_register_t *in = get_in_reg(node, input);
2369 bemit_modru(in, ext);
2371 bemit_mod_am(ext, node);
2375 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2377 const arch_register_t *out = get_out_reg(node, 0);
2378 bemit_unop(node, code, reg_gp_map[out->index], input);
2381 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2383 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2386 bemit8(size == 8 ? code : code + 1);
2387 bemit_mod_am(ext, node);
2390 static void bemit_immediate(const ir_node *node, bool relative)
2392 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2393 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2396 static void bemit_copy(const ir_node *copy)
2398 const arch_register_t *in = get_in_reg(copy, 0);
2399 const arch_register_t *out = get_out_reg(copy, 0);
2403 /* copies of vf nodes aren't real... */
2404 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2407 if (get_irn_mode(copy) == mode_E) {
2410 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2412 bemit_modrr(in, out);
2416 static void bemit_perm(const ir_node *node)
2418 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2419 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2420 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2422 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2424 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2425 if (in0->index == REG_GP_EAX) {
2426 bemit8(0x90 + reg_gp_map[in1->index]);
2427 } else if (in1->index == REG_GP_EAX) {
2428 bemit8(0x90 + reg_gp_map[in0->index]);
2431 bemit_modrr(in0, in1);
2433 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2434 panic("unimplemented"); // TODO implement
2435 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2436 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2437 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2438 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2440 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2443 panic("unexpected register class in be_Perm (%+F)", node);
2447 static void bemit_xor0(const ir_node *node)
2449 const arch_register_t *out = get_out_reg(node, 0);
2451 bemit_modrr(out, out);
2454 static void bemit_mov_const(const ir_node *node)
2456 const arch_register_t *out = get_out_reg(node, 0);
2457 bemit8(0xB8 + reg_gp_map[out->index]);
2458 bemit_immediate(node, false);
2462 * Creates a function for a Binop with 3 possible encodings.
2464 #define BINOP(op, op0, op1, op2, op2_ext) \
2465 static void bemit_ ## op(const ir_node *node) { \
2466 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2467 bemit_binop(node, op ## _codes); \
2470 /* insn def eax,imm imm */
2471 BINOP(add, 0x03, 0x05, 0x81, 0)
2472 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2473 BINOP(adc, 0x13, 0x15, 0x81, 2)
2474 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2475 BINOP(and, 0x23, 0x25, 0x81, 4)
2476 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2477 BINOP(xor, 0x33, 0x35, 0x81, 6)
2478 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2480 #define BINOPMEM(op, ext) \
2481 static void bemit_##op(const ir_node *node) \
2484 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2487 val = get_irn_n(node, n_ia32_unary_op); \
2488 if (is_ia32_Immediate(val)) { \
2489 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2490 int offset = attr->offset; \
2491 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2493 bemit_mod_am(ext, node); \
2497 bemit_mod_am(ext, node); \
2501 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2505 bemit8(ext << 3 | 1); \
2506 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2510 static void bemit_##op##8bit(const ir_node *node) \
2512 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2513 if (is_ia32_Immediate(val)) { \
2515 bemit_mod_am(ext, node); \
2516 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2519 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2531 * Creates a function for an Unop with code /ext encoding.
2533 #define UNOP(op, code, ext, input) \
2534 static void bemit_ ## op(const ir_node *node) { \
2535 bemit_unop(node, code, ext, input); \
2538 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2539 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2540 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2541 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2542 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2543 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2545 /* TODO: am support for IJmp */
2546 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2548 #define SHIFT(op, ext) \
2549 static void bemit_##op(const ir_node *node) \
2551 const arch_register_t *out = get_out_reg(node, 0); \
2552 ir_node *count = get_irn_n(node, 1); \
2553 if (is_ia32_Immediate(count)) { \
2554 int offset = get_ia32_immediate_attr_const(count)->offset; \
2555 if (offset == 1) { \
2557 bemit_modru(out, ext); \
2560 bemit_modru(out, ext); \
2565 bemit_modru(out, ext); \
2569 static void bemit_##op##mem(const ir_node *node) \
2572 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2575 count = get_irn_n(node, 1); \
2576 if (is_ia32_Immediate(count)) { \
2577 int offset = get_ia32_immediate_attr_const(count)->offset; \
2578 if (offset == 1) { \
2579 bemit8(size == 8 ? 0xD0 : 0xD1); \
2580 bemit_mod_am(ext, node); \
2582 bemit8(size == 8 ? 0xC0 : 0xC1); \
2583 bemit_mod_am(ext, node); \
2587 bemit8(size == 8 ? 0xD2 : 0xD3); \
2588 bemit_mod_am(ext, node); \
2598 static void bemit_shld(const ir_node *node)
2600 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2601 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2602 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2604 if (is_ia32_Immediate(count)) {
2606 bemit_modrr(out, in);
2607 bemit8(get_ia32_immediate_attr_const(count)->offset);
2610 bemit_modrr(out, in);
2614 static void bemit_shrd(const ir_node *node)
2616 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2617 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2618 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2620 if (is_ia32_Immediate(count)) {
2622 bemit_modrr(out, in);
2623 bemit8(get_ia32_immediate_attr_const(count)->offset);
2626 bemit_modrr(out, in);
2631 * binary emitter for setcc.
2633 static void bemit_setcc(const ir_node *node)
2635 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2637 ia32_condition_code_t cc = get_ia32_condcode(node);
2638 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2639 if (cc & ia32_cc_float_parity_cases) {
2640 if (cc & ia32_cc_negated) {
2643 bemit8(0x90 | pnc2cc(cc));
2644 bemit_modrm8(REG_LOW, dreg);
2649 bemit_modrm8(REG_HIGH, dreg);
2651 /* orb %>dreg, %<dreg */
2653 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2657 bemit8(0x90 | pnc2cc(cc));
2658 bemit_modrm8(REG_LOW, dreg);
2663 bemit_modrm8(REG_HIGH, dreg);
2665 /* andb %>dreg, %<dreg */
2667 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2672 bemit8(0x90 | pnc2cc(cc));
2673 bemit_modrm8(REG_LOW, dreg);
2677 static void bemit_cmovcc(const ir_node *node)
2679 const ia32_attr_t *attr = get_ia32_attr_const(node);
2680 int ins_permuted = attr->data.ins_permuted;
2681 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2682 ia32_condition_code_t cc = get_ia32_condcode(node);
2683 const arch_register_t *in_true;
2684 const arch_register_t *in_false;
2686 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2688 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2689 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2691 /* should be same constraint fullfilled? */
2692 if (out == in_false) {
2693 /* yes -> nothing to do */
2694 } else if (out == in_true) {
2695 assert(get_ia32_op_type(node) == ia32_Normal);
2696 ins_permuted = !ins_permuted;
2700 bemit8(0x8B); // mov %in_false, %out
2701 bemit_modrr(in_false, out);
2705 cc = ia32_negate_condition_code(cc);
2707 if (cc & ia32_cc_float_parity_cases)
2708 panic("cmov can't handle parity float cases");
2711 bemit8(0x40 | pnc2cc(cc));
2712 if (get_ia32_op_type(node) == ia32_Normal) {
2713 bemit_modrr(in_true, out);
2715 bemit_mod_am(reg_gp_map[out->index], node);
2719 static void bemit_cmp(const ir_node *node)
2721 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2727 right = get_irn_n(node, n_ia32_binary_right);
2728 if (is_ia32_Immediate(right)) {
2729 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2730 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2731 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2734 if (attr->symconst != NULL) {
2737 /* check for sign extension */
2738 size = get_signed_imm_size(attr->offset);
2743 bemit8(0x81 | SIGNEXT_IMM);
2744 /* cmp has this special mode */
2745 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2746 bemit_mod_am(7, node);
2748 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2749 bemit_modru(reg, 7);
2751 bemit8((unsigned char)attr->offset);
2755 /* check for eax variant: this variant is shorter for 32bit immediates only */
2756 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2758 bemit_mod_am(7, node);
2760 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2761 if (reg->index == REG_GP_EAX) {
2765 bemit_modru(reg, 7);
2768 if (ls_size == 16) {
2769 bemit16(attr->offset);
2771 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2775 panic("invalid imm size?!?");
2777 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2779 if (get_ia32_op_type(node) == ia32_Normal) {
2780 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2781 bemit_modrr(op2, out);
2783 bemit_mod_am(reg_gp_map[out->index], node);
2788 static void bemit_cmp8bit(const ir_node *node)
2790 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2791 if (is_ia32_Immediate(right)) {
2792 if (get_ia32_op_type(node) == ia32_Normal) {
2793 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2794 if (out->index == REG_GP_EAX) {
2798 bemit_modru(out, 7);
2802 bemit_mod_am(7, node);
2804 bemit8(get_ia32_immediate_attr_const(right)->offset);
2806 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2808 if (get_ia32_op_type(node) == ia32_Normal) {
2809 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2810 bemit_modrr(out, in);
2812 bemit_mod_am(reg_gp_map[out->index], node);
2817 static void bemit_test8bit(const ir_node *node)
2819 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2820 if (is_ia32_Immediate(right)) {
2821 if (get_ia32_op_type(node) == ia32_Normal) {
2822 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2823 if (out->index == REG_GP_EAX) {
2827 bemit_modru(out, 0);
2831 bemit_mod_am(0, node);
2833 bemit8(get_ia32_immediate_attr_const(right)->offset);
2835 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2837 if (get_ia32_op_type(node) == ia32_Normal) {
2838 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
2839 bemit_modrr(out, in);
2841 bemit_mod_am(reg_gp_map[out->index], node);
2846 static void bemit_imul(const ir_node *node)
2848 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2849 /* Do we need the immediate form? */
2850 if (is_ia32_Immediate(right)) {
2851 int imm = get_ia32_immediate_attr_const(right)->offset;
2852 if (get_signed_imm_size(imm) == 1) {
2853 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2856 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2861 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2865 static void bemit_dec(const ir_node *node)
2867 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
2868 bemit8(0x48 + reg_gp_map[out->index]);
2871 static void bemit_inc(const ir_node *node)
2873 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
2874 bemit8(0x40 + reg_gp_map[out->index]);
2877 #define UNOPMEM(op, code, ext) \
2878 static void bemit_##op(const ir_node *node) \
2880 bemit_unop_mem(node, code, ext); \
2883 UNOPMEM(notmem, 0xF6, 2)
2884 UNOPMEM(negmem, 0xF6, 3)
2885 UNOPMEM(incmem, 0xFE, 0)
2886 UNOPMEM(decmem, 0xFE, 1)
2888 static void bemit_ldtls(const ir_node *node)
2890 const arch_register_t *out = get_out_reg(node, 0);
2892 bemit8(0x65); // gs:
2893 if (out->index == REG_GP_EAX) {
2894 bemit8(0xA1); // movl 0, %eax
2896 bemit8(0x8B); // movl 0, %reg
2897 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2905 static void bemit_lea(const ir_node *node)
2907 const arch_register_t *out = get_out_reg(node, 0);
2909 bemit_mod_am(reg_gp_map[out->index], node);
2912 /* helper function for bemit_minus64bit */
2913 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2915 bemit8(0x8B); // movl %src, %dst
2916 bemit_modrr(src, dst);
2919 /* helper function for bemit_minus64bit */
2920 static void bemit_helper_neg(const arch_register_t *reg)
2922 bemit8(0xF7); // negl %reg
2923 bemit_modru(reg, 3);
2926 /* helper function for bemit_minus64bit */
2927 static void bemit_helper_sbb0(const arch_register_t *reg)
2929 bemit8(0x83); // sbbl $0, %reg
2930 bemit_modru(reg, 3);
2934 /* helper function for bemit_minus64bit */
2935 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2937 bemit8(0x1B); // sbbl %src, %dst
2938 bemit_modrr(src, dst);
2941 /* helper function for bemit_minus64bit */
2942 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2944 if (src->index == REG_GP_EAX) {
2945 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2946 } else if (dst->index == REG_GP_EAX) {
2947 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2949 bemit8(0x87); // xchgl %src, %dst
2950 bemit_modrr(src, dst);
2954 /* helper function for bemit_minus64bit */
2955 static void bemit_helper_zero(const arch_register_t *reg)
2957 bemit8(0x33); // xorl %reg, %reg
2958 bemit_modrr(reg, reg);
2961 static void bemit_minus64bit(const ir_node *node)
2963 const arch_register_t *in_lo = get_in_reg(node, 0);
2964 const arch_register_t *in_hi = get_in_reg(node, 1);
2965 const arch_register_t *out_lo = get_out_reg(node, 0);
2966 const arch_register_t *out_hi = get_out_reg(node, 1);
2968 if (out_lo == in_lo) {
2969 if (out_hi != in_hi) {
2970 /* a -> a, b -> d */
2973 /* a -> a, b -> b */
2976 } else if (out_lo == in_hi) {
2977 if (out_hi == in_lo) {
2978 /* a -> b, b -> a */
2979 bemit_helper_xchg(in_lo, in_hi);
2982 /* a -> b, b -> d */
2983 bemit_helper_mov(in_hi, out_hi);
2984 bemit_helper_mov(in_lo, out_lo);
2988 if (out_hi == in_lo) {
2989 /* a -> c, b -> a */
2990 bemit_helper_mov(in_lo, out_lo);
2992 } else if (out_hi == in_hi) {
2993 /* a -> c, b -> b */
2994 bemit_helper_mov(in_lo, out_lo);
2997 /* a -> c, b -> d */
2998 bemit_helper_mov(in_lo, out_lo);
3004 bemit_helper_neg( out_hi);
3005 bemit_helper_neg( out_lo);
3006 bemit_helper_sbb0(out_hi);
3010 bemit_helper_zero(out_hi);
3011 bemit_helper_neg( out_lo);
3012 bemit_helper_sbb( in_hi, out_hi);
3016 * Emit a single opcode.
3018 #define EMIT_SINGLEOP(op, code) \
3019 static void bemit_ ## op(const ir_node *node) { \
3024 //EMIT_SINGLEOP(daa, 0x27)
3025 //EMIT_SINGLEOP(das, 0x2F)
3026 //EMIT_SINGLEOP(aaa, 0x37)
3027 //EMIT_SINGLEOP(aas, 0x3F)
3028 //EMIT_SINGLEOP(nop, 0x90)
3029 EMIT_SINGLEOP(cwtl, 0x98)
3030 EMIT_SINGLEOP(cltd, 0x99)
3031 //EMIT_SINGLEOP(fwait, 0x9B)
3032 EMIT_SINGLEOP(sahf, 0x9E)
3033 //EMIT_SINGLEOP(popf, 0x9D)
3034 EMIT_SINGLEOP(leave, 0xC9)
3035 EMIT_SINGLEOP(int3, 0xCC)
3036 //EMIT_SINGLEOP(iret, 0xCF)
3037 //EMIT_SINGLEOP(xlat, 0xD7)
3038 //EMIT_SINGLEOP(lock, 0xF0)
3039 EMIT_SINGLEOP(rep, 0xF3)
3040 //EMIT_SINGLEOP(halt, 0xF4)
3041 EMIT_SINGLEOP(cmc, 0xF5)
3042 EMIT_SINGLEOP(stc, 0xF9)
3043 //EMIT_SINGLEOP(cli, 0xFA)
3044 //EMIT_SINGLEOP(sti, 0xFB)
3045 //EMIT_SINGLEOP(std, 0xFD)
3048 * Emits a MOV out, [MEM].
3050 static void bemit_load(const ir_node *node)
3052 const arch_register_t *out = get_out_reg(node, 0);
3054 if (out->index == REG_GP_EAX) {
3055 ir_node *base = get_irn_n(node, n_ia32_base);
3056 int has_base = !is_ia32_NoReg_GP(base);
3057 ir_node *idx = get_irn_n(node, n_ia32_index);
3058 int has_index = !is_ia32_NoReg_GP(idx);
3059 if (!has_base && !has_index) {
3060 ir_entity *ent = get_ia32_am_sc(node);
3061 int offs = get_ia32_am_offs_int(node);
3062 /* load from constant address to EAX can be encoded
3065 bemit_entity(ent, 0, offs, false);
3070 bemit_mod_am(reg_gp_map[out->index], node);
3074 * Emits a MOV [mem], in.
3076 static void bemit_store(const ir_node *node)
3078 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3079 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3081 if (is_ia32_Immediate(value)) {
3084 bemit_mod_am(0, node);
3085 bemit8(get_ia32_immediate_attr_const(value)->offset);
3086 } else if (size == 16) {
3089 bemit_mod_am(0, node);
3090 bemit16(get_ia32_immediate_attr_const(value)->offset);
3093 bemit_mod_am(0, node);
3094 bemit_immediate(value, false);
3097 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3099 if (in->index == REG_GP_EAX) {
3100 ir_node *base = get_irn_n(node, n_ia32_base);
3101 int has_base = !is_ia32_NoReg_GP(base);
3102 ir_node *idx = get_irn_n(node, n_ia32_index);
3103 int has_index = !is_ia32_NoReg_GP(idx);
3104 if (!has_base && !has_index) {
3105 ir_entity *ent = get_ia32_am_sc(node);
3106 int offs = get_ia32_am_offs_int(node);
3107 /* store to constant address from EAX can be encoded as
3108 * 0xA2/0xA3 [offset]*/
3116 bemit_entity(ent, 0, offs, false);
3128 bemit_mod_am(reg_gp_map[in->index], node);
3132 static void bemit_conv_i2i(const ir_node *node)
3134 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3143 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3144 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3145 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3151 static void bemit_push(const ir_node *node)
3153 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3155 if (is_ia32_Immediate(value)) {
3156 const ia32_immediate_attr_t *attr
3157 = get_ia32_immediate_attr_const(value);
3158 unsigned size = get_signed_imm_size(attr->offset);
3164 bemit8((unsigned char)attr->offset);
3169 bemit_immediate(value, false);
3172 } else if (is_ia32_NoReg_GP(value)) {
3174 bemit_mod_am(6, node);
3176 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3177 bemit8(0x50 + reg_gp_map[reg->index]);
3184 static void bemit_pop(const ir_node *node)
3186 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3187 bemit8(0x58 + reg_gp_map[reg->index]);
3190 static void bemit_popmem(const ir_node *node)
3193 bemit_mod_am(0, node);
3196 static void bemit_call(const ir_node *node)
3198 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3200 if (is_ia32_Immediate(proc)) {
3202 bemit_immediate(proc, true);
3204 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3208 static void bemit_jmp(const ir_node *dest_block)
3211 bemit_jmp_destination(dest_block);
3214 static void bemit_jump(const ir_node *node)
3216 if (can_be_fallthrough(node))
3219 bemit_jmp(get_cfop_target_block(node));
3222 static void bemit_jcc(int pnc, const ir_node *dest_block)
3224 unsigned char cc = pnc2cc(pnc);
3227 bemit_jmp_destination(dest_block);
3230 static void bemit_jp(bool odd, const ir_node *dest_block)
3234 bemit_jmp_destination(dest_block);
3237 static void bemit_ia32_jcc(const ir_node *node)
3239 ia32_condition_code_t cc = get_ia32_condcode(node);
3240 const ir_node *proj_true;
3241 const ir_node *proj_false;
3242 const ir_node *dest_true;
3243 const ir_node *dest_false;
3245 cc = determine_final_cc(node, 0, cc);
3247 /* get both Projs */
3248 proj_true = get_proj(node, pn_ia32_Jcc_true);
3249 assert(proj_true && "Jcc without true Proj");
3251 proj_false = get_proj(node, pn_ia32_Jcc_false);
3252 assert(proj_false && "Jcc without false Proj");
3254 if (can_be_fallthrough(proj_true)) {
3255 /* exchange both proj's so the second one can be omitted */
3256 const ir_node *t = proj_true;
3258 proj_true = proj_false;
3260 cc = ia32_negate_condition_code(cc);
3263 dest_true = get_cfop_target_block(proj_true);
3264 dest_false = get_cfop_target_block(proj_false);
3266 if (cc & ia32_cc_float_parity_cases) {
3267 /* Some floating point comparisons require a test of the parity flag,
3268 * which indicates that the result is unordered */
3269 if (cc & ia32_cc_negated) {
3270 bemit_jp(false, dest_true);
3272 /* we need a local label if the false proj is a fallthrough
3273 * as the falseblock might have no label emitted then */
3274 if (can_be_fallthrough(proj_false)) {
3276 bemit8(0x06); // jp + 6
3278 bemit_jp(false, dest_false);
3282 bemit_jcc(cc, dest_true);
3284 /* the second Proj might be a fallthrough */
3285 if (can_be_fallthrough(proj_false)) {
3286 /* it's a fallthrough */
3288 bemit_jmp(dest_false);
3292 static void bemit_switchjmp(const ir_node *node)
3294 ir_entity *jump_table = get_ia32_am_sc(node);
3295 long default_pn = get_ia32_default_pn(node);
3297 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3298 bemit_mod_am(0x05, node);
3300 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
3306 static void bemit_return(const ir_node *node)
3308 unsigned pop = be_Return_get_pop(node);
3309 if (pop > 0 || be_Return_get_emit_pop(node)) {
3311 assert(pop <= 0xffff);
3318 static void bemit_subsp(const ir_node *node)
3320 const arch_register_t *out;
3323 /* mov %esp, %out */
3325 out = get_out_reg(node, 1);
3326 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3329 static void bemit_incsp(const ir_node *node)
3332 const arch_register_t *reg;
3336 offs = be_get_IncSP_offset(node);
3347 size = get_signed_imm_size(offs);
3348 bemit8(size == 1 ? 0x83 : 0x81);
3350 reg = get_out_reg(node, 0);
3351 bemit_modru(reg, ext);
3360 static void bemit_copybi(const ir_node *node)
3362 unsigned size = get_ia32_copyb_size(node);
3364 bemit8(0xA4); // movsb
3367 bemit8(0xA5); // movsw
3371 bemit8(0xA5); // movsl
3375 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3377 if (get_ia32_op_type(node) == ia32_Normal) {
3378 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3379 const arch_register_t *in1 = x87_attr->x87[0];
3380 const arch_register_t *in = x87_attr->x87[1];
3381 const arch_register_t *out = x87_attr->x87[2];
3385 } else if (out == in) {
3389 if (out->index == 0) {
3391 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3394 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3397 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3402 bemit_mod_am(code, node);
3406 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3408 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3409 const arch_register_t *out = x87_attr->x87[2];
3411 bemit8(code + out->index);
3414 static void bemit_fabs(const ir_node *node)
3422 static void bemit_fadd(const ir_node *node)
3424 bemit_fbinop(node, 0, 0);
3427 static void bemit_faddp(const ir_node *node)
3429 bemit_fbinopp(node, 0xC0);
3432 static void bemit_fchs(const ir_node *node)
3440 static void bemit_fdiv(const ir_node *node)
3442 bemit_fbinop(node, 6, 7);
3445 static void bemit_fdivp(const ir_node *node)
3447 bemit_fbinopp(node, 0xF8);
3450 static void bemit_fdivr(const ir_node *node)
3452 bemit_fbinop(node, 7, 6);
3455 static void bemit_fdivrp(const ir_node *node)
3457 bemit_fbinopp(node, 0xF0);
3460 static void bemit_fild(const ir_node *node)
3462 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3464 bemit8(0xDF); // filds
3465 bemit_mod_am(0, node);
3469 bemit8(0xDB); // fildl
3470 bemit_mod_am(0, node);
3474 bemit8(0xDF); // fildll
3475 bemit_mod_am(5, node);
3479 panic("invalid mode size");
3483 static void bemit_fist(const ir_node *node)
3485 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3487 bemit8(0xDF); // fists
3491 bemit8(0xDB); // fistl
3495 panic("invalid mode size");
3497 bemit_mod_am(2, node);
3500 static void bemit_fistp(const ir_node *node)
3502 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3504 bemit8(0xDF); // fistps
3505 bemit_mod_am(3, node);
3509 bemit8(0xDB); // fistpl
3510 bemit_mod_am(3, node);
3514 bemit8(0xDF); // fistpll
3515 bemit_mod_am(7, node);
3519 panic("invalid mode size");
3523 static void bemit_fld(const ir_node *node)
3525 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3527 bemit8(0xD9); // flds
3528 bemit_mod_am(0, node);
3532 bemit8(0xDD); // fldl
3533 bemit_mod_am(0, node);
3538 bemit8(0xDB); // fldt
3539 bemit_mod_am(5, node);
3543 panic("invalid mode size");
3547 static void bemit_fld1(const ir_node *node)
3551 bemit8(0xE8); // fld1
3554 static void bemit_fldcw(const ir_node *node)
3556 bemit8(0xD9); // fldcw
3557 bemit_mod_am(5, node);
3560 static void bemit_fldz(const ir_node *node)
3564 bemit8(0xEE); // fldz
3567 static void bemit_fmul(const ir_node *node)
3569 bemit_fbinop(node, 1, 1);
3572 static void bemit_fmulp(const ir_node *node)
3574 bemit_fbinopp(node, 0xC8);
3577 static void bemit_fpop(const ir_node *node)
3579 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3581 bemit8(0xD8 + attr->x87[0]->index);
3584 static void bemit_fpush(const ir_node *node)
3586 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3588 bemit8(0xC0 + attr->x87[0]->index);
3591 static void bemit_fpushcopy(const ir_node *node)
3593 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3595 bemit8(0xC0 + attr->x87[0]->index);
3598 static void bemit_fst(const ir_node *node)
3600 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3602 bemit8(0xD9); // fsts
3606 bemit8(0xDD); // fstl
3610 panic("invalid mode size");
3612 bemit_mod_am(2, node);
3615 static void bemit_fstp(const ir_node *node)
3617 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3619 bemit8(0xD9); // fstps
3620 bemit_mod_am(3, node);
3624 bemit8(0xDD); // fstpl
3625 bemit_mod_am(3, node);
3630 bemit8(0xDB); // fstpt
3631 bemit_mod_am(7, node);
3635 panic("invalid mode size");
3639 static void bemit_fsub(const ir_node *node)
3641 bemit_fbinop(node, 4, 5);
3644 static void bemit_fsubp(const ir_node *node)
3646 bemit_fbinopp(node, 0xE8);
3649 static void bemit_fsubr(const ir_node *node)
3651 bemit_fbinop(node, 5, 4);
3654 static void bemit_fsubrp(const ir_node *node)
3656 bemit_fbinopp(node, 0xE0);
3659 static void bemit_fnstcw(const ir_node *node)
3661 bemit8(0xD9); // fnstcw
3662 bemit_mod_am(7, node);
3665 static void bemit_fnstsw(void)
3667 bemit8(0xDF); // fnstsw %ax
3671 static void bemit_ftstfnstsw(const ir_node *node)
3675 bemit8(0xD9); // ftst
3680 static void bemit_fucomi(const ir_node *node)
3682 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3683 bemit8(0xDB); // fucomi
3684 bemit8(0xE8 + attr->x87[1]->index);
3687 static void bemit_fucomip(const ir_node *node)
3689 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3690 bemit8(0xDF); // fucomip
3691 bemit8(0xE8 + attr->x87[1]->index);
3694 static void bemit_fucomfnstsw(const ir_node *node)
3696 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3697 bemit8(0xDD); // fucom
3698 bemit8(0xE0 + attr->x87[1]->index);
3702 static void bemit_fucompfnstsw(const ir_node *node)
3704 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3705 bemit8(0xDD); // fucomp
3706 bemit8(0xE8 + attr->x87[1]->index);
3710 static void bemit_fucomppfnstsw(const ir_node *node)
3714 bemit8(0xDA); // fucompp
3719 static void bemit_fxch(const ir_node *node)
3721 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3723 bemit8(0xC8 + attr->x87[0]->index);
3727 * The type of a emitter function.
3729 typedef void (*emit_func) (const ir_node *);
3732 * Set a node emitter. Make it a bit more type safe.
3734 static void register_emitter(ir_op *op, emit_func func)
3736 op->ops.generic = (op_func) func;
3739 static void ia32_register_binary_emitters(void)
3741 /* first clear the generic function pointer for all ops */
3742 clear_irp_opcodes_generic_func();
3744 /* benode emitter */
3745 register_emitter(op_be_Copy, bemit_copy);
3746 register_emitter(op_be_CopyKeep, bemit_copy);
3747 register_emitter(op_be_IncSP, bemit_incsp);
3748 register_emitter(op_be_Perm, bemit_perm);
3749 register_emitter(op_be_Return, bemit_return);
3750 register_emitter(op_ia32_Adc, bemit_adc);
3751 register_emitter(op_ia32_Add, bemit_add);
3752 register_emitter(op_ia32_AddMem, bemit_addmem);
3753 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3754 register_emitter(op_ia32_And, bemit_and);
3755 register_emitter(op_ia32_AndMem, bemit_andmem);
3756 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3757 register_emitter(op_ia32_Breakpoint, bemit_int3);
3758 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3759 register_emitter(op_ia32_Call, bemit_call);
3760 register_emitter(op_ia32_Cltd, bemit_cltd);
3761 register_emitter(op_ia32_Cmc, bemit_cmc);
3762 register_emitter(op_ia32_Cmp, bemit_cmp);
3763 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3764 register_emitter(op_ia32_Const, bemit_mov_const);
3765 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3766 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3767 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3768 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3769 register_emitter(op_ia32_Dec, bemit_dec);
3770 register_emitter(op_ia32_DecMem, bemit_decmem);
3771 register_emitter(op_ia32_Div, bemit_div);
3772 register_emitter(op_ia32_FldCW, bemit_fldcw);
3773 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3774 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3775 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3776 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3777 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3778 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3779 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3780 register_emitter(op_ia32_IDiv, bemit_idiv);
3781 register_emitter(op_ia32_IJmp, bemit_ijmp);
3782 register_emitter(op_ia32_IMul, bemit_imul);
3783 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3784 register_emitter(op_ia32_Inc, bemit_inc);
3785 register_emitter(op_ia32_IncMem, bemit_incmem);
3786 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3787 register_emitter(op_ia32_Jmp, bemit_jump);
3788 register_emitter(op_ia32_LdTls, bemit_ldtls);
3789 register_emitter(op_ia32_Lea, bemit_lea);
3790 register_emitter(op_ia32_Leave, bemit_leave);
3791 register_emitter(op_ia32_Load, bemit_load);
3792 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3793 register_emitter(op_ia32_Mul, bemit_mul);
3794 register_emitter(op_ia32_Neg, bemit_neg);
3795 register_emitter(op_ia32_NegMem, bemit_negmem);
3796 register_emitter(op_ia32_Not, bemit_not);
3797 register_emitter(op_ia32_NotMem, bemit_notmem);
3798 register_emitter(op_ia32_Or, bemit_or);
3799 register_emitter(op_ia32_OrMem, bemit_ormem);
3800 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3801 register_emitter(op_ia32_Pop, bemit_pop);
3802 register_emitter(op_ia32_PopEbp, bemit_pop);
3803 register_emitter(op_ia32_PopMem, bemit_popmem);
3804 register_emitter(op_ia32_Push, bemit_push);
3805 register_emitter(op_ia32_RepPrefix, bemit_rep);
3806 register_emitter(op_ia32_Rol, bemit_rol);
3807 register_emitter(op_ia32_RolMem, bemit_rolmem);
3808 register_emitter(op_ia32_Ror, bemit_ror);
3809 register_emitter(op_ia32_RorMem, bemit_rormem);
3810 register_emitter(op_ia32_Sahf, bemit_sahf);
3811 register_emitter(op_ia32_Sar, bemit_sar);
3812 register_emitter(op_ia32_SarMem, bemit_sarmem);
3813 register_emitter(op_ia32_Sbb, bemit_sbb);
3814 register_emitter(op_ia32_Setcc, bemit_setcc);
3815 register_emitter(op_ia32_Shl, bemit_shl);
3816 register_emitter(op_ia32_ShlD, bemit_shld);
3817 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3818 register_emitter(op_ia32_Shr, bemit_shr);
3819 register_emitter(op_ia32_ShrD, bemit_shrd);
3820 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3821 register_emitter(op_ia32_Stc, bemit_stc);
3822 register_emitter(op_ia32_Store, bemit_store);
3823 register_emitter(op_ia32_Store8Bit, bemit_store);
3824 register_emitter(op_ia32_Sub, bemit_sub);
3825 register_emitter(op_ia32_SubMem, bemit_submem);
3826 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3827 register_emitter(op_ia32_SubSP, bemit_subsp);
3828 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3829 register_emitter(op_ia32_Test, bemit_test);
3830 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3831 register_emitter(op_ia32_Xor, bemit_xor);
3832 register_emitter(op_ia32_Xor0, bemit_xor0);
3833 register_emitter(op_ia32_XorMem, bemit_xormem);
3834 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3835 register_emitter(op_ia32_fabs, bemit_fabs);
3836 register_emitter(op_ia32_fadd, bemit_fadd);
3837 register_emitter(op_ia32_faddp, bemit_faddp);
3838 register_emitter(op_ia32_fchs, bemit_fchs);
3839 register_emitter(op_ia32_fdiv, bemit_fdiv);
3840 register_emitter(op_ia32_fdivp, bemit_fdivp);
3841 register_emitter(op_ia32_fdivr, bemit_fdivr);
3842 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3843 register_emitter(op_ia32_fild, bemit_fild);
3844 register_emitter(op_ia32_fist, bemit_fist);
3845 register_emitter(op_ia32_fistp, bemit_fistp);
3846 register_emitter(op_ia32_fld, bemit_fld);
3847 register_emitter(op_ia32_fld1, bemit_fld1);
3848 register_emitter(op_ia32_fldz, bemit_fldz);
3849 register_emitter(op_ia32_fmul, bemit_fmul);
3850 register_emitter(op_ia32_fmulp, bemit_fmulp);
3851 register_emitter(op_ia32_fpop, bemit_fpop);
3852 register_emitter(op_ia32_fpush, bemit_fpush);
3853 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3854 register_emitter(op_ia32_fst, bemit_fst);
3855 register_emitter(op_ia32_fstp, bemit_fstp);
3856 register_emitter(op_ia32_fsub, bemit_fsub);
3857 register_emitter(op_ia32_fsubp, bemit_fsubp);
3858 register_emitter(op_ia32_fsubr, bemit_fsubr);
3859 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3860 register_emitter(op_ia32_fxch, bemit_fxch);
3862 /* ignore the following nodes */
3863 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3864 register_emitter(op_be_Keep, emit_Nothing);
3865 register_emitter(op_be_Start, emit_Nothing);
3866 register_emitter(op_Phi, emit_Nothing);
3867 register_emitter(op_Start, emit_Nothing);
3870 static void gen_binary_block(ir_node *block)
3874 ia32_emit_block_header(block);
3876 /* emit the contents of the block */
3877 sched_foreach(block, node) {
3878 ia32_emit_node(node);
3882 void ia32_gen_binary_routine(ir_graph *irg)
3884 ir_entity *entity = get_irg_entity(irg);
3885 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3886 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3887 ir_node **blk_sched = irg_data->blk_sched;
3890 isa = (ia32_isa_t*) arch_env;
3892 ia32_register_binary_emitters();
3894 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
3896 /* we use links to point to target blocks */
3897 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3898 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3900 /* initialize next block links */
3901 n = ARR_LEN(blk_sched);
3902 for (i = 0; i < n; ++i) {
3903 ir_node *block = blk_sched[i];
3904 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3906 set_irn_link(block, prev);
3909 for (i = 0; i < n; ++i) {
3910 ir_node *block = blk_sched[i];
3911 gen_binary_block(block);
3914 be_gas_emit_function_epilog(entity);
3915 be_dbg_method_end();
3917 be_emit_write_line();
3919 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3923 void ia32_init_emitter(void)
3925 lc_opt_entry_t *be_grp;
3926 lc_opt_entry_t *ia32_grp;
3928 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3929 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3931 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3935 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");