2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
76 static ir_label_t exc_label_id;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 static int is_fallthrough(const ir_node *cfgpred)
88 if (!is_Proj(cfgpred))
90 pred = get_Proj_pred(cfgpred);
91 if (is_ia32_SwitchJmp(pred))
97 static int block_needs_label(const ir_node *block)
100 int n_cfgpreds = get_Block_n_cfgpreds(block);
102 if (n_cfgpreds == 0) {
104 } else if (n_cfgpreds == 1) {
105 ir_node *cfgpred = get_Block_cfgpred(block, 0);
106 ir_node *cfgpred_block = get_nodes_block(cfgpred);
108 if (get_prev_block_sched(block) == cfgpred_block
109 && is_fallthrough(cfgpred)) {
118 * Returns the register at in position pos.
120 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
123 const arch_register_t *reg = NULL;
125 assert(get_irn_arity(irn) > pos && "Invalid IN position");
127 /* The out register of the operator at position pos is the
128 in register we need. */
129 op = get_irn_n(irn, pos);
131 reg = arch_get_irn_register(arch_env, op);
133 assert(reg && "no in register found");
135 if (reg == &ia32_gp_regs[REG_GP_NOREG])
136 panic("trying to emit noreg for %+F input %d", irn, pos);
138 /* in case of unknown register: just return a valid register */
139 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
140 const arch_register_req_t *req;
142 /* ask for the requirements */
143 req = arch_get_register_req(arch_env, irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(arch_env, irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = get_ia32_out_reg(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(arch_env, proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
214 static void emit_8bit_register(const arch_register_t *reg)
216 const char *reg_name = arch_register_get_name(reg);
219 be_emit_char(reg_name[1]);
223 static void emit_16bit_register(const arch_register_t *reg)
225 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
228 be_emit_string(reg_name);
231 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
233 const char *reg_name;
236 int size = get_mode_size_bits(mode);
238 case 8: emit_8bit_register(reg); return;
239 case 16: emit_16bit_register(reg); return;
241 assert(mode_is_float(mode) || size == 32);
244 reg_name = arch_register_get_name(reg);
247 be_emit_string(reg_name);
250 void ia32_emit_source_register(const ir_node *node, int pos)
252 const arch_register_t *reg = get_in_reg(node, pos);
254 emit_register(reg, NULL);
257 static void emit_ia32_Immediate(const ir_node *node);
259 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
261 const arch_register_t *reg;
262 ir_node *in = get_irn_n(node, pos);
263 if (is_ia32_Immediate(in)) {
264 emit_ia32_Immediate(in);
268 reg = get_in_reg(node, pos);
269 emit_8bit_register(reg);
272 void ia32_emit_dest_register(const ir_node *node, int pos)
274 const arch_register_t *reg = get_out_reg(node, pos);
276 emit_register(reg, NULL);
279 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
281 const arch_register_t *reg = get_out_reg(node, pos);
283 emit_register(reg, mode_Bu);
286 void ia32_emit_x87_register(const ir_node *node, int pos)
288 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
292 be_emit_string(attr->x87[pos]->name);
295 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
297 if (mode_is_float(mode)) {
298 switch(get_mode_size_bits(mode)) {
299 case 32: be_emit_char('s'); return;
300 case 64: be_emit_char('l'); return;
302 case 96: be_emit_char('t'); return;
305 assert(mode_is_int(mode) || mode_is_reference(mode));
306 switch(get_mode_size_bits(mode)) {
307 /* gas docu says q is the suffix but gcc, objdump and icc use ll
309 case 64: be_emit_cstring("ll"); return;
310 case 32: be_emit_char('l'); return;
311 case 16: be_emit_char('w'); return;
312 case 8: be_emit_char('b'); return;
315 panic("Can't output mode_suffix for %+F", mode);
318 void ia32_emit_mode_suffix(const ir_node *node)
320 ir_mode *mode = get_ia32_ls_mode(node);
324 ia32_emit_mode_suffix_mode(mode);
327 void ia32_emit_x87_mode_suffix(const ir_node *node)
329 /* we only need to emit the mode on address mode */
330 if (get_ia32_op_type(node) != ia32_Normal) {
331 ir_mode *mode = get_ia32_ls_mode(node);
332 assert(mode != NULL);
333 ia32_emit_mode_suffix_mode(mode);
337 static char get_xmm_mode_suffix(ir_mode *mode)
339 assert(mode_is_float(mode));
340 switch(get_mode_size_bits(mode)) {
343 default: panic("Invalid XMM mode");
347 void ia32_emit_xmm_mode_suffix(const ir_node *node)
349 ir_mode *mode = get_ia32_ls_mode(node);
350 assert(mode != NULL);
352 be_emit_char(get_xmm_mode_suffix(mode));
355 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
357 ir_mode *mode = get_ia32_ls_mode(node);
358 assert(mode != NULL);
359 be_emit_char(get_xmm_mode_suffix(mode));
362 void ia32_emit_extend_suffix(const ir_mode *mode)
364 if (get_mode_size_bits(mode) == 32)
366 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
369 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
371 ir_node *in = get_irn_n(node, pos);
372 if (is_ia32_Immediate(in)) {
373 emit_ia32_Immediate(in);
375 const ir_mode *mode = get_ia32_ls_mode(node);
376 const arch_register_t *reg = get_in_reg(node, pos);
377 emit_register(reg, mode);
382 * Emits registers and/or address mode of a binary operation.
384 void ia32_emit_binop(const ir_node *node)
386 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
387 const ir_mode *mode = get_ia32_ls_mode(node);
388 const arch_register_t *reg_left;
390 switch(get_ia32_op_type(node)) {
392 reg_left = get_in_reg(node, n_ia32_binary_left);
393 if (is_ia32_Immediate(right_op)) {
394 emit_ia32_Immediate(right_op);
395 be_emit_cstring(", ");
396 emit_register(reg_left, mode);
399 const arch_register_t *reg_right
400 = get_in_reg(node, n_ia32_binary_right);
401 emit_register(reg_right, mode);
402 be_emit_cstring(", ");
403 emit_register(reg_left, mode);
407 if (is_ia32_Immediate(right_op)) {
408 emit_ia32_Immediate(right_op);
409 be_emit_cstring(", ");
412 reg_left = get_in_reg(node, n_ia32_binary_left);
414 be_emit_cstring(", ");
415 emit_register(reg_left, mode);
419 panic("DestMode can't be output by %%binop anymore");
422 assert(0 && "unsupported op type");
427 * Emits registers and/or address mode of a binary operation.
429 void ia32_emit_x87_binop(const ir_node *node)
431 switch(get_ia32_op_type(node)) {
434 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
435 const arch_register_t *in1 = x87_attr->x87[0];
436 const arch_register_t *in2 = x87_attr->x87[1];
437 const arch_register_t *out = x87_attr->x87[2];
438 const arch_register_t *in;
440 in = out ? ((out == in2) ? in1 : in2) : in2;
441 out = out ? out : in1;
444 be_emit_string(arch_register_get_name(in));
445 be_emit_cstring(", %");
446 be_emit_string(arch_register_get_name(out));
454 assert(0 && "unsupported op type");
459 * Emits registers and/or address mode of a unary operation.
461 void ia32_emit_unop(const ir_node *node, int pos)
465 switch(get_ia32_op_type(node)) {
467 op = get_irn_n(node, pos);
468 if (is_ia32_Immediate(op)) {
469 emit_ia32_Immediate(op);
471 ia32_emit_source_register(node, pos);
479 assert(0 && "unsupported op type");
483 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
487 set_entity_backend_marked(entity, 1);
488 id = get_entity_ld_ident(entity);
491 if (get_entity_owner(entity) == get_tls_type()) {
492 if (get_entity_visibility(entity) == visibility_external_allocated) {
493 be_emit_cstring("@INDNTPOFF");
495 be_emit_cstring("@NTPOFF");
499 if (!no_pic_adjust && do_pic) {
500 /* TODO: only do this when necessary */
502 be_emit_string(pic_base_label);
507 * Emits address mode.
509 void ia32_emit_am(const ir_node *node)
511 ir_entity *ent = get_ia32_am_sc(node);
512 int offs = get_ia32_am_offs_int(node);
513 ir_node *base = get_irn_n(node, n_ia32_base);
514 int has_base = !is_ia32_NoReg_GP(base);
515 ir_node *index = get_irn_n(node, n_ia32_index);
516 int has_index = !is_ia32_NoReg_GP(index);
518 /* just to be sure... */
519 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
523 if (is_ia32_am_sc_sign(node))
525 ia32_emit_entity(ent, 0);
528 /* also handle special case if nothing is set */
529 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
531 be_emit_irprintf("%+d", offs);
533 be_emit_irprintf("%d", offs);
537 if (has_base || has_index) {
542 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
543 emit_register(reg, NULL);
546 /* emit index + scale */
548 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
551 emit_register(reg, NULL);
553 scale = get_ia32_am_scale(node);
555 be_emit_irprintf(",%d", 1 << scale);
562 static void emit_ia32_IMul(const ir_node *node)
564 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
565 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
567 be_emit_cstring("\timul");
568 ia32_emit_mode_suffix(node);
571 ia32_emit_binop(node);
573 /* do we need the 3-address form? */
574 if (is_ia32_NoReg_GP(left) ||
575 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
576 be_emit_cstring(", ");
577 emit_register(out_reg, get_ia32_ls_mode(node));
579 be_emit_finish_line_gas(node);
582 /*************************************************
585 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
586 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
587 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
588 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
590 *************************************************/
593 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
596 * coding of conditions
598 struct cmp2conditon_t {
604 * positive conditions for signed compares
606 static const struct cmp2conditon_t cmp2condition_s[] = {
607 { NULL, pn_Cmp_False }, /* always false */
608 { "e", pn_Cmp_Eq }, /* == */
609 { "l", pn_Cmp_Lt }, /* < */
610 { "le", pn_Cmp_Le }, /* <= */
611 { "g", pn_Cmp_Gt }, /* > */
612 { "ge", pn_Cmp_Ge }, /* >= */
613 { "ne", pn_Cmp_Lg }, /* != */
614 { NULL, pn_Cmp_Leg}, /* always true */
618 * positive conditions for unsigned compares
620 static const struct cmp2conditon_t cmp2condition_u[] = {
621 { NULL, pn_Cmp_False }, /* always false */
622 { "e", pn_Cmp_Eq }, /* == */
623 { "b", pn_Cmp_Lt }, /* < */
624 { "be", pn_Cmp_Le }, /* <= */
625 { "a", pn_Cmp_Gt }, /* > */
626 { "ae", pn_Cmp_Ge }, /* >= */
627 { "ne", pn_Cmp_Lg }, /* != */
628 { NULL, pn_Cmp_Leg }, /* always true */
632 * walks up a tree of copies/perms/spills/reloads to find the original value
633 * that is moved around
635 static ir_node *find_original_value(ir_node *node)
637 inc_irg_visited(current_ir_graph);
639 mark_irn_visited(node);
640 if (be_is_Copy(node)) {
641 node = be_get_Copy_op(node);
642 } else if (be_is_CopyKeep(node)) {
643 node = be_get_CopyKeep_op(node);
644 } else if (is_Proj(node)) {
645 ir_node *pred = get_Proj_pred(node);
646 if (be_is_Perm(pred)) {
647 node = get_irn_n(pred, get_Proj_proj(node));
648 } else if (be_is_MemPerm(pred)) {
649 node = get_irn_n(pred, get_Proj_proj(node) + 1);
650 } else if (is_ia32_Load(pred)) {
651 node = get_irn_n(pred, n_ia32_Load_mem);
655 } else if (is_ia32_Store(node)) {
656 node = get_irn_n(node, n_ia32_Store_val);
657 } else if (is_Phi(node)) {
659 arity = get_irn_arity(node);
660 for(i = 0; i < arity; ++i) {
661 ir_node *in = get_irn_n(node, i);
674 static int determine_final_pnc(const ir_node *node, int flags_pos,
677 ir_node *flags = get_irn_n(node, flags_pos);
678 const ia32_attr_t *flags_attr;
679 flags = skip_Proj(flags);
681 if (is_ia32_Sahf(flags)) {
682 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
683 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
684 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
685 cmp = find_original_value(cmp);
686 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
687 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
690 flags_attr = get_ia32_attr_const(cmp);
691 if (flags_attr->data.ins_permuted)
692 pnc = get_mirrored_pnc(pnc);
693 pnc |= ia32_pn_Cmp_float;
694 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
695 || is_ia32_Fucompi(flags)) {
696 flags_attr = get_ia32_attr_const(flags);
698 if (flags_attr->data.ins_permuted)
699 pnc = get_mirrored_pnc(pnc);
700 pnc |= ia32_pn_Cmp_float;
703 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
704 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
706 flags_attr = get_ia32_attr_const(flags);
708 if (flags_attr->data.ins_permuted)
709 pnc = get_mirrored_pnc(pnc);
710 if (flags_attr->data.cmp_unsigned)
711 pnc |= ia32_pn_Cmp_unsigned;
717 static void ia32_emit_cmp_suffix(int pnc)
721 if ((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
723 assert(cmp2condition_u[pnc].num == pnc);
724 str = cmp2condition_u[pnc].name;
727 assert(cmp2condition_s[pnc].num == pnc);
728 str = cmp2condition_s[pnc].name;
734 void ia32_emit_cmp_suffix_node(const ir_node *node,
737 const ia32_attr_t *attr = get_ia32_attr_const(node);
739 pn_Cmp pnc = get_ia32_condcode(node);
741 pnc = determine_final_pnc(node, flags_pos, pnc);
742 if (attr->data.ins_permuted) {
743 if (pnc & ia32_pn_Cmp_float) {
744 pnc = get_negated_pnc(pnc, mode_F);
746 pnc = get_negated_pnc(pnc, mode_Iu);
750 ia32_emit_cmp_suffix(pnc);
754 * Returns the target block for a control flow node.
756 static ir_node *get_cfop_target_block(const ir_node *irn)
758 assert(get_irn_mode(irn) == mode_X);
759 return get_irn_link(irn);
763 * Emits a block label for the given block.
765 static void ia32_emit_block_name(const ir_node *block)
767 if (has_Block_label(block)) {
768 be_emit_string(be_gas_block_label_prefix());
769 be_emit_irprintf("%lu", get_Block_label(block));
771 be_emit_cstring(BLOCK_PREFIX);
772 be_emit_irprintf("%ld", get_irn_node_nr(block));
777 * Emits an exception label for a given node.
779 static void ia32_emit_exc_label(const ir_node *node)
781 be_emit_string(be_gas_insn_label_prefix());
782 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
786 * Emits the target label for a control flow node.
788 static void ia32_emit_cfop_target(const ir_node *node)
790 ir_node *block = get_cfop_target_block(node);
792 ia32_emit_block_name(block);
796 * Returns the Proj with projection number proj and NOT mode_M
798 static ir_node *get_proj(const ir_node *node, long proj)
800 const ir_edge_t *edge;
803 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
805 foreach_out_edge(node, edge) {
806 src = get_edge_src_irn(edge);
808 assert(is_Proj(src) && "Proj expected");
809 if (get_irn_mode(src) == mode_M)
812 if (get_Proj_proj(src) == proj)
818 static int can_be_fallthrough(const ir_node *node)
820 ir_node *target_block = get_cfop_target_block(node);
821 ir_node *block = get_nodes_block(node);
822 return get_prev_block_sched(target_block) == block;
826 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
828 static void emit_ia32_Jcc(const ir_node *node)
830 int need_parity_label = 0;
831 const ir_node *proj_true;
832 const ir_node *proj_false;
833 const ir_node *block;
834 pn_Cmp pnc = get_ia32_condcode(node);
836 pnc = determine_final_pnc(node, 0, pnc);
839 proj_true = get_proj(node, pn_ia32_Jcc_true);
840 assert(proj_true && "Jcc without true Proj");
842 proj_false = get_proj(node, pn_ia32_Jcc_false);
843 assert(proj_false && "Jcc without false Proj");
845 block = get_nodes_block(node);
847 if (can_be_fallthrough(proj_true)) {
848 /* exchange both proj's so the second one can be omitted */
849 const ir_node *t = proj_true;
851 proj_true = proj_false;
853 if (pnc & ia32_pn_Cmp_float) {
854 pnc = get_negated_pnc(pnc, mode_F);
856 pnc = get_negated_pnc(pnc, mode_Iu);
860 if (pnc & ia32_pn_Cmp_float) {
861 /* Some floating point comparisons require a test of the parity flag,
862 * which indicates that the result is unordered */
865 be_emit_cstring("\tjp ");
866 ia32_emit_cfop_target(proj_true);
867 be_emit_finish_line_gas(proj_true);
872 be_emit_cstring("\tjnp ");
873 ia32_emit_cfop_target(proj_true);
874 be_emit_finish_line_gas(proj_true);
880 /* we need a local label if the false proj is a fallthrough
881 * as the falseblock might have no label emitted then */
882 if (can_be_fallthrough(proj_false)) {
883 need_parity_label = 1;
884 be_emit_cstring("\tjp 1f");
886 be_emit_cstring("\tjp ");
887 ia32_emit_cfop_target(proj_false);
889 be_emit_finish_line_gas(proj_false);
895 be_emit_cstring("\tjp ");
896 ia32_emit_cfop_target(proj_true);
897 be_emit_finish_line_gas(proj_true);
905 be_emit_cstring("\tj");
906 ia32_emit_cmp_suffix(pnc);
908 ia32_emit_cfop_target(proj_true);
909 be_emit_finish_line_gas(proj_true);
912 if (need_parity_label) {
913 be_emit_cstring("1:");
914 be_emit_write_line();
917 /* the second Proj might be a fallthrough */
918 if (can_be_fallthrough(proj_false)) {
919 be_emit_cstring("\t/* fallthrough to ");
920 ia32_emit_cfop_target(proj_false);
921 be_emit_cstring(" */");
922 be_emit_finish_line_gas(proj_false);
924 be_emit_cstring("\tjmp ");
925 ia32_emit_cfop_target(proj_false);
926 be_emit_finish_line_gas(proj_false);
930 static void emit_ia32_CMov(const ir_node *node)
932 const ia32_attr_t *attr = get_ia32_attr_const(node);
933 int ins_permuted = attr->data.ins_permuted;
934 const arch_register_t *out = arch_get_irn_register(arch_env, node);
935 pn_Cmp pnc = get_ia32_condcode(node);
936 const arch_register_t *in_true;
937 const arch_register_t *in_false;
939 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
941 in_true = arch_get_irn_register(arch_env,
942 get_irn_n(node, n_ia32_CMov_val_true));
943 in_false = arch_get_irn_register(arch_env,
944 get_irn_n(node, n_ia32_CMov_val_false));
946 /* should be same constraint fullfilled? */
947 if (out == in_false) {
948 /* yes -> nothing to do */
949 } else if (out == in_true) {
950 const arch_register_t *tmp;
952 assert(get_ia32_op_type(node) == ia32_Normal);
954 ins_permuted = !ins_permuted;
961 be_emit_cstring("\tmovl ");
962 emit_register(in_false, NULL);
963 be_emit_cstring(", ");
964 emit_register(out, NULL);
965 be_emit_finish_line_gas(node);
969 if (pnc & ia32_pn_Cmp_float) {
970 pnc = get_negated_pnc(pnc, mode_F);
972 pnc = get_negated_pnc(pnc, mode_Iu);
976 /* TODO: handling of Nans isn't correct yet */
978 be_emit_cstring("\tcmov");
979 ia32_emit_cmp_suffix(pnc);
981 if (get_ia32_op_type(node) == ia32_AddrModeS) {
984 emit_register(in_true, get_ia32_ls_mode(node));
986 be_emit_cstring(", ");
987 emit_register(out, get_ia32_ls_mode(node));
988 be_emit_finish_line_gas(node);
991 /*********************************************************
994 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
995 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
996 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
997 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1000 *********************************************************/
1002 /* jump table entry (target and corresponding number) */
1003 typedef struct _branch_t {
1008 /* jump table for switch generation */
1009 typedef struct _jmp_tbl_t {
1010 ir_node *defProj; /**< default target */
1011 long min_value; /**< smallest switch case */
1012 long max_value; /**< largest switch case */
1013 long num_branches; /**< number of jumps */
1014 char *label; /**< label of the jump table */
1015 branch_t *branches; /**< jump array */
1019 * Compare two variables of type branch_t. Used to sort all switch cases
1021 static int ia32_cmp_branch_t(const void *a, const void *b)
1023 branch_t *b1 = (branch_t *)a;
1024 branch_t *b2 = (branch_t *)b;
1026 if (b1->value <= b2->value)
1033 * Emits code for a SwitchJmp (creates a jump table if
1034 * possible otherwise a cmp-jmp cascade). Port from
1037 static void emit_ia32_SwitchJmp(const ir_node *node)
1039 unsigned long interval;
1045 const ir_edge_t *edge;
1047 /* fill the table structure */
1048 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1049 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1051 tbl.num_branches = get_irn_n_edges(node) - 1;
1052 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1053 tbl.min_value = INT_MAX;
1054 tbl.max_value = INT_MIN;
1056 default_pn = get_ia32_condcode(node);
1058 /* go over all proj's and collect them */
1059 foreach_out_edge(node, edge) {
1060 proj = get_edge_src_irn(edge);
1061 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1063 pnc = get_Proj_proj(proj);
1065 /* check for default proj */
1066 if (pnc == default_pn) {
1067 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1070 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1071 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1073 /* create branch entry */
1074 tbl.branches[i].target = proj;
1075 tbl.branches[i].value = pnc;
1080 assert(i == tbl.num_branches);
1082 /* sort the branches by their number */
1083 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1085 /* two-complement's magic make this work without overflow */
1086 interval = tbl.max_value - tbl.min_value;
1088 /* emit the table */
1089 be_emit_cstring("\tcmpl $");
1090 be_emit_irprintf("%u, ", interval);
1091 ia32_emit_source_register(node, 0);
1092 be_emit_finish_line_gas(node);
1094 be_emit_cstring("\tja ");
1095 ia32_emit_cfop_target(tbl.defProj);
1096 be_emit_finish_line_gas(node);
1098 if (tbl.num_branches > 1) {
1100 be_emit_cstring("\tjmp *");
1101 be_emit_string(tbl.label);
1102 be_emit_cstring("(,");
1103 ia32_emit_source_register(node, 0);
1104 be_emit_cstring(",4)");
1105 be_emit_finish_line_gas(node);
1107 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1108 be_emit_cstring("\t.align 4\n");
1109 be_emit_write_line();
1111 be_emit_string(tbl.label);
1112 be_emit_cstring(":\n");
1113 be_emit_write_line();
1115 be_emit_cstring(".long ");
1116 ia32_emit_cfop_target(tbl.branches[0].target);
1117 be_emit_finish_line_gas(NULL);
1119 last_value = tbl.branches[0].value;
1120 for (i = 1; i < tbl.num_branches; ++i) {
1121 while (++last_value < tbl.branches[i].value) {
1122 be_emit_cstring(".long ");
1123 ia32_emit_cfop_target(tbl.defProj);
1124 be_emit_finish_line_gas(NULL);
1126 be_emit_cstring(".long ");
1127 ia32_emit_cfop_target(tbl.branches[i].target);
1128 be_emit_finish_line_gas(NULL);
1130 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1132 /* one jump is enough */
1133 be_emit_cstring("\tjmp ");
1134 ia32_emit_cfop_target(tbl.branches[0].target);
1135 be_emit_finish_line_gas(node);
1145 * Emits code for a unconditional jump.
1147 static void emit_Jmp(const ir_node *node)
1151 /* for now, the code works for scheduled and non-schedules blocks */
1152 block = get_nodes_block(node);
1154 /* we have a block schedule */
1155 if (can_be_fallthrough(node)) {
1156 be_emit_cstring("\t/* fallthrough to ");
1157 ia32_emit_cfop_target(node);
1158 be_emit_cstring(" */");
1160 be_emit_cstring("\tjmp ");
1161 ia32_emit_cfop_target(node);
1163 be_emit_finish_line_gas(node);
1166 static void emit_ia32_Immediate(const ir_node *node)
1168 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1171 if (attr->symconst != NULL) {
1174 ia32_emit_entity(attr->symconst, 0);
1176 if (attr->symconst == NULL || attr->offset != 0) {
1177 if (attr->symconst != NULL) {
1178 be_emit_irprintf("%+d", attr->offset);
1180 be_emit_irprintf("0x%X", attr->offset);
1186 * Emit an inline assembler operand.
1188 * @param node the ia32_ASM node
1189 * @param s points to the operand (a %c)
1191 * @return pointer to the first char in s NOT in the current operand
1193 static const char* emit_asm_operand(const ir_node *node, const char *s)
1195 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1196 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1198 const arch_register_t *reg;
1199 const ia32_asm_reg_t *asm_regs = attr->register_map;
1200 const ia32_asm_reg_t *asm_reg;
1201 const char *reg_name;
1210 /* parse modifiers */
1213 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1237 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1238 "'%c' for asm op\n", node, c);
1244 sscanf(s, "%d%n", &num, &p);
1246 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1253 if (num < 0 || num >= ARR_LEN(asm_regs)) {
1254 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1255 "input/output (%+F)\n", node);
1258 asm_reg = & asm_regs[num];
1259 assert(asm_reg->valid);
1262 if (asm_reg->use_input == 0) {
1263 reg = get_out_reg(node, asm_reg->inout_pos);
1265 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1267 /* might be an immediate value */
1268 if (is_ia32_Immediate(pred)) {
1269 emit_ia32_Immediate(pred);
1272 reg = get_in_reg(node, asm_reg->inout_pos);
1275 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1276 "(%+F)\n", num, node);
1280 if (asm_reg->memory) {
1285 if (modifier != 0) {
1289 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1292 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1295 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1298 panic("Invalid asm op modifier");
1300 be_emit_string(reg_name);
1302 emit_register(reg, asm_reg->mode);
1305 if (asm_reg->memory) {
1313 * Emits code for an ASM pseudo op.
1315 static void emit_ia32_Asm(const ir_node *node)
1317 const void *gen_attr = get_irn_generic_attr_const(node);
1318 const ia32_asm_attr_t *attr
1319 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1320 ident *asm_text = attr->asm_text;
1321 const char *s = get_id_str(asm_text);
1323 be_emit_cstring("#APP\t");
1324 be_emit_finish_line_gas(node);
1331 s = emit_asm_operand(node, s);
1338 be_emit_write_line();
1340 be_emit_cstring("#NO_APP\n");
1341 be_emit_write_line();
1344 /**********************************
1347 * | | ___ _ __ _ _| |_) |
1348 * | | / _ \| '_ \| | | | _ <
1349 * | |___| (_) | |_) | |_| | |_) |
1350 * \_____\___/| .__/ \__, |____/
1353 **********************************/
1356 * Emit movsb/w instructions to make mov count divideable by 4
1358 static void emit_CopyB_prolog(unsigned size)
1360 be_emit_cstring("\tcld");
1361 be_emit_finish_line_gas(NULL);
1365 be_emit_cstring("\tmovsb");
1366 be_emit_finish_line_gas(NULL);
1369 be_emit_cstring("\tmovsw");
1370 be_emit_finish_line_gas(NULL);
1373 be_emit_cstring("\tmovsb");
1374 be_emit_finish_line_gas(NULL);
1375 be_emit_cstring("\tmovsw");
1376 be_emit_finish_line_gas(NULL);
1382 * Emit rep movsd instruction for memcopy.
1384 static void emit_ia32_CopyB(const ir_node *node)
1386 unsigned size = get_ia32_copyb_size(node);
1388 emit_CopyB_prolog(size);
1390 be_emit_cstring("\trep movsd");
1391 be_emit_finish_line_gas(node);
1395 * Emits unrolled memcopy.
1397 static void emit_ia32_CopyB_i(const ir_node *node)
1399 unsigned size = get_ia32_copyb_size(node);
1401 emit_CopyB_prolog(size & 0x3);
1405 be_emit_cstring("\tmovsd");
1406 be_emit_finish_line_gas(NULL);
1412 /***************************
1416 * | | / _ \| '_ \ \ / /
1417 * | |___| (_) | | | \ V /
1418 * \_____\___/|_| |_|\_/
1420 ***************************/
1423 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1425 static void emit_ia32_Conv_with_FP(const ir_node *node)
1427 ir_mode *ls_mode = get_ia32_ls_mode(node);
1428 int ls_bits = get_mode_size_bits(ls_mode);
1430 be_emit_cstring("\tcvt");
1432 if (is_ia32_Conv_I2FP(node)) {
1433 if (ls_bits == 32) {
1434 be_emit_cstring("si2ss");
1436 be_emit_cstring("si2sd");
1438 } else if (is_ia32_Conv_FP2I(node)) {
1439 if (ls_bits == 32) {
1440 be_emit_cstring("ss2si");
1442 be_emit_cstring("sd2si");
1445 assert(is_ia32_Conv_FP2FP(node));
1446 if (ls_bits == 32) {
1447 be_emit_cstring("sd2ss");
1449 be_emit_cstring("ss2sd");
1454 switch(get_ia32_op_type(node)) {
1456 ia32_emit_source_register(node, n_ia32_unary_op);
1458 case ia32_AddrModeS:
1462 assert(0 && "unsupported op type for Conv");
1464 be_emit_cstring(", ");
1465 ia32_emit_dest_register(node, 0);
1466 be_emit_finish_line_gas(node);
1469 static void emit_ia32_Conv_I2FP(const ir_node *node)
1471 emit_ia32_Conv_with_FP(node);
1474 static void emit_ia32_Conv_FP2I(const ir_node *node)
1476 emit_ia32_Conv_with_FP(node);
1479 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1481 emit_ia32_Conv_with_FP(node);
1485 * Emits code for an Int conversion.
1487 static void emit_ia32_Conv_I2I(const ir_node *node)
1489 const char *sign_suffix;
1490 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1491 int smaller_bits = get_mode_size_bits(smaller_mode);
1493 const arch_register_t *in_reg, *out_reg;
1495 assert(!mode_is_float(smaller_mode));
1496 assert(smaller_bits == 8 || smaller_bits == 16);
1498 signed_mode = mode_is_signed(smaller_mode);
1499 sign_suffix = signed_mode ? "s" : "z";
1501 out_reg = get_out_reg(node, 0);
1503 switch(get_ia32_op_type(node)) {
1505 in_reg = get_in_reg(node, n_ia32_unary_op);
1507 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1508 out_reg == &ia32_gp_regs[REG_EAX] &&
1512 /* argument and result are both in EAX and */
1513 /* signedness is ok: -> use the smaller cwtl opcode */
1514 be_emit_cstring("\tcwtl");
1516 be_emit_cstring("\tmov");
1517 be_emit_string(sign_suffix);
1518 ia32_emit_mode_suffix_mode(smaller_mode);
1519 be_emit_cstring("l ");
1520 emit_register(in_reg, smaller_mode);
1521 be_emit_cstring(", ");
1522 emit_register(out_reg, NULL);
1525 case ia32_AddrModeS: {
1526 be_emit_cstring("\tmov");
1527 be_emit_string(sign_suffix);
1528 ia32_emit_mode_suffix_mode(smaller_mode);
1529 be_emit_cstring("l ");
1531 be_emit_cstring(", ");
1532 emit_register(out_reg, NULL);
1536 panic("unsupported op type for Conv");
1538 be_emit_finish_line_gas(node);
1542 /*******************************************
1545 * | |__ ___ _ __ ___ __| | ___ ___
1546 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1547 * | |_) | __/ | | | (_) | (_| | __/\__ \
1548 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1550 *******************************************/
1553 * Emits a backend call
1555 static void emit_be_Call(const ir_node *node)
1557 ir_entity *ent = be_Call_get_entity(node);
1559 be_emit_cstring("\tcall ");
1561 ia32_emit_entity(ent, 1);
1563 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1565 emit_register(reg, NULL);
1567 be_emit_finish_line_gas(node);
1571 * Emits code to increase stack pointer.
1573 static void emit_be_IncSP(const ir_node *node)
1575 int offs = be_get_IncSP_offset(node);
1576 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1582 be_emit_cstring("\tsubl $");
1583 be_emit_irprintf("%u, ", offs);
1584 emit_register(reg, NULL);
1586 be_emit_cstring("\taddl $");
1587 be_emit_irprintf("%u, ", -offs);
1588 emit_register(reg, NULL);
1590 be_emit_finish_line_gas(node);
1594 * Emits code for Copy/CopyKeep.
1596 static void Copy_emitter(const ir_node *node, const ir_node *op)
1598 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1599 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1605 if (is_unknown_reg(in))
1607 /* copies of vf nodes aren't real... */
1608 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1611 mode = get_irn_mode(node);
1612 if (mode == mode_E) {
1613 be_emit_cstring("\tmovsd ");
1614 emit_register(in, NULL);
1615 be_emit_cstring(", ");
1616 emit_register(out, NULL);
1618 be_emit_cstring("\tmovl ");
1619 emit_register(in, NULL);
1620 be_emit_cstring(", ");
1621 emit_register(out, NULL);
1623 be_emit_finish_line_gas(node);
1626 static void emit_be_Copy(const ir_node *node)
1628 Copy_emitter(node, be_get_Copy_op(node));
1631 static void emit_be_CopyKeep(const ir_node *node)
1633 Copy_emitter(node, be_get_CopyKeep_op(node));
1637 * Emits code for exchange.
1639 static void emit_be_Perm(const ir_node *node)
1641 const arch_register_t *in0, *in1;
1642 const arch_register_class_t *cls0, *cls1;
1644 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1645 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1647 cls0 = arch_register_get_class(in0);
1648 cls1 = arch_register_get_class(in1);
1650 assert(cls0 == cls1 && "Register class mismatch at Perm");
1652 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1653 be_emit_cstring("\txchg ");
1654 emit_register(in1, NULL);
1655 be_emit_cstring(", ");
1656 emit_register(in0, NULL);
1657 be_emit_finish_line_gas(node);
1658 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1659 be_emit_cstring("\txorpd ");
1660 emit_register(in1, NULL);
1661 be_emit_cstring(", ");
1662 emit_register(in0, NULL);
1663 be_emit_finish_line_gas(NULL);
1665 be_emit_cstring("\txorpd ");
1666 emit_register(in0, NULL);
1667 be_emit_cstring(", ");
1668 emit_register(in1, NULL);
1669 be_emit_finish_line_gas(NULL);
1671 be_emit_cstring("\txorpd ");
1672 emit_register(in1, NULL);
1673 be_emit_cstring(", ");
1674 emit_register(in0, NULL);
1675 be_emit_finish_line_gas(node);
1676 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1678 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1681 panic("unexpected register class in be_Perm (%+F)", node);
1686 * Emits code for Constant loading.
1688 static void emit_ia32_Const(const ir_node *node)
1690 be_emit_cstring("\tmovl ");
1691 emit_ia32_Immediate(node);
1692 be_emit_cstring(", ");
1693 ia32_emit_dest_register(node, 0);
1695 be_emit_finish_line_gas(node);
1699 * Emits code to load the TLS base
1701 static void emit_ia32_LdTls(const ir_node *node)
1703 be_emit_cstring("\tmovl %gs:0, ");
1704 ia32_emit_dest_register(node, 0);
1705 be_emit_finish_line_gas(node);
1708 /* helper function for emit_ia32_Minus64Bit */
1709 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1711 be_emit_cstring("\tmovl ");
1712 emit_register(src, NULL);
1713 be_emit_cstring(", ");
1714 emit_register(dst, NULL);
1715 be_emit_finish_line_gas(node);
1718 /* helper function for emit_ia32_Minus64Bit */
1719 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1721 be_emit_cstring("\tnegl ");
1722 emit_register(reg, NULL);
1723 be_emit_finish_line_gas(node);
1726 /* helper function for emit_ia32_Minus64Bit */
1727 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1729 be_emit_cstring("\tsbbl $0, ");
1730 emit_register(reg, NULL);
1731 be_emit_finish_line_gas(node);
1734 /* helper function for emit_ia32_Minus64Bit */
1735 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1737 be_emit_cstring("\tsbbl ");
1738 emit_register(src, NULL);
1739 be_emit_cstring(", ");
1740 emit_register(dst, NULL);
1741 be_emit_finish_line_gas(node);
1744 /* helper function for emit_ia32_Minus64Bit */
1745 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1747 be_emit_cstring("\txchgl ");
1748 emit_register(src, NULL);
1749 be_emit_cstring(", ");
1750 emit_register(dst, NULL);
1751 be_emit_finish_line_gas(node);
1754 /* helper function for emit_ia32_Minus64Bit */
1755 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1757 be_emit_cstring("\txorl ");
1758 emit_register(reg, NULL);
1759 be_emit_cstring(", ");
1760 emit_register(reg, NULL);
1761 be_emit_finish_line_gas(node);
1764 static void emit_ia32_Minus64Bit(const ir_node *node)
1766 const arch_register_t *in_lo = get_in_reg(node, 0);
1767 const arch_register_t *in_hi = get_in_reg(node, 1);
1768 const arch_register_t *out_lo = get_out_reg(node, 0);
1769 const arch_register_t *out_hi = get_out_reg(node, 1);
1771 if (out_lo == in_lo) {
1772 if (out_hi != in_hi) {
1773 /* a -> a, b -> d */
1776 /* a -> a, b -> b */
1779 } else if (out_lo == in_hi) {
1780 if (out_hi == in_lo) {
1781 /* a -> b, b -> a */
1782 emit_xchg(node, in_lo, in_hi);
1785 /* a -> b, b -> d */
1786 emit_mov(node, in_hi, out_hi);
1787 emit_mov(node, in_lo, out_lo);
1791 if (out_hi == in_lo) {
1792 /* a -> c, b -> a */
1793 emit_mov(node, in_lo, out_lo);
1795 } else if (out_hi == in_hi) {
1796 /* a -> c, b -> b */
1797 emit_mov(node, in_lo, out_lo);
1800 /* a -> c, b -> d */
1801 emit_mov(node, in_lo, out_lo);
1807 emit_neg( node, out_hi);
1808 emit_neg( node, out_lo);
1809 emit_sbb0(node, out_hi);
1813 emit_zero(node, out_hi);
1814 emit_neg( node, out_lo);
1815 emit_sbb( node, in_hi, out_hi);
1818 static void emit_ia32_GetEIP(const ir_node *node)
1820 be_emit_cstring("\tcall ");
1821 be_emit_string(pic_base_label);
1822 be_emit_finish_line_gas(node);
1824 be_emit_string(pic_base_label);
1825 be_emit_cstring(":\n");
1826 be_emit_write_line();
1828 be_emit_cstring("\tpopl ");
1829 ia32_emit_dest_register(node, 0);
1831 be_emit_write_line();
1834 static void emit_be_Return(const ir_node *node)
1837 be_emit_cstring("\tret");
1839 pop = be_Return_get_pop(node);
1840 if (pop > 0 || be_Return_get_emit_pop(node)) {
1841 be_emit_irprintf(" $%d", pop);
1843 be_emit_finish_line_gas(node);
1846 static void emit_Nothing(const ir_node *node)
1852 /***********************************************************************************
1855 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1856 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1857 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1858 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1860 ***********************************************************************************/
1863 * Enters the emitter functions for handled nodes into the generic
1864 * pointer of an opcode.
1866 static void ia32_register_emitters(void)
1868 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1869 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1870 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1871 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1872 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1873 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1875 /* first clear the generic function pointer for all ops */
1876 clear_irp_opcodes_generic_func();
1878 /* register all emitter functions defined in spec */
1879 ia32_register_spec_emitters();
1881 /* other ia32 emitter functions */
1885 IA32_EMIT(SwitchJmp);
1888 IA32_EMIT(Conv_I2FP);
1889 IA32_EMIT(Conv_FP2I);
1890 IA32_EMIT(Conv_FP2FP);
1891 IA32_EMIT(Conv_I2I);
1892 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1895 IA32_EMIT(Minus64Bit);
1899 /* benode emitter */
1924 typedef void (*emit_func_ptr) (const ir_node *);
1927 * Emits code for a node.
1929 static void ia32_emit_node(ir_node *node)
1931 ir_op *op = get_irn_op(node);
1933 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1935 if (is_ia32_irn(node) && get_ia32_exc_label(node)) {
1936 /* emit the exception label of this instruction */
1937 ia32_assign_exc_label(node);
1939 if (op->ops.generic) {
1940 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1942 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1947 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1953 * Emits gas alignment directives
1955 static void ia32_emit_alignment(unsigned align, unsigned skip)
1957 be_emit_cstring("\t.p2align ");
1958 be_emit_irprintf("%u,,%u\n", align, skip);
1959 be_emit_write_line();
1963 * Emits gas alignment directives for Labels depended on cpu architecture.
1965 static void ia32_emit_align_label(void)
1967 unsigned align = ia32_cg_config.label_alignment;
1968 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1969 ia32_emit_alignment(align, maximum_skip);
1973 * Test whether a block should be aligned.
1974 * For cpus in the P4/Athlon class it is useful to align jump labels to
1975 * 16 bytes. However we should only do that if the alignment nops before the
1976 * label aren't executed more often than we have jumps to the label.
1978 static int should_align_block(const ir_node *block)
1980 static const double DELTA = .0001;
1981 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1982 ir_node *prev = get_prev_block_sched(block);
1984 double prev_freq = 0; /**< execfreq of the fallthrough block */
1985 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1988 if (exec_freq == NULL)
1990 if (ia32_cg_config.label_alignment_factor <= 0)
1993 block_freq = get_block_execfreq(exec_freq, block);
1994 if (block_freq < DELTA)
1997 n_cfgpreds = get_Block_n_cfgpreds(block);
1998 for(i = 0; i < n_cfgpreds; ++i) {
1999 const ir_node *pred = get_Block_cfgpred_block(block, i);
2000 double pred_freq = get_block_execfreq(exec_freq, pred);
2003 prev_freq += pred_freq;
2005 jmp_freq += pred_freq;
2009 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2012 jmp_freq /= prev_freq;
2014 return jmp_freq > ia32_cg_config.label_alignment_factor;
2018 * Emit the block header for a block.
2020 * @param block the block
2021 * @param prev_block the previous block
2023 static void ia32_emit_block_header(ir_node *block)
2025 ir_graph *irg = current_ir_graph;
2026 int need_label = block_needs_label(block);
2028 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2030 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2033 if (ia32_cg_config.label_alignment > 0) {
2034 /* align the current block if:
2035 * a) if should be aligned due to its execution frequency
2036 * b) there is no fall-through here
2038 if (should_align_block(block)) {
2039 ia32_emit_align_label();
2041 /* if the predecessor block has no fall-through,
2042 we can always align the label. */
2044 int has_fallthrough = 0;
2046 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2047 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2048 if (can_be_fallthrough(cfg_pred)) {
2049 has_fallthrough = 1;
2054 if (!has_fallthrough)
2055 ia32_emit_align_label();
2059 if (need_label || has_Block_label(block)) {
2060 ia32_emit_block_name(block);
2063 be_emit_pad_comment();
2064 be_emit_cstring(" /* ");
2066 be_emit_cstring("\t/* ");
2067 ia32_emit_block_name(block);
2068 be_emit_cstring(": ");
2071 be_emit_cstring("preds:");
2073 /* emit list of pred blocks in comment */
2074 arity = get_irn_arity(block);
2075 for (i = 0; i < arity; ++i) {
2076 ir_node *predblock = get_Block_cfgpred_block(block, i);
2077 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2079 if (exec_freq != NULL) {
2080 be_emit_irprintf(" freq: %f",
2081 get_block_execfreq(exec_freq, block));
2083 be_emit_cstring(" */\n");
2084 be_emit_write_line();
2088 * Walks over the nodes in a block connected by scheduling edges
2089 * and emits code for each node.
2091 static void ia32_gen_block(ir_node *block)
2095 ia32_emit_block_header(block);
2097 /* emit the contents of the block */
2098 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2099 sched_foreach(block, node) {
2100 ia32_emit_node(node);
2104 typedef struct exc_entry {
2105 ir_node *exc_instr; /** The instruction that can issue an exception. */
2106 ir_node *block; /** The block to call then. */
2111 * Sets labels for control flow nodes (jump target).
2112 * Links control predecessors to there destination blocks.
2114 static void ia32_gen_labels(ir_node *block, void *data)
2116 exc_entry **exc_list = data;
2120 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2121 pred = get_Block_cfgpred(block, n);
2122 set_irn_link(pred, block);
2124 pred = skip_Proj(pred);
2125 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2130 ARR_APP1(exc_entry, *exc_list, e);
2131 set_irn_link(pred, block);
2137 * Assign and emit an exception label if the current instruction can fail.
2139 void ia32_assign_exc_label(ir_node *node)
2141 if (get_ia32_exc_label(node)) {
2142 /* assign a new ID to the instruction */
2143 set_ia32_exc_label_id(node, ++exc_label_id);
2145 ia32_emit_exc_label(node);
2147 be_emit_pad_comment();
2148 be_emit_cstring("/* exception to Block ");
2149 ia32_emit_cfop_target(node);
2150 be_emit_cstring(" */\n");
2151 be_emit_write_line();
2156 * Compare two exception_entries.
2158 static int cmp_exc_entry(const void *a, const void *b)
2160 const exc_entry *ea = a;
2161 const exc_entry *eb = b;
2163 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2169 * Main driver. Emits the code for one routine.
2171 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2173 ir_entity *entity = get_irg_entity(irg);
2174 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2178 isa = (const ia32_isa_t*) cg->arch_env;
2179 arch_env = cg->arch_env;
2180 do_pic = cg->birg->main_env->options->pic;
2182 ia32_register_emitters();
2184 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2186 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2187 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2189 /* we use links to point to target blocks */
2190 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2191 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2193 /* initialize next block links */
2194 n = ARR_LEN(cg->blk_sched);
2195 for (i = 0; i < n; ++i) {
2196 ir_node *block = cg->blk_sched[i];
2197 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2199 set_irn_link(block, prev);
2202 for (i = 0; i < n; ++i) {
2203 ir_node *block = cg->blk_sched[i];
2205 ia32_gen_block(block);
2208 be_gas_emit_function_epilog(entity);
2209 be_dbg_method_end();
2211 be_emit_write_line();
2213 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2215 /* Sort the exception table using the exception label id's.
2216 Those are ascending with ascending addresses. */
2217 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2221 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2222 be_emit_cstring("\t.long ");
2223 ia32_emit_exc_label(exc_list[i].exc_instr);
2225 be_emit_cstring("\t.long ");
2226 ia32_emit_block_name(exc_list[i].block);
2230 DEL_ARR_F(exc_list);
2233 void ia32_init_emitter(void)
2235 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");