2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
26 #include "../be_dbgout.h"
28 #include "ia32_emitter.h"
29 #include "gen_ia32_emitter.h"
30 #include "gen_ia32_regalloc_if.h"
31 #include "ia32_nodes_attr.h"
32 #include "ia32_new_nodes.h"
33 #include "ia32_map_regs.h"
34 #include "bearch_ia32_t.h"
36 #define BLOCK_PREFIX(x) ".L" x
38 #define SNPRINTF_BUF_LEN 128
40 /* global arch_env for lc_printf functions */
41 static const arch_env_t *arch_env = NULL;
43 /** by default, we generate assembler code for the Linux gas */
44 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
47 * Switch to a new section
49 void ia32_switch_section(FILE *F, section_t sec) {
50 static section_t curr_sec = NO_SECTION;
51 static const char *text[ASM_MAX][SECTION_MAX] = {
57 ".section\t.tbss,\"awT\",@nobits",
58 ".section\t.ctors,\"aw\",@progbits"
63 ".section .rdata,\"dr\"",
65 ".section\t.tbss,\"awT\",@nobits",
66 ".section\t.ctors,\"aw\",@progbits"
85 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
93 static void ia32_dump_function_object(FILE *F, const char *name)
95 switch (asm_flavour) {
97 fprintf(F, "\t.type\t%s, @function\n", name);
100 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
107 static void ia32_dump_function_size(FILE *F, const char *name)
109 switch (asm_flavour) {
111 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
118 /*************************************************************
120 * (_) | | / _| | | | |
121 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
122 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
123 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
124 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
127 *************************************************************/
129 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
131 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
132 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
133 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
137 * returns true if a node has x87 registers
139 static INLINE int has_x87_register(const ir_node *n) {
140 return is_irn_machine_user(n, 0);
143 /* We always pass the ir_node which is a pointer. */
144 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
145 return lc_arg_type_ptr;
150 * Returns the register at in position pos.
152 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
154 const arch_register_t *reg = NULL;
156 assert(get_irn_arity(irn) > pos && "Invalid IN position");
158 /* The out register of the operator at position pos is the
159 in register we need. */
160 op = get_irn_n(irn, pos);
162 reg = arch_get_irn_register(arch_env, op);
164 assert(reg && "no in register found");
166 /* in case of unknown: just return a register */
167 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
168 reg = &ia32_gp_regs[REG_EAX];
169 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
170 reg = &ia32_xmm_regs[REG_XMM0];
171 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
172 reg = &ia32_vfp_regs[REG_VF0];
178 * Returns the register at out position pos.
180 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
182 const arch_register_t *reg = NULL;
184 /* 1st case: irn is not of mode_T, so it has only */
185 /* one OUT register -> good */
186 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
187 /* Proj with the corresponding projnum for the register */
189 if (get_irn_mode(irn) != mode_T) {
190 reg = arch_get_irn_register(arch_env, irn);
192 else if (is_ia32_irn(irn)) {
193 reg = get_ia32_out_reg(irn, pos);
196 const ir_edge_t *edge;
198 foreach_out_edge(irn, edge) {
199 proj = get_edge_src_irn(edge);
200 assert(is_Proj(proj) && "non-Proj from mode_T node");
201 if (get_Proj_proj(proj) == pos) {
202 reg = arch_get_irn_register(arch_env, proj);
208 assert(reg && "no out register found");
218 * Returns the name of the in register at position pos.
220 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
221 const arch_register_t *reg;
223 if (in_out == IN_REG) {
224 reg = get_in_reg(irn, pos);
226 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
227 /* FIXME: works for binop only */
228 assert(2 <= pos && pos <= 3);
229 reg = get_ia32_attr(irn)->x87[pos - 2];
233 /* destination address mode nodes don't have outputs */
234 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
238 reg = get_out_reg(irn, pos);
239 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
240 reg = get_ia32_attr(irn)->x87[pos + 2];
242 return arch_register_get_name(reg);
246 * Get the register name for a node.
248 static int ia32_get_reg_name(lc_appendable_t *app,
249 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
252 ir_node *irn = arg->v_ptr;
253 int nr = occ->width - 1;
256 return lc_appendable_snadd(app, "(null)", 6);
258 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
260 /* append the stupid % to register names */
261 lc_appendable_chadd(app, '%');
262 return lc_appendable_snadd(app, buf, strlen(buf));
266 * Get the x87 register name for a node.
268 static int ia32_get_x87_name(lc_appendable_t *app,
269 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
272 ir_node *irn = arg->v_ptr;
273 int nr = occ->width - 1;
277 return lc_appendable_snadd(app, "(null)", 6);
279 attr = get_ia32_attr(irn);
280 buf = attr->x87[nr]->name;
281 lc_appendable_chadd(app, '%');
282 return lc_appendable_snadd(app, buf, strlen(buf));
286 * Returns the tarval, offset or scale of an ia32 as a string.
288 static int ia32_const_to_str(lc_appendable_t *app,
289 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
292 ir_node *irn = arg->v_ptr;
295 return lc_arg_append(app, occ, "(null)", 6);
297 if (occ->conversion == 'C') {
298 buf = get_ia32_cnst(irn);
301 buf = get_ia32_am_offs(irn);
304 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
308 * Determines the SSE suffix depending on the mode.
310 static int ia32_get_mode_suffix(lc_appendable_t *app,
311 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
313 ir_node *irn = arg->v_ptr;
314 ir_mode *mode = get_irn_mode(irn);
316 if (mode == mode_T) {
317 mode = get_ia32_res_mode(irn);
319 mode = get_ia32_ls_mode(irn);
323 return lc_arg_append(app, occ, "(null)", 6);
325 if (mode_is_float(mode)) {
326 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
329 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
334 * Return the ia32 printf arg environment.
335 * We use the firm environment with some additional handlers.
337 const lc_arg_env_t *ia32_get_arg_env(void) {
338 static lc_arg_env_t *env = NULL;
340 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
341 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
342 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
343 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
346 /* extend the firm printer */
347 env = firm_get_arg_env();
349 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
350 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
351 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
352 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
353 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
354 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
360 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
361 switch(get_mode_size_bits(mode)) {
363 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
365 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
367 return (char *)arch_register_get_name(reg);
372 * Emits registers and/or address mode of a binary operation.
374 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
375 static char *buf = NULL;
377 /* verify that this function is never called on non-AM supporting operations */
378 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
380 #define PRODUCES_RESULT(n) \
381 (!(is_ia32_St(n) || \
382 is_ia32_Store8Bit(n) || \
383 is_ia32_CondJmp(n) || \
384 is_ia32_xCondJmp(n) || \
385 is_ia32_CmpSet(n) || \
386 is_ia32_xCmpSet(n) || \
387 is_ia32_SwitchJmp(n)))
390 buf = xcalloc(1, SNPRINTF_BUF_LEN);
393 memset(buf, 0, SNPRINTF_BUF_LEN);
396 switch(get_ia32_op_type(n)) {
398 if (is_ia32_ImmConst(n)) {
399 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
401 else if (is_ia32_ImmSymConst(n)) {
402 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
405 const arch_register_t *in1 = get_in_reg(n, 2);
406 const arch_register_t *in2 = get_in_reg(n, 3);
407 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
408 const arch_register_t *in;
411 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
412 out = out ? out : in1;
413 in_name = arch_register_get_name(in);
415 if (is_ia32_emit_cl(n)) {
416 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
420 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
424 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
425 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
426 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
429 if (PRODUCES_RESULT(n)) {
430 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
433 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
438 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
439 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
440 ia32_emit_am(n, env),
441 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
442 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
445 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
446 ir_mode *mode = get_ia32_res_mode(n);
449 mode = mode ? mode : get_ia32_ls_mode(n);
450 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
452 if (is_ia32_emit_cl(n)) {
453 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
457 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
461 assert(0 && "unsupported op type");
464 #undef PRODUCES_RESULT
470 * Returns the xxx PTR string for a given mode
472 * @param mode the mode
473 * @param x87_insn if non-zero returns the string for a x87 instruction
474 * else for a SSE instruction
476 static const char *pointer_size(ir_mode *mode, int x87_insn)
479 switch (get_mode_size_bits(mode)) {
480 case 8: return "BYTE PTR";
481 case 16: return "WORD PTR";
482 case 32: return "DWORD PTR";
488 case 96: return "XWORD PTR";
489 default: return NULL;
496 * Emits registers and/or address mode of a binary operation.
498 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
499 static char *buf = NULL;
501 /* verify that this function is never called on non-AM supporting operations */
502 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
505 buf = xcalloc(1, SNPRINTF_BUF_LEN);
508 memset(buf, 0, SNPRINTF_BUF_LEN);
511 switch(get_ia32_op_type(n)) {
513 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
514 ir_mode *mode = get_ia32_ls_mode(n);
515 const char *p = pointer_size(mode, 1);
516 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
519 ia32_attr_t *attr = get_ia32_attr(n);
520 const arch_register_t *in1 = attr->x87[0];
521 const arch_register_t *in2 = attr->x87[1];
522 const arch_register_t *out = attr->x87[2];
523 const arch_register_t *in;
526 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
527 out = out ? out : in1;
528 in_name = arch_register_get_name(in);
530 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
535 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
538 assert(0 && "unsupported op type");
545 * Emits registers and/or address mode of a unary operation.
547 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
548 static char *buf = NULL;
551 buf = xcalloc(1, SNPRINTF_BUF_LEN);
554 memset(buf, 0, SNPRINTF_BUF_LEN);
557 switch(get_ia32_op_type(n)) {
559 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
560 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
563 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
564 /* MulS and Mulh implicitly multiply by EAX */
565 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
568 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
572 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
576 Mulh is emitted via emit_unop
577 imul [MEM] means EDX:EAX <- EAX * [MEM]
579 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
580 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
583 assert(0 && "unsupported op type");
590 * Emits address mode.
592 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
593 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
597 static struct obstack *obst = NULL;
598 ir_mode *mode = get_ia32_ls_mode(n);
600 if (! is_ia32_Lea(n))
601 assert(mode && "AM node must have ls_mode attribute set.");
604 obst = xcalloc(1, sizeof(*obst));
607 obstack_free(obst, NULL);
610 /* obstack_free with NULL results in an uninitialized obstack */
613 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
615 obstack_printf(obst, "%s ", p);
617 /* emit address mode symconst */
618 if (get_ia32_am_sc(n)) {
619 if (is_ia32_am_sc_sign(n))
620 obstack_printf(obst, "-");
621 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
624 if (am_flav & ia32_B) {
625 obstack_printf(obst, "[");
626 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
630 if (am_flav & ia32_I) {
632 obstack_printf(obst, "+");
635 obstack_printf(obst, "[");
638 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
640 if (am_flav & ia32_S) {
641 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
647 if (am_flav & ia32_O) {
648 s = get_ia32_am_offs(n);
651 /* omit explicit + if there was no base or index */
653 obstack_printf(obst, "[");
658 obstack_printf(obst, s);
664 obstack_printf(obst, "] ");
666 obstack_1grow(obst, '\0');
667 s = obstack_finish(obst);
675 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
677 static char buf[SNPRINTF_BUF_LEN];
678 ir_mode *mode = get_ia32_ls_mode(irn);
679 const char *adr = get_ia32_cnst(irn);
680 const char *pref = pointer_size(mode, has_x87_register(irn));
682 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
687 * Formated print of commands and comments.
689 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
691 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
694 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
696 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
702 * Add a number to a prefix. This number will not be used a second time.
704 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
705 static unsigned long id = 0;
706 snprintf(buf, buflen, "%s%lu", prefix, ++id);
712 /*************************************************
715 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
716 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
717 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
718 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
720 *************************************************/
723 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
726 * coding of conditions
728 struct cmp2conditon_t {
734 * positive conditions for signed compares
736 static const struct cmp2conditon_t cmp2condition_s[] = {
737 { NULL, pn_Cmp_False }, /* always false */
738 { "e", pn_Cmp_Eq }, /* == */
739 { "l", pn_Cmp_Lt }, /* < */
740 { "le", pn_Cmp_Le }, /* <= */
741 { "g", pn_Cmp_Gt }, /* > */
742 { "ge", pn_Cmp_Ge }, /* >= */
743 { "ne", pn_Cmp_Lg }, /* != */
744 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
745 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
746 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
747 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
748 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
749 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
750 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
751 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
752 { NULL, pn_Cmp_True }, /* always true */
756 * positive conditions for unsigned compares
758 static const struct cmp2conditon_t cmp2condition_u[] = {
759 { NULL, pn_Cmp_False }, /* always false */
760 { "e", pn_Cmp_Eq }, /* == */
761 { "b", pn_Cmp_Lt }, /* < */
762 { "be", pn_Cmp_Le }, /* <= */
763 { "a", pn_Cmp_Gt }, /* > */
764 { "ae", pn_Cmp_Ge }, /* >= */
765 { "ne", pn_Cmp_Lg }, /* != */
766 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
767 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
768 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
769 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
770 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
771 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
772 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
773 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
774 { NULL, pn_Cmp_True }, /* always true */
778 * returns the condition code
780 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
782 assert(cmp2condition_s[cmp_code].num == cmp_code);
783 assert(cmp2condition_u[cmp_code].num == cmp_code);
785 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
789 * Returns the target block for a control flow node.
791 static ir_node *get_cfop_target_block(const ir_node *irn) {
792 return get_irn_link(irn);
796 * Returns the target label for a control flow node.
798 static char *get_cfop_target(const ir_node *irn, char *buf) {
799 ir_node *bl = get_cfop_target_block(irn);
801 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
805 /** Return the next block in Block schedule */
806 static ir_node *next_blk_sched(const ir_node *block) {
807 return get_irn_link(block);
811 * Returns the Proj with projection number proj and NOT mode_M
813 static ir_node *get_proj(const ir_node *irn, long proj) {
814 const ir_edge_t *edge;
817 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
819 foreach_out_edge(irn, edge) {
820 src = get_edge_src_irn(edge);
822 assert(is_Proj(src) && "Proj expected");
823 if (get_irn_mode(src) == mode_M)
826 if (get_Proj_proj(src) == proj)
833 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
835 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
836 const ir_node *proj_true;
837 const ir_node *proj_false;
838 const ir_node *block;
839 const ir_node *next_block;
840 char buf[SNPRINTF_BUF_LEN];
841 char cmd_buf[SNPRINTF_BUF_LEN];
842 char cmnt_buf[SNPRINTF_BUF_LEN];
847 /* get both Proj's */
848 proj_true = get_proj(irn, pn_Cond_true);
849 assert(proj_true && "CondJmp without true Proj");
851 proj_false = get_proj(irn, pn_Cond_false);
852 assert(proj_false && "CondJmp without false Proj");
854 pnc = get_ia32_pncode(irn);
856 /* for now, the code works for scheduled and non-schedules blocks */
857 block = get_nodes_block(irn);
859 /* we have a block schedule */
860 next_block = next_blk_sched(block);
862 if (get_cfop_target_block(proj_true) == next_block) {
863 /* exchange both proj's so the second one can be omitted */
864 const ir_node *t = proj_true;
865 proj_true = proj_false;
869 pnc = get_negated_pnc(pnc, mode);
872 /* the first Proj must always be created */
873 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
874 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
875 get_cmp_suffix(pnc, is_unsigned),
876 get_cfop_target(proj_true, buf));
877 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
878 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
881 /* the second Proj might be a fallthrough */
882 if (get_cfop_target_block(proj_false) != next_block) {
883 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
884 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
888 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
894 * Emits code for conditional jump.
896 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
898 char cmd_buf[SNPRINTF_BUF_LEN];
899 char cmnt_buf[SNPRINTF_BUF_LEN];
901 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
902 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
904 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
908 * Emits code for conditional jump with two variables.
910 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
911 CondJmp_emitter(irn, env);
915 * Emits code for conditional test and jump.
917 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
919 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
922 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
923 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
924 char cmd_buf[SNPRINTF_BUF_LEN];
925 char cmnt_buf[SNPRINTF_BUF_LEN];
928 op2 = arch_register_get_name(get_in_reg(irn, 1));
930 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
931 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
934 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
940 * Emits code for conditional test and jump with two variables.
942 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
943 TestJmp_emitter(irn, env);
946 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
948 char cmd_buf[SNPRINTF_BUF_LEN];
949 char cmnt_buf[SNPRINTF_BUF_LEN];
951 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
952 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
954 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
957 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
959 char cmd_buf[SNPRINTF_BUF_LEN];
960 char cmnt_buf[SNPRINTF_BUF_LEN];
962 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
963 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
965 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
969 * Emits code for conditional SSE floating point jump with two variables.
971 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
973 char cmd_buf[SNPRINTF_BUF_LEN];
974 char cmnt_buf[SNPRINTF_BUF_LEN];
976 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
977 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
979 finish_CondJmp(F, irn, mode_F);
984 * Emits code for conditional x87 floating point jump with two variables.
986 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
988 char cmd_buf[SNPRINTF_BUF_LEN];
989 char cmnt_buf[SNPRINTF_BUF_LEN];
990 ia32_attr_t *attr = get_ia32_attr(irn);
991 const char *reg = attr->x87[1]->name;
992 const char *instr = "fcom";
995 switch (get_ia32_irn_opcode(irn)) {
996 case iro_ia32_fcomrJmp:
998 case iro_ia32_fcomJmp:
1002 case iro_ia32_fcomrpJmp:
1004 case iro_ia32_fcompJmp:
1007 case iro_ia32_fcomrppJmp:
1009 case iro_ia32_fcomppJmp:
1016 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1018 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1019 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1021 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1022 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1024 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1025 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1028 /* the compare flags must be evaluated using carry , ie unsigned */
1029 finish_CondJmp(F, irn, mode_Iu);
1032 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1034 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1035 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1036 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1037 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1038 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1039 int idx_left = 2 - is_PsiCondCMov;
1040 int idx_right = 3 - is_PsiCondCMov;
1042 char cmd_buf[SNPRINTF_BUF_LEN];
1043 char cmnt_buf[SNPRINTF_BUF_LEN];
1044 const arch_register_t *in1, *in2, *out;
1046 out = arch_get_irn_register(env->arch_env, irn);
1047 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1048 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1050 /* we have to emit the cmp first, because the destination register */
1051 /* could be one of the compare registers */
1052 if (is_ia32_CmpCMov(irn)) {
1053 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1055 else if (is_ia32_xCmpCMov(irn)) {
1056 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1058 else if (is_PsiCondCMov) {
1059 /* omit compare because flags are already set by And/Or */
1060 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1063 assert(0 && "unsupported CMov");
1065 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1068 if (REGS_ARE_EQUAL(out, in2)) {
1069 /* best case: default in == out -> do nothing */
1071 else if (REGS_ARE_EQUAL(out, in1)) {
1072 /* true in == out -> need complement compare and exchange true and default in */
1073 ir_node *t = get_irn_n(irn, idx_left);
1074 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1075 set_irn_n(irn, idx_right, t);
1077 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1081 /* out is different from in: need copy default -> out */
1083 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1085 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1087 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1092 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1094 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1096 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1100 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1101 CMov_emitter(irn, env);
1104 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1105 CMov_emitter(irn, env);
1108 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1109 CMov_emitter(irn, env);
1112 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1114 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1115 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1116 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1117 const char *reg8bit;
1119 char cmd_buf[SNPRINTF_BUF_LEN];
1120 char cmnt_buf[SNPRINTF_BUF_LEN];
1121 const arch_register_t *out;
1123 out = arch_get_irn_register(env->arch_env, irn);
1124 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1126 if (is_ia32_CmpSet(irn)) {
1127 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1129 else if (is_ia32_xCmpSet(irn)) {
1130 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1132 else if (is_ia32_PsiCondSet(irn)) {
1133 /* omit compare because flags are already set by And/Or */
1134 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1137 assert(0 && "unsupported Set");
1139 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1142 /* use mov to clear target because it doesn't affect the eflags */
1143 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1144 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1147 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1148 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1152 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1153 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1156 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1157 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1160 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1161 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1164 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1166 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1168 long pnc = get_ia32_pncode(irn);
1169 long unord = pnc & pn_Cmp_Uo;
1170 char cmd_buf[SNPRINTF_BUF_LEN];
1171 char cmnt_buf[SNPRINTF_BUF_LEN];
1174 case pn_Cmp_Leg: /* odered */
1177 case pn_Cmp_Uo: /* unordered */
1181 case pn_Cmp_Eq: /* == */
1185 case pn_Cmp_Lt: /* < */
1189 case pn_Cmp_Le: /* <= */
1193 case pn_Cmp_Gt: /* > */
1197 case pn_Cmp_Ge: /* >= */
1201 case pn_Cmp_Lg: /* != */
1206 assert(sse_pnc >= 0 && "unsupported compare");
1208 if (unord && sse_pnc != 3) {
1210 We need a separate compare against unordered.
1211 Quick and Dirty solution:
1212 - get some memory on stack
1216 - and result and stored result
1219 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1220 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1222 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1223 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1225 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1226 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1230 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1231 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1234 if (unord && sse_pnc != 3) {
1235 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1236 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1238 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1239 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1244 /*********************************************************
1247 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1248 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1249 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1250 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1253 *********************************************************/
1255 /* jump table entry (target and corresponding number) */
1256 typedef struct _branch_t {
1261 /* jump table for switch generation */
1262 typedef struct _jmp_tbl_t {
1263 ir_node *defProj; /**< default target */
1264 int min_value; /**< smallest switch case */
1265 int max_value; /**< largest switch case */
1266 int num_branches; /**< number of jumps */
1267 char *label; /**< label of the jump table */
1268 branch_t *branches; /**< jump array */
1272 * Compare two variables of type branch_t. Used to sort all switch cases
1274 static int ia32_cmp_branch_t(const void *a, const void *b) {
1275 branch_t *b1 = (branch_t *)a;
1276 branch_t *b2 = (branch_t *)b;
1278 if (b1->value <= b2->value)
1285 * Emits code for a SwitchJmp (creates a jump table if
1286 * possible otherwise a cmp-jmp cascade). Port from
1289 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1290 unsigned long interval;
1291 char buf[SNPRINTF_BUF_LEN];
1292 int last_value, i, pn;
1295 const ir_edge_t *edge;
1296 const lc_arg_env_t *env = ia32_get_arg_env();
1297 FILE *F = emit_env->out;
1298 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1300 /* fill the table structure */
1301 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1302 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1304 tbl.num_branches = get_irn_n_edges(irn);
1305 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1306 tbl.min_value = INT_MAX;
1307 tbl.max_value = INT_MIN;
1310 /* go over all proj's and collect them */
1311 foreach_out_edge(irn, edge) {
1312 proj = get_edge_src_irn(edge);
1313 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1315 pn = get_Proj_proj(proj);
1317 /* create branch entry */
1318 tbl.branches[i].target = proj;
1319 tbl.branches[i].value = pn;
1321 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1322 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1324 /* check for default proj */
1325 if (pn == get_ia32_pncode(irn)) {
1326 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1333 /* sort the branches by their number */
1334 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1336 /* two-complement's magic make this work without overflow */
1337 interval = tbl.max_value - tbl.min_value;
1339 /* emit the table */
1340 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1341 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1344 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1345 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1348 if (tbl.num_branches > 1) {
1351 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1352 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1355 ia32_switch_section(F, SECTION_RODATA);
1356 fprintf(F, "\t.align 4\n");
1358 fprintf(F, "%s:\n", tbl.label);
1360 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1361 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1364 last_value = tbl.branches[0].value;
1365 for (i = 1; i < tbl.num_branches; ++i) {
1366 while (++last_value < tbl.branches[i].value) {
1367 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1368 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1371 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1372 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1375 ia32_switch_section(F, SECTION_TEXT);
1378 /* one jump is enough */
1379 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1380 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1391 * Emits code for a unconditional jump.
1393 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1394 ir_node *block, *next_bl;
1396 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1398 /* for now, the code works for scheduled and non-schedules blocks */
1399 block = get_nodes_block(irn);
1401 /* we have a block schedule */
1402 next_bl = next_blk_sched(block);
1403 if (get_cfop_target_block(irn) != next_bl) {
1404 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1405 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1409 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1414 /****************************
1417 * _ __ _ __ ___ _ ___
1418 * | '_ \| '__/ _ \| |/ __|
1419 * | |_) | | | (_) | |\__ \
1420 * | .__/|_| \___/| ||___/
1423 ****************************/
1426 * Emits code for a proj -> node
1428 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1429 ir_node *pred = get_Proj_pred(irn);
1431 if (get_irn_op(pred) == op_Start) {
1432 switch(get_Proj_proj(irn)) {
1433 case pn_Start_X_initial_exec:
1442 /**********************************
1445 * | | ___ _ __ _ _| |_) |
1446 * | | / _ \| '_ \| | | | _ <
1447 * | |___| (_) | |_) | |_| | |_) |
1448 * \_____\___/| .__/ \__, |____/
1451 **********************************/
1454 * Emit movsb/w instructions to make mov count divideable by 4
1456 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1457 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1459 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1461 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1462 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1467 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1468 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1472 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1473 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1477 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1478 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1480 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1481 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1489 * Emit rep movsd instruction for memcopy.
1491 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1492 FILE *F = emit_env->out;
1493 tarval *tv = get_ia32_Immop_tarval(irn);
1494 int rem = get_tarval_long(tv);
1495 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1497 emit_CopyB_prolog(F, irn, rem);
1499 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1500 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1505 * Emits unrolled memcopy.
1507 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1508 tarval *tv = get_ia32_Immop_tarval(irn);
1509 int size = get_tarval_long(tv);
1510 FILE *F = emit_env->out;
1511 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1513 emit_CopyB_prolog(F, irn, size & 0x3);
1517 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1518 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1525 /***************************
1529 * | | / _ \| '_ \ \ / /
1530 * | |___| (_) | | | \ V /
1531 * \_____\___/|_| |_|\_/
1533 ***************************/
1536 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1538 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1539 FILE *F = emit_env->out;
1540 const lc_arg_env_t *env = ia32_get_arg_env();
1541 ir_mode *src_mode = get_ia32_src_mode(irn);
1542 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1543 char *from, *to, buf[64];
1544 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1546 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1547 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1549 switch(get_ia32_op_type(irn)) {
1551 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1553 case ia32_AddrModeS:
1554 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1557 assert(0 && "unsupported op type for Conv");
1560 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1561 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1565 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1566 emit_ia32_Conv_with_FP(irn, emit_env);
1569 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1570 emit_ia32_Conv_with_FP(irn, emit_env);
1573 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1574 emit_ia32_Conv_with_FP(irn, emit_env);
1578 * Emits code for an Int conversion.
1580 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1581 FILE *F = emit_env->out;
1582 const lc_arg_env_t *env = ia32_get_arg_env();
1583 char *move_cmd = "movzx";
1584 char *conv_cmd = NULL;
1585 ir_mode *src_mode = get_ia32_src_mode(irn);
1586 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1588 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1589 const arch_register_t *in_reg, *out_reg;
1591 n = get_mode_size_bits(src_mode);
1592 m = get_mode_size_bits(tgt_mode);
1594 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1596 if (n == 8 || m == 8)
1598 else if (n == 16 || m == 16)
1601 printf("%d -> %d unsupported\n", n, m);
1602 assert(0 && "unsupported Conv_I2I");
1606 switch(get_ia32_op_type(irn)) {
1608 in_reg = get_in_reg(irn, 2);
1609 out_reg = get_out_reg(irn, 0);
1611 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1612 REGS_ARE_EQUAL(out_reg, in_reg) &&
1613 mode_is_signed(n < m ? src_mode : tgt_mode))
1615 /* argument and result are both in EAX and */
1616 /* signedness is ok: -> use converts */
1617 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1619 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1620 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1622 /* argument and result are in the same register */
1623 /* and signedness is ok: -> use and with mask */
1624 int mask = (1 << (n < m ? n : m)) - 1;
1625 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1628 /* use move w/o sign extension */
1629 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1630 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1634 case ia32_AddrModeS:
1635 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1636 move_cmd, irn, ia32_emit_am(irn, emit_env));
1639 assert(0 && "unsupported op type for Conv");
1642 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1643 irn, n, src_mode, m, tgt_mode);
1649 * Emits code for an 8Bit Int conversion.
1651 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1652 emit_ia32_Conv_I2I(irn, emit_env);
1656 /*******************************************
1659 * | |__ ___ _ __ ___ __| | ___ ___
1660 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1661 * | |_) | __/ | | | (_) | (_| | __/\__ \
1662 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1664 *******************************************/
1667 * Emits a backend call
1669 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1670 FILE *F = emit_env->out;
1671 entity *ent = be_Call_get_entity(irn);
1672 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1675 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1678 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1681 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1687 * Emits code to increase stack pointer.
1689 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1690 FILE *F = emit_env->out;
1691 int offs = be_get_IncSP_offset(irn);
1692 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1696 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1698 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1699 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1702 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1703 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1710 * Emits code to set stack pointer.
1712 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1713 FILE *F = emit_env->out;
1714 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1716 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1717 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1722 * Emits code for Copy/CopyKeep.
1724 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1725 FILE *F = emit_env->out;
1726 const arch_env_t *aenv = emit_env->arch_env;
1727 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1729 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1730 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1733 if (mode_is_float(get_irn_mode(irn)))
1734 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1736 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1737 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1741 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1742 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1745 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1746 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1750 * Emits code for exchange.
1752 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1753 FILE *F = emit_env->out;
1754 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1755 const arch_register_t *in1, *in2;
1756 const arch_register_class_t *cls1, *cls2;
1758 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1759 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1761 cls1 = arch_register_get_class(in1);
1762 cls2 = arch_register_get_class(in2);
1764 assert(cls1 == cls2 && "Register class mismatch at Perm");
1766 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1767 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1769 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1770 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1771 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1773 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1777 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1782 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1787 * Emits code for Constant loading.
1789 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1791 char cmd_buf[256], cmnt_buf[256];
1792 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1793 ir_mode *mode = get_irn_mode(n);
1794 tarval *tv = get_ia32_Immop_tarval(n);
1796 if (get_ia32_op_type(n) == ia32_SymConst) {
1797 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1798 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1800 assert(mode == get_tarval_mode(tv));
1801 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1802 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1803 const char *instr = "xor";
1804 if (env->isa->opt_arch == arch_pentium_4) {
1805 /* P4 prefers sub r, r, others xor r, r */
1808 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1809 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1811 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1812 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1815 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1819 * Emits code to increase stack pointer.
1821 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1822 FILE *F = emit_env->out;
1823 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1825 if (is_ia32_ImmConst(irn)) {
1826 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1828 else if (is_ia32_ImmSymConst(irn)) {
1829 if (get_ia32_op_type(irn) == ia32_Normal)
1830 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1831 else /* source address mode */
1832 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1835 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1837 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1843 * Emits code to increase stack pointer.
1845 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1846 FILE *F = emit_env->out;
1847 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1849 if (is_ia32_ImmConst(irn)) {
1850 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1852 else if (is_ia32_ImmSymConst(irn)) {
1853 if (get_ia32_op_type(irn) == ia32_Normal)
1854 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1855 else /* source address mode */
1856 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1859 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1861 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1867 * Emits code to load the TLS base
1869 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1870 FILE *F = emit_env->out;
1871 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1873 switch (asm_flavour) {
1875 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1878 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1881 assert(0 && "unsupported TLS");
1884 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1889 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1891 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1893 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1896 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1899 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1903 /***********************************************************************************
1906 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1907 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1908 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1909 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1911 ***********************************************************************************/
1914 * Enters the emitter functions for handled nodes into the generic
1915 * pointer of an opcode.
1917 static void ia32_register_emitters(void) {
1919 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1920 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1921 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1922 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1923 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1924 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1926 /* first clear the generic function pointer for all ops */
1927 clear_irp_opcodes_generic_func();
1929 /* register all emitter functions defined in spec */
1930 ia32_register_spec_emitters();
1932 /* other ia32 emitter functions */
1938 IA32_EMIT(PsiCondCMov);
1940 IA32_EMIT(PsiCondSet);
1941 IA32_EMIT(SwitchJmp);
1944 IA32_EMIT(Conv_I2FP);
1945 IA32_EMIT(Conv_FP2I);
1946 IA32_EMIT(Conv_FP2FP);
1947 IA32_EMIT(Conv_I2I);
1948 IA32_EMIT(Conv_I2I8Bit);
1955 IA32_EMIT(xCmpCMov);
1956 IA32_EMIT(xCondJmp);
1957 IA32_EMIT2(fcomJmp, x87CondJmp);
1958 IA32_EMIT2(fcompJmp, x87CondJmp);
1959 IA32_EMIT2(fcomppJmp, x87CondJmp);
1960 IA32_EMIT2(fcomrJmp, x87CondJmp);
1961 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1962 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1964 /* benode emitter */
1990 static unsigned last_line = -1;
1991 static const char *last_file = NULL;
1992 static unsigned num = -1;
1994 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
1995 dbg_info *db = get_irn_dbg_info(irn);
1997 const char *fname = be_retrieve_dbg_info(db, &lineno);
1999 if (fname && last_line != lineno) {
2003 snprintf(name, sizeof(name), ".Ld%u", ++num);
2005 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2006 fprintf(F, "%s:\n", name);
2011 * Emits code for a node.
2013 static void ia32_emit_node(const ir_node *irn, void *env) {
2014 ia32_emit_env_t *emit_env = env;
2015 ir_op *op = get_irn_op(irn);
2016 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2018 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2020 if (op->ops.generic) {
2021 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2022 ia32_emit_dbg(irn, emit_env);
2026 emit_Nothing(irn, env);
2027 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2032 * Emits gas alignment directives
2034 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2035 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2039 * Emits gas alignment directives for Functions depended on cpu architecture.
2041 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2042 unsigned align; unsigned maximum_skip;
2057 maximum_skip = (1 << align) - 1;
2058 ia32_emit_alignment(F, align, maximum_skip);
2062 * Emits gas alignment directives for Labels depended on cpu architecture.
2064 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2065 unsigned align; unsigned maximum_skip;
2080 maximum_skip = (1 << align) - 1;
2081 ia32_emit_alignment(F, align, maximum_skip);
2085 * Walks over the nodes in a block connected by scheduling edges
2086 * and emits code for each node.
2088 static void ia32_gen_block(ir_node *block, void *env) {
2089 ia32_emit_env_t *emit_env = env;
2091 int need_label = block != get_irg_start_block(get_irn_irg(block));
2092 FILE *F = emit_env->out;
2094 if (! is_Block(block))
2097 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2098 /* if the extended block scheduler is used, only leader blocks need
2100 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2104 char cmd_buf[SNPRINTF_BUF_LEN];
2107 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2109 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2110 get_irn_node_nr(block));
2111 fprintf(F, "%-43s ", cmd_buf);
2113 /* emit list of pred blocks in comment */
2114 fprintf(F, "/* preds:");
2116 arity = get_irn_arity(block);
2117 for(i = 0; i < arity; ++i) {
2118 ir_node *predblock = get_Block_cfgpred_block(block, i);
2119 fprintf(F, " %ld", get_irn_node_nr(predblock));
2121 fprintf(F, " */\n");
2124 /* emit the contents of the block */
2125 sched_foreach(block, irn) {
2126 ia32_emit_node(irn, env);
2131 * Emits code for function start.
2133 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2134 entity *irg_ent = get_irg_entity(irg);
2135 const char *irg_name = get_entity_ld_name(irg_ent);
2136 cpu_support cpu = emit_env->isa->opt_arch;
2139 ia32_switch_section(F, SECTION_TEXT);
2140 be_dbg_method(emit_env->cg->birg->main_env->db_handle, irg_ent);
2141 ia32_emit_align_func(F, cpu);
2142 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2143 fprintf(F, ".globl %s\n", irg_name);
2145 ia32_dump_function_object(F, irg_name);
2146 fprintf(F, "%s:\n", irg_name);
2150 * Emits code for function end
2152 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
2153 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2155 ia32_dump_function_size(F, irg_name);
2161 * Sets labels for control flow nodes (jump target)
2162 * TODO: Jump optimization
2164 static void ia32_gen_labels(ir_node *block, void *env) {
2166 int n = get_Block_n_cfgpreds(block);
2168 for (n--; n >= 0; n--) {
2169 pred = get_Block_cfgpred(block, n);
2170 set_irn_link(pred, block);
2175 * Main driver. Emits the code for one routine.
2177 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2178 ia32_emit_env_t emit_env;
2182 emit_env.arch_env = cg->arch_env;
2184 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2185 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2187 /* set the global arch_env (needed by print hooks) */
2188 arch_env = cg->arch_env;
2190 ia32_register_emitters();
2192 ia32_emit_func_prolog(F, irg, &emit_env);
2193 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2195 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2196 int i, n = ARR_LEN(cg->blk_sched);
2198 for (i = 0; i < n;) {
2201 block = cg->blk_sched[i];
2203 next_bl = i < n ? cg->blk_sched[i] : NULL;
2205 /* set here the link. the emitter expects to find the next block here */
2206 set_irn_link(block, next_bl);
2207 ia32_gen_block(block, &emit_env);
2211 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2212 in the block schedule. As this number should NEVER be equal the next block,
2213 we does not need a clear block link here. */
2214 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2217 ia32_emit_func_epilog(F, irg);