2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
76 static ir_label_t exc_label_id;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 static int is_fallthrough(const ir_node *cfgpred)
88 if (!is_Proj(cfgpred))
90 pred = get_Proj_pred(cfgpred);
91 if (is_ia32_SwitchJmp(pred))
97 static int block_needs_label(const ir_node *block)
100 int n_cfgpreds = get_Block_n_cfgpreds(block);
102 if (n_cfgpreds == 0) {
104 } else if (n_cfgpreds == 1) {
105 ir_node *cfgpred = get_Block_cfgpred(block, 0);
106 ir_node *cfgpred_block = get_nodes_block(cfgpred);
108 if (get_prev_block_sched(block) == cfgpred_block
109 && is_fallthrough(cfgpred)) {
118 * Returns the register at in position pos.
120 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
123 const arch_register_t *reg = NULL;
125 assert(get_irn_arity(irn) > pos && "Invalid IN position");
127 /* The out register of the operator at position pos is the
128 in register we need. */
129 op = get_irn_n(irn, pos);
131 reg = arch_get_irn_register(arch_env, op);
133 assert(reg && "no in register found");
135 if (reg == &ia32_gp_regs[REG_GP_NOREG])
136 panic("trying to emit noreg for %+F input %d", irn, pos);
138 /* in case of unknown register: just return a valid register */
139 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
140 const arch_register_req_t *req;
142 /* ask for the requirements */
143 req = arch_get_register_req(arch_env, irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(arch_env, irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = get_ia32_out_reg(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(arch_env, proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
214 static void emit_8bit_register(const arch_register_t *reg)
216 const char *reg_name = arch_register_get_name(reg);
219 be_emit_char(reg_name[1]);
223 static void emit_16bit_register(const arch_register_t *reg)
225 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
228 be_emit_string(reg_name);
231 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
233 const char *reg_name;
236 int size = get_mode_size_bits(mode);
238 case 8: emit_8bit_register(reg); return;
239 case 16: emit_16bit_register(reg); return;
241 assert(mode_is_float(mode) || size == 32);
244 reg_name = arch_register_get_name(reg);
247 be_emit_string(reg_name);
250 void ia32_emit_source_register(const ir_node *node, int pos)
252 const arch_register_t *reg = get_in_reg(node, pos);
254 emit_register(reg, NULL);
257 static void emit_ia32_Immediate(const ir_node *node);
259 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
261 const arch_register_t *reg;
262 ir_node *in = get_irn_n(node, pos);
263 if (is_ia32_Immediate(in)) {
264 emit_ia32_Immediate(in);
268 reg = get_in_reg(node, pos);
269 emit_8bit_register(reg);
272 void ia32_emit_dest_register(const ir_node *node, int pos)
274 const arch_register_t *reg = get_out_reg(node, pos);
276 emit_register(reg, NULL);
279 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
281 const arch_register_t *reg = get_out_reg(node, pos);
283 emit_register(reg, mode_Bu);
286 void ia32_emit_x87_register(const ir_node *node, int pos)
288 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
292 be_emit_string(attr->x87[pos]->name);
295 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
297 if (mode_is_float(mode)) {
298 switch(get_mode_size_bits(mode)) {
299 case 32: be_emit_char('s'); return;
300 case 64: be_emit_char('l'); return;
302 case 96: be_emit_char('t'); return;
305 assert(mode_is_int(mode) || mode_is_reference(mode));
306 switch(get_mode_size_bits(mode)) {
307 /* gas docu says q is the suffix but gcc, objdump and icc use ll
309 case 64: be_emit_cstring("ll"); return;
310 case 32: be_emit_char('l'); return;
311 case 16: be_emit_char('w'); return;
312 case 8: be_emit_char('b'); return;
315 panic("Can't output mode_suffix for %+F", mode);
318 void ia32_emit_mode_suffix(const ir_node *node)
320 ir_mode *mode = get_ia32_ls_mode(node);
324 ia32_emit_mode_suffix_mode(mode);
327 void ia32_emit_x87_mode_suffix(const ir_node *node)
329 /* we only need to emit the mode on address mode */
330 if (get_ia32_op_type(node) != ia32_Normal) {
331 ir_mode *mode = get_ia32_ls_mode(node);
332 assert(mode != NULL);
333 ia32_emit_mode_suffix_mode(mode);
337 static char get_xmm_mode_suffix(ir_mode *mode)
339 assert(mode_is_float(mode));
340 switch(get_mode_size_bits(mode)) {
343 default: panic("Invalid XMM mode");
347 void ia32_emit_xmm_mode_suffix(const ir_node *node)
349 ir_mode *mode = get_ia32_ls_mode(node);
350 assert(mode != NULL);
352 be_emit_char(get_xmm_mode_suffix(mode));
355 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
357 ir_mode *mode = get_ia32_ls_mode(node);
358 assert(mode != NULL);
359 be_emit_char(get_xmm_mode_suffix(mode));
362 void ia32_emit_extend_suffix(const ir_mode *mode)
364 if (get_mode_size_bits(mode) == 32)
366 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
369 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
371 ir_node *in = get_irn_n(node, pos);
372 if (is_ia32_Immediate(in)) {
373 emit_ia32_Immediate(in);
375 const ir_mode *mode = get_ia32_ls_mode(node);
376 const arch_register_t *reg = get_in_reg(node, pos);
377 emit_register(reg, mode);
382 * Emits registers and/or address mode of a binary operation.
384 void ia32_emit_binop(const ir_node *node)
386 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
387 const ir_mode *mode = get_ia32_ls_mode(node);
388 const arch_register_t *reg_left;
390 switch(get_ia32_op_type(node)) {
392 reg_left = get_in_reg(node, n_ia32_binary_left);
393 if (is_ia32_Immediate(right_op)) {
394 emit_ia32_Immediate(right_op);
395 be_emit_cstring(", ");
396 emit_register(reg_left, mode);
399 const arch_register_t *reg_right
400 = get_in_reg(node, n_ia32_binary_right);
401 emit_register(reg_right, mode);
402 be_emit_cstring(", ");
403 emit_register(reg_left, mode);
407 if (is_ia32_Immediate(right_op)) {
408 emit_ia32_Immediate(right_op);
409 be_emit_cstring(", ");
412 reg_left = get_in_reg(node, n_ia32_binary_left);
414 be_emit_cstring(", ");
415 emit_register(reg_left, mode);
419 panic("DestMode can't be output by %%binop anymore");
422 assert(0 && "unsupported op type");
427 * Emits registers and/or address mode of a binary operation.
429 void ia32_emit_x87_binop(const ir_node *node)
431 switch(get_ia32_op_type(node)) {
434 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
435 const arch_register_t *in1 = x87_attr->x87[0];
436 const arch_register_t *in2 = x87_attr->x87[1];
437 const arch_register_t *out = x87_attr->x87[2];
438 const arch_register_t *in;
440 in = out ? ((out == in2) ? in1 : in2) : in2;
441 out = out ? out : in1;
444 be_emit_string(arch_register_get_name(in));
445 be_emit_cstring(", %");
446 be_emit_string(arch_register_get_name(out));
454 assert(0 && "unsupported op type");
459 * Emits registers and/or address mode of a unary operation.
461 void ia32_emit_unop(const ir_node *node, int pos)
465 switch(get_ia32_op_type(node)) {
467 op = get_irn_n(node, pos);
468 if (is_ia32_Immediate(op)) {
469 emit_ia32_Immediate(op);
471 ia32_emit_source_register(node, pos);
479 assert(0 && "unsupported op type");
483 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
487 set_entity_backend_marked(entity, 1);
488 id = get_entity_ld_ident(entity);
491 if (get_entity_owner(entity) == get_tls_type()) {
492 if (get_entity_visibility(entity) == visibility_external_allocated) {
493 be_emit_cstring("@INDNTPOFF");
495 be_emit_cstring("@NTPOFF");
499 if (!no_pic_adjust && do_pic) {
500 /* TODO: only do this when necessary */
502 be_emit_string(pic_base_label);
507 * Emits address mode.
509 void ia32_emit_am(const ir_node *node)
511 ir_entity *ent = get_ia32_am_sc(node);
512 int offs = get_ia32_am_offs_int(node);
513 ir_node *base = get_irn_n(node, n_ia32_base);
514 int has_base = !is_ia32_NoReg_GP(base);
515 ir_node *index = get_irn_n(node, n_ia32_index);
516 int has_index = !is_ia32_NoReg_GP(index);
518 /* just to be sure... */
519 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
523 if (is_ia32_am_sc_sign(node))
525 ia32_emit_entity(ent, 0);
528 /* also handle special case if nothing is set */
529 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
531 be_emit_irprintf("%+d", offs);
533 be_emit_irprintf("%d", offs);
537 if (has_base || has_index) {
542 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
543 emit_register(reg, NULL);
546 /* emit index + scale */
548 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
551 emit_register(reg, NULL);
553 scale = get_ia32_am_scale(node);
555 be_emit_irprintf(",%d", 1 << scale);
562 static void emit_ia32_IMul(const ir_node *node)
564 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
565 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
567 be_emit_cstring("\timul");
568 ia32_emit_mode_suffix(node);
571 ia32_emit_binop(node);
573 /* do we need the 3-address form? */
574 if (is_ia32_NoReg_GP(left) ||
575 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
576 be_emit_cstring(", ");
577 emit_register(out_reg, get_ia32_ls_mode(node));
579 be_emit_finish_line_gas(node);
582 /*************************************************
585 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
586 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
587 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
588 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
590 *************************************************/
593 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
596 * coding of conditions
598 struct cmp2conditon_t {
604 * positive conditions for signed compares
606 static const struct cmp2conditon_t cmp2condition_s[] = {
607 { NULL, pn_Cmp_False }, /* always false */
608 { "e", pn_Cmp_Eq }, /* == */
609 { "l", pn_Cmp_Lt }, /* < */
610 { "le", pn_Cmp_Le }, /* <= */
611 { "g", pn_Cmp_Gt }, /* > */
612 { "ge", pn_Cmp_Ge }, /* >= */
613 { "ne", pn_Cmp_Lg }, /* != */
614 { NULL, pn_Cmp_Leg}, /* always true */
618 * positive conditions for unsigned compares
620 static const struct cmp2conditon_t cmp2condition_u[] = {
621 { NULL, pn_Cmp_False }, /* always false */
622 { "e", pn_Cmp_Eq }, /* == */
623 { "b", pn_Cmp_Lt }, /* < */
624 { "be", pn_Cmp_Le }, /* <= */
625 { "a", pn_Cmp_Gt }, /* > */
626 { "ae", pn_Cmp_Ge }, /* >= */
627 { "ne", pn_Cmp_Lg }, /* != */
628 { NULL, pn_Cmp_Leg }, /* always true */
632 * walks up a tree of copies/perms/spills/reloads to find the original value
633 * that is moved around
635 static ir_node *find_original_value(ir_node *node)
637 if (irn_visited(node))
640 mark_irn_visited(node);
641 if (be_is_Copy(node)) {
642 return find_original_value(be_get_Copy_op(node));
643 } else if (be_is_CopyKeep(node)) {
644 return find_original_value(be_get_CopyKeep_op(node));
645 } else if (is_Proj(node)) {
646 ir_node *pred = get_Proj_pred(node);
647 if (be_is_Perm(pred)) {
648 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
649 } else if (be_is_MemPerm(pred)) {
650 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
651 } else if (is_ia32_Load(pred)) {
652 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
656 } else if (is_ia32_Store(node)) {
657 return find_original_value(get_irn_n(node, n_ia32_Store_val));
658 } else if (is_Phi(node)) {
660 arity = get_irn_arity(node);
661 for (i = 0; i < arity; ++i) {
662 ir_node *in = get_irn_n(node, i);
663 ir_node *res = find_original_value(in);
674 static int determine_final_pnc(const ir_node *node, int flags_pos,
677 ir_node *flags = get_irn_n(node, flags_pos);
678 const ia32_attr_t *flags_attr;
679 flags = skip_Proj(flags);
681 if (is_ia32_Sahf(flags)) {
682 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
683 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
684 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
685 inc_irg_visited(current_ir_graph);
686 cmp = find_original_value(cmp);
688 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
689 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
692 flags_attr = get_ia32_attr_const(cmp);
693 if (flags_attr->data.ins_permuted)
694 pnc = get_mirrored_pnc(pnc);
695 pnc |= ia32_pn_Cmp_float;
696 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
697 || is_ia32_Fucompi(flags)) {
698 flags_attr = get_ia32_attr_const(flags);
700 if (flags_attr->data.ins_permuted)
701 pnc = get_mirrored_pnc(pnc);
702 pnc |= ia32_pn_Cmp_float;
704 flags_attr = get_ia32_attr_const(flags);
706 if (flags_attr->data.ins_permuted)
707 pnc = get_mirrored_pnc(pnc);
708 if (flags_attr->data.cmp_unsigned)
709 pnc |= ia32_pn_Cmp_unsigned;
715 static void ia32_emit_cmp_suffix(int pnc)
719 if ((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
721 assert(cmp2condition_u[pnc].num == pnc);
722 str = cmp2condition_u[pnc].name;
725 assert(cmp2condition_s[pnc].num == pnc);
726 str = cmp2condition_s[pnc].name;
732 void ia32_emit_cmp_suffix_node(const ir_node *node,
735 const ia32_attr_t *attr = get_ia32_attr_const(node);
737 pn_Cmp pnc = get_ia32_condcode(node);
739 pnc = determine_final_pnc(node, flags_pos, pnc);
740 if (attr->data.ins_permuted) {
741 if (pnc & ia32_pn_Cmp_float) {
742 pnc = get_negated_pnc(pnc, mode_F);
744 pnc = get_negated_pnc(pnc, mode_Iu);
748 ia32_emit_cmp_suffix(pnc);
752 * Returns the target block for a control flow node.
754 static ir_node *get_cfop_target_block(const ir_node *irn)
756 assert(get_irn_mode(irn) == mode_X);
757 return get_irn_link(irn);
761 * Emits a block label for the given block.
763 static void ia32_emit_block_name(const ir_node *block)
765 if (has_Block_label(block)) {
766 be_emit_string(be_gas_block_label_prefix());
767 be_emit_irprintf("%lu", get_Block_label(block));
769 be_emit_cstring(BLOCK_PREFIX);
770 be_emit_irprintf("%ld", get_irn_node_nr(block));
775 * Emits an exception label for a given node.
777 static void ia32_emit_exc_label(const ir_node *node)
779 be_emit_string(be_gas_insn_label_prefix());
780 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
784 * Emits the target label for a control flow node.
786 static void ia32_emit_cfop_target(const ir_node *node)
788 ir_node *block = get_cfop_target_block(node);
790 ia32_emit_block_name(block);
794 * Returns the Proj with projection number proj and NOT mode_M
796 static ir_node *get_proj(const ir_node *node, long proj)
798 const ir_edge_t *edge;
801 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
803 foreach_out_edge(node, edge) {
804 src = get_edge_src_irn(edge);
806 assert(is_Proj(src) && "Proj expected");
807 if (get_irn_mode(src) == mode_M)
810 if (get_Proj_proj(src) == proj)
816 static int can_be_fallthrough(const ir_node *node)
818 ir_node *target_block = get_cfop_target_block(node);
819 ir_node *block = get_nodes_block(node);
820 return get_prev_block_sched(target_block) == block;
824 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
826 static void emit_ia32_Jcc(const ir_node *node)
828 int need_parity_label = 0;
829 const ir_node *proj_true;
830 const ir_node *proj_false;
831 const ir_node *block;
832 pn_Cmp pnc = get_ia32_condcode(node);
834 pnc = determine_final_pnc(node, 0, pnc);
837 proj_true = get_proj(node, pn_ia32_Jcc_true);
838 assert(proj_true && "Jcc without true Proj");
840 proj_false = get_proj(node, pn_ia32_Jcc_false);
841 assert(proj_false && "Jcc without false Proj");
843 block = get_nodes_block(node);
845 if (can_be_fallthrough(proj_true)) {
846 /* exchange both proj's so the second one can be omitted */
847 const ir_node *t = proj_true;
849 proj_true = proj_false;
851 if (pnc & ia32_pn_Cmp_float) {
852 pnc = get_negated_pnc(pnc, mode_F);
854 pnc = get_negated_pnc(pnc, mode_Iu);
858 if (pnc & ia32_pn_Cmp_float) {
859 /* Some floating point comparisons require a test of the parity flag,
860 * which indicates that the result is unordered */
863 be_emit_cstring("\tjp ");
864 ia32_emit_cfop_target(proj_true);
865 be_emit_finish_line_gas(proj_true);
870 be_emit_cstring("\tjnp ");
871 ia32_emit_cfop_target(proj_true);
872 be_emit_finish_line_gas(proj_true);
878 /* we need a local label if the false proj is a fallthrough
879 * as the falseblock might have no label emitted then */
880 if (can_be_fallthrough(proj_false)) {
881 need_parity_label = 1;
882 be_emit_cstring("\tjp 1f");
884 be_emit_cstring("\tjp ");
885 ia32_emit_cfop_target(proj_false);
887 be_emit_finish_line_gas(proj_false);
893 be_emit_cstring("\tjp ");
894 ia32_emit_cfop_target(proj_true);
895 be_emit_finish_line_gas(proj_true);
903 be_emit_cstring("\tj");
904 ia32_emit_cmp_suffix(pnc);
906 ia32_emit_cfop_target(proj_true);
907 be_emit_finish_line_gas(proj_true);
910 if (need_parity_label) {
911 be_emit_cstring("1:");
912 be_emit_write_line();
915 /* the second Proj might be a fallthrough */
916 if (can_be_fallthrough(proj_false)) {
917 be_emit_cstring("\t/* fallthrough to ");
918 ia32_emit_cfop_target(proj_false);
919 be_emit_cstring(" */");
920 be_emit_finish_line_gas(proj_false);
922 be_emit_cstring("\tjmp ");
923 ia32_emit_cfop_target(proj_false);
924 be_emit_finish_line_gas(proj_false);
928 static void emit_ia32_CMov(const ir_node *node)
930 const ia32_attr_t *attr = get_ia32_attr_const(node);
931 int ins_permuted = attr->data.ins_permuted;
932 const arch_register_t *out = arch_get_irn_register(arch_env, node);
933 pn_Cmp pnc = get_ia32_condcode(node);
934 const arch_register_t *in_true;
935 const arch_register_t *in_false;
937 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
939 in_true = arch_get_irn_register(arch_env,
940 get_irn_n(node, n_ia32_CMov_val_true));
941 in_false = arch_get_irn_register(arch_env,
942 get_irn_n(node, n_ia32_CMov_val_false));
944 /* should be same constraint fullfilled? */
945 if (out == in_false) {
946 /* yes -> nothing to do */
947 } else if (out == in_true) {
948 const arch_register_t *tmp;
950 assert(get_ia32_op_type(node) == ia32_Normal);
952 ins_permuted = !ins_permuted;
959 be_emit_cstring("\tmovl ");
960 emit_register(in_false, NULL);
961 be_emit_cstring(", ");
962 emit_register(out, NULL);
963 be_emit_finish_line_gas(node);
967 if (pnc & ia32_pn_Cmp_float) {
968 pnc = get_negated_pnc(pnc, mode_F);
970 pnc = get_negated_pnc(pnc, mode_Iu);
974 /* TODO: handling of Nans isn't correct yet */
976 be_emit_cstring("\tcmov");
977 ia32_emit_cmp_suffix(pnc);
979 if (get_ia32_op_type(node) == ia32_AddrModeS) {
982 emit_register(in_true, get_ia32_ls_mode(node));
984 be_emit_cstring(", ");
985 emit_register(out, get_ia32_ls_mode(node));
986 be_emit_finish_line_gas(node);
989 /*********************************************************
992 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
993 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
994 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
995 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
998 *********************************************************/
1000 /* jump table entry (target and corresponding number) */
1001 typedef struct _branch_t {
1006 /* jump table for switch generation */
1007 typedef struct _jmp_tbl_t {
1008 ir_node *defProj; /**< default target */
1009 long min_value; /**< smallest switch case */
1010 long max_value; /**< largest switch case */
1011 long num_branches; /**< number of jumps */
1012 char *label; /**< label of the jump table */
1013 branch_t *branches; /**< jump array */
1017 * Compare two variables of type branch_t. Used to sort all switch cases
1019 static int ia32_cmp_branch_t(const void *a, const void *b)
1021 branch_t *b1 = (branch_t *)a;
1022 branch_t *b2 = (branch_t *)b;
1024 if (b1->value <= b2->value)
1031 * Emits code for a SwitchJmp (creates a jump table if
1032 * possible otherwise a cmp-jmp cascade). Port from
1035 static void emit_ia32_SwitchJmp(const ir_node *node)
1037 unsigned long interval;
1043 const ir_edge_t *edge;
1045 /* fill the table structure */
1046 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1047 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1049 tbl.num_branches = get_irn_n_edges(node) - 1;
1050 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1051 tbl.min_value = INT_MAX;
1052 tbl.max_value = INT_MIN;
1054 default_pn = get_ia32_condcode(node);
1056 /* go over all proj's and collect them */
1057 foreach_out_edge(node, edge) {
1058 proj = get_edge_src_irn(edge);
1059 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1061 pnc = get_Proj_proj(proj);
1063 /* check for default proj */
1064 if (pnc == default_pn) {
1065 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1068 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1069 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1071 /* create branch entry */
1072 tbl.branches[i].target = proj;
1073 tbl.branches[i].value = pnc;
1078 assert(i == tbl.num_branches);
1080 /* sort the branches by their number */
1081 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1083 /* two-complement's magic make this work without overflow */
1084 interval = tbl.max_value - tbl.min_value;
1086 /* emit the table */
1087 be_emit_cstring("\tcmpl $");
1088 be_emit_irprintf("%u, ", interval);
1089 ia32_emit_source_register(node, 0);
1090 be_emit_finish_line_gas(node);
1092 be_emit_cstring("\tja ");
1093 ia32_emit_cfop_target(tbl.defProj);
1094 be_emit_finish_line_gas(node);
1096 if (tbl.num_branches > 1) {
1098 be_emit_cstring("\tjmp *");
1099 be_emit_string(tbl.label);
1100 be_emit_cstring("(,");
1101 ia32_emit_source_register(node, 0);
1102 be_emit_cstring(",4)");
1103 be_emit_finish_line_gas(node);
1105 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1106 be_emit_cstring("\t.align 4\n");
1107 be_emit_write_line();
1109 be_emit_string(tbl.label);
1110 be_emit_cstring(":\n");
1111 be_emit_write_line();
1113 be_emit_cstring(".long ");
1114 ia32_emit_cfop_target(tbl.branches[0].target);
1115 be_emit_finish_line_gas(NULL);
1117 last_value = tbl.branches[0].value;
1118 for (i = 1; i < tbl.num_branches; ++i) {
1119 while (++last_value < tbl.branches[i].value) {
1120 be_emit_cstring(".long ");
1121 ia32_emit_cfop_target(tbl.defProj);
1122 be_emit_finish_line_gas(NULL);
1124 be_emit_cstring(".long ");
1125 ia32_emit_cfop_target(tbl.branches[i].target);
1126 be_emit_finish_line_gas(NULL);
1128 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1130 /* one jump is enough */
1131 be_emit_cstring("\tjmp ");
1132 ia32_emit_cfop_target(tbl.branches[0].target);
1133 be_emit_finish_line_gas(node);
1143 * Emits code for a unconditional jump.
1145 static void emit_Jmp(const ir_node *node)
1149 /* for now, the code works for scheduled and non-schedules blocks */
1150 block = get_nodes_block(node);
1152 /* we have a block schedule */
1153 if (can_be_fallthrough(node)) {
1154 be_emit_cstring("\t/* fallthrough to ");
1155 ia32_emit_cfop_target(node);
1156 be_emit_cstring(" */");
1158 be_emit_cstring("\tjmp ");
1159 ia32_emit_cfop_target(node);
1161 be_emit_finish_line_gas(node);
1164 static void emit_ia32_Immediate(const ir_node *node)
1166 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1169 if (attr->symconst != NULL) {
1172 ia32_emit_entity(attr->symconst, 0);
1174 if (attr->symconst == NULL || attr->offset != 0) {
1175 if (attr->symconst != NULL) {
1176 be_emit_irprintf("%+d", attr->offset);
1178 be_emit_irprintf("0x%X", attr->offset);
1184 * Emit an inline assembler operand.
1186 * @param node the ia32_ASM node
1187 * @param s points to the operand (a %c)
1189 * @return pointer to the first char in s NOT in the current operand
1191 static const char* emit_asm_operand(const ir_node *node, const char *s)
1193 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1194 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1196 const arch_register_t *reg;
1197 const ia32_asm_reg_t *asm_regs = attr->register_map;
1198 const ia32_asm_reg_t *asm_reg;
1199 const char *reg_name;
1208 /* parse modifiers */
1211 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1235 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1236 "'%c' for asm op\n", node, c);
1242 sscanf(s, "%d%n", &num, &p);
1244 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1251 if (num < 0 || num >= ARR_LEN(asm_regs)) {
1252 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1253 "input/output (%+F)\n", node);
1256 asm_reg = & asm_regs[num];
1257 assert(asm_reg->valid);
1260 if (asm_reg->use_input == 0) {
1261 reg = get_out_reg(node, asm_reg->inout_pos);
1263 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1265 /* might be an immediate value */
1266 if (is_ia32_Immediate(pred)) {
1267 emit_ia32_Immediate(pred);
1270 reg = get_in_reg(node, asm_reg->inout_pos);
1273 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1274 "(%+F)\n", num, node);
1278 if (asm_reg->memory) {
1283 if (modifier != 0) {
1287 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1290 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1293 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1296 panic("Invalid asm op modifier");
1298 be_emit_string(reg_name);
1300 emit_register(reg, asm_reg->mode);
1303 if (asm_reg->memory) {
1311 * Emits code for an ASM pseudo op.
1313 static void emit_ia32_Asm(const ir_node *node)
1315 const void *gen_attr = get_irn_generic_attr_const(node);
1316 const ia32_asm_attr_t *attr
1317 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1318 ident *asm_text = attr->asm_text;
1319 const char *s = get_id_str(asm_text);
1321 be_emit_cstring("#APP\t");
1322 be_emit_finish_line_gas(node);
1329 s = emit_asm_operand(node, s);
1336 be_emit_write_line();
1338 be_emit_cstring("#NO_APP\n");
1339 be_emit_write_line();
1342 /**********************************
1345 * | | ___ _ __ _ _| |_) |
1346 * | | / _ \| '_ \| | | | _ <
1347 * | |___| (_) | |_) | |_| | |_) |
1348 * \_____\___/| .__/ \__, |____/
1351 **********************************/
1354 * Emit movsb/w instructions to make mov count divideable by 4
1356 static void emit_CopyB_prolog(unsigned size)
1358 be_emit_cstring("\tcld");
1359 be_emit_finish_line_gas(NULL);
1363 be_emit_cstring("\tmovsb");
1364 be_emit_finish_line_gas(NULL);
1367 be_emit_cstring("\tmovsw");
1368 be_emit_finish_line_gas(NULL);
1371 be_emit_cstring("\tmovsb");
1372 be_emit_finish_line_gas(NULL);
1373 be_emit_cstring("\tmovsw");
1374 be_emit_finish_line_gas(NULL);
1380 * Emit rep movsd instruction for memcopy.
1382 static void emit_ia32_CopyB(const ir_node *node)
1384 unsigned size = get_ia32_copyb_size(node);
1386 emit_CopyB_prolog(size);
1388 be_emit_cstring("\trep movsd");
1389 be_emit_finish_line_gas(node);
1393 * Emits unrolled memcopy.
1395 static void emit_ia32_CopyB_i(const ir_node *node)
1397 unsigned size = get_ia32_copyb_size(node);
1399 emit_CopyB_prolog(size & 0x3);
1403 be_emit_cstring("\tmovsd");
1404 be_emit_finish_line_gas(NULL);
1410 /***************************
1414 * | | / _ \| '_ \ \ / /
1415 * | |___| (_) | | | \ V /
1416 * \_____\___/|_| |_|\_/
1418 ***************************/
1421 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1423 static void emit_ia32_Conv_with_FP(const ir_node *node)
1425 ir_mode *ls_mode = get_ia32_ls_mode(node);
1426 int ls_bits = get_mode_size_bits(ls_mode);
1428 be_emit_cstring("\tcvt");
1430 if (is_ia32_Conv_I2FP(node)) {
1431 if (ls_bits == 32) {
1432 be_emit_cstring("si2ss");
1434 be_emit_cstring("si2sd");
1436 } else if (is_ia32_Conv_FP2I(node)) {
1437 if (ls_bits == 32) {
1438 be_emit_cstring("ss2si");
1440 be_emit_cstring("sd2si");
1443 assert(is_ia32_Conv_FP2FP(node));
1444 if (ls_bits == 32) {
1445 be_emit_cstring("sd2ss");
1447 be_emit_cstring("ss2sd");
1452 switch(get_ia32_op_type(node)) {
1454 ia32_emit_source_register(node, n_ia32_unary_op);
1456 case ia32_AddrModeS:
1460 assert(0 && "unsupported op type for Conv");
1462 be_emit_cstring(", ");
1463 ia32_emit_dest_register(node, 0);
1464 be_emit_finish_line_gas(node);
1467 static void emit_ia32_Conv_I2FP(const ir_node *node)
1469 emit_ia32_Conv_with_FP(node);
1472 static void emit_ia32_Conv_FP2I(const ir_node *node)
1474 emit_ia32_Conv_with_FP(node);
1477 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1479 emit_ia32_Conv_with_FP(node);
1483 * Emits code for an Int conversion.
1485 static void emit_ia32_Conv_I2I(const ir_node *node)
1487 const char *sign_suffix;
1488 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1489 int smaller_bits = get_mode_size_bits(smaller_mode);
1491 const arch_register_t *in_reg, *out_reg;
1493 assert(!mode_is_float(smaller_mode));
1494 assert(smaller_bits == 8 || smaller_bits == 16);
1496 signed_mode = mode_is_signed(smaller_mode);
1497 sign_suffix = signed_mode ? "s" : "z";
1499 out_reg = get_out_reg(node, 0);
1501 switch(get_ia32_op_type(node)) {
1503 in_reg = get_in_reg(node, n_ia32_unary_op);
1505 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1506 out_reg == &ia32_gp_regs[REG_EAX] &&
1510 /* argument and result are both in EAX and */
1511 /* signedness is ok: -> use the smaller cwtl opcode */
1512 be_emit_cstring("\tcwtl");
1514 be_emit_cstring("\tmov");
1515 be_emit_string(sign_suffix);
1516 ia32_emit_mode_suffix_mode(smaller_mode);
1517 be_emit_cstring("l ");
1518 emit_register(in_reg, smaller_mode);
1519 be_emit_cstring(", ");
1520 emit_register(out_reg, NULL);
1523 case ia32_AddrModeS: {
1524 be_emit_cstring("\tmov");
1525 be_emit_string(sign_suffix);
1526 ia32_emit_mode_suffix_mode(smaller_mode);
1527 be_emit_cstring("l ");
1529 be_emit_cstring(", ");
1530 emit_register(out_reg, NULL);
1534 panic("unsupported op type for Conv");
1536 be_emit_finish_line_gas(node);
1540 /*******************************************
1543 * | |__ ___ _ __ ___ __| | ___ ___
1544 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1545 * | |_) | __/ | | | (_) | (_| | __/\__ \
1546 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1548 *******************************************/
1551 * Emits a backend call
1553 static void emit_be_Call(const ir_node *node)
1555 ir_entity *ent = be_Call_get_entity(node);
1557 be_emit_cstring("\tcall ");
1559 ia32_emit_entity(ent, 1);
1561 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1563 emit_register(reg, NULL);
1565 be_emit_finish_line_gas(node);
1569 * Emits code to increase stack pointer.
1571 static void emit_be_IncSP(const ir_node *node)
1573 int offs = be_get_IncSP_offset(node);
1574 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1580 be_emit_cstring("\tsubl $");
1581 be_emit_irprintf("%u, ", offs);
1582 emit_register(reg, NULL);
1584 be_emit_cstring("\taddl $");
1585 be_emit_irprintf("%u, ", -offs);
1586 emit_register(reg, NULL);
1588 be_emit_finish_line_gas(node);
1592 * Emits code for Copy/CopyKeep.
1594 static void Copy_emitter(const ir_node *node, const ir_node *op)
1596 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1597 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1603 if (is_unknown_reg(in))
1605 /* copies of vf nodes aren't real... */
1606 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1609 mode = get_irn_mode(node);
1610 if (mode == mode_E) {
1611 be_emit_cstring("\tmovsd ");
1612 emit_register(in, NULL);
1613 be_emit_cstring(", ");
1614 emit_register(out, NULL);
1616 be_emit_cstring("\tmovl ");
1617 emit_register(in, NULL);
1618 be_emit_cstring(", ");
1619 emit_register(out, NULL);
1621 be_emit_finish_line_gas(node);
1624 static void emit_be_Copy(const ir_node *node)
1626 Copy_emitter(node, be_get_Copy_op(node));
1629 static void emit_be_CopyKeep(const ir_node *node)
1631 Copy_emitter(node, be_get_CopyKeep_op(node));
1635 * Emits code for exchange.
1637 static void emit_be_Perm(const ir_node *node)
1639 const arch_register_t *in0, *in1;
1640 const arch_register_class_t *cls0, *cls1;
1642 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1643 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1645 cls0 = arch_register_get_class(in0);
1646 cls1 = arch_register_get_class(in1);
1648 assert(cls0 == cls1 && "Register class mismatch at Perm");
1650 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1651 be_emit_cstring("\txchg ");
1652 emit_register(in1, NULL);
1653 be_emit_cstring(", ");
1654 emit_register(in0, NULL);
1655 be_emit_finish_line_gas(node);
1656 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1657 be_emit_cstring("\txorpd ");
1658 emit_register(in1, NULL);
1659 be_emit_cstring(", ");
1660 emit_register(in0, NULL);
1661 be_emit_finish_line_gas(NULL);
1663 be_emit_cstring("\txorpd ");
1664 emit_register(in0, NULL);
1665 be_emit_cstring(", ");
1666 emit_register(in1, NULL);
1667 be_emit_finish_line_gas(NULL);
1669 be_emit_cstring("\txorpd ");
1670 emit_register(in1, NULL);
1671 be_emit_cstring(", ");
1672 emit_register(in0, NULL);
1673 be_emit_finish_line_gas(node);
1674 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1676 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1679 panic("unexpected register class in be_Perm (%+F)", node);
1684 * Emits code for Constant loading.
1686 static void emit_ia32_Const(const ir_node *node)
1688 be_emit_cstring("\tmovl ");
1689 emit_ia32_Immediate(node);
1690 be_emit_cstring(", ");
1691 ia32_emit_dest_register(node, 0);
1693 be_emit_finish_line_gas(node);
1697 * Emits code to load the TLS base
1699 static void emit_ia32_LdTls(const ir_node *node)
1701 be_emit_cstring("\tmovl %gs:0, ");
1702 ia32_emit_dest_register(node, 0);
1703 be_emit_finish_line_gas(node);
1706 /* helper function for emit_ia32_Minus64Bit */
1707 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1709 be_emit_cstring("\tmovl ");
1710 emit_register(src, NULL);
1711 be_emit_cstring(", ");
1712 emit_register(dst, NULL);
1713 be_emit_finish_line_gas(node);
1716 /* helper function for emit_ia32_Minus64Bit */
1717 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1719 be_emit_cstring("\tnegl ");
1720 emit_register(reg, NULL);
1721 be_emit_finish_line_gas(node);
1724 /* helper function for emit_ia32_Minus64Bit */
1725 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1727 be_emit_cstring("\tsbbl $0, ");
1728 emit_register(reg, NULL);
1729 be_emit_finish_line_gas(node);
1732 /* helper function for emit_ia32_Minus64Bit */
1733 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1735 be_emit_cstring("\tsbbl ");
1736 emit_register(src, NULL);
1737 be_emit_cstring(", ");
1738 emit_register(dst, NULL);
1739 be_emit_finish_line_gas(node);
1742 /* helper function for emit_ia32_Minus64Bit */
1743 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1745 be_emit_cstring("\txchgl ");
1746 emit_register(src, NULL);
1747 be_emit_cstring(", ");
1748 emit_register(dst, NULL);
1749 be_emit_finish_line_gas(node);
1752 /* helper function for emit_ia32_Minus64Bit */
1753 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1755 be_emit_cstring("\txorl ");
1756 emit_register(reg, NULL);
1757 be_emit_cstring(", ");
1758 emit_register(reg, NULL);
1759 be_emit_finish_line_gas(node);
1762 static void emit_ia32_Minus64Bit(const ir_node *node)
1764 const arch_register_t *in_lo = get_in_reg(node, 0);
1765 const arch_register_t *in_hi = get_in_reg(node, 1);
1766 const arch_register_t *out_lo = get_out_reg(node, 0);
1767 const arch_register_t *out_hi = get_out_reg(node, 1);
1769 if (out_lo == in_lo) {
1770 if (out_hi != in_hi) {
1771 /* a -> a, b -> d */
1774 /* a -> a, b -> b */
1777 } else if (out_lo == in_hi) {
1778 if (out_hi == in_lo) {
1779 /* a -> b, b -> a */
1780 emit_xchg(node, in_lo, in_hi);
1783 /* a -> b, b -> d */
1784 emit_mov(node, in_hi, out_hi);
1785 emit_mov(node, in_lo, out_lo);
1789 if (out_hi == in_lo) {
1790 /* a -> c, b -> a */
1791 emit_mov(node, in_lo, out_lo);
1793 } else if (out_hi == in_hi) {
1794 /* a -> c, b -> b */
1795 emit_mov(node, in_lo, out_lo);
1798 /* a -> c, b -> d */
1799 emit_mov(node, in_lo, out_lo);
1805 emit_neg( node, out_hi);
1806 emit_neg( node, out_lo);
1807 emit_sbb0(node, out_hi);
1811 emit_zero(node, out_hi);
1812 emit_neg( node, out_lo);
1813 emit_sbb( node, in_hi, out_hi);
1816 static void emit_ia32_GetEIP(const ir_node *node)
1818 be_emit_cstring("\tcall ");
1819 be_emit_string(pic_base_label);
1820 be_emit_finish_line_gas(node);
1822 be_emit_string(pic_base_label);
1823 be_emit_cstring(":\n");
1824 be_emit_write_line();
1826 be_emit_cstring("\tpopl ");
1827 ia32_emit_dest_register(node, 0);
1829 be_emit_write_line();
1832 static void emit_be_Return(const ir_node *node)
1835 be_emit_cstring("\tret");
1837 pop = be_Return_get_pop(node);
1838 if (pop > 0 || be_Return_get_emit_pop(node)) {
1839 be_emit_irprintf(" $%d", pop);
1841 be_emit_finish_line_gas(node);
1844 static void emit_Nothing(const ir_node *node)
1850 /***********************************************************************************
1853 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1854 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1855 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1856 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1858 ***********************************************************************************/
1861 * Enters the emitter functions for handled nodes into the generic
1862 * pointer of an opcode.
1864 static void ia32_register_emitters(void)
1866 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1867 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1868 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1869 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1870 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1871 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1873 /* first clear the generic function pointer for all ops */
1874 clear_irp_opcodes_generic_func();
1876 /* register all emitter functions defined in spec */
1877 ia32_register_spec_emitters();
1879 /* other ia32 emitter functions */
1883 IA32_EMIT(SwitchJmp);
1886 IA32_EMIT(Conv_I2FP);
1887 IA32_EMIT(Conv_FP2I);
1888 IA32_EMIT(Conv_FP2FP);
1889 IA32_EMIT(Conv_I2I);
1890 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1893 IA32_EMIT(Minus64Bit);
1897 /* benode emitter */
1922 typedef void (*emit_func_ptr) (const ir_node *);
1925 * Emits code for a node.
1927 static void ia32_emit_node(ir_node *node)
1929 ir_op *op = get_irn_op(node);
1931 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1933 if (is_ia32_irn(node) && get_ia32_exc_label(node)) {
1934 /* emit the exception label of this instruction */
1935 ia32_assign_exc_label(node);
1937 if (op->ops.generic) {
1938 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1940 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1945 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1951 * Emits gas alignment directives
1953 static void ia32_emit_alignment(unsigned align, unsigned skip)
1955 be_emit_cstring("\t.p2align ");
1956 be_emit_irprintf("%u,,%u\n", align, skip);
1957 be_emit_write_line();
1961 * Emits gas alignment directives for Labels depended on cpu architecture.
1963 static void ia32_emit_align_label(void)
1965 unsigned align = ia32_cg_config.label_alignment;
1966 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1967 ia32_emit_alignment(align, maximum_skip);
1971 * Test whether a block should be aligned.
1972 * For cpus in the P4/Athlon class it is useful to align jump labels to
1973 * 16 bytes. However we should only do that if the alignment nops before the
1974 * label aren't executed more often than we have jumps to the label.
1976 static int should_align_block(const ir_node *block)
1978 static const double DELTA = .0001;
1979 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1980 ir_node *prev = get_prev_block_sched(block);
1982 double prev_freq = 0; /**< execfreq of the fallthrough block */
1983 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1986 if (exec_freq == NULL)
1988 if (ia32_cg_config.label_alignment_factor <= 0)
1991 block_freq = get_block_execfreq(exec_freq, block);
1992 if (block_freq < DELTA)
1995 n_cfgpreds = get_Block_n_cfgpreds(block);
1996 for(i = 0; i < n_cfgpreds; ++i) {
1997 const ir_node *pred = get_Block_cfgpred_block(block, i);
1998 double pred_freq = get_block_execfreq(exec_freq, pred);
2001 prev_freq += pred_freq;
2003 jmp_freq += pred_freq;
2007 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2010 jmp_freq /= prev_freq;
2012 return jmp_freq > ia32_cg_config.label_alignment_factor;
2016 * Emit the block header for a block.
2018 * @param block the block
2019 * @param prev_block the previous block
2021 static void ia32_emit_block_header(ir_node *block)
2023 ir_graph *irg = current_ir_graph;
2024 int need_label = block_needs_label(block);
2026 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2028 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2031 if (ia32_cg_config.label_alignment > 0) {
2032 /* align the current block if:
2033 * a) if should be aligned due to its execution frequency
2034 * b) there is no fall-through here
2036 if (should_align_block(block)) {
2037 ia32_emit_align_label();
2039 /* if the predecessor block has no fall-through,
2040 we can always align the label. */
2042 int has_fallthrough = 0;
2044 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2045 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2046 if (can_be_fallthrough(cfg_pred)) {
2047 has_fallthrough = 1;
2052 if (!has_fallthrough)
2053 ia32_emit_align_label();
2057 if (need_label || has_Block_label(block)) {
2058 ia32_emit_block_name(block);
2061 be_emit_pad_comment();
2062 be_emit_cstring(" /* ");
2064 be_emit_cstring("\t/* ");
2065 ia32_emit_block_name(block);
2066 be_emit_cstring(": ");
2069 be_emit_cstring("preds:");
2071 /* emit list of pred blocks in comment */
2072 arity = get_irn_arity(block);
2073 for (i = 0; i < arity; ++i) {
2074 ir_node *predblock = get_Block_cfgpred_block(block, i);
2075 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2077 if (exec_freq != NULL) {
2078 be_emit_irprintf(" freq: %f",
2079 get_block_execfreq(exec_freq, block));
2081 be_emit_cstring(" */\n");
2082 be_emit_write_line();
2086 * Walks over the nodes in a block connected by scheduling edges
2087 * and emits code for each node.
2089 static void ia32_gen_block(ir_node *block)
2093 ia32_emit_block_header(block);
2095 /* emit the contents of the block */
2096 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2097 sched_foreach(block, node) {
2098 ia32_emit_node(node);
2102 typedef struct exc_entry {
2103 ir_node *exc_instr; /** The instruction that can issue an exception. */
2104 ir_node *block; /** The block to call then. */
2109 * Sets labels for control flow nodes (jump target).
2110 * Links control predecessors to there destination blocks.
2112 static void ia32_gen_labels(ir_node *block, void *data)
2114 exc_entry **exc_list = data;
2118 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2119 pred = get_Block_cfgpred(block, n);
2120 set_irn_link(pred, block);
2122 pred = skip_Proj(pred);
2123 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2128 ARR_APP1(exc_entry, *exc_list, e);
2129 set_irn_link(pred, block);
2135 * Assign and emit an exception label if the current instruction can fail.
2137 void ia32_assign_exc_label(ir_node *node)
2139 if (get_ia32_exc_label(node)) {
2140 /* assign a new ID to the instruction */
2141 set_ia32_exc_label_id(node, ++exc_label_id);
2143 ia32_emit_exc_label(node);
2145 be_emit_pad_comment();
2146 be_emit_cstring("/* exception to Block ");
2147 ia32_emit_cfop_target(node);
2148 be_emit_cstring(" */\n");
2149 be_emit_write_line();
2154 * Compare two exception_entries.
2156 static int cmp_exc_entry(const void *a, const void *b)
2158 const exc_entry *ea = a;
2159 const exc_entry *eb = b;
2161 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2167 * Main driver. Emits the code for one routine.
2169 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2171 ir_entity *entity = get_irg_entity(irg);
2172 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2176 isa = (const ia32_isa_t*) cg->arch_env;
2177 arch_env = cg->arch_env;
2178 do_pic = cg->birg->main_env->options->pic;
2180 ia32_register_emitters();
2182 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2184 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2185 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2187 /* we use links to point to target blocks */
2188 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2189 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2191 /* initialize next block links */
2192 n = ARR_LEN(cg->blk_sched);
2193 for (i = 0; i < n; ++i) {
2194 ir_node *block = cg->blk_sched[i];
2195 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2197 set_irn_link(block, prev);
2200 for (i = 0; i < n; ++i) {
2201 ir_node *block = cg->blk_sched[i];
2203 ia32_gen_block(block);
2206 be_gas_emit_function_epilog(entity);
2207 be_dbg_method_end();
2209 be_emit_write_line();
2211 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2213 /* Sort the exception table using the exception label id's.
2214 Those are ascending with ascending addresses. */
2215 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2219 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2220 be_emit_cstring("\t.long ");
2221 ia32_emit_exc_label(exc_list[i].exc_instr);
2223 be_emit_cstring("\t.long ");
2224 ia32_emit_block_name(exc_list[i].block);
2228 DEL_ARR_F(exc_list);
2231 void ia32_init_emitter(void)
2233 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");