2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
43 #include "raw_bitset.h"
47 #include "../besched.h"
48 #include "../benode.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
73 static char pic_base_label[128];
74 static ir_label_t exc_label_id;
75 static int mark_spill_reload = 0;
78 /** Return the next block in Block schedule */
79 static ir_node *get_prev_block_sched(const ir_node *block)
81 return get_irn_link(block);
84 /** Checks if the current block is a fall-through target. */
85 static int is_fallthrough(const ir_node *cfgpred)
89 if (!is_Proj(cfgpred))
91 pred = get_Proj_pred(cfgpred);
92 if (is_ia32_SwitchJmp(pred))
99 * returns non-zero if the given block needs a label
100 * because of being a jump-target (and not a fall-through)
102 static int block_needs_label(const ir_node *block)
105 int n_cfgpreds = get_Block_n_cfgpreds(block);
107 if (has_Block_entity(block))
110 if (n_cfgpreds == 0) {
112 } else if (n_cfgpreds == 1) {
113 ir_node *cfgpred = get_Block_cfgpred(block, 0);
114 ir_node *cfgpred_block = get_nodes_block(cfgpred);
116 if (get_prev_block_sched(block) == cfgpred_block
117 && is_fallthrough(cfgpred)) {
126 * Returns the register at in position pos.
128 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
131 const arch_register_t *reg = NULL;
133 assert(get_irn_arity(irn) > pos && "Invalid IN position");
135 /* The out register of the operator at position pos is the
136 in register we need. */
137 op = get_irn_n(irn, pos);
139 reg = arch_get_irn_register(op);
141 assert(reg && "no in register found");
143 if (reg == &ia32_gp_regs[REG_GP_NOREG])
144 panic("trying to emit noreg for %+F input %d", irn, pos);
146 /* in case of unknown register: just return a valid register */
147 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
148 const arch_register_req_t *req = arch_get_register_req(irn, pos);
150 if (arch_register_req_is(req, limited)) {
151 /* in case of limited requirements: get the first allowed register */
152 unsigned idx = rbitset_next(req->limited, 0, 1);
153 reg = arch_register_for_index(req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%lu", prefix, ++id);
208 /*************************************************************
210 * (_) | | / _| | | | |
211 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
212 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
213 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
214 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
217 *************************************************************/
220 * Emit the name of the 8bit low register
222 static void emit_8bit_register(const arch_register_t *reg)
224 const char *reg_name = arch_register_get_name(reg);
227 be_emit_char(reg_name[1]);
232 * Emit the name of the 8bit high register
234 static void emit_8bit_register_high(const arch_register_t *reg)
236 const char *reg_name = arch_register_get_name(reg);
239 be_emit_char(reg_name[1]);
243 static void emit_16bit_register(const arch_register_t *reg)
245 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
248 be_emit_string(reg_name);
252 * emit a register, possible shortened by a mode
254 * @param reg the register
255 * @param mode the mode of the register or NULL for full register
257 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
259 const char *reg_name;
262 int size = get_mode_size_bits(mode);
264 case 8: emit_8bit_register(reg); return;
265 case 16: emit_16bit_register(reg); return;
267 assert(mode_is_float(mode) || size == 32);
270 reg_name = arch_register_get_name(reg);
273 be_emit_string(reg_name);
276 void ia32_emit_source_register(const ir_node *node, int pos)
278 const arch_register_t *reg = get_in_reg(node, pos);
280 emit_register(reg, NULL);
283 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
285 be_gas_emit_entity(entity);
287 if (get_entity_owner(entity) == get_tls_type()) {
288 if (get_entity_visibility(entity) == ir_visibility_external) {
289 be_emit_cstring("@INDNTPOFF");
291 be_emit_cstring("@NTPOFF");
295 if (do_pic && !no_pic_adjust) {
297 be_emit_string(pic_base_label);
301 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
303 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
305 if (attr->symconst != NULL) {
308 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
310 if (attr->symconst == NULL || attr->offset != 0) {
311 if (attr->symconst != NULL) {
312 be_emit_irprintf("%+d", attr->offset);
314 be_emit_irprintf("0x%X", attr->offset);
319 static void emit_ia32_Immediate(const ir_node *node)
322 emit_ia32_Immediate_no_prefix(node);
325 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
327 const arch_register_t *reg;
328 const ir_node *in = get_irn_n(node, pos);
329 if (is_ia32_Immediate(in)) {
330 emit_ia32_Immediate(in);
334 reg = get_in_reg(node, pos);
335 emit_8bit_register(reg);
338 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
340 const arch_register_t *reg = get_in_reg(node, pos);
341 emit_8bit_register_high(reg);
344 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
346 const arch_register_t *reg;
347 const ir_node *in = get_irn_n(node, pos);
348 if (is_ia32_Immediate(in)) {
349 emit_ia32_Immediate(in);
353 reg = get_in_reg(node, pos);
354 emit_16bit_register(reg);
357 void ia32_emit_dest_register(const ir_node *node, int pos)
359 const arch_register_t *reg = get_out_reg(node, pos);
361 emit_register(reg, NULL);
364 void ia32_emit_dest_register_size(const ir_node *node, int pos)
366 const arch_register_t *reg = get_out_reg(node, pos);
368 emit_register(reg, get_ia32_ls_mode(node));
371 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
373 const arch_register_t *reg = get_out_reg(node, pos);
375 emit_register(reg, mode_Bu);
378 void ia32_emit_x87_register(const ir_node *node, int pos)
380 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
384 be_emit_string(attr->x87[pos]->name);
387 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
389 assert(mode_is_int(mode) || mode_is_reference(mode));
390 switch (get_mode_size_bits(mode)) {
391 case 8: be_emit_char('b'); return;
392 case 16: be_emit_char('w'); return;
393 case 32: be_emit_char('l'); return;
394 /* gas docu says q is the suffix but gcc, objdump and icc use ll
396 case 64: be_emit_cstring("ll"); return;
398 panic("Can't output mode_suffix for %+F", mode);
401 void ia32_emit_mode_suffix(const ir_node *node)
403 ir_mode *mode = get_ia32_ls_mode(node);
407 ia32_emit_mode_suffix_mode(mode);
410 void ia32_emit_x87_mode_suffix(const ir_node *node)
414 /* we only need to emit the mode on address mode */
415 if (get_ia32_op_type(node) == ia32_Normal)
418 mode = get_ia32_ls_mode(node);
419 assert(mode != NULL);
421 if (mode_is_float(mode)) {
422 switch (get_mode_size_bits(mode)) {
423 case 32: be_emit_char('s'); return;
424 case 64: be_emit_char('l'); return;
426 case 96: be_emit_char('t'); return;
429 assert(mode_is_int(mode));
430 switch (get_mode_size_bits(mode)) {
431 case 16: be_emit_char('s'); return;
432 case 32: be_emit_char('l'); return;
433 /* gas docu says q is the suffix but gcc, objdump and icc use ll
435 case 64: be_emit_cstring("ll"); return;
438 panic("Can't output mode_suffix for %+F", mode);
441 static char get_xmm_mode_suffix(ir_mode *mode)
443 assert(mode_is_float(mode));
444 switch(get_mode_size_bits(mode)) {
447 default: panic("Invalid XMM mode");
451 void ia32_emit_xmm_mode_suffix(const ir_node *node)
453 ir_mode *mode = get_ia32_ls_mode(node);
454 assert(mode != NULL);
456 be_emit_char(get_xmm_mode_suffix(mode));
459 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
461 ir_mode *mode = get_ia32_ls_mode(node);
462 assert(mode != NULL);
463 be_emit_char(get_xmm_mode_suffix(mode));
466 void ia32_emit_extend_suffix(const ir_node *node)
468 ir_mode *mode = get_ia32_ls_mode(node);
469 if (get_mode_size_bits(mode) == 32)
471 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
472 ia32_emit_mode_suffix_mode(mode);
475 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
477 ir_node *in = get_irn_n(node, pos);
478 if (is_ia32_Immediate(in)) {
479 emit_ia32_Immediate(in);
481 const ir_mode *mode = get_ia32_ls_mode(node);
482 const arch_register_t *reg = get_in_reg(node, pos);
483 emit_register(reg, mode);
488 * Returns the target block for a control flow node.
490 static ir_node *get_cfop_target_block(const ir_node *irn)
492 assert(get_irn_mode(irn) == mode_X);
493 return get_irn_link(irn);
497 * Emits a block label for the given block.
499 static void ia32_emit_block_name(const ir_node *block)
501 if (has_Block_entity(block)) {
502 ir_entity *entity = get_Block_entity(block);
503 be_gas_emit_entity(entity);
505 be_emit_cstring(BLOCK_PREFIX);
506 be_emit_irprintf("%ld", get_irn_node_nr(block));
511 * Emits the target label for a control flow node.
513 static void ia32_emit_cfop_target(const ir_node *node)
515 ir_node *block = get_cfop_target_block(node);
516 ia32_emit_block_name(block);
520 * positive conditions for signed compares
522 static const char *const cmp2condition_s[] = {
523 NULL, /* always false */
530 NULL /* always true */
534 * positive conditions for unsigned compares
536 static const char *const cmp2condition_u[] = {
537 NULL, /* always false */
544 NULL /* always true */
548 * Emit the suffix for a compare instruction.
550 static void ia32_emit_cmp_suffix(int pnc)
554 if (pnc == ia32_pn_Cmp_parity) {
559 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
560 str = cmp2condition_u[pnc & 7];
562 str = cmp2condition_s[pnc & 7];
568 typedef enum ia32_emit_mod_t {
569 EMIT_RESPECT_LS = 1U << 0,
570 EMIT_ALTERNATE_AM = 1U << 1,
572 EMIT_HIGH_REG = 1U << 3,
573 EMIT_LOW_REG = 1U << 4
577 * Emits address mode.
579 void ia32_emit_am(const ir_node *node)
581 ir_entity *ent = get_ia32_am_sc(node);
582 int offs = get_ia32_am_offs_int(node);
583 ir_node *base = get_irn_n(node, n_ia32_base);
584 int has_base = !is_ia32_NoReg_GP(base);
585 ir_node *index = get_irn_n(node, n_ia32_index);
586 int has_index = !is_ia32_NoReg_GP(index);
588 /* just to be sure... */
589 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
593 const ia32_attr_t *attr = get_ia32_attr_const(node);
594 if (is_ia32_am_sc_sign(node))
596 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
599 /* also handle special case if nothing is set */
600 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
602 be_emit_irprintf("%+d", offs);
604 be_emit_irprintf("%d", offs);
608 if (has_base || has_index) {
613 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
614 emit_register(reg, NULL);
617 /* emit index + scale */
619 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
622 emit_register(reg, NULL);
624 scale = get_ia32_am_scale(node);
626 be_emit_irprintf(",%d", 1 << scale);
634 * fmt parameter output
635 * ---- ---------------------- ---------------------------------------------
637 * %AM <node> address mode of the node
638 * %AR const arch_register_t* address mode of the node or register
639 * %ASx <node> address mode of the node or source register x
640 * %Dx <node> destination register x
641 * %I <node> immediate of the node
642 * %L <node> control flow target of the node
643 * %M <node> mode suffix of the node
644 * %P int condition code
645 * %R const arch_register_t* register
646 * %Sx <node> source register x
647 * %s const char* string
648 * %u unsigned int unsigned int
649 * %d signed int signed int
652 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
653 * * modifier does not prefix immediates with $, but AM with *
654 * l modifier for %lu and %ld
655 * > modifier to output high 8bit register (ah, bh)
656 * < modifier to output low 8bit register (al, bl)
658 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
664 const char *start = fmt;
665 ia32_emit_mod_t mod = 0;
667 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
670 be_emit_string_len(start, fmt - start);
674 be_emit_finish_line_gas(node);
687 case '*': mod |= EMIT_ALTERNATE_AM; break;
688 case '#': mod |= EMIT_RESPECT_LS; break;
689 case 'l': mod |= EMIT_LONG; break;
690 case '>': mod |= EMIT_HIGH_REG; break;
691 case '<': mod |= EMIT_LOW_REG; break;
708 if (mod & EMIT_ALTERNATE_AM)
714 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
715 if (get_ia32_op_type(node) == ia32_AddrModeS) {
718 if (mod & EMIT_ALTERNATE_AM)
720 emit_register(reg, NULL);
726 if (get_ia32_op_type(node) == ia32_AddrModeS) {
730 assert(get_ia32_op_type(node) == ia32_Normal);
735 default: goto unknown;
742 const arch_register_t *reg;
744 if (*fmt < '0' || '9' <= *fmt)
748 reg = get_out_reg(node, pos);
749 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
754 if (!(mod & EMIT_ALTERNATE_AM))
756 emit_ia32_Immediate_no_prefix(node);
760 ia32_emit_cfop_target(node);
764 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
769 int pnc = va_arg(ap, int);
770 ia32_emit_cmp_suffix(pnc);
775 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
776 if (mod & EMIT_HIGH_REG) {
777 emit_8bit_register_high(reg);
778 } else if (mod & EMIT_LOW_REG) {
779 emit_8bit_register(reg);
781 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
791 if (*fmt < '0' || '9' <= *fmt)
795 in = get_irn_n(node, pos);
796 if (is_ia32_Immediate(in)) {
797 if (!(mod & EMIT_ALTERNATE_AM))
799 emit_ia32_Immediate_no_prefix(in);
801 const arch_register_t *reg;
803 if (mod & EMIT_ALTERNATE_AM)
805 reg = get_in_reg(node, pos);
806 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
812 const char *str = va_arg(ap, const char*);
818 if (mod & EMIT_LONG) {
819 unsigned long num = va_arg(ap, unsigned long);
820 be_emit_irprintf("%lu", num);
822 unsigned num = va_arg(ap, unsigned);
823 be_emit_irprintf("%u", num);
828 if (mod & EMIT_LONG) {
829 long num = va_arg(ap, long);
830 be_emit_irprintf("%ld", num);
832 int num = va_arg(ap, int);
833 be_emit_irprintf("%d", num);
839 panic("unknown format conversion in ia32_emitf()");
847 * Emits registers and/or address mode of a binary operation.
849 void ia32_emit_binop(const ir_node *node)
851 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
852 ia32_emitf(node, "%#S4, %#AS3");
854 ia32_emitf(node, "%#AS4, %#S3");
859 * Emits registers and/or address mode of a binary operation.
861 void ia32_emit_x87_binop(const ir_node *node)
863 switch(get_ia32_op_type(node)) {
866 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
867 const arch_register_t *in1 = x87_attr->x87[0];
868 const arch_register_t *in = x87_attr->x87[1];
869 const arch_register_t *out = x87_attr->x87[2];
873 } else if (out == in) {
878 be_emit_string(arch_register_get_name(in));
879 be_emit_cstring(", %");
880 be_emit_string(arch_register_get_name(out));
888 assert(0 && "unsupported op type");
893 * Emits registers and/or address mode of a unary operation.
895 void ia32_emit_unop(const ir_node *node, int pos)
899 ia32_emitf(node, fmt);
902 static void emit_ia32_IMul(const ir_node *node)
904 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
905 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
907 /* do we need the 3-address form? */
908 if (is_ia32_NoReg_GP(left) ||
909 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
910 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
912 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
917 * walks up a tree of copies/perms/spills/reloads to find the original value
918 * that is moved around
920 static ir_node *find_original_value(ir_node *node)
922 if (irn_visited(node))
925 mark_irn_visited(node);
926 if (be_is_Copy(node)) {
927 return find_original_value(be_get_Copy_op(node));
928 } else if (be_is_CopyKeep(node)) {
929 return find_original_value(be_get_CopyKeep_op(node));
930 } else if (is_Proj(node)) {
931 ir_node *pred = get_Proj_pred(node);
932 if (be_is_Perm(pred)) {
933 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
934 } else if (be_is_MemPerm(pred)) {
935 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
936 } else if (is_ia32_Load(pred)) {
937 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
941 } else if (is_ia32_Store(node)) {
942 return find_original_value(get_irn_n(node, n_ia32_Store_val));
943 } else if (is_Phi(node)) {
945 arity = get_irn_arity(node);
946 for (i = 0; i < arity; ++i) {
947 ir_node *in = get_irn_n(node, i);
948 ir_node *res = find_original_value(in);
959 static int determine_final_pnc(const ir_node *node, int flags_pos, int pnc)
961 ir_node *flags = get_irn_n(node, flags_pos);
962 const ia32_attr_t *flags_attr;
963 flags = skip_Proj(flags);
965 if (is_ia32_Sahf(flags)) {
966 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
967 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
968 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
969 inc_irg_visited(current_ir_graph);
970 cmp = find_original_value(cmp);
972 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
973 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
976 flags_attr = get_ia32_attr_const(cmp);
977 if (flags_attr->data.ins_permuted)
978 pnc = get_mirrored_pnc(pnc);
979 pnc |= ia32_pn_Cmp_float;
980 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
981 || is_ia32_Fucompi(flags)) {
982 flags_attr = get_ia32_attr_const(flags);
984 if (flags_attr->data.ins_permuted)
985 pnc = get_mirrored_pnc(pnc);
986 pnc |= ia32_pn_Cmp_float;
988 flags_attr = get_ia32_attr_const(flags);
990 if (flags_attr->data.ins_permuted)
991 pnc = get_mirrored_pnc(pnc);
992 if (flags_attr->data.cmp_unsigned)
993 pnc |= ia32_pn_Cmp_unsigned;
999 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
1001 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
1002 return get_negated_pnc(pnc, mode);
1005 void ia32_emit_cmp_suffix_node(const ir_node *node,
1008 const ia32_attr_t *attr = get_ia32_attr_const(node);
1010 pn_Cmp pnc = get_ia32_condcode(node);
1012 pnc = determine_final_pnc(node, flags_pos, pnc);
1013 if (attr->data.ins_permuted)
1014 pnc = get_inversed_pnc(pnc);
1016 ia32_emit_cmp_suffix(pnc);
1020 * Emits an exception label for a given node.
1022 static void ia32_emit_exc_label(const ir_node *node)
1024 be_emit_string(be_gas_insn_label_prefix());
1025 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1029 * Returns the Proj with projection number proj and NOT mode_M
1031 static ir_node *get_proj(const ir_node *node, long proj)
1033 const ir_edge_t *edge;
1036 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1038 foreach_out_edge(node, edge) {
1039 src = get_edge_src_irn(edge);
1041 assert(is_Proj(src) && "Proj expected");
1042 if (get_irn_mode(src) == mode_M)
1045 if (get_Proj_proj(src) == proj)
1051 static int can_be_fallthrough(const ir_node *node)
1053 ir_node *target_block = get_cfop_target_block(node);
1054 ir_node *block = get_nodes_block(node);
1055 return get_prev_block_sched(target_block) == block;
1059 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1061 static void emit_ia32_Jcc(const ir_node *node)
1063 int need_parity_label = 0;
1064 const ir_node *proj_true;
1065 const ir_node *proj_false;
1066 const ir_node *block;
1067 pn_Cmp pnc = get_ia32_condcode(node);
1069 pnc = determine_final_pnc(node, 0, pnc);
1071 /* get both Projs */
1072 proj_true = get_proj(node, pn_ia32_Jcc_true);
1073 assert(proj_true && "Jcc without true Proj");
1075 proj_false = get_proj(node, pn_ia32_Jcc_false);
1076 assert(proj_false && "Jcc without false Proj");
1078 block = get_nodes_block(node);
1080 if (can_be_fallthrough(proj_true)) {
1081 /* exchange both proj's so the second one can be omitted */
1082 const ir_node *t = proj_true;
1084 proj_true = proj_false;
1086 pnc = ia32_get_negated_pnc(pnc);
1089 if (pnc & ia32_pn_Cmp_float) {
1090 /* Some floating point comparisons require a test of the parity flag,
1091 * which indicates that the result is unordered */
1092 switch (pnc & 0x0f) {
1094 ia32_emitf(proj_true, "\tjp %L\n");
1099 ia32_emitf(proj_true, "\tjnp %L\n");
1105 /* we need a local label if the false proj is a fallthrough
1106 * as the falseblock might have no label emitted then */
1107 if (can_be_fallthrough(proj_false)) {
1108 need_parity_label = 1;
1109 ia32_emitf(proj_false, "\tjp 1f\n");
1111 ia32_emitf(proj_false, "\tjp %L\n");
1118 ia32_emitf(proj_true, "\tjp %L\n");
1126 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1129 if (need_parity_label) {
1130 ia32_emitf(NULL, "1:\n");
1133 /* the second Proj might be a fallthrough */
1134 if (can_be_fallthrough(proj_false)) {
1135 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1137 ia32_emitf(proj_false, "\tjmp %L\n");
1142 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1145 static void emit_ia32_Setcc(const ir_node *node)
1147 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1149 pn_Cmp pnc = get_ia32_condcode(node);
1150 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1151 if (pnc & ia32_pn_Cmp_float) {
1152 switch (pnc & 0x0f) {
1154 ia32_emitf(node, "\tsetp %#R\n", dreg);
1158 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1164 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1165 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1166 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1172 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1173 ia32_emitf(node, "\tsetp %>R\n", dreg);
1174 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1181 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1184 static void emit_ia32_CMovcc(const ir_node *node)
1186 const ia32_attr_t *attr = get_ia32_attr_const(node);
1187 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1188 pn_Cmp pnc = get_ia32_condcode(node);
1189 const arch_register_t *in_true;
1190 const arch_register_t *in_false;
1192 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1193 /* although you can't set ins_permuted in the constructor it might still
1194 be set by memory operand folding */
1195 if (attr->data.ins_permuted)
1196 pnc = get_inversed_pnc(pnc);
1198 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1199 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1201 /* should be same constraint fullfilled? */
1202 if (out == in_false) {
1203 /* yes -> nothing to do */
1204 } else if (out == in_true) {
1205 const arch_register_t *tmp;
1207 assert(get_ia32_op_type(node) == ia32_Normal);
1209 pnc = ia32_get_negated_pnc(pnc);
1216 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1219 /* TODO: handling of Nans isn't correct yet */
1220 if (pnc & ia32_pn_Cmp_float) {
1221 switch (pnc & 0x0f) {
1230 panic("CMov with floatingpoint compare/parity not supported yet");
1234 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1237 /*********************************************************
1240 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1241 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1242 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1243 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1246 *********************************************************/
1248 /* jump table entry (target and corresponding number) */
1249 typedef struct _branch_t {
1254 /* jump table for switch generation */
1255 typedef struct _jmp_tbl_t {
1256 ir_node *defProj; /**< default target */
1257 long min_value; /**< smallest switch case */
1258 long max_value; /**< largest switch case */
1259 long num_branches; /**< number of jumps */
1260 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1261 branch_t *branches; /**< jump array */
1265 * Compare two variables of type branch_t. Used to sort all switch cases
1267 static int ia32_cmp_branch_t(const void *a, const void *b)
1269 branch_t *b1 = (branch_t *)a;
1270 branch_t *b2 = (branch_t *)b;
1272 if (b1->value <= b2->value)
1278 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1284 const ir_edge_t *edge;
1286 /* fill the table structure */
1287 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, ".TBL_");
1288 tbl->defProj = NULL;
1289 tbl->num_branches = get_irn_n_edges(node) - 1;
1290 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1291 tbl->min_value = LONG_MAX;
1292 tbl->max_value = LONG_MIN;
1294 default_pn = get_ia32_condcode(node);
1296 /* go over all proj's and collect them */
1297 foreach_out_edge(node, edge) {
1298 proj = get_edge_src_irn(edge);
1299 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1301 pnc = get_Proj_proj(proj);
1303 /* check for default proj */
1304 if (pnc == default_pn) {
1305 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1306 tbl->defProj = proj;
1308 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1309 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1311 /* create branch entry */
1312 tbl->branches[i].target = proj;
1313 tbl->branches[i].value = pnc;
1318 assert(i == tbl->num_branches);
1320 /* sort the branches by their number */
1321 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1325 * Emits code for a SwitchJmp (creates a jump table if
1326 * possible otherwise a cmp-jmp cascade). Port from
1329 static void emit_ia32_SwitchJmp(const ir_node *node)
1331 unsigned long interval;
1335 /* fill the table structure */
1336 generate_jump_table(&tbl, node);
1338 /* two-complement's magic make this work without overflow */
1339 interval = tbl.max_value - tbl.min_value;
1341 /* emit the table */
1342 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1343 ia32_emitf(tbl.defProj, "\tja %L\n");
1345 if (tbl.num_branches > 1) {
1347 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1349 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1350 ia32_emitf(NULL, "\t.align 4\n");
1351 ia32_emitf(NULL, "%s:\n", tbl.label);
1353 last_value = tbl.branches[0].value;
1354 for (i = 0; i != tbl.num_branches; ++i) {
1355 while (last_value != tbl.branches[i].value) {
1356 ia32_emitf(tbl.defProj, ".long %L\n");
1359 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1362 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1364 /* one jump is enough */
1365 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1372 * Emits code for a unconditional jump.
1374 static void emit_ia32_Jmp(const ir_node *node)
1378 /* for now, the code works for scheduled and non-schedules blocks */
1379 block = get_nodes_block(node);
1381 /* we have a block schedule */
1382 if (can_be_fallthrough(node)) {
1383 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1385 ia32_emitf(node, "\tjmp %L\n");
1390 * Emit an inline assembler operand.
1392 * @param node the ia32_ASM node
1393 * @param s points to the operand (a %c)
1395 * @return pointer to the first char in s NOT in the current operand
1397 static const char* emit_asm_operand(const ir_node *node, const char *s)
1399 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1400 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1402 const arch_register_t *reg;
1403 const ia32_asm_reg_t *asm_regs = attr->register_map;
1404 const ia32_asm_reg_t *asm_reg;
1405 const char *reg_name;
1414 /* parse modifiers */
1417 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1442 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1449 sscanf(s, "%d%n", &num, &p);
1451 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1458 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1460 "Error: Custom assembler references invalid input/output (%+F)\n",
1464 asm_reg = & asm_regs[num];
1465 assert(asm_reg->valid);
1468 if (asm_reg->use_input == 0) {
1469 reg = get_out_reg(node, asm_reg->inout_pos);
1471 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1473 /* might be an immediate value */
1474 if (is_ia32_Immediate(pred)) {
1475 emit_ia32_Immediate(pred);
1478 reg = get_in_reg(node, asm_reg->inout_pos);
1482 "Warning: no register assigned for %d asm op (%+F)\n",
1487 if (asm_reg->memory) {
1492 if (modifier != 0) {
1496 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1499 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1502 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1505 panic("Invalid asm op modifier");
1507 be_emit_string(reg_name);
1509 emit_register(reg, asm_reg->mode);
1512 if (asm_reg->memory) {
1520 * Emits code for an ASM pseudo op.
1522 static void emit_ia32_Asm(const ir_node *node)
1524 const void *gen_attr = get_irn_generic_attr_const(node);
1525 const ia32_asm_attr_t *attr
1526 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1527 ident *asm_text = attr->asm_text;
1528 const char *s = get_id_str(asm_text);
1530 ia32_emitf(node, "#APP\t\n");
1537 s = emit_asm_operand(node, s);
1543 ia32_emitf(NULL, "\n#NO_APP\n");
1546 /**********************************
1549 * | | ___ _ __ _ _| |_) |
1550 * | | / _ \| '_ \| | | | _ <
1551 * | |___| (_) | |_) | |_| | |_) |
1552 * \_____\___/| .__/ \__, |____/
1555 **********************************/
1558 * Emit movsb/w instructions to make mov count divideable by 4
1560 static void emit_CopyB_prolog(unsigned size)
1563 ia32_emitf(NULL, "\tmovsb\n");
1565 ia32_emitf(NULL, "\tmovsw\n");
1569 * Emit rep movsd instruction for memcopy.
1571 static void emit_ia32_CopyB(const ir_node *node)
1573 unsigned size = get_ia32_copyb_size(node);
1575 emit_CopyB_prolog(size);
1576 ia32_emitf(node, "\trep movsd\n");
1580 * Emits unrolled memcopy.
1582 static void emit_ia32_CopyB_i(const ir_node *node)
1584 unsigned size = get_ia32_copyb_size(node);
1586 emit_CopyB_prolog(size);
1590 ia32_emitf(NULL, "\tmovsd\n");
1596 /***************************
1600 * | | / _ \| '_ \ \ / /
1601 * | |___| (_) | | | \ V /
1602 * \_____\___/|_| |_|\_/
1604 ***************************/
1607 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1609 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1612 ir_mode *ls_mode = get_ia32_ls_mode(node);
1613 int ls_bits = get_mode_size_bits(ls_mode);
1614 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1616 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1619 static void emit_ia32_Conv_I2FP(const ir_node *node)
1621 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1624 static void emit_ia32_Conv_FP2I(const ir_node *node)
1626 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1629 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1631 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1635 * Emits code for an Int conversion.
1637 static void emit_ia32_Conv_I2I(const ir_node *node)
1639 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1640 int signed_mode = mode_is_signed(smaller_mode);
1641 const char *sign_suffix;
1643 assert(!mode_is_float(smaller_mode));
1645 sign_suffix = signed_mode ? "s" : "z";
1646 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1652 static void emit_ia32_Call(const ir_node *node)
1654 /* Special case: Call must not have its immediates prefixed by $, instead
1655 * address mode is prefixed by *. */
1656 ia32_emitf(node, "\tcall %*AS3\n");
1660 /*******************************************
1663 * | |__ ___ _ __ ___ __| | ___ ___
1664 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1665 * | |_) | __/ | | | (_) | (_| | __/\__ \
1666 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1668 *******************************************/
1671 * Emits code to increase stack pointer.
1673 static void emit_be_IncSP(const ir_node *node)
1675 int offs = be_get_IncSP_offset(node);
1681 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1683 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1687 static inline bool is_unknown_reg(const arch_register_t *reg)
1689 if(reg == &ia32_gp_regs[REG_GP_UKNWN]
1690 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1691 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1698 * Emits code for Copy/CopyKeep.
1700 static void Copy_emitter(const ir_node *node, const ir_node *op)
1702 const arch_register_t *in = arch_get_irn_register(op);
1703 const arch_register_t *out = arch_get_irn_register(node);
1708 if (is_unknown_reg(in))
1710 /* copies of vf nodes aren't real... */
1711 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1714 if (get_irn_mode(node) == mode_E) {
1715 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1717 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1721 static void emit_be_Copy(const ir_node *node)
1723 Copy_emitter(node, be_get_Copy_op(node));
1726 static void emit_be_CopyKeep(const ir_node *node)
1728 Copy_emitter(node, be_get_CopyKeep_op(node));
1732 * Emits code for exchange.
1734 static void emit_be_Perm(const ir_node *node)
1736 const arch_register_t *in0, *in1;
1737 const arch_register_class_t *cls0, *cls1;
1739 in0 = arch_get_irn_register(get_irn_n(node, 0));
1740 in1 = arch_get_irn_register(get_irn_n(node, 1));
1742 cls0 = arch_register_get_class(in0);
1743 cls1 = arch_register_get_class(in1);
1745 assert(cls0 == cls1 && "Register class mismatch at Perm");
1747 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1748 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1749 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1750 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1751 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1752 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1753 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1755 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1758 panic("unexpected register class in be_Perm (%+F)", node);
1763 * Emits code for Constant loading.
1765 static void emit_ia32_Const(const ir_node *node)
1767 ia32_emitf(node, "\tmovl %I, %D0\n");
1771 * Emits code to load the TLS base
1773 static void emit_ia32_LdTls(const ir_node *node)
1775 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1778 /* helper function for emit_ia32_Minus64Bit */
1779 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1781 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1784 /* helper function for emit_ia32_Minus64Bit */
1785 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1787 ia32_emitf(node, "\tnegl %R\n", reg);
1790 /* helper function for emit_ia32_Minus64Bit */
1791 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1793 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1796 /* helper function for emit_ia32_Minus64Bit */
1797 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1799 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1802 /* helper function for emit_ia32_Minus64Bit */
1803 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1805 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1808 /* helper function for emit_ia32_Minus64Bit */
1809 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1811 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1814 static void emit_ia32_Minus64Bit(const ir_node *node)
1816 const arch_register_t *in_lo = get_in_reg(node, 0);
1817 const arch_register_t *in_hi = get_in_reg(node, 1);
1818 const arch_register_t *out_lo = get_out_reg(node, 0);
1819 const arch_register_t *out_hi = get_out_reg(node, 1);
1821 if (out_lo == in_lo) {
1822 if (out_hi != in_hi) {
1823 /* a -> a, b -> d */
1826 /* a -> a, b -> b */
1829 } else if (out_lo == in_hi) {
1830 if (out_hi == in_lo) {
1831 /* a -> b, b -> a */
1832 emit_xchg(node, in_lo, in_hi);
1835 /* a -> b, b -> d */
1836 emit_mov(node, in_hi, out_hi);
1837 emit_mov(node, in_lo, out_lo);
1841 if (out_hi == in_lo) {
1842 /* a -> c, b -> a */
1843 emit_mov(node, in_lo, out_lo);
1845 } else if (out_hi == in_hi) {
1846 /* a -> c, b -> b */
1847 emit_mov(node, in_lo, out_lo);
1850 /* a -> c, b -> d */
1851 emit_mov(node, in_lo, out_lo);
1857 emit_neg( node, out_hi);
1858 emit_neg( node, out_lo);
1859 emit_sbb0(node, out_hi);
1863 emit_zero(node, out_hi);
1864 emit_neg( node, out_lo);
1865 emit_sbb( node, in_hi, out_hi);
1868 static void emit_ia32_GetEIP(const ir_node *node)
1870 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1871 ia32_emitf(NULL, "%s:\n", pic_base_label);
1872 ia32_emitf(node, "\tpopl %D0\n");
1875 static void emit_ia32_ClimbFrame(const ir_node *node)
1877 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1879 ia32_emitf(node, "\tmovl %S0, %D0\n");
1880 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1881 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1882 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1883 ia32_emitf(node, "\tdec %S1\n");
1884 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1887 static void emit_be_Return(const ir_node *node)
1889 unsigned pop = be_Return_get_pop(node);
1891 if (pop > 0 || be_Return_get_emit_pop(node)) {
1892 ia32_emitf(node, "\tret $%u\n", pop);
1894 ia32_emitf(node, "\tret\n");
1898 static void emit_Nothing(const ir_node *node)
1904 /***********************************************************************************
1907 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1908 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1909 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1910 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1912 ***********************************************************************************/
1915 * Enters the emitter functions for handled nodes into the generic
1916 * pointer of an opcode.
1918 static void ia32_register_emitters(void)
1920 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1921 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1922 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1923 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1924 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1925 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1927 /* first clear the generic function pointer for all ops */
1928 clear_irp_opcodes_generic_func();
1930 /* register all emitter functions defined in spec */
1931 ia32_register_spec_emitters();
1933 /* other ia32 emitter functions */
1934 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1939 IA32_EMIT(Conv_FP2FP);
1940 IA32_EMIT(Conv_FP2I);
1941 IA32_EMIT(Conv_I2FP);
1942 IA32_EMIT(Conv_I2I);
1950 IA32_EMIT(Minus64Bit);
1951 IA32_EMIT(SwitchJmp);
1952 IA32_EMIT(ClimbFrame);
1955 /* benode emitter */
1976 typedef void (*emit_func_ptr) (const ir_node *);
1979 * Assign and emit an exception label if the current instruction can fail.
1981 static void ia32_assign_exc_label(ir_node *node)
1983 /* assign a new ID to the instruction */
1984 set_ia32_exc_label_id(node, ++exc_label_id);
1986 ia32_emit_exc_label(node);
1988 be_emit_pad_comment();
1989 be_emit_cstring("/* exception to Block ");
1990 ia32_emit_cfop_target(node);
1991 be_emit_cstring(" */\n");
1992 be_emit_write_line();
1996 * Emits code for a node.
1998 static void ia32_emit_node(ir_node *node)
2000 ir_op *op = get_irn_op(node);
2002 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2004 if (is_ia32_irn(node)) {
2005 if (get_ia32_exc_label(node)) {
2006 /* emit the exception label of this instruction */
2007 ia32_assign_exc_label(node);
2009 if (mark_spill_reload) {
2010 if (is_ia32_is_spill(node)) {
2011 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
2013 if (is_ia32_is_reload(node)) {
2014 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
2016 if (is_ia32_is_remat(node)) {
2017 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
2021 if (op->ops.generic) {
2022 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2024 be_dbg_set_dbg_info(get_irn_dbg_info(node));
2029 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
2035 * Emits gas alignment directives
2037 static void ia32_emit_alignment(unsigned align, unsigned skip)
2039 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
2043 * Emits gas alignment directives for Labels depended on cpu architecture.
2045 static void ia32_emit_align_label(void)
2047 unsigned align = ia32_cg_config.label_alignment;
2048 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
2049 ia32_emit_alignment(align, maximum_skip);
2053 * Test whether a block should be aligned.
2054 * For cpus in the P4/Athlon class it is useful to align jump labels to
2055 * 16 bytes. However we should only do that if the alignment nops before the
2056 * label aren't executed more often than we have jumps to the label.
2058 static int should_align_block(const ir_node *block)
2060 static const double DELTA = .0001;
2061 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2062 ir_node *prev = get_prev_block_sched(block);
2064 double prev_freq = 0; /**< execfreq of the fallthrough block */
2065 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2068 if (exec_freq == NULL)
2070 if (ia32_cg_config.label_alignment_factor <= 0)
2073 block_freq = get_block_execfreq(exec_freq, block);
2074 if (block_freq < DELTA)
2077 n_cfgpreds = get_Block_n_cfgpreds(block);
2078 for(i = 0; i < n_cfgpreds; ++i) {
2079 const ir_node *pred = get_Block_cfgpred_block(block, i);
2080 double pred_freq = get_block_execfreq(exec_freq, pred);
2083 prev_freq += pred_freq;
2085 jmp_freq += pred_freq;
2089 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2092 jmp_freq /= prev_freq;
2094 return jmp_freq > ia32_cg_config.label_alignment_factor;
2098 * Emit the block header for a block.
2100 * @param block the block
2101 * @param prev_block the previous block
2103 static void ia32_emit_block_header(ir_node *block)
2105 ir_graph *irg = current_ir_graph;
2106 int need_label = block_needs_label(block);
2108 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2110 if (block == get_irg_end_block(irg))
2113 if (ia32_cg_config.label_alignment > 0) {
2114 /* align the current block if:
2115 * a) if should be aligned due to its execution frequency
2116 * b) there is no fall-through here
2118 if (should_align_block(block)) {
2119 ia32_emit_align_label();
2121 /* if the predecessor block has no fall-through,
2122 we can always align the label. */
2124 int has_fallthrough = 0;
2126 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2127 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2128 if (can_be_fallthrough(cfg_pred)) {
2129 has_fallthrough = 1;
2134 if (!has_fallthrough)
2135 ia32_emit_align_label();
2140 ia32_emit_block_name(block);
2143 be_emit_pad_comment();
2144 be_emit_cstring(" /* ");
2146 be_emit_cstring("\t/* ");
2147 ia32_emit_block_name(block);
2148 be_emit_cstring(": ");
2151 be_emit_cstring("preds:");
2153 /* emit list of pred blocks in comment */
2154 arity = get_irn_arity(block);
2156 be_emit_cstring(" none");
2158 for (i = 0; i < arity; ++i) {
2159 ir_node *predblock = get_Block_cfgpred_block(block, i);
2160 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2163 if (exec_freq != NULL) {
2164 be_emit_irprintf(", freq: %f",
2165 get_block_execfreq(exec_freq, block));
2167 be_emit_cstring(" */\n");
2168 be_emit_write_line();
2172 * Walks over the nodes in a block connected by scheduling edges
2173 * and emits code for each node.
2175 static void ia32_gen_block(ir_node *block)
2179 ia32_emit_block_header(block);
2181 /* emit the contents of the block */
2182 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2183 sched_foreach(block, node) {
2184 ia32_emit_node(node);
2188 typedef struct exc_entry {
2189 ir_node *exc_instr; /** The instruction that can issue an exception. */
2190 ir_node *block; /** The block to call then. */
2195 * Sets labels for control flow nodes (jump target).
2196 * Links control predecessors to there destination blocks.
2198 static void ia32_gen_labels(ir_node *block, void *data)
2200 exc_entry **exc_list = data;
2204 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2205 pred = get_Block_cfgpred(block, n);
2206 set_irn_link(pred, block);
2208 pred = skip_Proj(pred);
2209 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2214 ARR_APP1(exc_entry, *exc_list, e);
2215 set_irn_link(pred, block);
2221 * Compare two exception_entries.
2223 static int cmp_exc_entry(const void *a, const void *b)
2225 const exc_entry *ea = a;
2226 const exc_entry *eb = b;
2228 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2234 * Main driver. Emits the code for one routine.
2236 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2238 ir_entity *entity = get_irg_entity(irg);
2239 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2244 do_pic = cg->birg->main_env->options->pic;
2246 be_gas_elf_type_char = '@';
2248 ia32_register_emitters();
2250 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2252 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2253 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2255 /* we use links to point to target blocks */
2256 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2257 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2259 /* initialize next block links */
2260 n = ARR_LEN(cg->blk_sched);
2261 for (i = 0; i < n; ++i) {
2262 ir_node *block = cg->blk_sched[i];
2263 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2265 set_irn_link(block, prev);
2268 for (i = 0; i < n; ++i) {
2269 ir_node *block = cg->blk_sched[i];
2271 ia32_gen_block(block);
2274 be_gas_emit_function_epilog(entity);
2275 be_dbg_method_end();
2277 be_emit_write_line();
2279 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2281 /* Sort the exception table using the exception label id's.
2282 Those are ascending with ascending addresses. */
2283 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2287 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2288 be_emit_cstring("\t.long ");
2289 ia32_emit_exc_label(exc_list[i].exc_instr);
2291 be_emit_cstring("\t.long ");
2292 ia32_emit_block_name(exc_list[i].block);
2296 DEL_ARR_F(exc_list);
2299 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2300 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2304 /* ==== Experimental binary emitter ==== */
2306 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2307 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2308 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2309 static unsigned char pnc_map_signed[8];
2310 static unsigned char pnc_map_unsigned[8];
2312 static void build_reg_map(void)
2314 reg_gp_map[REG_EAX] = 0x0;
2315 reg_gp_map[REG_ECX] = 0x1;
2316 reg_gp_map[REG_EDX] = 0x2;
2317 reg_gp_map[REG_EBX] = 0x3;
2318 reg_gp_map[REG_ESP] = 0x4;
2319 reg_gp_map[REG_EBP] = 0x5;
2320 reg_gp_map[REG_ESI] = 0x6;
2321 reg_gp_map[REG_EDI] = 0x7;
2323 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2324 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2325 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2326 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2327 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2328 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2330 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2331 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2332 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2333 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2334 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2335 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2338 /** Returns the encoding for a pnc field. */
2339 static unsigned char pnc2cc(int pnc)
2342 if (pnc == ia32_pn_Cmp_parity) {
2344 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2345 cc = pnc_map_unsigned[pnc & 0x07];
2347 cc = pnc_map_signed[pnc & 0x07];
2353 /** Sign extension bit values for binops */
2355 UNSIGNED_IMM = 0, /**< unsigned immediate */
2356 SIGNEXT_IMM = 2, /**< sign extended immediate */
2359 /** The mod encoding of the ModR/M */
2361 MOD_IND = 0x00, /**< [reg1] */
2362 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2363 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2364 MOD_REG = 0xC0 /**< reg1 */
2367 /** create R/M encoding for ModR/M */
2368 #define ENC_RM(x) (x)
2369 /** create REG encoding for ModR/M */
2370 #define ENC_REG(x) ((x) << 3)
2372 /** create encoding for a SIB byte */
2373 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2375 /* Node: The following routines are supposed to append bytes, words, dwords
2376 to the output stream.
2377 Currently the implementation is stupid in that it still creates output
2378 for an "assembler" in the form of .byte, .long
2379 We will change this when enough infrastructure is there to create complete
2380 machine code in memory/object files */
2382 static void bemit8(const unsigned char byte)
2384 be_emit_irprintf("\t.byte 0x%x\n", byte);
2385 be_emit_write_line();
2388 static void bemit16(const unsigned short u16)
2390 be_emit_irprintf("\t.word 0x%x\n", u16);
2391 be_emit_write_line();
2394 static void bemit32(const unsigned u32)
2396 be_emit_irprintf("\t.long 0x%x\n", u32);
2397 be_emit_write_line();
2401 * Emit address of an entity. If @p is_relative is true then a relative
2402 * offset from behind the address to the entity is created.
2404 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2407 if (entity == NULL) {
2412 /* the final version should remember the position in the bytestream
2413 and patch it with the correct address at linktime... */
2414 be_emit_cstring("\t.long ");
2417 be_gas_emit_entity(entity);
2419 if (get_entity_owner(entity) == get_tls_type()) {
2420 if (get_entity_visibility(entity) == ir_visibility_external) {
2421 be_emit_cstring("@INDNTPOFF");
2423 be_emit_cstring("@NTPOFF");
2428 be_emit_cstring("-.");
2433 be_emit_irprintf("%+d", offset);
2436 be_emit_write_line();
2439 static void bemit_jmp_destination(const ir_node *dest_block)
2441 be_emit_cstring("\t.long ");
2442 ia32_emit_block_name(dest_block);
2443 be_emit_cstring(" - . - 4\n");
2444 be_emit_write_line();
2447 /* end emit routines, all emitters following here should only use the functions
2450 typedef enum reg_modifier {
2455 /** Create a ModR/M byte for src1,src2 registers */
2456 static void bemit_modrr(const arch_register_t *src1,
2457 const arch_register_t *src2)
2459 unsigned char modrm = MOD_REG;
2460 modrm |= ENC_RM(reg_gp_map[src1->index]);
2461 modrm |= ENC_REG(reg_gp_map[src2->index]);
2465 /** Create a ModR/M8 byte for src1,src2 registers */
2466 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2467 reg_modifier_t high_part2, const arch_register_t *src2)
2469 unsigned char modrm = MOD_REG;
2470 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2471 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2475 /** Create a ModR/M byte for one register and extension */
2476 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2478 unsigned char modrm = MOD_REG;
2480 modrm |= ENC_RM(reg_gp_map[reg->index]);
2481 modrm |= ENC_REG(ext);
2485 /** Create a ModR/M8 byte for one register */
2486 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2488 unsigned char modrm = MOD_REG;
2489 assert(reg_gp_map[reg->index] < 4);
2490 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2496 * Calculate the size of an signed immediate in bytes.
2498 * @param offset an offset
2500 static unsigned get_signed_imm_size(int offset)
2502 if (-128 <= offset && offset < 128) {
2504 } else if (-32768 <= offset && offset < 32768) {
2512 * Emit an address mode.
2514 * @param reg content of the reg field: either a register index or an opcode extension
2515 * @param node the node
2517 static void bemit_mod_am(unsigned reg, const ir_node *node)
2519 ir_entity *ent = get_ia32_am_sc(node);
2520 int offs = get_ia32_am_offs_int(node);
2521 ir_node *base = get_irn_n(node, n_ia32_base);
2522 int has_base = !is_ia32_NoReg_GP(base);
2523 ir_node *index = get_irn_n(node, n_ia32_index);
2524 int has_index = !is_ia32_NoReg_GP(index);
2527 unsigned emitoffs = 0;
2528 bool emitsib = false;
2531 /* set the mod part depending on displacement */
2533 modrm |= MOD_IND_WORD_OFS;
2535 } else if (offs == 0) {
2538 } else if (-128 <= offs && offs < 128) {
2539 modrm |= MOD_IND_BYTE_OFS;
2542 modrm |= MOD_IND_WORD_OFS;
2547 const arch_register_t *base_reg = arch_get_irn_register(base);
2548 base_enc = reg_gp_map[base_reg->index];
2550 /* Use the EBP encoding + MOD_IND if NO base register. There is
2551 * always a 32bit offset present in this case. */
2557 /* Determine if we need a SIB byte. */
2559 const arch_register_t *reg_index = arch_get_irn_register(index);
2560 int scale = get_ia32_am_scale(node);
2562 /* R/M set to ESP means SIB in 32bit mode. */
2563 modrm |= ENC_RM(0x04);
2564 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2566 } else if (base_enc == 0x04) {
2567 /* for the above reason we are forced to emit a SIB when base is ESP.
2568 * Only the base is used, index must be ESP too, which means no index.
2570 modrm |= ENC_RM(0x04);
2571 sib = ENC_SIB(0, 0x04, 0x04);
2574 modrm |= ENC_RM(base_enc);
2577 /* We are forced to emit an 8bit offset as EBP base without offset is a
2578 * special case for SIB without base register. */
2579 if (base_enc == 0x05 && emitoffs == 0) {
2580 modrm |= MOD_IND_BYTE_OFS;
2584 modrm |= ENC_REG(reg);
2590 /* emit displacement */
2591 if (emitoffs == 8) {
2592 bemit8((unsigned) offs);
2593 } else if (emitoffs == 32) {
2594 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2599 * Emit a binop with a immediate operand.
2601 * @param node the node to emit
2602 * @param opcode_eax the opcode for the op eax, imm variant
2603 * @param opcode the opcode for the reg, imm variant
2604 * @param ruval the opcode extension for opcode
2606 static void bemit_binop_with_imm(
2607 const ir_node *node,
2608 unsigned char opcode_ax,
2609 unsigned char opcode, unsigned char ruval)
2611 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2612 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2613 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2616 /* Some instructions (test) have no short form with 32bit value + 8bit
2618 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2621 /* check for sign extension */
2622 size = get_signed_imm_size(attr->offset);
2627 bemit8(opcode | SIGNEXT_IMM);
2628 /* cmp has this special mode */
2629 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2630 bemit_mod_am(ruval, node);
2632 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2633 bemit_modru(reg, ruval);
2635 bemit8((unsigned char)attr->offset);
2639 /* check for eax variant: this variant is shorter for 32bit immediates only */
2640 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2642 bemit_mod_am(ruval, node);
2644 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2645 if (reg->index == REG_EAX) {
2649 bemit_modru(reg, ruval);
2652 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2655 panic("invalid imm size?!?");
2661 static void bemit_binop_2(const ir_node *node, unsigned code)
2663 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2665 if (get_ia32_op_type(node) == ia32_Normal) {
2666 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2667 bemit_modrr(op2, out);
2669 bemit_mod_am(reg_gp_map[out->index], node);
2676 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2678 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2679 if (is_ia32_Immediate(right)) {
2680 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2682 bemit_binop_2(node, opcodes[0]);
2689 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2692 if (get_ia32_op_type(node) == ia32_Normal) {
2693 const arch_register_t *in = get_in_reg(node, input);
2694 bemit_modru(in, ext);
2696 bemit_mod_am(ext, node);
2700 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2702 const arch_register_t *out = get_out_reg(node, 0);
2703 bemit_unop(node, code, reg_gp_map[out->index], input);
2706 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2708 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2711 bemit8(size == 8 ? code : code + 1);
2712 bemit_mod_am(ext, node);
2715 static void bemit_immediate(const ir_node *node, bool relative)
2717 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2718 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2721 static void bemit_copy(const ir_node *copy)
2723 const arch_register_t *in = get_in_reg(copy, 0);
2724 const arch_register_t *out = get_out_reg(copy, 0);
2726 if (in == out || is_unknown_reg(in))
2728 /* copies of vf nodes aren't real... */
2729 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2732 if (get_irn_mode(copy) == mode_E) {
2735 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2737 bemit_modrr(in, out);
2741 static void bemit_perm(const ir_node *node)
2743 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2744 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2745 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2747 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2749 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2750 if (in0->index == REG_EAX) {
2751 bemit8(0x90 + reg_gp_map[in1->index]);
2752 } else if (in1->index == REG_EAX) {
2753 bemit8(0x90 + reg_gp_map[in0->index]);
2756 bemit_modrr(in0, in1);
2758 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2759 panic("unimplemented"); // TODO implement
2760 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2761 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2762 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2763 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2765 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2768 panic("unexpected register class in be_Perm (%+F)", node);
2772 static void bemit_xor0(const ir_node *node)
2774 const arch_register_t *out = get_out_reg(node, 0);
2776 bemit_modrr(out, out);
2779 static void bemit_mov_const(const ir_node *node)
2781 const arch_register_t *out = get_out_reg(node, 0);
2782 bemit8(0xB8 + reg_gp_map[out->index]);
2783 bemit_immediate(node, false);
2787 * Creates a function for a Binop with 3 possible encodings.
2789 #define BINOP(op, op0, op1, op2, op2_ext) \
2790 static void bemit_ ## op(const ir_node *node) { \
2791 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2792 bemit_binop(node, op ## _codes); \
2795 /* insn def eax,imm imm */
2796 BINOP(add, 0x03, 0x05, 0x81, 0)
2797 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2798 BINOP(adc, 0x13, 0x15, 0x81, 2)
2799 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2800 BINOP(and, 0x23, 0x25, 0x81, 4)
2801 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2802 BINOP(xor, 0x33, 0x35, 0x81, 6)
2803 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2805 #define BINOPMEM(op, ext) \
2806 static void bemit_##op(const ir_node *node) \
2809 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2812 val = get_irn_n(node, n_ia32_unary_op); \
2813 if (is_ia32_Immediate(val)) { \
2814 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2815 int offset = attr->offset; \
2816 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2818 bemit_mod_am(ext, node); \
2822 bemit_mod_am(ext, node); \
2826 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2830 bemit8(ext << 3 | 1); \
2831 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2835 static void bemit_##op##8bit(const ir_node *node) \
2837 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2838 if (is_ia32_Immediate(val)) { \
2840 bemit_mod_am(ext, node); \
2841 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2844 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2856 * Creates a function for an Unop with code /ext encoding.
2858 #define UNOP(op, code, ext, input) \
2859 static void bemit_ ## op(const ir_node *node) { \
2860 bemit_unop(node, code, ext, input); \
2863 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2864 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2865 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2866 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2867 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2868 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2870 /* TODO: am support for IJmp */
2871 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2873 #define SHIFT(op, ext) \
2874 static void bemit_##op(const ir_node *node) \
2876 const arch_register_t *out = get_out_reg(node, 0); \
2877 ir_node *count = get_irn_n(node, 1); \
2878 if (is_ia32_Immediate(count)) { \
2879 int offset = get_ia32_immediate_attr_const(count)->offset; \
2880 if (offset == 1) { \
2882 bemit_modru(out, ext); \
2885 bemit_modru(out, ext); \
2890 bemit_modru(out, ext); \
2894 static void bemit_##op##mem(const ir_node *node) \
2897 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2900 count = get_irn_n(node, 1); \
2901 if (is_ia32_Immediate(count)) { \
2902 int offset = get_ia32_immediate_attr_const(count)->offset; \
2903 if (offset == 1) { \
2904 bemit8(size == 8 ? 0xD0 : 0xD1); \
2905 bemit_mod_am(ext, node); \
2907 bemit8(size == 8 ? 0xC0 : 0xC1); \
2908 bemit_mod_am(ext, node); \
2912 bemit8(size == 8 ? 0xD2 : 0xD3); \
2913 bemit_mod_am(ext, node); \
2923 static void bemit_shld(const ir_node *node)
2925 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2926 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2927 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2929 if (is_ia32_Immediate(count)) {
2931 bemit_modrr(out, in);
2932 bemit8(get_ia32_immediate_attr_const(count)->offset);
2935 bemit_modrr(out, in);
2939 static void bemit_shrd(const ir_node *node)
2941 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2942 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2943 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2945 if (is_ia32_Immediate(count)) {
2947 bemit_modrr(out, in);
2948 bemit8(get_ia32_immediate_attr_const(count)->offset);
2951 bemit_modrr(out, in);
2956 * binary emitter for setcc.
2958 static void bemit_setcc(const ir_node *node)
2960 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2962 pn_Cmp pnc = get_ia32_condcode(node);
2963 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
2964 if (pnc & ia32_pn_Cmp_float) {
2965 switch (pnc & 0x0f) {
2970 bemit_modrm8(REG_LOW, dreg);
2977 bemit_modrm8(REG_LOW, dreg);
2985 bemit8(0x90 | pnc2cc(pnc));
2986 bemit_modrm8(REG_LOW, dreg);
2991 bemit_modrm8(REG_HIGH, dreg);
2993 /* andb %>dreg, %<dreg */
2995 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
3003 bemit8(0x90 | pnc2cc(pnc));
3004 bemit_modrm8(REG_LOW, dreg);
3009 bemit_modrm8(REG_HIGH, dreg);
3011 /* orb %>dreg, %<dreg */
3013 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
3022 bemit8(0x90 | pnc2cc(pnc));
3023 bemit_modrm8(REG_LOW, dreg);
3026 static void bemit_cmovcc(const ir_node *node)
3028 const ia32_attr_t *attr = get_ia32_attr_const(node);
3029 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
3030 pn_Cmp pnc = get_ia32_condcode(node);
3031 const arch_register_t *in_true;
3032 const arch_register_t *in_false;
3034 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
3036 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
3037 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
3039 if (attr->data.ins_permuted)
3040 pnc = get_inversed_pnc(pnc);
3041 /* should be same constraint fullfilled? */
3042 if (out == in_false) {
3043 /* yes -> nothing to do */
3044 } else if (out == in_true) {
3045 assert(get_ia32_op_type(node) == ia32_Normal);
3046 pnc = ia32_get_negated_pnc(pnc);
3050 bemit8(0x8B); // mov %in_false, %out
3051 bemit_modrr(in_false, out);
3054 /* TODO: handling of Nans isn't correct yet */
3057 bemit8(0x40 | pnc2cc(pnc));
3058 if (get_ia32_op_type(node) == ia32_Normal) {
3059 bemit_modrr(in_true, out);
3061 bemit_mod_am(reg_gp_map[out->index], node);
3065 static void bemit_cmp(const ir_node *node)
3067 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
3073 right = get_irn_n(node, n_ia32_binary_right);
3074 if (is_ia32_Immediate(right)) {
3075 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
3076 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
3077 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
3080 if (attr->symconst != NULL) {
3083 /* check for sign extension */
3084 size = get_signed_imm_size(attr->offset);
3089 bemit8(0x81 | SIGNEXT_IMM);
3090 /* cmp has this special mode */
3091 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3092 bemit_mod_am(7, node);
3094 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3095 bemit_modru(reg, 7);
3097 bemit8((unsigned char)attr->offset);
3101 /* check for eax variant: this variant is shorter for 32bit immediates only */
3102 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3104 bemit_mod_am(7, node);
3106 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3107 if (reg->index == REG_EAX) {
3111 bemit_modru(reg, 7);
3114 if (ls_size == 16) {
3115 bemit16(attr->offset);
3117 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3121 panic("invalid imm size?!?");
3123 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3125 if (get_ia32_op_type(node) == ia32_Normal) {
3126 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3127 bemit_modrr(op2, out);
3129 bemit_mod_am(reg_gp_map[out->index], node);
3134 static void bemit_cmp8bit(const ir_node *node)
3136 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3137 if (is_ia32_Immediate(right)) {
3138 if (get_ia32_op_type(node) == ia32_Normal) {
3139 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3140 if (out->index == REG_EAX) {
3144 bemit_modru(out, 7);
3148 bemit_mod_am(7, node);
3150 bemit8(get_ia32_immediate_attr_const(right)->offset);
3152 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3154 if (get_ia32_op_type(node) == ia32_Normal) {
3155 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3156 bemit_modrr(out, in);
3158 bemit_mod_am(reg_gp_map[out->index], node);
3163 static void bemit_test8bit(const ir_node *node)
3165 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3166 if (is_ia32_Immediate(right)) {
3167 if (get_ia32_op_type(node) == ia32_Normal) {
3168 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3169 if (out->index == REG_EAX) {
3173 bemit_modru(out, 0);
3177 bemit_mod_am(0, node);
3179 bemit8(get_ia32_immediate_attr_const(right)->offset);
3181 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3183 if (get_ia32_op_type(node) == ia32_Normal) {
3184 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3185 bemit_modrr(out, in);
3187 bemit_mod_am(reg_gp_map[out->index], node);
3192 static void bemit_imul(const ir_node *node)
3194 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3195 /* Do we need the immediate form? */
3196 if (is_ia32_Immediate(right)) {
3197 int imm = get_ia32_immediate_attr_const(right)->offset;
3198 if (get_signed_imm_size(imm) == 1) {
3199 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3202 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3207 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3211 static void bemit_dec(const ir_node *node)
3213 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3214 bemit8(0x48 + reg_gp_map[out->index]);
3217 static void bemit_inc(const ir_node *node)
3219 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3220 bemit8(0x40 + reg_gp_map[out->index]);
3223 #define UNOPMEM(op, code, ext) \
3224 static void bemit_##op(const ir_node *node) \
3226 bemit_unop_mem(node, code, ext); \
3229 UNOPMEM(notmem, 0xF6, 2)
3230 UNOPMEM(negmem, 0xF6, 3)
3231 UNOPMEM(incmem, 0xFE, 0)
3232 UNOPMEM(decmem, 0xFE, 1)
3234 static void bemit_ldtls(const ir_node *node)
3236 const arch_register_t *out = get_out_reg(node, 0);
3238 bemit8(0x65); // gs:
3239 if (out->index == REG_EAX) {
3240 bemit8(0xA1); // movl 0, %eax
3242 bemit8(0x8B); // movl 0, %reg
3243 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3251 static void bemit_lea(const ir_node *node)
3253 const arch_register_t *out = get_out_reg(node, 0);
3255 bemit_mod_am(reg_gp_map[out->index], node);
3258 /* helper function for bemit_minus64bit */
3259 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3261 bemit8(0x8B); // movl %src, %dst
3262 bemit_modrr(src, dst);
3265 /* helper function for bemit_minus64bit */
3266 static void bemit_helper_neg(const arch_register_t *reg)
3268 bemit8(0xF7); // negl %reg
3269 bemit_modru(reg, 3);
3272 /* helper function for bemit_minus64bit */
3273 static void bemit_helper_sbb0(const arch_register_t *reg)
3275 bemit8(0x83); // sbbl $0, %reg
3276 bemit_modru(reg, 3);
3280 /* helper function for bemit_minus64bit */
3281 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3283 bemit8(0x1B); // sbbl %src, %dst
3284 bemit_modrr(src, dst);
3287 /* helper function for bemit_minus64bit */
3288 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3290 if (src->index == REG_EAX) {
3291 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3292 } else if (dst->index == REG_EAX) {
3293 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3295 bemit8(0x87); // xchgl %src, %dst
3296 bemit_modrr(src, dst);
3300 /* helper function for bemit_minus64bit */
3301 static void bemit_helper_zero(const arch_register_t *reg)
3303 bemit8(0x33); // xorl %reg, %reg
3304 bemit_modrr(reg, reg);
3307 static void bemit_minus64bit(const ir_node *node)
3309 const arch_register_t *in_lo = get_in_reg(node, 0);
3310 const arch_register_t *in_hi = get_in_reg(node, 1);
3311 const arch_register_t *out_lo = get_out_reg(node, 0);
3312 const arch_register_t *out_hi = get_out_reg(node, 1);
3314 if (out_lo == in_lo) {
3315 if (out_hi != in_hi) {
3316 /* a -> a, b -> d */
3319 /* a -> a, b -> b */
3322 } else if (out_lo == in_hi) {
3323 if (out_hi == in_lo) {
3324 /* a -> b, b -> a */
3325 bemit_helper_xchg(in_lo, in_hi);
3328 /* a -> b, b -> d */
3329 bemit_helper_mov(in_hi, out_hi);
3330 bemit_helper_mov(in_lo, out_lo);
3334 if (out_hi == in_lo) {
3335 /* a -> c, b -> a */
3336 bemit_helper_mov(in_lo, out_lo);
3338 } else if (out_hi == in_hi) {
3339 /* a -> c, b -> b */
3340 bemit_helper_mov(in_lo, out_lo);
3343 /* a -> c, b -> d */
3344 bemit_helper_mov(in_lo, out_lo);
3350 bemit_helper_neg( out_hi);
3351 bemit_helper_neg( out_lo);
3352 bemit_helper_sbb0(out_hi);
3356 bemit_helper_zero(out_hi);
3357 bemit_helper_neg( out_lo);
3358 bemit_helper_sbb( in_hi, out_hi);
3362 * Emit a single opcode.
3364 #define EMIT_SINGLEOP(op, code) \
3365 static void bemit_ ## op(const ir_node *node) { \
3370 //EMIT_SINGLEOP(daa, 0x27)
3371 //EMIT_SINGLEOP(das, 0x2F)
3372 //EMIT_SINGLEOP(aaa, 0x37)
3373 //EMIT_SINGLEOP(aas, 0x3F)
3374 //EMIT_SINGLEOP(nop, 0x90)
3375 EMIT_SINGLEOP(cwtl, 0x98)
3376 EMIT_SINGLEOP(cltd, 0x99)
3377 //EMIT_SINGLEOP(fwait, 0x9B)
3378 EMIT_SINGLEOP(sahf, 0x9E)
3379 //EMIT_SINGLEOP(popf, 0x9D)
3380 EMIT_SINGLEOP(leave, 0xC9)
3381 EMIT_SINGLEOP(int3, 0xCC)
3382 //EMIT_SINGLEOP(iret, 0xCF)
3383 //EMIT_SINGLEOP(xlat, 0xD7)
3384 //EMIT_SINGLEOP(lock, 0xF0)
3385 EMIT_SINGLEOP(rep, 0xF3)
3386 //EMIT_SINGLEOP(halt, 0xF4)
3387 EMIT_SINGLEOP(cmc, 0xF5)
3388 EMIT_SINGLEOP(stc, 0xF9)
3389 //EMIT_SINGLEOP(cli, 0xFA)
3390 //EMIT_SINGLEOP(sti, 0xFB)
3391 //EMIT_SINGLEOP(std, 0xFD)
3394 * Emits a MOV out, [MEM].
3396 static void bemit_load(const ir_node *node)
3398 const arch_register_t *out = get_out_reg(node, 0);
3400 if (out->index == REG_EAX) {
3401 ir_node *base = get_irn_n(node, n_ia32_base);
3402 int has_base = !is_ia32_NoReg_GP(base);
3403 ir_node *index = get_irn_n(node, n_ia32_index);
3404 int has_index = !is_ia32_NoReg_GP(index);
3405 if (!has_base && !has_index) {
3406 ir_entity *ent = get_ia32_am_sc(node);
3407 int offs = get_ia32_am_offs_int(node);
3408 /* load from constant address to EAX can be encoded
3411 bemit_entity(ent, 0, offs, false);
3416 bemit_mod_am(reg_gp_map[out->index], node);
3420 * Emits a MOV [mem], in.
3422 static void bemit_store(const ir_node *node)
3424 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3425 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3427 if (is_ia32_Immediate(value)) {
3430 bemit_mod_am(0, node);
3431 bemit8(get_ia32_immediate_attr_const(value)->offset);
3432 } else if (size == 16) {
3435 bemit_mod_am(0, node);
3436 bemit16(get_ia32_immediate_attr_const(value)->offset);
3439 bemit_mod_am(0, node);
3440 bemit_immediate(value, false);
3443 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3445 if (in->index == REG_EAX) {
3446 ir_node *base = get_irn_n(node, n_ia32_base);
3447 int has_base = !is_ia32_NoReg_GP(base);
3448 ir_node *index = get_irn_n(node, n_ia32_index);
3449 int has_index = !is_ia32_NoReg_GP(index);
3450 if (!has_base && !has_index) {
3451 ir_entity *ent = get_ia32_am_sc(node);
3452 int offs = get_ia32_am_offs_int(node);
3453 /* store to constant address from EAX can be encoded as
3454 * 0xA2/0xA3 [offset]*/
3462 bemit_entity(ent, 0, offs, false);
3474 bemit_mod_am(reg_gp_map[in->index], node);
3478 static void bemit_conv_i2i(const ir_node *node)
3480 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3489 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3490 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3491 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3497 static void bemit_push(const ir_node *node)
3499 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3501 if (is_ia32_Immediate(value)) {
3502 const ia32_immediate_attr_t *attr
3503 = get_ia32_immediate_attr_const(value);
3504 unsigned size = get_signed_imm_size(attr->offset);
3510 bemit8((unsigned char)attr->offset);
3515 bemit_immediate(value, false);
3518 } else if (is_ia32_NoReg_GP(value)) {
3520 bemit_mod_am(6, node);
3522 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3523 bemit8(0x50 + reg_gp_map[reg->index]);
3530 static void bemit_pop(const ir_node *node)
3532 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3533 bemit8(0x58 + reg_gp_map[reg->index]);
3536 static void bemit_popmem(const ir_node *node)
3539 bemit_mod_am(0, node);
3542 static void bemit_call(const ir_node *node)
3544 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3546 if (is_ia32_Immediate(proc)) {
3548 bemit_immediate(proc, true);
3550 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3554 static void bemit_jmp(const ir_node *dest_block)
3557 bemit_jmp_destination(dest_block);
3560 static void bemit_jump(const ir_node *node)
3562 if (can_be_fallthrough(node))
3565 bemit_jmp(get_cfop_target_block(node));
3568 static void bemit_jcc(int pnc, const ir_node *dest_block)
3570 unsigned char cc = pnc2cc(pnc);
3573 bemit_jmp_destination(dest_block);
3576 static void bemit_jp(bool odd, const ir_node *dest_block)
3580 bemit_jmp_destination(dest_block);
3583 static void bemit_ia32_jcc(const ir_node *node)
3585 int pnc = get_ia32_condcode(node);
3586 const ir_node *proj_true;
3587 const ir_node *proj_false;
3588 const ir_node *dest_true;
3589 const ir_node *dest_false;
3590 const ir_node *block;
3592 pnc = determine_final_pnc(node, 0, pnc);
3594 /* get both Projs */
3595 proj_true = get_proj(node, pn_ia32_Jcc_true);
3596 assert(proj_true && "Jcc without true Proj");
3598 proj_false = get_proj(node, pn_ia32_Jcc_false);
3599 assert(proj_false && "Jcc without false Proj");
3601 block = get_nodes_block(node);
3603 if (can_be_fallthrough(proj_true)) {
3604 /* exchange both proj's so the second one can be omitted */
3605 const ir_node *t = proj_true;
3607 proj_true = proj_false;
3609 pnc = ia32_get_negated_pnc(pnc);
3612 dest_true = get_cfop_target_block(proj_true);
3613 dest_false = get_cfop_target_block(proj_false);
3615 if (pnc & ia32_pn_Cmp_float) {
3616 /* Some floating point comparisons require a test of the parity flag,
3617 * which indicates that the result is unordered */
3620 bemit_jp(false, dest_true);
3625 bemit_jp(true, dest_true);
3631 /* we need a local label if the false proj is a fallthrough
3632 * as the falseblock might have no label emitted then */
3633 if (can_be_fallthrough(proj_false)) {
3635 bemit8(0x06); // jp + 6
3637 bemit_jp(false, dest_false);
3644 bemit_jp(false, dest_true);
3652 bemit_jcc(pnc, dest_true);
3655 /* the second Proj might be a fallthrough */
3656 if (can_be_fallthrough(proj_false)) {
3657 /* it's a fallthrough */
3659 bemit_jmp(dest_false);
3663 static void bemit_switchjmp(const ir_node *node)
3665 unsigned long interval;
3669 const arch_register_t *in;
3671 /* fill the table structure */
3672 generate_jump_table(&tbl, node);
3674 /* two-complement's magic make this work without overflow */
3675 interval = tbl.max_value - tbl.min_value;
3677 in = get_in_reg(node, 0);
3678 /* emit the table */
3679 if (get_signed_imm_size(interval) == 1) {
3680 bemit8(0x83); // cmpl $imm8, %in
3684 bemit8(0x81); // cmpl $imm32, %in
3688 bemit8(0x0F); // ja tbl.defProj
3690 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3692 if (tbl.num_branches > 1) {
3694 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3695 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3696 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3697 be_emit_irprintf("\t.long %s\n", tbl.label);
3699 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3700 be_emit_cstring(".align 4\n");
3701 be_emit_irprintf("%s:\n", tbl.label);
3703 last_value = tbl.branches[0].value;
3704 for (i = 0; i != tbl.num_branches; ++i) {
3705 while (last_value != tbl.branches[i].value) {
3706 ia32_emitf(tbl.defProj, ".long %L\n");
3709 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3712 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3714 /* one jump is enough */
3715 panic("switch only has one case");
3716 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3719 be_emit_write_line();
3727 static void bemit_return(const ir_node *node)
3729 unsigned pop = be_Return_get_pop(node);
3730 if (pop > 0 || be_Return_get_emit_pop(node)) {
3732 assert(pop <= 0xffff);
3739 static void bemit_subsp(const ir_node *node)
3741 const arch_register_t *out;
3744 /* mov %esp, %out */
3746 out = get_out_reg(node, 1);
3747 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3750 static void bemit_incsp(const ir_node *node)
3753 const arch_register_t *reg;
3757 offs = be_get_IncSP_offset(node);
3768 size = get_signed_imm_size(offs);
3769 bemit8(size == 1 ? 0x83 : 0x81);
3771 reg = get_out_reg(node, 0);
3772 bemit_modru(reg, ext);
3781 static void bemit_copybi(const ir_node *node)
3783 unsigned size = get_ia32_copyb_size(node);
3785 bemit8(0xA4); // movsb
3788 bemit8(0xA5); // movsw
3792 bemit8(0xA5); // movsl
3796 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3798 if (get_ia32_op_type(node) == ia32_Normal) {
3799 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3800 const arch_register_t *in1 = x87_attr->x87[0];
3801 const arch_register_t *in = x87_attr->x87[1];
3802 const arch_register_t *out = x87_attr->x87[2];
3806 } else if (out == in) {
3810 if (out->index == 0) {
3812 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3815 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3818 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3823 bemit_mod_am(code, node);
3827 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3829 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3830 const arch_register_t *out = x87_attr->x87[2];
3832 bemit8(code + out->index);
3835 static void bemit_fabs(const ir_node *node)
3843 static void bemit_fadd(const ir_node *node)
3845 bemit_fbinop(node, 0, 0);
3848 static void bemit_faddp(const ir_node *node)
3850 bemit_fbinopp(node, 0xC0);
3853 static void bemit_fchs(const ir_node *node)
3861 static void bemit_fdiv(const ir_node *node)
3863 bemit_fbinop(node, 6, 7);
3866 static void bemit_fdivp(const ir_node *node)
3868 bemit_fbinopp(node, 0xF8);
3871 static void bemit_fdivr(const ir_node *node)
3873 bemit_fbinop(node, 7, 6);
3876 static void bemit_fdivrp(const ir_node *node)
3878 bemit_fbinopp(node, 0xF0);
3881 static void bemit_fild(const ir_node *node)
3883 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3885 bemit8(0xDF); // filds
3886 bemit_mod_am(0, node);
3890 bemit8(0xDB); // fildl
3891 bemit_mod_am(0, node);
3895 bemit8(0xDF); // fildll
3896 bemit_mod_am(5, node);
3900 panic("invalid mode size");
3904 static void bemit_fist(const ir_node *node)
3906 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3908 bemit8(0xDF); // fists
3912 bemit8(0xDB); // fistl
3916 panic("invalid mode size");
3918 bemit_mod_am(2, node);
3921 static void bemit_fistp(const ir_node *node)
3923 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3925 bemit8(0xDF); // fistps
3926 bemit_mod_am(3, node);
3930 bemit8(0xDB); // fistpl
3931 bemit_mod_am(3, node);
3935 bemit8(0xDF); // fistpll
3936 bemit_mod_am(7, node);
3940 panic("invalid mode size");
3944 static void bemit_fld(const ir_node *node)
3946 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3948 bemit8(0xD9); // flds
3949 bemit_mod_am(0, node);
3953 bemit8(0xDD); // fldl
3954 bemit_mod_am(0, node);
3959 bemit8(0xDB); // fldt
3960 bemit_mod_am(5, node);
3964 panic("invalid mode size");
3968 static void bemit_fld1(const ir_node *node)
3972 bemit8(0xE8); // fld1
3975 static void bemit_fldcw(const ir_node *node)
3977 bemit8(0xD9); // fldcw
3978 bemit_mod_am(5, node);
3981 static void bemit_fldz(const ir_node *node)
3985 bemit8(0xEE); // fldz
3988 static void bemit_fmul(const ir_node *node)
3990 bemit_fbinop(node, 1, 1);
3993 static void bemit_fmulp(const ir_node *node)
3995 bemit_fbinopp(node, 0xC8);
3998 static void bemit_fpop(const ir_node *node)
4000 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4002 bemit8(0xD8 + attr->x87[0]->index);
4005 static void bemit_fpush(const ir_node *node)
4007 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4009 bemit8(0xC0 + attr->x87[0]->index);
4012 static void bemit_fpushcopy(const ir_node *node)
4014 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4016 bemit8(0xC0 + attr->x87[0]->index);
4019 static void bemit_fst(const ir_node *node)
4021 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4023 bemit8(0xD9); // fsts
4027 bemit8(0xDD); // fstl
4031 panic("invalid mode size");
4033 bemit_mod_am(2, node);
4036 static void bemit_fstp(const ir_node *node)
4038 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4040 bemit8(0xD9); // fstps
4041 bemit_mod_am(3, node);
4045 bemit8(0xDD); // fstpl
4046 bemit_mod_am(3, node);
4051 bemit8(0xDB); // fstpt
4052 bemit_mod_am(7, node);
4056 panic("invalid mode size");
4060 static void bemit_fsub(const ir_node *node)
4062 bemit_fbinop(node, 4, 5);
4065 static void bemit_fsubp(const ir_node *node)
4067 bemit_fbinopp(node, 0xE8);
4070 static void bemit_fsubr(const ir_node *node)
4072 bemit_fbinop(node, 5, 4);
4075 static void bemit_fsubrp(const ir_node *node)
4077 bemit_fbinopp(node, 0xE0);
4080 static void bemit_fnstcw(const ir_node *node)
4082 bemit8(0xD9); // fnstcw
4083 bemit_mod_am(7, node);
4086 static void bemit_fnstsw(void)
4088 bemit8(0xDF); // fnstsw %ax
4092 static void bemit_ftstfnstsw(const ir_node *node)
4096 bemit8(0xD9); // ftst
4101 static void bemit_fucomi(const ir_node *node)
4103 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4104 bemit8(0xDB); // fucomi
4105 bemit8(0xE8 + attr->x87[1]->index);
4108 static void bemit_fucomip(const ir_node *node)
4110 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4111 bemit8(0xDF); // fucomip
4112 bemit8(0xE8 + attr->x87[1]->index);
4115 static void bemit_fucomfnstsw(const ir_node *node)
4117 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4118 bemit8(0xDD); // fucom
4119 bemit8(0xE0 + attr->x87[1]->index);
4123 static void bemit_fucompfnstsw(const ir_node *node)
4125 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4126 bemit8(0xDD); // fucomp
4127 bemit8(0xE8 + attr->x87[1]->index);
4131 static void bemit_fucomppfnstsw(const ir_node *node)
4135 bemit8(0xDA); // fucompp
4140 static void bemit_fxch(const ir_node *node)
4142 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4144 bemit8(0xC8 + attr->x87[0]->index);
4148 * The type of a emitter function.
4150 typedef void (*emit_func) (const ir_node *);
4153 * Set a node emitter. Make it a bit more type safe.
4155 static void register_emitter(ir_op *op, emit_func func)
4157 op->ops.generic = (op_func) func;
4160 static void ia32_register_binary_emitters(void)
4162 /* first clear the generic function pointer for all ops */
4163 clear_irp_opcodes_generic_func();
4165 /* benode emitter */
4166 register_emitter(op_be_Copy, bemit_copy);
4167 register_emitter(op_be_CopyKeep, bemit_copy);
4168 register_emitter(op_be_IncSP, bemit_incsp);
4169 register_emitter(op_be_Perm, bemit_perm);
4170 register_emitter(op_be_Return, bemit_return);
4171 register_emitter(op_ia32_Adc, bemit_adc);
4172 register_emitter(op_ia32_Add, bemit_add);
4173 register_emitter(op_ia32_AddMem, bemit_addmem);
4174 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4175 register_emitter(op_ia32_And, bemit_and);
4176 register_emitter(op_ia32_AndMem, bemit_andmem);
4177 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4178 register_emitter(op_ia32_Breakpoint, bemit_int3);
4179 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4180 register_emitter(op_ia32_Call, bemit_call);
4181 register_emitter(op_ia32_Cltd, bemit_cltd);
4182 register_emitter(op_ia32_Cmc, bemit_cmc);
4183 register_emitter(op_ia32_Cmp, bemit_cmp);
4184 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4185 register_emitter(op_ia32_Const, bemit_mov_const);
4186 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4187 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4188 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4189 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4190 register_emitter(op_ia32_Dec, bemit_dec);
4191 register_emitter(op_ia32_DecMem, bemit_decmem);
4192 register_emitter(op_ia32_Div, bemit_div);
4193 register_emitter(op_ia32_FldCW, bemit_fldcw);
4194 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4195 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4196 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4197 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4198 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4199 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4200 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4201 register_emitter(op_ia32_IDiv, bemit_idiv);
4202 register_emitter(op_ia32_IJmp, bemit_ijmp);
4203 register_emitter(op_ia32_IMul, bemit_imul);
4204 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4205 register_emitter(op_ia32_Inc, bemit_inc);
4206 register_emitter(op_ia32_IncMem, bemit_incmem);
4207 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4208 register_emitter(op_ia32_Jmp, bemit_jump);
4209 register_emitter(op_ia32_LdTls, bemit_ldtls);
4210 register_emitter(op_ia32_Lea, bemit_lea);
4211 register_emitter(op_ia32_Leave, bemit_leave);
4212 register_emitter(op_ia32_Load, bemit_load);
4213 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4214 register_emitter(op_ia32_Mul, bemit_mul);
4215 register_emitter(op_ia32_Neg, bemit_neg);
4216 register_emitter(op_ia32_NegMem, bemit_negmem);
4217 register_emitter(op_ia32_Not, bemit_not);
4218 register_emitter(op_ia32_NotMem, bemit_notmem);
4219 register_emitter(op_ia32_Or, bemit_or);
4220 register_emitter(op_ia32_OrMem, bemit_ormem);
4221 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4222 register_emitter(op_ia32_Pop, bemit_pop);
4223 register_emitter(op_ia32_PopEbp, bemit_pop);
4224 register_emitter(op_ia32_PopMem, bemit_popmem);
4225 register_emitter(op_ia32_Push, bemit_push);
4226 register_emitter(op_ia32_RepPrefix, bemit_rep);
4227 register_emitter(op_ia32_Rol, bemit_rol);
4228 register_emitter(op_ia32_RolMem, bemit_rolmem);
4229 register_emitter(op_ia32_Ror, bemit_ror);
4230 register_emitter(op_ia32_RorMem, bemit_rormem);
4231 register_emitter(op_ia32_Sahf, bemit_sahf);
4232 register_emitter(op_ia32_Sar, bemit_sar);
4233 register_emitter(op_ia32_SarMem, bemit_sarmem);
4234 register_emitter(op_ia32_Sbb, bemit_sbb);
4235 register_emitter(op_ia32_Setcc, bemit_setcc);
4236 register_emitter(op_ia32_Shl, bemit_shl);
4237 register_emitter(op_ia32_ShlD, bemit_shld);
4238 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4239 register_emitter(op_ia32_Shr, bemit_shr);
4240 register_emitter(op_ia32_ShrD, bemit_shrd);
4241 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4242 register_emitter(op_ia32_Stc, bemit_stc);
4243 register_emitter(op_ia32_Store, bemit_store);
4244 register_emitter(op_ia32_Store8Bit, bemit_store);
4245 register_emitter(op_ia32_Sub, bemit_sub);
4246 register_emitter(op_ia32_SubMem, bemit_submem);
4247 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4248 register_emitter(op_ia32_SubSP, bemit_subsp);
4249 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4250 register_emitter(op_ia32_Test, bemit_test);
4251 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4252 register_emitter(op_ia32_Xor, bemit_xor);
4253 register_emitter(op_ia32_Xor0, bemit_xor0);
4254 register_emitter(op_ia32_XorMem, bemit_xormem);
4255 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4256 register_emitter(op_ia32_fabs, bemit_fabs);
4257 register_emitter(op_ia32_fadd, bemit_fadd);
4258 register_emitter(op_ia32_faddp, bemit_faddp);
4259 register_emitter(op_ia32_fchs, bemit_fchs);
4260 register_emitter(op_ia32_fdiv, bemit_fdiv);
4261 register_emitter(op_ia32_fdivp, bemit_fdivp);
4262 register_emitter(op_ia32_fdivr, bemit_fdivr);
4263 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4264 register_emitter(op_ia32_fild, bemit_fild);
4265 register_emitter(op_ia32_fist, bemit_fist);
4266 register_emitter(op_ia32_fistp, bemit_fistp);
4267 register_emitter(op_ia32_fld, bemit_fld);
4268 register_emitter(op_ia32_fld1, bemit_fld1);
4269 register_emitter(op_ia32_fldz, bemit_fldz);
4270 register_emitter(op_ia32_fmul, bemit_fmul);
4271 register_emitter(op_ia32_fmulp, bemit_fmulp);
4272 register_emitter(op_ia32_fpop, bemit_fpop);
4273 register_emitter(op_ia32_fpush, bemit_fpush);
4274 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4275 register_emitter(op_ia32_fst, bemit_fst);
4276 register_emitter(op_ia32_fstp, bemit_fstp);
4277 register_emitter(op_ia32_fsub, bemit_fsub);
4278 register_emitter(op_ia32_fsubp, bemit_fsubp);
4279 register_emitter(op_ia32_fsubr, bemit_fsubr);
4280 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4281 register_emitter(op_ia32_fxch, bemit_fxch);
4283 /* ignore the following nodes */
4284 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4285 register_emitter(op_be_Barrier, emit_Nothing);
4286 register_emitter(op_be_Keep, emit_Nothing);
4287 register_emitter(op_be_Start, emit_Nothing);
4288 register_emitter(op_Phi, emit_Nothing);
4289 register_emitter(op_Start, emit_Nothing);
4292 static void gen_binary_block(ir_node *block)
4296 ia32_emit_block_header(block);
4298 /* emit the contents of the block */
4299 sched_foreach(block, node) {
4300 ia32_emit_node(node);
4304 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
4306 ir_entity *entity = get_irg_entity(irg);
4312 ia32_register_binary_emitters();
4314 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4316 /* we use links to point to target blocks */
4317 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4318 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4320 /* initialize next block links */
4321 n = ARR_LEN(cg->blk_sched);
4322 for (i = 0; i < n; ++i) {
4323 ir_node *block = cg->blk_sched[i];
4324 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4326 set_irn_link(block, prev);
4329 for (i = 0; i < n; ++i) {
4330 ir_node *block = cg->blk_sched[i];
4331 gen_binary_block(block);
4334 be_gas_emit_function_epilog(entity);
4335 be_dbg_method_end();
4337 be_emit_write_line();
4339 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4345 void ia32_init_emitter(void)
4347 lc_opt_entry_t *be_grp;
4348 lc_opt_entry_t *ia32_grp;
4350 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4351 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4353 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4357 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");