2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
157 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
160 be_emit_char(reg->name[1]); /* get the basic name of the register */
165 * Emit the name of the 8bit high register
167 static void emit_8bit_register_high(const arch_register_t *reg)
169 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
170 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
173 be_emit_char(reg->name[1]); /* get the basic name of the register */
177 static void emit_16bit_register(const arch_register_t *reg)
180 be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
184 * emit a register, possible shortened by a mode
186 * @param reg the register
187 * @param mode the mode of the register or NULL for full register
189 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
192 int size = get_mode_size_bits(mode);
194 case 8: emit_8bit_register(reg); return;
195 case 16: emit_16bit_register(reg); return;
197 assert(mode_is_float(mode) || size == 32);
201 be_emit_string(reg->name);
204 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
206 be_gas_emit_entity(entity);
208 if (get_entity_owner(entity) == get_tls_type()) {
209 if (!entity_has_definition(entity)) {
210 be_emit_cstring("@INDNTPOFF");
212 be_emit_cstring("@NTPOFF");
216 if (do_pic && !no_pic_adjust) {
218 be_emit_string(pic_base_label);
222 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
224 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
226 if (attr->symconst != NULL) {
229 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
231 if (attr->symconst == NULL || attr->offset != 0) {
232 if (attr->symconst != NULL) {
233 be_emit_irprintf("%+d", attr->offset);
235 be_emit_irprintf("0x%X", attr->offset);
240 static void emit_ia32_Immediate(const ir_node *node)
243 emit_ia32_Immediate_no_prefix(node);
246 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
248 assert(mode_is_int(mode) || mode_is_reference(mode));
249 switch (get_mode_size_bits(mode)) {
250 case 8: be_emit_char('b'); return;
251 case 16: be_emit_char('w'); return;
252 case 32: be_emit_char('l'); return;
253 /* gas docu says q is the suffix but gcc, objdump and icc use ll
255 case 64: be_emit_cstring("ll"); return;
257 panic("Can't output mode_suffix for %+F", mode);
260 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
264 /* we only need to emit the mode on address mode */
265 if (get_ia32_op_type(node) == ia32_Normal)
268 mode = get_ia32_ls_mode(node);
269 assert(mode != NULL);
271 if (mode_is_float(mode)) {
272 switch (get_mode_size_bits(mode)) {
273 case 32: be_emit_char('s'); return;
274 case 64: be_emit_char('l'); return;
275 /* long doubles have different sizes due to alignment on different
279 case 128: be_emit_char('t'); return;
282 assert(mode_is_int(mode) || mode_is_reference(mode));
283 switch (get_mode_size_bits(mode)) {
284 case 16: be_emit_char('s'); return;
285 case 32: be_emit_char('l'); return;
286 /* gas docu says q is the suffix but gcc, objdump and icc use ll
288 case 64: be_emit_cstring("ll"); return;
291 panic("Can't output mode_suffix for %+F", mode);
294 static char get_xmm_mode_suffix(ir_mode *mode)
296 assert(mode_is_float(mode));
297 switch (get_mode_size_bits(mode)) {
300 default: panic("Invalid XMM mode");
304 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
306 ir_mode *mode = get_ia32_ls_mode(node);
307 assert(mode != NULL);
308 be_emit_char(get_xmm_mode_suffix(mode));
312 * Returns the target block for a control flow node.
314 static ir_node *get_cfop_target_block(const ir_node *irn)
316 assert(get_irn_mode(irn) == mode_X);
317 return (ir_node*)get_irn_link(irn);
321 * Emits the target label for a control flow node.
323 static void ia32_emit_cfop_target(const ir_node *node)
325 ir_node *block = get_cfop_target_block(node);
326 be_gas_emit_block_name(block);
330 * Emit the suffix for a compare instruction.
332 static void ia32_emit_condition_code(ia32_condition_code_t cc)
335 case ia32_cc_overflow: be_emit_cstring("o"); return;
336 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
337 case ia32_cc_float_below:
338 case ia32_cc_float_unordered_below:
339 case ia32_cc_below: be_emit_cstring("b"); return;
340 case ia32_cc_float_above_equal:
341 case ia32_cc_float_unordered_above_equal:
342 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
343 case ia32_cc_float_equal:
344 case ia32_cc_equal: be_emit_cstring("e"); return;
345 case ia32_cc_float_not_equal:
346 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
347 case ia32_cc_float_below_equal:
348 case ia32_cc_float_unordered_below_equal:
349 case ia32_cc_below_equal: be_emit_cstring("be"); return;
350 case ia32_cc_float_above:
351 case ia32_cc_float_unordered_above:
352 case ia32_cc_above: be_emit_cstring("a"); return;
353 case ia32_cc_sign: be_emit_cstring("s"); return;
354 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
355 case ia32_cc_parity: be_emit_cstring("p"); return;
356 case ia32_cc_not_parity: be_emit_cstring("np"); return;
357 case ia32_cc_less: be_emit_cstring("l"); return;
358 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
359 case ia32_cc_less_equal: be_emit_cstring("le"); return;
360 case ia32_cc_greater: be_emit_cstring("g"); return;
361 case ia32_cc_float_parity_cases:
362 case ia32_cc_additional_float_cases:
365 panic("Invalid ia32 condition code");
368 typedef enum ia32_emit_mod_t {
370 EMIT_RESPECT_LS = 1U << 0,
371 EMIT_ALTERNATE_AM = 1U << 1,
373 EMIT_HIGH_REG = 1U << 3,
374 EMIT_LOW_REG = 1U << 4,
375 EMIT_16BIT_REG = 1U << 5
377 ENUM_BITSET(ia32_emit_mod_t)
380 * Emits address mode.
382 static void ia32_emit_am(ir_node const *const node)
384 ir_entity *ent = get_ia32_am_sc(node);
385 int offs = get_ia32_am_offs_int(node);
386 ir_node *base = get_irn_n(node, n_ia32_base);
387 int has_base = !is_ia32_NoReg_GP(base);
388 ir_node *idx = get_irn_n(node, n_ia32_index);
389 int has_index = !is_ia32_NoReg_GP(idx);
391 /* just to be sure... */
392 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
394 if (get_ia32_am_tls_segment(node))
395 be_emit_cstring("%gs:");
399 const ia32_attr_t *attr = get_ia32_attr_const(node);
400 if (is_ia32_am_sc_sign(node))
402 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
405 /* also handle special case if nothing is set */
406 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
408 be_emit_irprintf("%+d", offs);
410 be_emit_irprintf("%d", offs);
414 if (has_base || has_index) {
419 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
420 emit_register(reg, NULL);
423 /* emit index + scale */
425 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
428 emit_register(reg, NULL);
430 scale = get_ia32_am_scale(node);
432 be_emit_irprintf(",%d", 1 << scale);
439 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
441 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
448 const char *start = fmt;
449 ia32_emit_mod_t mod = EMIT_NONE;
451 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
454 be_emit_string_len(start, fmt - start);
459 be_emit_write_line();
473 case '*': mod |= EMIT_ALTERNATE_AM; break;
474 case '#': mod |= EMIT_RESPECT_LS; break;
475 case 'l': mod |= EMIT_LONG; break;
476 case '>': mod |= EMIT_HIGH_REG; break;
477 case '<': mod |= EMIT_LOW_REG; break;
478 case '^': mod |= EMIT_16BIT_REG; break;
487 arch_register_t const *reg;
497 if (get_ia32_op_type(node) == ia32_AddrModeS) {
500 assert(get_ia32_op_type(node) == ia32_Normal);
501 ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
502 arch_register_t const *const out = x87_attr->x87[2];
503 arch_register_t const * in = x87_attr->x87[1];
505 in = x87_attr->x87[0];
506 be_emit_irprintf("%%%s, %%%s", in->name, out->name);
512 if (mod & EMIT_ALTERNATE_AM)
518 reg = va_arg(ap, const arch_register_t*);
519 if (get_ia32_op_type(node) == ia32_AddrModeS) {
526 if (get_ia32_op_type(node) == ia32_AddrModeS) {
530 assert(get_ia32_op_type(node) == ia32_Normal);
534 default: goto unknown;
540 imm = get_irn_n(node, n_ia32_binary_right);
541 if (is_ia32_Immediate(imm)) {
542 emit_ia32_Immediate(imm);
543 be_emit_cstring(", ");
544 if (get_ia32_op_type(node) == ia32_AddrModeS) {
547 assert(get_ia32_op_type(node) == ia32_Normal);
548 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
549 emit_register(reg, get_ia32_ls_mode(node));
552 if (get_ia32_op_type(node) == ia32_AddrModeS) {
555 assert(get_ia32_op_type(node) == ia32_Normal);
556 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
557 emit_register(reg, get_ia32_ls_mode(node));
559 be_emit_cstring(", ");
560 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
561 emit_register(reg, get_ia32_ls_mode(node));
566 if (*fmt < '0' || '9' < *fmt)
568 reg = arch_get_irn_register_out(node, *fmt++ - '0');
574 ia32_emit_x87_mode_suffix(node);
575 } else if (*fmt == 'P') {
577 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
580 } else if (*fmt == 'R') {
582 /* NOTE: Work around a gas quirk for non-commutative operations if the
583 * destination register is not %st0. In this case r/non-r is swapped.
584 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
585 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
586 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
587 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
588 * In fact this corresponds to the encoding of the instruction:
589 * - The r suffix selects whether %st0 is on the left (no r) or on the
590 * right (r) side of the executed operation.
591 * - The placement of %st0 selects whether the result is written to
592 * %st0 (right) or the other register (left).
593 * This results in testing whether the left operand register is %st0
594 * instead of the expected test whether the output register equals the
595 * left operand register. */
596 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
597 if (get_ia32_op_type(node) == ia32_Normal ?
598 attr->x87[0] != &ia32_registers[REG_ST0] :
599 attr->attr.data.ins_permuted)
601 } else if (*fmt == 'X') {
603 ia32_emit_xmm_mode_suffix(node);
604 } else if ('0' <= *fmt && *fmt <= '2') {
605 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
607 be_emit_string(attr->x87[*fmt++ - '0']->name);
616 if (!(mod & EMIT_ALTERNATE_AM))
618 emit_ia32_Immediate_no_prefix(imm);
622 ia32_emit_cfop_target(node);
626 ir_mode *mode = get_ia32_ls_mode(node);
629 if (mod & EMIT_RESPECT_LS) {
630 if (get_mode_size_bits(mode) == 32)
632 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
634 ia32_emit_mode_suffix_mode(mode);
639 ia32_condition_code_t cc;
642 cc = (ia32_condition_code_t)va_arg(ap, int);
643 } else if ('0' <= *fmt && *fmt <= '9') {
644 cc = get_ia32_condcode(node);
645 cc = determine_final_cc(node, *fmt - '0', cc);
650 ia32_emit_condition_code(cc);
655 reg = va_arg(ap, const arch_register_t*);
657 if (mod & EMIT_ALTERNATE_AM)
659 if (mod & EMIT_HIGH_REG) {
660 emit_8bit_register_high(reg);
661 } else if (mod & EMIT_LOW_REG) {
662 emit_8bit_register(reg);
663 } else if (mod & EMIT_16BIT_REG) {
664 emit_16bit_register(reg);
666 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
674 if (*fmt < '0' || '9' < *fmt)
678 imm = get_irn_n(node, pos);
679 if (is_ia32_Immediate(imm)) {
682 reg = arch_get_irn_register_in(node, pos);
688 const char *str = va_arg(ap, const char*);
694 if (mod & EMIT_LONG) {
695 unsigned long num = va_arg(ap, unsigned long);
696 be_emit_irprintf("%lu", num);
698 unsigned num = va_arg(ap, unsigned);
699 be_emit_irprintf("%u", num);
704 if (mod & EMIT_LONG) {
705 long num = va_arg(ap, long);
706 be_emit_irprintf("%ld", num);
708 int num = va_arg(ap, int);
709 be_emit_irprintf("%d", num);
715 panic("unknown format conversion");
719 be_emit_finish_line_gas(node);
723 static void emit_ia32_IMul(const ir_node *node)
725 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
726 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
728 /* do we need the 3-address form? */
729 if (is_ia32_NoReg_GP(left) ||
730 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
731 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
733 ia32_emitf(node, "imul%M %#AS4, %#S3");
738 * walks up a tree of copies/perms/spills/reloads to find the original value
739 * that is moved around
741 static ir_node *find_original_value(ir_node *node)
743 if (irn_visited(node))
746 mark_irn_visited(node);
747 if (be_is_Copy(node)) {
748 return find_original_value(be_get_Copy_op(node));
749 } else if (be_is_CopyKeep(node)) {
750 return find_original_value(be_get_CopyKeep_op(node));
751 } else if (is_Proj(node)) {
752 ir_node *pred = get_Proj_pred(node);
753 if (be_is_Perm(pred)) {
754 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
755 } else if (be_is_MemPerm(pred)) {
756 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
757 } else if (is_ia32_Load(pred)) {
758 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
759 } else if (is_ia32_Store(pred)) {
760 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
764 } else if (is_Phi(node)) {
766 arity = get_irn_arity(node);
767 for (i = 0; i < arity; ++i) {
768 ir_node *in = get_irn_n(node, i);
769 ir_node *res = find_original_value(in);
780 static ia32_condition_code_t determine_final_cc(const ir_node *node,
781 int flags_pos, ia32_condition_code_t cc)
783 ir_node *flags = get_irn_n(node, flags_pos);
784 const ia32_attr_t *flags_attr;
785 flags = skip_Proj(flags);
787 if (is_ia32_Sahf(flags)) {
788 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
789 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
790 inc_irg_visited(current_ir_graph);
791 cmp = find_original_value(cmp);
793 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
796 flags_attr = get_ia32_attr_const(cmp);
798 flags_attr = get_ia32_attr_const(flags);
801 if (flags_attr->data.ins_permuted)
802 cc = ia32_invert_condition_code(cc);
807 * Emits an exception label for a given node.
809 static void ia32_emit_exc_label(const ir_node *node)
811 be_emit_string(be_gas_insn_label_prefix());
812 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
816 * Returns the Proj with projection number proj and NOT mode_M
818 static ir_node *get_proj(const ir_node *node, long proj)
822 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
824 foreach_out_edge(node, edge) {
825 src = get_edge_src_irn(edge);
827 assert(is_Proj(src) && "Proj expected");
828 if (get_irn_mode(src) == mode_M)
831 if (get_Proj_proj(src) == proj)
837 static int can_be_fallthrough(const ir_node *node)
839 ir_node *target_block = get_cfop_target_block(node);
840 ir_node *block = get_nodes_block(node);
841 return get_prev_block_sched(target_block) == block;
845 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
847 static void emit_ia32_Jcc(const ir_node *node)
849 int need_parity_label = 0;
850 ia32_condition_code_t cc = get_ia32_condcode(node);
851 const ir_node *proj_true;
852 const ir_node *proj_false;
854 cc = determine_final_cc(node, 0, cc);
857 proj_true = get_proj(node, pn_ia32_Jcc_true);
858 assert(proj_true && "Jcc without true Proj");
860 proj_false = get_proj(node, pn_ia32_Jcc_false);
861 assert(proj_false && "Jcc without false Proj");
863 if (can_be_fallthrough(proj_true)) {
864 /* exchange both proj's so the second one can be omitted */
865 const ir_node *t = proj_true;
867 proj_true = proj_false;
869 cc = ia32_negate_condition_code(cc);
872 if (cc & ia32_cc_float_parity_cases) {
873 /* Some floating point comparisons require a test of the parity flag,
874 * which indicates that the result is unordered */
875 if (cc & ia32_cc_negated) {
876 ia32_emitf(proj_true, "jp %L");
878 /* we need a local label if the false proj is a fallthrough
879 * as the falseblock might have no label emitted then */
880 if (can_be_fallthrough(proj_false)) {
881 need_parity_label = 1;
882 ia32_emitf(proj_false, "jp 1f");
884 ia32_emitf(proj_false, "jp %L");
888 ia32_emitf(proj_true, "j%PX %L", (int)cc);
889 if (need_parity_label) {
890 be_emit_cstring("1:\n");
891 be_emit_write_line();
894 /* the second Proj might be a fallthrough */
895 if (can_be_fallthrough(proj_false)) {
896 if (be_options.verbose_asm)
897 ia32_emitf(proj_false, "/* fallthrough to %L */");
899 ia32_emitf(proj_false, "jmp %L");
904 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
907 static void emit_ia32_Setcc(const ir_node *node)
909 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
911 ia32_condition_code_t cc = get_ia32_condcode(node);
912 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
913 if (cc & ia32_cc_float_parity_cases) {
914 if (cc & ia32_cc_negated) {
915 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
916 ia32_emitf(node, "setp %>R", dreg);
917 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
919 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
920 ia32_emitf(node, "setnp %>R", dreg);
921 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
924 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
928 static void emit_ia32_CMovcc(const ir_node *node)
930 const ia32_attr_t *attr = get_ia32_attr_const(node);
931 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
932 ia32_condition_code_t cc = get_ia32_condcode(node);
933 const arch_register_t *in_true;
934 const arch_register_t *in_false;
936 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
937 /* although you can't set ins_permuted in the constructor it might still
938 * be set by memory operand folding
939 * Permuting inputs of a cmov means the condition is negated!
941 if (attr->data.ins_permuted)
942 cc = ia32_negate_condition_code(cc);
944 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
945 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
947 /* should be same constraint fullfilled? */
948 if (out == in_false) {
949 /* yes -> nothing to do */
950 } else if (out == in_true) {
951 const arch_register_t *tmp;
953 assert(get_ia32_op_type(node) == ia32_Normal);
955 cc = ia32_negate_condition_code(cc);
962 ia32_emitf(node, "movl %R, %R", in_false, out);
965 if (cc & ia32_cc_float_parity_cases) {
966 panic("CMov with floatingpoint compare/parity not supported yet");
969 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
973 * Emits code for a SwitchJmp
975 static void emit_ia32_SwitchJmp(const ir_node *node)
977 ir_entity *jump_table = get_ia32_am_sc(node);
978 const ir_switch_table *table = get_ia32_switch_table(node);
980 ia32_emitf(node, "jmp %*AM");
981 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
985 * Emits code for a unconditional jump.
987 static void emit_ia32_Jmp(const ir_node *node)
989 /* we have a block schedule */
990 if (can_be_fallthrough(node)) {
991 if (be_options.verbose_asm)
992 ia32_emitf(node, "/* fallthrough to %L */");
994 ia32_emitf(node, "jmp %L");
999 * Emit an inline assembler operand.
1001 * @param node the ia32_ASM node
1002 * @param s points to the operand (a %c)
1004 * @return pointer to the first char in s NOT in the current operand
1006 static const char* emit_asm_operand(const ir_node *node, const char *s)
1008 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1009 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1011 const arch_register_t *reg;
1012 const ia32_asm_reg_t *asm_regs = attr->register_map;
1013 const ia32_asm_reg_t *asm_reg;
1022 /* parse modifiers */
1025 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1050 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1057 if (sscanf(s, "%d%n", &num, &p) != 1) {
1058 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1065 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1067 "Error: Custom assembler references invalid input/output (%+F)\n",
1071 asm_reg = & asm_regs[num];
1072 assert(asm_reg->valid);
1075 if (asm_reg->use_input == 0) {
1076 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1078 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1080 /* might be an immediate value */
1081 if (is_ia32_Immediate(pred)) {
1082 emit_ia32_Immediate(pred);
1085 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1089 "Warning: no register assigned for %d asm op (%+F)\n",
1094 if (asm_reg->memory) {
1099 if (modifier != 0) {
1102 emit_8bit_register(reg);
1105 emit_8bit_register_high(reg);
1108 emit_16bit_register(reg);
1111 panic("Invalid asm op modifier");
1114 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1117 if (asm_reg->memory) {
1125 * Emits code for an ASM pseudo op.
1127 static void emit_ia32_Asm(const ir_node *node)
1129 const void *gen_attr = get_irn_generic_attr_const(node);
1130 const ia32_asm_attr_t *attr
1131 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1132 ident *asm_text = attr->asm_text;
1133 const char *s = get_id_str(asm_text);
1135 be_emit_cstring("#APP\n");
1136 be_emit_write_line();
1143 s = emit_asm_operand(node, s);
1149 be_emit_cstring("\n#NO_APP\n");
1150 be_emit_write_line();
1155 * Emit movsb/w instructions to make mov count divideable by 4
1157 static void emit_CopyB_prolog(unsigned size)
1160 ia32_emitf(NULL, "movsb");
1162 ia32_emitf(NULL, "movsw");
1166 * Emit rep movsd instruction for memcopy.
1168 static void emit_ia32_CopyB(const ir_node *node)
1170 unsigned size = get_ia32_copyb_size(node);
1172 emit_CopyB_prolog(size);
1173 ia32_emitf(node, "rep movsd");
1177 * Emits unrolled memcopy.
1179 static void emit_ia32_CopyB_i(const ir_node *node)
1181 unsigned size = get_ia32_copyb_size(node);
1183 emit_CopyB_prolog(size);
1187 ia32_emitf(NULL, "movsd");
1193 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1195 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1198 ir_mode *ls_mode = get_ia32_ls_mode(node);
1199 int ls_bits = get_mode_size_bits(ls_mode);
1200 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1202 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1205 static void emit_ia32_Conv_I2FP(const ir_node *node)
1207 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1210 static void emit_ia32_Conv_FP2I(const ir_node *node)
1212 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1215 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1217 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1221 * Emits code to increase stack pointer.
1223 static void emit_be_IncSP(const ir_node *node)
1225 int offs = be_get_IncSP_offset(node);
1231 ia32_emitf(node, "subl $%u, %D0", offs);
1233 ia32_emitf(node, "addl $%u, %D0", -offs);
1238 * Emits code for Copy/CopyKeep.
1240 static void Copy_emitter(const ir_node *node, const ir_node *op)
1242 const arch_register_t *in = arch_get_irn_register(op);
1243 const arch_register_t *out = arch_get_irn_register(node);
1248 /* copies of vf nodes aren't real... */
1249 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1252 ia32_emitf(node, "movl %R, %R", in, out);
1255 static void emit_be_Copy(const ir_node *node)
1257 Copy_emitter(node, be_get_Copy_op(node));
1260 static void emit_be_CopyKeep(const ir_node *node)
1262 Copy_emitter(node, be_get_CopyKeep_op(node));
1266 * Emits code for exchange.
1268 static void emit_be_Perm(const ir_node *node)
1270 const arch_register_t *in0, *in1;
1271 const arch_register_class_t *cls0, *cls1;
1273 in0 = arch_get_irn_register(get_irn_n(node, 0));
1274 in1 = arch_get_irn_register(get_irn_n(node, 1));
1276 cls0 = arch_register_get_class(in0);
1277 cls1 = arch_register_get_class(in1);
1279 assert(cls0 == cls1 && "Register class mismatch at Perm");
1281 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1282 ia32_emitf(node, "xchg %R, %R", in1, in0);
1283 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1284 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1285 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1286 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1287 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1289 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1292 panic("unexpected register class in be_Perm (%+F)", node);
1296 /* helper function for emit_ia32_Minus64Bit */
1297 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1299 ia32_emitf(node, "movl %R, %R", src, dst);
1302 /* helper function for emit_ia32_Minus64Bit */
1303 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1305 ia32_emitf(node, "negl %R", reg);
1308 /* helper function for emit_ia32_Minus64Bit */
1309 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1311 ia32_emitf(node, "sbbl $0, %R", reg);
1314 /* helper function for emit_ia32_Minus64Bit */
1315 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1317 ia32_emitf(node, "sbbl %R, %R", src, dst);
1320 /* helper function for emit_ia32_Minus64Bit */
1321 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1323 ia32_emitf(node, "xchgl %R, %R", src, dst);
1326 /* helper function for emit_ia32_Minus64Bit */
1327 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1329 ia32_emitf(node, "xorl %R, %R", reg, reg);
1332 static void emit_ia32_Minus64Bit(const ir_node *node)
1334 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1335 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1336 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1337 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1339 if (out_lo == in_lo) {
1340 if (out_hi != in_hi) {
1341 /* a -> a, b -> d */
1344 /* a -> a, b -> b */
1347 } else if (out_lo == in_hi) {
1348 if (out_hi == in_lo) {
1349 /* a -> b, b -> a */
1350 emit_xchg(node, in_lo, in_hi);
1353 /* a -> b, b -> d */
1354 emit_mov(node, in_hi, out_hi);
1355 emit_mov(node, in_lo, out_lo);
1359 if (out_hi == in_lo) {
1360 /* a -> c, b -> a */
1361 emit_mov(node, in_lo, out_lo);
1363 } else if (out_hi == in_hi) {
1364 /* a -> c, b -> b */
1365 emit_mov(node, in_lo, out_lo);
1368 /* a -> c, b -> d */
1369 emit_mov(node, in_lo, out_lo);
1375 emit_neg( node, out_hi);
1376 emit_neg( node, out_lo);
1377 emit_sbb0(node, out_hi);
1381 emit_zero(node, out_hi);
1382 emit_neg( node, out_lo);
1383 emit_sbb( node, in_hi, out_hi);
1386 static void emit_ia32_GetEIP(const ir_node *node)
1388 ia32_emitf(node, "call %s", pic_base_label);
1389 be_emit_irprintf("%s:\n", pic_base_label);
1390 be_emit_write_line();
1391 ia32_emitf(node, "popl %D0");
1394 static void emit_ia32_ClimbFrame(const ir_node *node)
1396 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1398 ia32_emitf(node, "movl %S0, %D0");
1399 ia32_emitf(node, "movl $%u, %S1", attr->count);
1400 be_gas_emit_block_name(node);
1401 be_emit_cstring(":\n");
1402 be_emit_write_line();
1403 ia32_emitf(node, "movl (%D0), %D0");
1404 ia32_emitf(node, "dec %S1");
1405 be_emit_cstring("\tjnz ");
1406 be_gas_emit_block_name(node);
1407 be_emit_finish_line_gas(node);
1410 static void emit_be_Return(const ir_node *node)
1412 unsigned pop = be_Return_get_pop(node);
1414 if (pop > 0 || be_Return_get_emit_pop(node)) {
1415 ia32_emitf(node, "ret $%u", pop);
1417 ia32_emitf(node, "ret");
1421 static void emit_Nothing(const ir_node *node)
1428 * Enters the emitter functions for handled nodes into the generic
1429 * pointer of an opcode.
1431 static void ia32_register_emitters(void)
1433 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1434 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1435 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1436 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1437 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1439 /* first clear the generic function pointer for all ops */
1440 ir_clear_opcodes_generic_func();
1442 /* register all emitter functions defined in spec */
1443 ia32_register_spec_emitters();
1445 /* other ia32 emitter functions */
1448 IA32_EMIT(Conv_FP2FP);
1449 IA32_EMIT(Conv_FP2I);
1450 IA32_EMIT(Conv_I2FP);
1457 IA32_EMIT(Minus64Bit);
1458 IA32_EMIT(SwitchJmp);
1459 IA32_EMIT(ClimbFrame);
1462 /* benode emitter */
1481 typedef void (*emit_func_ptr) (const ir_node *);
1484 * Assign and emit an exception label if the current instruction can fail.
1486 static void ia32_assign_exc_label(ir_node *node)
1488 /* assign a new ID to the instruction */
1489 set_ia32_exc_label_id(node, ++exc_label_id);
1491 ia32_emit_exc_label(node);
1493 be_emit_pad_comment();
1494 be_emit_cstring("/* exception to Block ");
1495 ia32_emit_cfop_target(node);
1496 be_emit_cstring(" */\n");
1497 be_emit_write_line();
1501 * Emits code for a node.
1503 static void ia32_emit_node(ir_node *node)
1505 ir_op *op = get_irn_op(node);
1507 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1509 if (is_ia32_irn(node)) {
1510 if (get_ia32_exc_label(node)) {
1511 /* emit the exception label of this instruction */
1512 ia32_assign_exc_label(node);
1514 if (mark_spill_reload) {
1515 if (is_ia32_is_spill(node)) {
1516 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1518 if (is_ia32_is_reload(node)) {
1519 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1521 if (is_ia32_is_remat(node)) {
1522 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1526 if (op->ops.generic) {
1527 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1529 be_dwarf_location(get_irn_dbg_info(node));
1534 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1539 int sp_change = arch_get_sp_bias(node);
1540 if (sp_change != 0) {
1541 assert(sp_change != SP_BIAS_RESET);
1542 callframe_offset += sp_change;
1543 be_dwarf_callframe_offset(callframe_offset);
1549 * Emits gas alignment directives
1551 static void ia32_emit_alignment(unsigned align, unsigned skip)
1553 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1557 * Emits gas alignment directives for Labels depended on cpu architecture.
1559 static void ia32_emit_align_label(void)
1561 unsigned align = ia32_cg_config.label_alignment;
1562 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1563 ia32_emit_alignment(align, maximum_skip);
1567 * Test whether a block should be aligned.
1568 * For cpus in the P4/Athlon class it is useful to align jump labels to
1569 * 16 bytes. However we should only do that if the alignment nops before the
1570 * label aren't executed more often than we have jumps to the label.
1572 static int should_align_block(const ir_node *block)
1574 static const double DELTA = .0001;
1575 ir_node *prev = get_prev_block_sched(block);
1576 double prev_freq = 0; /**< execfreq of the fallthrough block */
1577 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1581 if (ia32_cg_config.label_alignment_factor <= 0)
1584 block_freq = get_block_execfreq(block);
1585 if (block_freq < DELTA)
1588 n_cfgpreds = get_Block_n_cfgpreds(block);
1589 for (i = 0; i < n_cfgpreds; ++i) {
1590 const ir_node *pred = get_Block_cfgpred_block(block, i);
1591 double pred_freq = get_block_execfreq(pred);
1594 prev_freq += pred_freq;
1596 jmp_freq += pred_freq;
1600 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1603 jmp_freq /= prev_freq;
1605 return jmp_freq > ia32_cg_config.label_alignment_factor;
1609 * Emit the block header for a block.
1611 * @param block the block
1612 * @param prev_block the previous block
1614 static void ia32_emit_block_header(ir_node *block)
1616 ir_graph *irg = current_ir_graph;
1617 int need_label = block_needs_label(block);
1619 if (block == get_irg_end_block(irg))
1622 if (ia32_cg_config.label_alignment > 0) {
1623 /* align the current block if:
1624 * a) if should be aligned due to its execution frequency
1625 * b) there is no fall-through here
1627 if (should_align_block(block)) {
1628 ia32_emit_align_label();
1630 /* if the predecessor block has no fall-through,
1631 we can always align the label. */
1633 int has_fallthrough = 0;
1635 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1636 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1637 if (can_be_fallthrough(cfg_pred)) {
1638 has_fallthrough = 1;
1643 if (!has_fallthrough)
1644 ia32_emit_align_label();
1648 be_gas_begin_block(block, need_label);
1652 * Walks over the nodes in a block connected by scheduling edges
1653 * and emits code for each node.
1655 static void ia32_gen_block(ir_node *block)
1657 ia32_emit_block_header(block);
1660 ir_graph *irg = get_irn_irg(block);
1661 callframe_offset = 4; /* 4 bytes for the return address */
1662 /* ESP guessing, TODO perform a real ESP simulation */
1663 if (block != get_irg_start_block(irg)) {
1664 callframe_offset += frame_type_size;
1666 be_dwarf_callframe_offset(callframe_offset);
1669 /* emit the contents of the block */
1670 be_dwarf_location(get_irn_dbg_info(block));
1671 sched_foreach(block, node) {
1672 ia32_emit_node(node);
1676 typedef struct exc_entry {
1677 ir_node *exc_instr; /** The instruction that can issue an exception. */
1678 ir_node *block; /** The block to call then. */
1683 * Sets labels for control flow nodes (jump target).
1684 * Links control predecessors to there destination blocks.
1686 static void ia32_gen_labels(ir_node *block, void *data)
1688 exc_entry **exc_list = (exc_entry**)data;
1692 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1693 pred = get_Block_cfgpred(block, n);
1694 set_irn_link(pred, block);
1696 pred = skip_Proj(pred);
1697 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1702 ARR_APP1(exc_entry, *exc_list, e);
1703 set_irn_link(pred, block);
1709 * Compare two exception_entries.
1711 static int cmp_exc_entry(const void *a, const void *b)
1713 const exc_entry *ea = (const exc_entry*)a;
1714 const exc_entry *eb = (const exc_entry*)b;
1716 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1721 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1723 ir_entity *entity = get_irg_entity(irg);
1724 ir_type *type = get_entity_type(entity);
1725 size_t n_params = get_method_n_params(type);
1726 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1727 ir_type *arg_type = layout->arg_type;
1728 size_t n_members = get_compound_n_members(arg_type);
1729 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1732 for (i = 0; i < n_members; ++i) {
1733 ir_entity *member = get_compound_member(arg_type, i);
1735 if (!is_parameter_entity(member))
1737 param = get_entity_parameter_number(member);
1738 if (param == IR_VA_START_PARAMETER_NUMBER)
1740 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1741 infos[param].reg = NULL;
1742 infos[param].entity = member;
1749 * Main driver. Emits the code for one routine.
1751 void ia32_gen_routine(ir_graph *irg)
1753 ir_entity *entity = get_irg_entity(irg);
1754 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1755 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1756 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1757 ir_node **blk_sched = irg_data->blk_sched;
1758 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1759 parameter_dbg_info_t *infos;
1762 isa = (ia32_isa_t*) arch_env;
1763 do_pic = be_options.pic;
1765 be_gas_elf_type_char = '@';
1767 ia32_register_emitters();
1769 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1771 infos = construct_parameter_infos(irg);
1772 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1776 sp_relative = layout->sp_relative;
1777 if (layout->sp_relative) {
1778 ir_type *frame_type = get_irg_frame_type(irg);
1779 frame_type_size = get_type_size_bytes(frame_type);
1780 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1782 /* well not entirely correct here, we should emit this after the
1783 * "movl esp, ebp" */
1784 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1785 /* TODO: do not hardcode the following */
1786 be_dwarf_callframe_offset(8);
1787 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1790 /* we use links to point to target blocks */
1791 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1792 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1794 /* initialize next block links */
1795 n = ARR_LEN(blk_sched);
1796 for (i = 0; i < n; ++i) {
1797 ir_node *block = blk_sched[i];
1798 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1800 set_irn_link(block, prev);
1803 for (i = 0; i < n; ++i) {
1804 ir_node *block = blk_sched[i];
1806 ia32_gen_block(block);
1809 be_gas_emit_function_epilog(entity);
1811 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1813 /* Sort the exception table using the exception label id's.
1814 Those are ascending with ascending addresses. */
1815 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1819 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1820 be_emit_cstring("\t.long ");
1821 ia32_emit_exc_label(exc_list[e].exc_instr);
1823 be_emit_cstring("\t.long ");
1824 be_gas_emit_block_name(exc_list[e].block);
1828 DEL_ARR_F(exc_list);
1831 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1832 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1836 /* ==== Experimental binary emitter ==== */
1838 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1839 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1840 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1842 static void build_reg_map(void)
1844 reg_gp_map[REG_GP_EAX] = 0x0;
1845 reg_gp_map[REG_GP_ECX] = 0x1;
1846 reg_gp_map[REG_GP_EDX] = 0x2;
1847 reg_gp_map[REG_GP_EBX] = 0x3;
1848 reg_gp_map[REG_GP_ESP] = 0x4;
1849 reg_gp_map[REG_GP_EBP] = 0x5;
1850 reg_gp_map[REG_GP_ESI] = 0x6;
1851 reg_gp_map[REG_GP_EDI] = 0x7;
1854 /** Returns the encoding for a pnc field. */
1855 static unsigned char pnc2cc(ia32_condition_code_t cc)
1860 /** Sign extension bit values for binops */
1862 UNSIGNED_IMM = 0, /**< unsigned immediate */
1863 SIGNEXT_IMM = 2, /**< sign extended immediate */
1866 /** The mod encoding of the ModR/M */
1868 MOD_IND = 0x00, /**< [reg1] */
1869 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1870 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1871 MOD_REG = 0xC0 /**< reg1 */
1874 /** create R/M encoding for ModR/M */
1875 #define ENC_RM(x) (x)
1876 /** create REG encoding for ModR/M */
1877 #define ENC_REG(x) ((x) << 3)
1879 /** create encoding for a SIB byte */
1880 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1882 /* Node: The following routines are supposed to append bytes, words, dwords
1883 to the output stream.
1884 Currently the implementation is stupid in that it still creates output
1885 for an "assembler" in the form of .byte, .long
1886 We will change this when enough infrastructure is there to create complete
1887 machine code in memory/object files */
1889 static void bemit8(const unsigned char byte)
1891 be_emit_irprintf("\t.byte 0x%x\n", byte);
1892 be_emit_write_line();
1895 static void bemit16(const unsigned short u16)
1897 be_emit_irprintf("\t.word 0x%x\n", u16);
1898 be_emit_write_line();
1901 static void bemit32(const unsigned u32)
1903 be_emit_irprintf("\t.long 0x%x\n", u32);
1904 be_emit_write_line();
1908 * Emit address of an entity. If @p is_relative is true then a relative
1909 * offset from behind the address to the entity is created.
1911 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1914 if (entity == NULL) {
1919 /* the final version should remember the position in the bytestream
1920 and patch it with the correct address at linktime... */
1921 be_emit_cstring("\t.long ");
1924 be_gas_emit_entity(entity);
1926 if (get_entity_owner(entity) == get_tls_type()) {
1927 if (!entity_has_definition(entity)) {
1928 be_emit_cstring("@INDNTPOFF");
1930 be_emit_cstring("@NTPOFF");
1935 be_emit_cstring("-.");
1940 be_emit_irprintf("%+d", offset);
1943 be_emit_write_line();
1946 static void bemit_jmp_destination(const ir_node *dest_block)
1948 be_emit_cstring("\t.long ");
1949 be_gas_emit_block_name(dest_block);
1950 be_emit_cstring(" - . - 4\n");
1951 be_emit_write_line();
1954 /* end emit routines, all emitters following here should only use the functions
1957 typedef enum reg_modifier {
1962 /** Create a ModR/M byte for src1,src2 registers */
1963 static void bemit_modrr(const arch_register_t *src1,
1964 const arch_register_t *src2)
1966 unsigned char modrm = MOD_REG;
1967 modrm |= ENC_RM(reg_gp_map[src1->index]);
1968 modrm |= ENC_REG(reg_gp_map[src2->index]);
1972 /** Create a ModR/M8 byte for src1,src2 registers */
1973 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1974 reg_modifier_t high_part2, const arch_register_t *src2)
1976 unsigned char modrm = MOD_REG;
1977 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1978 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1982 /** Create a ModR/M byte for one register and extension */
1983 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1985 unsigned char modrm = MOD_REG;
1987 modrm |= ENC_RM(reg_gp_map[reg->index]);
1988 modrm |= ENC_REG(ext);
1992 /** Create a ModR/M8 byte for one register */
1993 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1995 unsigned char modrm = MOD_REG;
1996 assert(reg_gp_map[reg->index] < 4);
1997 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2003 * Calculate the size of an signed immediate in bytes.
2005 * @param offset an offset
2007 static unsigned get_signed_imm_size(int offset)
2009 if (-128 <= offset && offset < 128) {
2011 } else if (-32768 <= offset && offset < 32768) {
2019 * Emit an address mode.
2021 * @param reg content of the reg field: either a register index or an opcode extension
2022 * @param node the node
2024 static void bemit_mod_am(unsigned reg, const ir_node *node)
2026 ir_entity *ent = get_ia32_am_sc(node);
2027 int offs = get_ia32_am_offs_int(node);
2028 ir_node *base = get_irn_n(node, n_ia32_base);
2029 int has_base = !is_ia32_NoReg_GP(base);
2030 ir_node *idx = get_irn_n(node, n_ia32_index);
2031 int has_index = !is_ia32_NoReg_GP(idx);
2034 unsigned emitoffs = 0;
2035 bool emitsib = false;
2038 /* set the mod part depending on displacement */
2040 modrm |= MOD_IND_WORD_OFS;
2042 } else if (offs == 0) {
2045 } else if (-128 <= offs && offs < 128) {
2046 modrm |= MOD_IND_BYTE_OFS;
2049 modrm |= MOD_IND_WORD_OFS;
2054 const arch_register_t *base_reg = arch_get_irn_register(base);
2055 base_enc = reg_gp_map[base_reg->index];
2057 /* Use the EBP encoding + MOD_IND if NO base register. There is
2058 * always a 32bit offset present in this case. */
2064 /* Determine if we need a SIB byte. */
2066 const arch_register_t *reg_index = arch_get_irn_register(idx);
2067 int scale = get_ia32_am_scale(node);
2069 /* R/M set to ESP means SIB in 32bit mode. */
2070 modrm |= ENC_RM(0x04);
2071 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2073 } else if (base_enc == 0x04) {
2074 /* for the above reason we are forced to emit a SIB when base is ESP.
2075 * Only the base is used, index must be ESP too, which means no index.
2077 modrm |= ENC_RM(0x04);
2078 sib = ENC_SIB(0, 0x04, 0x04);
2081 modrm |= ENC_RM(base_enc);
2084 /* We are forced to emit an 8bit offset as EBP base without offset is a
2085 * special case for SIB without base register. */
2086 if (base_enc == 0x05 && emitoffs == 0) {
2087 modrm |= MOD_IND_BYTE_OFS;
2091 modrm |= ENC_REG(reg);
2097 /* emit displacement */
2098 if (emitoffs == 8) {
2099 bemit8((unsigned) offs);
2100 } else if (emitoffs == 32) {
2101 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2106 * Emit a binop with a immediate operand.
2108 * @param node the node to emit
2109 * @param opcode_eax the opcode for the op eax, imm variant
2110 * @param opcode the opcode for the reg, imm variant
2111 * @param ruval the opcode extension for opcode
2113 static void bemit_binop_with_imm(
2114 const ir_node *node,
2115 unsigned char opcode_ax,
2116 unsigned char opcode, unsigned char ruval)
2118 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2119 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2120 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2123 /* Some instructions (test) have no short form with 32bit value + 8bit
2125 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2128 /* check for sign extension */
2129 size = get_signed_imm_size(attr->offset);
2134 bemit8(opcode | SIGNEXT_IMM);
2135 /* cmp has this special mode */
2136 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2137 bemit_mod_am(ruval, node);
2139 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2140 bemit_modru(reg, ruval);
2142 bemit8((unsigned char)attr->offset);
2146 /* check for eax variant: this variant is shorter for 32bit immediates only */
2147 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2149 bemit_mod_am(ruval, node);
2151 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2152 if (reg->index == REG_GP_EAX) {
2156 bemit_modru(reg, ruval);
2159 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2162 panic("invalid imm size?!?");
2168 static void bemit_binop_2(const ir_node *node, unsigned code)
2170 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2172 if (get_ia32_op_type(node) == ia32_Normal) {
2173 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2174 bemit_modrr(op2, out);
2176 bemit_mod_am(reg_gp_map[out->index], node);
2183 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2185 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2186 if (is_ia32_Immediate(right)) {
2187 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2189 bemit_binop_2(node, opcodes[0]);
2196 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2199 if (get_ia32_op_type(node) == ia32_Normal) {
2200 const arch_register_t *in = arch_get_irn_register_in(node, input);
2201 bemit_modru(in, ext);
2203 bemit_mod_am(ext, node);
2207 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2209 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2210 bemit_unop(node, code, reg_gp_map[out->index], input);
2213 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2215 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2218 bemit8(size == 8 ? code : code + 1);
2219 bemit_mod_am(ext, node);
2222 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2225 bemit_unop_reg(node, code, input);
2228 static void bemit_immediate(const ir_node *node, bool relative)
2230 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2231 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2234 static void bemit_copy(const ir_node *copy)
2236 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2237 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2241 /* copies of vf nodes aren't real... */
2242 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2245 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2247 bemit_modrr(in, out);
2250 static void bemit_perm(const ir_node *node)
2252 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2253 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2254 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2256 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2258 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2259 if (in0->index == REG_GP_EAX) {
2260 bemit8(0x90 + reg_gp_map[in1->index]);
2261 } else if (in1->index == REG_GP_EAX) {
2262 bemit8(0x90 + reg_gp_map[in0->index]);
2265 bemit_modrr(in0, in1);
2267 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2268 panic("unimplemented"); // TODO implement
2269 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2270 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2271 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2272 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2274 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2277 panic("unexpected register class in be_Perm (%+F)", node);
2281 static void bemit_xor0(const ir_node *node)
2283 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2285 bemit_modrr(out, out);
2288 static void bemit_mov_const(const ir_node *node)
2290 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2291 bemit8(0xB8 + reg_gp_map[out->index]);
2292 bemit_immediate(node, false);
2296 * Creates a function for a Binop with 3 possible encodings.
2298 #define BINOP(op, op0, op1, op2, op2_ext) \
2299 static void bemit_ ## op(const ir_node *node) { \
2300 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2301 bemit_binop(node, op ## _codes); \
2304 /* insn def eax,imm imm */
2305 BINOP(add, 0x03, 0x05, 0x81, 0)
2306 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2307 BINOP(adc, 0x13, 0x15, 0x81, 2)
2308 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2309 BINOP(and, 0x23, 0x25, 0x81, 4)
2310 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2311 BINOP(xor, 0x33, 0x35, 0x81, 6)
2312 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2314 #define BINOPMEM(op, ext) \
2315 static void bemit_##op(const ir_node *node) \
2318 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2321 val = get_irn_n(node, n_ia32_unary_op); \
2322 if (is_ia32_Immediate(val)) { \
2323 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2324 int offset = attr->offset; \
2325 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2327 bemit_mod_am(ext, node); \
2331 bemit_mod_am(ext, node); \
2335 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2339 bemit8(ext << 3 | 1); \
2340 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2344 static void bemit_##op##8bit(const ir_node *node) \
2346 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2347 if (is_ia32_Immediate(val)) { \
2349 bemit_mod_am(ext, node); \
2350 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2353 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2365 * Creates a function for an Unop with code /ext encoding.
2367 #define UNOP(op, code, ext, input) \
2368 static void bemit_ ## op(const ir_node *node) { \
2369 bemit_unop(node, code, ext, input); \
2372 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2373 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2374 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2375 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2376 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2377 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2379 /* TODO: am support for IJmp */
2380 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2382 #define SHIFT(op, ext) \
2383 static void bemit_##op(const ir_node *node) \
2385 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2386 ir_node *count = get_irn_n(node, 1); \
2387 if (is_ia32_Immediate(count)) { \
2388 int offset = get_ia32_immediate_attr_const(count)->offset; \
2389 if (offset == 1) { \
2391 bemit_modru(out, ext); \
2394 bemit_modru(out, ext); \
2399 bemit_modru(out, ext); \
2403 static void bemit_##op##mem(const ir_node *node) \
2406 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2409 count = get_irn_n(node, 1); \
2410 if (is_ia32_Immediate(count)) { \
2411 int offset = get_ia32_immediate_attr_const(count)->offset; \
2412 if (offset == 1) { \
2413 bemit8(size == 8 ? 0xD0 : 0xD1); \
2414 bemit_mod_am(ext, node); \
2416 bemit8(size == 8 ? 0xC0 : 0xC1); \
2417 bemit_mod_am(ext, node); \
2421 bemit8(size == 8 ? 0xD2 : 0xD3); \
2422 bemit_mod_am(ext, node); \
2432 static void bemit_shld(const ir_node *node)
2434 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2435 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2436 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2438 if (is_ia32_Immediate(count)) {
2440 bemit_modrr(out, in);
2441 bemit8(get_ia32_immediate_attr_const(count)->offset);
2444 bemit_modrr(out, in);
2448 static void bemit_shrd(const ir_node *node)
2450 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2451 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2452 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2454 if (is_ia32_Immediate(count)) {
2456 bemit_modrr(out, in);
2457 bemit8(get_ia32_immediate_attr_const(count)->offset);
2460 bemit_modrr(out, in);
2464 static void bemit_sbb0(ir_node const *const node)
2466 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2467 unsigned char const reg = reg_gp_map[out->index];
2469 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2473 * binary emitter for setcc.
2475 static void bemit_setcc(const ir_node *node)
2477 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2479 ia32_condition_code_t cc = get_ia32_condcode(node);
2480 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2481 if (cc & ia32_cc_float_parity_cases) {
2482 if (cc & ia32_cc_negated) {
2485 bemit8(0x90 | pnc2cc(cc));
2486 bemit_modrm8(REG_LOW, dreg);
2491 bemit_modrm8(REG_HIGH, dreg);
2493 /* orb %>dreg, %<dreg */
2495 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2499 bemit8(0x90 | pnc2cc(cc));
2500 bemit_modrm8(REG_LOW, dreg);
2505 bemit_modrm8(REG_HIGH, dreg);
2507 /* andb %>dreg, %<dreg */
2509 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2514 bemit8(0x90 | pnc2cc(cc));
2515 bemit_modrm8(REG_LOW, dreg);
2519 static void bemit_bsf(ir_node const *const node)
2521 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2524 static void bemit_bsr(ir_node const *const node)
2526 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2529 static void bemit_bswap(ir_node const *const node)
2532 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2535 static void bemit_bt(ir_node const *const node)
2538 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2539 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2540 if (is_ia32_Immediate(right)) {
2541 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2542 int const offset = attr->offset;
2543 assert(!attr->symconst);
2544 assert(get_signed_imm_size(offset) == 1);
2546 bemit_modru(lreg, 4);
2550 bemit_modrr(lreg, arch_get_irn_register(right));
2554 static void bemit_cmovcc(const ir_node *node)
2556 const ia32_attr_t *attr = get_ia32_attr_const(node);
2557 int ins_permuted = attr->data.ins_permuted;
2558 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2559 ia32_condition_code_t cc = get_ia32_condcode(node);
2560 const arch_register_t *in_true;
2561 const arch_register_t *in_false;
2563 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2565 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2566 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2568 /* should be same constraint fullfilled? */
2569 if (out == in_false) {
2570 /* yes -> nothing to do */
2571 } else if (out == in_true) {
2572 assert(get_ia32_op_type(node) == ia32_Normal);
2573 ins_permuted = !ins_permuted;
2577 bemit8(0x8B); // mov %in_false, %out
2578 bemit_modrr(in_false, out);
2582 cc = ia32_negate_condition_code(cc);
2584 if (cc & ia32_cc_float_parity_cases)
2585 panic("cmov can't handle parity float cases");
2588 bemit8(0x40 | pnc2cc(cc));
2589 if (get_ia32_op_type(node) == ia32_Normal) {
2590 bemit_modrr(in_true, out);
2592 bemit_mod_am(reg_gp_map[out->index], node);
2596 static void bemit_cmp(const ir_node *node)
2598 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2604 right = get_irn_n(node, n_ia32_binary_right);
2605 if (is_ia32_Immediate(right)) {
2606 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2607 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2608 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2611 if (attr->symconst != NULL) {
2614 /* check for sign extension */
2615 size = get_signed_imm_size(attr->offset);
2620 bemit8(0x81 | SIGNEXT_IMM);
2621 /* cmp has this special mode */
2622 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2623 bemit_mod_am(7, node);
2625 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2626 bemit_modru(reg, 7);
2628 bemit8((unsigned char)attr->offset);
2632 /* check for eax variant: this variant is shorter for 32bit immediates only */
2633 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2635 bemit_mod_am(7, node);
2637 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2638 if (reg->index == REG_GP_EAX) {
2642 bemit_modru(reg, 7);
2645 if (ls_size == 16) {
2646 bemit16(attr->offset);
2648 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2652 panic("invalid imm size?!?");
2654 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2656 if (get_ia32_op_type(node) == ia32_Normal) {
2657 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2658 bemit_modrr(op2, out);
2660 bemit_mod_am(reg_gp_map[out->index], node);
2665 static void bemit_cmp8bit(const ir_node *node)
2667 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2668 if (is_ia32_Immediate(right)) {
2669 if (get_ia32_op_type(node) == ia32_Normal) {
2670 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2671 if (out->index == REG_GP_EAX) {
2675 bemit_modru(out, 7);
2679 bemit_mod_am(7, node);
2681 bemit8(get_ia32_immediate_attr_const(right)->offset);
2683 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2685 if (get_ia32_op_type(node) == ia32_Normal) {
2686 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2687 bemit_modrr(out, in);
2689 bemit_mod_am(reg_gp_map[out->index], node);
2694 static void bemit_test8bit(const ir_node *node)
2696 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2697 if (is_ia32_Immediate(right)) {
2698 if (get_ia32_op_type(node) == ia32_Normal) {
2699 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2700 if (out->index == REG_GP_EAX) {
2704 bemit_modru(out, 0);
2708 bemit_mod_am(0, node);
2710 bemit8(get_ia32_immediate_attr_const(right)->offset);
2712 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2714 if (get_ia32_op_type(node) == ia32_Normal) {
2715 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2716 bemit_modrr(out, in);
2718 bemit_mod_am(reg_gp_map[out->index], node);
2723 static void bemit_imul(const ir_node *node)
2725 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2726 /* Do we need the immediate form? */
2727 if (is_ia32_Immediate(right)) {
2728 int imm = get_ia32_immediate_attr_const(right)->offset;
2729 if (get_signed_imm_size(imm) == 1) {
2730 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2733 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2737 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2741 static void bemit_dec(const ir_node *node)
2743 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2744 bemit8(0x48 + reg_gp_map[out->index]);
2747 static void bemit_inc(const ir_node *node)
2749 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2750 bemit8(0x40 + reg_gp_map[out->index]);
2753 #define UNOPMEM(op, code, ext) \
2754 static void bemit_##op(const ir_node *node) \
2756 bemit_unop_mem(node, code, ext); \
2759 UNOPMEM(notmem, 0xF6, 2)
2760 UNOPMEM(negmem, 0xF6, 3)
2761 UNOPMEM(incmem, 0xFE, 0)
2762 UNOPMEM(decmem, 0xFE, 1)
2764 static void bemit_ldtls(const ir_node *node)
2766 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2768 bemit8(0x65); // gs:
2769 if (out->index == REG_GP_EAX) {
2770 bemit8(0xA1); // movl 0, %eax
2772 bemit8(0x8B); // movl 0, %reg
2773 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2781 static void bemit_lea(const ir_node *node)
2783 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2785 bemit_mod_am(reg_gp_map[out->index], node);
2788 /* helper function for bemit_minus64bit */
2789 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2791 bemit8(0x8B); // movl %src, %dst
2792 bemit_modrr(src, dst);
2795 /* helper function for bemit_minus64bit */
2796 static void bemit_helper_neg(const arch_register_t *reg)
2798 bemit8(0xF7); // negl %reg
2799 bemit_modru(reg, 3);
2802 /* helper function for bemit_minus64bit */
2803 static void bemit_helper_sbb0(const arch_register_t *reg)
2805 bemit8(0x83); // sbbl $0, %reg
2806 bemit_modru(reg, 3);
2810 /* helper function for bemit_minus64bit */
2811 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2813 bemit8(0x1B); // sbbl %src, %dst
2814 bemit_modrr(src, dst);
2817 /* helper function for bemit_minus64bit */
2818 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2820 if (src->index == REG_GP_EAX) {
2821 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2822 } else if (dst->index == REG_GP_EAX) {
2823 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2825 bemit8(0x87); // xchgl %src, %dst
2826 bemit_modrr(src, dst);
2830 /* helper function for bemit_minus64bit */
2831 static void bemit_helper_zero(const arch_register_t *reg)
2833 bemit8(0x33); // xorl %reg, %reg
2834 bemit_modrr(reg, reg);
2837 static void bemit_minus64bit(const ir_node *node)
2839 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2840 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2841 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2842 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2844 if (out_lo == in_lo) {
2845 if (out_hi != in_hi) {
2846 /* a -> a, b -> d */
2849 /* a -> a, b -> b */
2852 } else if (out_lo == in_hi) {
2853 if (out_hi == in_lo) {
2854 /* a -> b, b -> a */
2855 bemit_helper_xchg(in_lo, in_hi);
2858 /* a -> b, b -> d */
2859 bemit_helper_mov(in_hi, out_hi);
2860 bemit_helper_mov(in_lo, out_lo);
2864 if (out_hi == in_lo) {
2865 /* a -> c, b -> a */
2866 bemit_helper_mov(in_lo, out_lo);
2868 } else if (out_hi == in_hi) {
2869 /* a -> c, b -> b */
2870 bemit_helper_mov(in_lo, out_lo);
2873 /* a -> c, b -> d */
2874 bemit_helper_mov(in_lo, out_lo);
2880 bemit_helper_neg( out_hi);
2881 bemit_helper_neg( out_lo);
2882 bemit_helper_sbb0(out_hi);
2886 bemit_helper_zero(out_hi);
2887 bemit_helper_neg( out_lo);
2888 bemit_helper_sbb( in_hi, out_hi);
2892 * Emit a single opcode.
2894 #define EMIT_SINGLEOP(op, code) \
2895 static void bemit_ ## op(const ir_node *node) { \
2900 //EMIT_SINGLEOP(daa, 0x27)
2901 //EMIT_SINGLEOP(das, 0x2F)
2902 //EMIT_SINGLEOP(aaa, 0x37)
2903 //EMIT_SINGLEOP(aas, 0x3F)
2904 //EMIT_SINGLEOP(nop, 0x90)
2905 EMIT_SINGLEOP(cwtl, 0x98)
2906 EMIT_SINGLEOP(cltd, 0x99)
2907 //EMIT_SINGLEOP(fwait, 0x9B)
2908 EMIT_SINGLEOP(sahf, 0x9E)
2909 //EMIT_SINGLEOP(popf, 0x9D)
2910 EMIT_SINGLEOP(leave, 0xC9)
2911 EMIT_SINGLEOP(int3, 0xCC)
2912 //EMIT_SINGLEOP(iret, 0xCF)
2913 //EMIT_SINGLEOP(xlat, 0xD7)
2914 //EMIT_SINGLEOP(lock, 0xF0)
2915 EMIT_SINGLEOP(rep, 0xF3)
2916 //EMIT_SINGLEOP(halt, 0xF4)
2917 EMIT_SINGLEOP(cmc, 0xF5)
2918 EMIT_SINGLEOP(stc, 0xF9)
2919 //EMIT_SINGLEOP(cli, 0xFA)
2920 //EMIT_SINGLEOP(sti, 0xFB)
2921 //EMIT_SINGLEOP(std, 0xFD)
2924 * Emits a MOV out, [MEM].
2926 static void bemit_load(const ir_node *node)
2928 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2930 if (out->index == REG_GP_EAX) {
2931 ir_node *base = get_irn_n(node, n_ia32_base);
2932 int has_base = !is_ia32_NoReg_GP(base);
2933 ir_node *idx = get_irn_n(node, n_ia32_index);
2934 int has_index = !is_ia32_NoReg_GP(idx);
2935 if (!has_base && !has_index) {
2936 ir_entity *ent = get_ia32_am_sc(node);
2937 int offs = get_ia32_am_offs_int(node);
2938 /* load from constant address to EAX can be encoded
2941 bemit_entity(ent, 0, offs, false);
2946 bemit_mod_am(reg_gp_map[out->index], node);
2950 * Emits a MOV [mem], in.
2952 static void bemit_store(const ir_node *node)
2954 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2955 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2957 if (is_ia32_Immediate(value)) {
2960 bemit_mod_am(0, node);
2961 bemit8(get_ia32_immediate_attr_const(value)->offset);
2962 } else if (size == 16) {
2965 bemit_mod_am(0, node);
2966 bemit16(get_ia32_immediate_attr_const(value)->offset);
2969 bemit_mod_am(0, node);
2970 bemit_immediate(value, false);
2973 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2975 if (in->index == REG_GP_EAX) {
2976 ir_node *base = get_irn_n(node, n_ia32_base);
2977 int has_base = !is_ia32_NoReg_GP(base);
2978 ir_node *idx = get_irn_n(node, n_ia32_index);
2979 int has_index = !is_ia32_NoReg_GP(idx);
2980 if (!has_base && !has_index) {
2981 ir_entity *ent = get_ia32_am_sc(node);
2982 int offs = get_ia32_am_offs_int(node);
2983 /* store to constant address from EAX can be encoded as
2984 * 0xA2/0xA3 [offset]*/
2992 bemit_entity(ent, 0, offs, false);
3004 bemit_mod_am(reg_gp_map[in->index], node);
3008 static void bemit_conv_i2i(const ir_node *node)
3013 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
3014 unsigned opcode = 0xB6;
3015 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3016 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3017 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3020 static void bemit_popcnt(ir_node const *const node)
3023 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
3029 static void bemit_push(const ir_node *node)
3031 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3033 if (is_ia32_Immediate(value)) {
3034 const ia32_immediate_attr_t *attr
3035 = get_ia32_immediate_attr_const(value);
3036 unsigned size = get_signed_imm_size(attr->offset);
3042 bemit8((unsigned char)attr->offset);
3047 bemit_immediate(value, false);
3050 } else if (is_ia32_NoReg_GP(value)) {
3052 bemit_mod_am(6, node);
3054 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3055 bemit8(0x50 + reg_gp_map[reg->index]);
3062 static void bemit_pop(const ir_node *node)
3064 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3065 bemit8(0x58 + reg_gp_map[reg->index]);
3068 static void bemit_popmem(const ir_node *node)
3071 bemit_mod_am(0, node);
3074 static void bemit_call(const ir_node *node)
3076 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3078 if (is_ia32_Immediate(proc)) {
3080 bemit_immediate(proc, true);
3082 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3086 static void bemit_jmp(const ir_node *dest_block)
3089 bemit_jmp_destination(dest_block);
3092 static void bemit_jump(const ir_node *node)
3094 if (can_be_fallthrough(node))
3097 bemit_jmp(get_cfop_target_block(node));
3100 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3102 unsigned char cc = pnc2cc(pnc);
3105 bemit_jmp_destination(dest_block);
3108 static void bemit_jp(bool odd, const ir_node *dest_block)
3112 bemit_jmp_destination(dest_block);
3115 static void bemit_ia32_jcc(const ir_node *node)
3117 ia32_condition_code_t cc = get_ia32_condcode(node);
3118 const ir_node *proj_true;
3119 const ir_node *proj_false;
3120 const ir_node *dest_true;
3121 const ir_node *dest_false;
3123 cc = determine_final_cc(node, 0, cc);
3125 /* get both Projs */
3126 proj_true = get_proj(node, pn_ia32_Jcc_true);
3127 assert(proj_true && "Jcc without true Proj");
3129 proj_false = get_proj(node, pn_ia32_Jcc_false);
3130 assert(proj_false && "Jcc without false Proj");
3132 if (can_be_fallthrough(proj_true)) {
3133 /* exchange both proj's so the second one can be omitted */
3134 const ir_node *t = proj_true;
3136 proj_true = proj_false;
3138 cc = ia32_negate_condition_code(cc);
3141 dest_true = get_cfop_target_block(proj_true);
3142 dest_false = get_cfop_target_block(proj_false);
3144 if (cc & ia32_cc_float_parity_cases) {
3145 /* Some floating point comparisons require a test of the parity flag,
3146 * which indicates that the result is unordered */
3147 if (cc & ia32_cc_negated) {
3148 bemit_jp(false, dest_true);
3150 /* we need a local label if the false proj is a fallthrough
3151 * as the falseblock might have no label emitted then */
3152 if (can_be_fallthrough(proj_false)) {
3154 bemit8(0x06); // jp + 6
3156 bemit_jp(false, dest_false);
3160 bemit_jcc(cc, dest_true);
3162 /* the second Proj might be a fallthrough */
3163 if (can_be_fallthrough(proj_false)) {
3164 /* it's a fallthrough */
3166 bemit_jmp(dest_false);
3170 static void bemit_switchjmp(const ir_node *node)
3172 ir_entity *jump_table = get_ia32_am_sc(node);
3173 const ir_switch_table *table = get_ia32_switch_table(node);
3175 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3176 bemit_mod_am(0x05, node);
3178 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3184 static void bemit_return(const ir_node *node)
3186 unsigned pop = be_Return_get_pop(node);
3187 if (pop > 0 || be_Return_get_emit_pop(node)) {
3189 assert(pop <= 0xffff);
3196 static void bemit_subsp(const ir_node *node)
3198 const arch_register_t *out;
3201 /* mov %esp, %out */
3203 out = arch_get_irn_register_out(node, 1);
3204 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3207 static void bemit_incsp(const ir_node *node)
3210 const arch_register_t *reg;
3214 offs = be_get_IncSP_offset(node);
3225 size = get_signed_imm_size(offs);
3226 bemit8(size == 1 ? 0x83 : 0x81);
3228 reg = arch_get_irn_register_out(node, 0);
3229 bemit_modru(reg, ext);
3238 static void bemit_copybi(const ir_node *node)
3240 unsigned size = get_ia32_copyb_size(node);
3242 bemit8(0xA4); // movsb
3245 bemit8(0xA5); // movsw
3249 bemit8(0xA5); // movsl
3253 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3255 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3256 arch_register_t const *const st0 = &ia32_registers[REG_ST0];
3257 if (get_ia32_op_type(node) == ia32_Normal) {
3258 arch_register_t const *const out = attr->x87[2];
3259 assert(out == attr->x87[0] || out == attr->x87[1]);
3260 assert(!attr->attr.data.ins_permuted);
3262 unsigned char op0 = 0xD8;
3263 if (out != st0) op0 |= 0x04;
3264 if (attr->pop) op0 |= 0x02;
3267 unsigned op = op_rev;
3268 arch_register_t const *reg = attr->x87[0];
3273 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(reg->index));
3275 assert(attr->x87[2] == st0);
3278 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3279 bemit8(size == 32 ? 0xD8 : 0xDC);
3280 bemit_mod_am(attr->attr.data.ins_permuted ? op_rev : op_fwd, node);
3284 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3287 bemit8(op1 + get_ia32_x87_attr_const(node)->x87[0]->index);
3290 static void bemit_fabs(const ir_node *node)
3298 static void bemit_fadd(const ir_node *node)
3300 bemit_fbinop(node, 0, 0);
3303 static void bemit_fchs(const ir_node *node)
3311 static void bemit_fdiv(const ir_node *node)
3313 bemit_fbinop(node, 6, 7);
3316 static void bemit_ffreep(ir_node const *const node)
3318 bemit_fop_reg(node, 0xDF, 0xC0);
3321 static void bemit_fild(const ir_node *node)
3323 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3325 bemit8(0xDF); // filds
3326 bemit_mod_am(0, node);
3330 bemit8(0xDB); // fildl
3331 bemit_mod_am(0, node);
3335 bemit8(0xDF); // fildll
3336 bemit_mod_am(5, node);
3340 panic("invalid mode size");
3344 static void bemit_fist(const ir_node *node)
3347 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3349 case 16: bemit8(0xDF); op = 2; break; // fist[p]s
3350 case 32: bemit8(0xDB); op = 2; break; // fist[p]l
3351 case 64: bemit8(0xDF); op = 6; break; // fistpll
3352 default: panic("invalid mode size");
3354 if (get_ia32_x87_attr_const(node)->pop)
3356 // There is only a pop variant for 64 bit integer store.
3357 assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
3358 bemit_mod_am(op, node);
3361 static void bemit_fisttp(ir_node const *const node)
3363 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3364 case 16: bemit8(0xDF); break; // fisttps
3365 case 32: bemit8(0xDB); break; // fisttpl
3366 case 64: bemit8(0xDD); break; // fisttpll
3367 default: panic("Invalid mode size");
3369 bemit_mod_am(1, node);
3372 static void bemit_fld(const ir_node *node)
3374 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3376 bemit8(0xD9); // flds
3377 bemit_mod_am(0, node);
3381 bemit8(0xDD); // fldl
3382 bemit_mod_am(0, node);
3387 bemit8(0xDB); // fldt
3388 bemit_mod_am(5, node);
3392 panic("invalid mode size");
3396 static void bemit_fld1(const ir_node *node)
3400 bemit8(0xE8); // fld1
3403 static void bemit_fldcw(const ir_node *node)
3405 bemit8(0xD9); // fldcw
3406 bemit_mod_am(5, node);
3409 static void bemit_fldz(const ir_node *node)
3413 bemit8(0xEE); // fldz
3416 static void bemit_fmul(const ir_node *node)
3418 bemit_fbinop(node, 1, 1);
3421 static void bemit_fpop(const ir_node *node)
3423 bemit_fop_reg(node, 0xDD, 0xD8);
3426 static void bemit_fpush(const ir_node *node)
3428 bemit_fop_reg(node, 0xD9, 0xC0);
3431 static void bemit_fpushcopy(const ir_node *node)
3433 bemit_fop_reg(node, 0xD9, 0xC0);
3436 static void bemit_fst(const ir_node *node)
3439 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3441 case 32: bemit8(0xD9); op = 2; break; // fst[p]s
3442 case 64: bemit8(0xDD); op = 2; break; // fst[p]l
3444 case 96: bemit8(0xDB); op = 6; break; // fstpt
3445 default: panic("invalid mode size");
3447 if (get_ia32_x87_attr_const(node)->pop)
3449 // There is only a pop variant for long double store.
3450 assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
3451 bemit_mod_am(op, node);
3454 static void bemit_fsub(const ir_node *node)
3456 bemit_fbinop(node, 4, 5);
3459 static void bemit_fnstcw(const ir_node *node)
3461 bemit8(0xD9); // fnstcw
3462 bemit_mod_am(7, node);
3465 static void bemit_fnstsw(void)
3467 bemit8(0xDF); // fnstsw %ax
3471 static void bemit_ftstfnstsw(const ir_node *node)
3475 bemit8(0xD9); // ftst
3480 static void bemit_fucomi(const ir_node *node)
3482 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3483 bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
3484 bemit8(0xE8 + attr->x87[1]->index);
3487 static void bemit_fucomfnstsw(const ir_node *node)
3489 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3490 bemit8(0xDD); // fucom[p]
3491 bemit8((attr->pop ? 0xE8 : 0xE0) + attr->x87[1]->index);
3495 static void bemit_fucomppfnstsw(const ir_node *node)
3499 bemit8(0xDA); // fucompp
3504 static void bemit_fxch(const ir_node *node)
3506 bemit_fop_reg(node, 0xD9, 0xC8);
3510 * The type of a emitter function.
3512 typedef void (*emit_func) (const ir_node *);
3515 * Set a node emitter. Make it a bit more type safe.
3517 static void register_emitter(ir_op *op, emit_func func)
3519 op->ops.generic = (op_func) func;
3522 static void ia32_register_binary_emitters(void)
3524 /* first clear the generic function pointer for all ops */
3525 ir_clear_opcodes_generic_func();
3527 /* benode emitter */
3528 register_emitter(op_be_Copy, bemit_copy);
3529 register_emitter(op_be_CopyKeep, bemit_copy);
3530 register_emitter(op_be_IncSP, bemit_incsp);
3531 register_emitter(op_be_Perm, bemit_perm);
3532 register_emitter(op_be_Return, bemit_return);
3533 register_emitter(op_ia32_Adc, bemit_adc);
3534 register_emitter(op_ia32_Add, bemit_add);
3535 register_emitter(op_ia32_AddMem, bemit_addmem);
3536 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3537 register_emitter(op_ia32_And, bemit_and);
3538 register_emitter(op_ia32_AndMem, bemit_andmem);
3539 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3540 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3541 register_emitter(op_ia32_Breakpoint, bemit_int3);
3542 register_emitter(op_ia32_Bsf, bemit_bsf);
3543 register_emitter(op_ia32_Bsr, bemit_bsr);
3544 register_emitter(op_ia32_Bswap, bemit_bswap);
3545 register_emitter(op_ia32_Bt, bemit_bt);
3546 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3547 register_emitter(op_ia32_Call, bemit_call);
3548 register_emitter(op_ia32_Cltd, bemit_cltd);
3549 register_emitter(op_ia32_Cmc, bemit_cmc);
3550 register_emitter(op_ia32_Cmp, bemit_cmp);
3551 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3552 register_emitter(op_ia32_Const, bemit_mov_const);
3553 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3554 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3555 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3556 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3557 register_emitter(op_ia32_Dec, bemit_dec);
3558 register_emitter(op_ia32_DecMem, bemit_decmem);
3559 register_emitter(op_ia32_Div, bemit_div);
3560 register_emitter(op_ia32_FldCW, bemit_fldcw);
3561 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3562 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3563 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3564 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3565 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3566 register_emitter(op_ia32_IDiv, bemit_idiv);
3567 register_emitter(op_ia32_IJmp, bemit_ijmp);
3568 register_emitter(op_ia32_IMul, bemit_imul);
3569 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3570 register_emitter(op_ia32_Inc, bemit_inc);
3571 register_emitter(op_ia32_IncMem, bemit_incmem);
3572 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3573 register_emitter(op_ia32_Jmp, bemit_jump);
3574 register_emitter(op_ia32_LdTls, bemit_ldtls);
3575 register_emitter(op_ia32_Lea, bemit_lea);
3576 register_emitter(op_ia32_Leave, bemit_leave);
3577 register_emitter(op_ia32_Load, bemit_load);
3578 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3579 register_emitter(op_ia32_Mul, bemit_mul);
3580 register_emitter(op_ia32_Neg, bemit_neg);
3581 register_emitter(op_ia32_NegMem, bemit_negmem);
3582 register_emitter(op_ia32_Not, bemit_not);
3583 register_emitter(op_ia32_NotMem, bemit_notmem);
3584 register_emitter(op_ia32_Or, bemit_or);
3585 register_emitter(op_ia32_OrMem, bemit_ormem);
3586 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3587 register_emitter(op_ia32_Pop, bemit_pop);
3588 register_emitter(op_ia32_PopEbp, bemit_pop);
3589 register_emitter(op_ia32_PopMem, bemit_popmem);
3590 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3591 register_emitter(op_ia32_Push, bemit_push);
3592 register_emitter(op_ia32_RepPrefix, bemit_rep);
3593 register_emitter(op_ia32_Rol, bemit_rol);
3594 register_emitter(op_ia32_RolMem, bemit_rolmem);
3595 register_emitter(op_ia32_Ror, bemit_ror);
3596 register_emitter(op_ia32_RorMem, bemit_rormem);
3597 register_emitter(op_ia32_Sahf, bemit_sahf);
3598 register_emitter(op_ia32_Sar, bemit_sar);
3599 register_emitter(op_ia32_SarMem, bemit_sarmem);
3600 register_emitter(op_ia32_Sbb, bemit_sbb);
3601 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3602 register_emitter(op_ia32_Setcc, bemit_setcc);
3603 register_emitter(op_ia32_Shl, bemit_shl);
3604 register_emitter(op_ia32_ShlD, bemit_shld);
3605 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3606 register_emitter(op_ia32_Shr, bemit_shr);
3607 register_emitter(op_ia32_ShrD, bemit_shrd);
3608 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3609 register_emitter(op_ia32_Stc, bemit_stc);
3610 register_emitter(op_ia32_Store, bemit_store);
3611 register_emitter(op_ia32_Store8Bit, bemit_store);
3612 register_emitter(op_ia32_Sub, bemit_sub);
3613 register_emitter(op_ia32_SubMem, bemit_submem);
3614 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3615 register_emitter(op_ia32_SubSP, bemit_subsp);
3616 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3617 register_emitter(op_ia32_Test, bemit_test);
3618 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3619 register_emitter(op_ia32_Xor, bemit_xor);
3620 register_emitter(op_ia32_Xor0, bemit_xor0);
3621 register_emitter(op_ia32_XorMem, bemit_xormem);
3622 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3623 register_emitter(op_ia32_fabs, bemit_fabs);
3624 register_emitter(op_ia32_fadd, bemit_fadd);
3625 register_emitter(op_ia32_fchs, bemit_fchs);
3626 register_emitter(op_ia32_fdiv, bemit_fdiv);
3627 register_emitter(op_ia32_ffreep, bemit_ffreep);
3628 register_emitter(op_ia32_fild, bemit_fild);
3629 register_emitter(op_ia32_fist, bemit_fist);
3630 register_emitter(op_ia32_fisttp, bemit_fisttp);
3631 register_emitter(op_ia32_fld, bemit_fld);
3632 register_emitter(op_ia32_fld1, bemit_fld1);
3633 register_emitter(op_ia32_fldz, bemit_fldz);
3634 register_emitter(op_ia32_fmul, bemit_fmul);
3635 register_emitter(op_ia32_fpop, bemit_fpop);
3636 register_emitter(op_ia32_fpush, bemit_fpush);
3637 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3638 register_emitter(op_ia32_fst, bemit_fst);
3639 register_emitter(op_ia32_fsub, bemit_fsub);
3640 register_emitter(op_ia32_fxch, bemit_fxch);
3642 /* ignore the following nodes */
3643 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3644 register_emitter(op_ia32_Unknown, emit_Nothing);
3645 register_emitter(op_be_Keep, emit_Nothing);
3646 register_emitter(op_be_Start, emit_Nothing);
3647 register_emitter(op_Phi, emit_Nothing);
3648 register_emitter(op_Start, emit_Nothing);
3651 static void gen_binary_block(ir_node *block)
3653 ia32_emit_block_header(block);
3655 /* emit the contents of the block */
3656 sched_foreach(block, node) {
3657 ia32_emit_node(node);
3661 void ia32_gen_binary_routine(ir_graph *irg)
3663 ir_entity *entity = get_irg_entity(irg);
3664 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3665 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3666 ir_node **blk_sched = irg_data->blk_sched;
3668 parameter_dbg_info_t *infos;
3670 isa = (ia32_isa_t*) arch_env;
3672 ia32_register_binary_emitters();
3674 infos = construct_parameter_infos(irg);
3675 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3679 /* we use links to point to target blocks */
3680 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3681 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3683 /* initialize next block links */
3684 n = ARR_LEN(blk_sched);
3685 for (i = 0; i < n; ++i) {
3686 ir_node *block = blk_sched[i];
3687 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3689 set_irn_link(block, prev);
3692 for (i = 0; i < n; ++i) {
3693 ir_node *block = blk_sched[i];
3694 gen_binary_block(block);
3697 be_gas_emit_function_epilog(entity);
3699 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3703 void ia32_init_emitter(void)
3705 lc_opt_entry_t *be_grp;
3706 lc_opt_entry_t *ia32_grp;
3708 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3709 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3711 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3715 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");