2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 if(reg == &ia32_gp_regs[REG_GP_NOREG])
90 panic("trying to emit noreg");
92 /* in case of unknown register: just return a valid register */
93 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
94 const arch_register_req_t *req;
96 /* ask for the requirements */
97 req = arch_get_register_req(arch_env, irn, pos);
99 if (arch_register_req_is(req, limited)) {
100 /* in case of limited requirements: get the first allowed register */
101 unsigned idx = rbitset_next(req->limited, 0, 1);
102 reg = arch_register_for_index(req->cls, idx);
104 /* otherwise get first register in class */
105 reg = arch_register_for_index(req->cls, 0);
113 * Returns the register at out position pos.
116 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
119 const arch_env_t *arch_env = env->arch_env;
121 const arch_register_t *reg = NULL;
123 /* 1st case: irn is not of mode_T, so it has only */
124 /* one OUT register -> good */
125 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
126 /* Proj with the corresponding projnum for the register */
128 if (get_irn_mode(irn) != mode_T) {
129 reg = arch_get_irn_register(arch_env, irn);
130 } else if (is_ia32_irn(irn)) {
131 reg = get_ia32_out_reg(irn, pos);
133 const ir_edge_t *edge;
135 foreach_out_edge(irn, edge) {
136 proj = get_edge_src_irn(edge);
137 assert(is_Proj(proj) && "non-Proj from mode_T node");
138 if (get_Proj_proj(proj) == pos) {
139 reg = arch_get_irn_register(arch_env, proj);
145 assert(reg && "no out register found");
150 * Determine the gnu assembler suffix that indicates a mode
153 char get_mode_suffix(const ir_mode *mode) {
154 if(mode_is_float(mode)) {
155 switch(get_mode_size_bits(mode)) {
165 assert(mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode));
166 switch(get_mode_size_bits(mode)) {
177 panic("Can't output mode_suffix for %+F\n", mode);
181 int produces_result(const ir_node *node) {
183 !is_ia32_CmpSet(node) &&
184 !is_ia32_CondJmp(node) &&
186 !is_ia32_SwitchJmp(node) &&
187 !is_ia32_TestJmp(node) &&
188 !is_ia32_xCmpSet(node) &&
189 !is_ia32_xCondJmp(node) &&
190 !is_ia32_CmpCMov(node) &&
191 !is_ia32_TestCMov(node) &&
192 !is_ia32_CmpSet(node) && /* this is correct, the Cmp has no result */
193 !is_ia32_TestSet(node);
197 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
198 const arch_register_t *reg) {
199 switch(get_mode_size_bits(mode)) {
201 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
203 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
205 return (char *)arch_register_get_name(reg);
210 * Add a number to a prefix. This number will not be used a second time.
213 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
214 static unsigned long id = 0;
215 snprintf(buf, buflen, "%s%lu", prefix, ++id);
219 /*************************************************************
221 * (_) | | / _| | | | |
222 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
223 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
224 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
225 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
228 *************************************************************/
230 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
231 // be_emit_env_t* so we cheat a bit...
232 #define be_emit_char(env,c) be_emit_char(env->emit,c)
233 #define be_emit_string(env,s) be_emit_string(env->emit,s)
234 #undef be_emit_cstring
235 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
236 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
237 #define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
238 #define be_emit_write_line(env) be_emit_write_line(env->emit)
239 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
240 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
242 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
244 const arch_register_t *reg = get_in_reg(env, node, pos);
245 const char *reg_name = arch_register_get_name(reg);
247 assert(pos < get_irn_arity(node));
249 be_emit_char(env, '%');
250 be_emit_string(env, reg_name);
253 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
254 const arch_register_t *reg = get_out_reg(env, node, pos);
255 const char *reg_name = arch_register_get_name(reg);
257 be_emit_char(env, '%');
258 be_emit_string(env, reg_name);
261 static void ia32_emit_register(ia32_emit_env_t *env, const arch_register_t *reg)
263 const char *reg_name = arch_register_get_name(reg);
265 be_emit_char(env, '%');
266 be_emit_string(env, reg_name);
269 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
271 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
274 be_emit_char(env, '%');
275 be_emit_string(env, attr->x87[pos]->name);
278 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
284 be_emit_char(env, '$');
286 switch(get_ia32_immop_type(node)) {
288 tv = get_ia32_Immop_tarval(node);
289 be_emit_tarval(env, tv);
291 case ia32_ImmSymConst:
292 ent = get_ia32_Immop_symconst(node);
293 set_entity_backend_marked(ent, 1);
294 id = get_entity_ld_ident(ent);
295 be_emit_ident(env, id);
302 be_emit_string(env, "BAD");
307 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
309 be_emit_char(env, get_mode_suffix(mode));
312 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
314 ir_mode *mode = get_ia32_ls_mode(node);
318 ia32_emit_mode_suffix_mode(env, mode);
321 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
323 ir_mode *mode = get_ia32_ls_mode(node);
325 ia32_emit_mode_suffix_mode(env, mode);
329 char get_xmm_mode_suffix(ir_mode *mode)
331 assert(mode_is_float(mode));
332 switch(get_mode_size_bits(mode)) {
343 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
345 ir_mode *mode = get_ia32_ls_mode(node);
346 assert(mode != NULL);
347 be_emit_char(env, 's');
348 be_emit_char(env, get_xmm_mode_suffix(mode));
351 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
353 ir_mode *mode = get_ia32_ls_mode(node);
354 assert(mode != NULL);
355 be_emit_char(env, get_xmm_mode_suffix(mode));
358 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
360 if(get_mode_size_bits(mode) == 32)
362 if(mode_is_signed(mode)) {
363 be_emit_char(env, 's');
365 be_emit_char(env, 'z');
370 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
372 switch (be_gas_flavour) {
373 case GAS_FLAVOUR_NORMAL:
374 be_emit_cstring(env, "\t.type\t");
375 be_emit_string(env, name);
376 be_emit_cstring(env, ", @function\n");
377 be_emit_write_line(env);
379 case GAS_FLAVOUR_MINGW:
380 be_emit_cstring(env, "\t.def\t");
381 be_emit_string(env, name);
382 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
383 be_emit_write_line(env);
391 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
393 switch (be_gas_flavour) {
394 case GAS_FLAVOUR_NORMAL:
395 be_emit_cstring(env, "\t.size\t");
396 be_emit_string(env, name);
397 be_emit_cstring(env, ", .-");
398 be_emit_string(env, name);
399 be_emit_char(env, '\n');
400 be_emit_write_line(env);
409 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node);
412 * Emits registers and/or address mode of a binary operation.
414 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
416 const ir_node *right_op = get_irn_n(node, 3);
418 switch(get_ia32_op_type(node)) {
420 if(is_ia32_Immediate(right_op)) {
421 emit_ia32_Immediate(env, right_op);
422 be_emit_cstring(env, ", ");
423 ia32_emit_source_register(env, node, 2);
425 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
426 ia32_emit_immediate(env, node);
427 be_emit_cstring(env, ", ");
428 ia32_emit_source_register(env, node, 2);
430 const arch_register_t *in1 = get_in_reg(env, node, 2);
431 const arch_register_t *in2 = get_in_reg(env, node, 3);
432 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
433 const arch_register_t *in;
436 in = out ? ((out == in2) ? in1 : in2) : in2;
437 out = out ? out : in1;
438 in_name = arch_register_get_name(in);
440 if (is_ia32_emit_cl(node)) {
441 assert(in == &ia32_gp_regs[REG_ECX]);
445 be_emit_char(env, '%');
446 be_emit_string(env, in_name);
447 be_emit_cstring(env, ", %");
448 be_emit_string(env, arch_register_get_name(out));
452 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
453 assert(!produces_result(node) &&
454 "Source AM with Const must not produce result");
455 ia32_emit_immediate(env, node);
456 be_emit_cstring(env, ", ");
457 ia32_emit_am(env, node);
458 } else if(is_ia32_Immediate(right_op)) {
459 assert(!produces_result(node) &&
460 "Source AM with Const must not produce result");
462 emit_ia32_Immediate(env, right_op);
463 be_emit_cstring(env, ", ");
464 ia32_emit_am(env, node);
465 } else if (produces_result(node)) {
466 ia32_emit_am(env, node);
467 be_emit_cstring(env, ", ");
468 ia32_emit_dest_register(env, node, 0);
470 ia32_emit_am(env, node);
471 be_emit_cstring(env, ", ");
472 ia32_emit_source_register(env, node, 2);
476 right_pos = get_irn_arity(node) >= 5 ? 3 : 2;
477 right_op = get_irn_n(node, right_pos);
478 if(is_ia32_Immediate(right_op)) {
479 emit_ia32_Immediate(env, right_op);
480 be_emit_cstring(env, ", ");
481 ia32_emit_am(env, node);
483 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
484 ia32_emit_immediate(env, node);
485 be_emit_cstring(env, ", ");
486 ia32_emit_am(env, node);
488 const arch_register_t *in1 = get_in_reg(env, node, right_pos);
489 ir_mode *mode = get_ia32_ls_mode(node);
492 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
494 if (is_ia32_emit_cl(node)) {
495 assert(in1 == &ia32_gp_regs[REG_ECX]);
499 be_emit_char(env, '%');
500 be_emit_string(env, in_name);
501 be_emit_cstring(env, ", ");
502 ia32_emit_am(env, node);
506 assert(0 && "unsupported op type");
511 * Emits registers and/or address mode of a binary operation.
513 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
514 switch(get_ia32_op_type(node)) {
516 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
517 // should not happen...
520 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
521 const arch_register_t *in1 = x87_attr->x87[0];
522 const arch_register_t *in2 = x87_attr->x87[1];
523 const arch_register_t *out = x87_attr->x87[2];
524 const arch_register_t *in;
526 in = out ? ((out == in2) ? in1 : in2) : in2;
527 out = out ? out : in1;
529 be_emit_char(env, '%');
530 be_emit_string(env, arch_register_get_name(in));
531 be_emit_cstring(env, ", %");
532 be_emit_string(env, arch_register_get_name(out));
537 ia32_emit_am(env, node);
540 assert(0 && "unsupported op type");
544 void ia32_emit_am_or_dest_register(ia32_emit_env_t *env, const ir_node *node,
546 if(get_ia32_op_type(node) == ia32_Normal) {
547 ia32_emit_dest_register(env, node, pos);
549 assert(get_ia32_op_type(node) == ia32_AddrModeD);
550 ia32_emit_am(env, node);
555 * Emits registers and/or address mode of a unary operation.
557 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node, int pos) {
560 switch(get_ia32_op_type(node)) {
562 op = get_irn_n(node, pos);
563 if (is_ia32_Immediate(op)) {
564 emit_ia32_Immediate(env, op);
565 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
566 ia32_emit_immediate(env, node);
568 ia32_emit_source_register(env, node, pos);
573 ia32_emit_am(env, node);
576 assert(0 && "unsupported op type");
581 * Emits address mode.
583 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
584 ir_entity *ent = get_ia32_am_sc(node);
585 int offs = get_ia32_am_offs_int(node);
586 ir_node *base = get_irn_n(node, 0);
587 int has_base = !is_ia32_NoReg_GP(base);
588 ir_node *index = get_irn_n(node, 1);
589 int has_index = !is_ia32_NoReg_GP(index);
591 /* just to be sure... */
592 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
598 set_entity_backend_marked(ent, 1);
599 id = get_entity_ld_ident(ent);
600 if (is_ia32_am_sc_sign(node))
601 be_emit_char(env, '-');
602 be_emit_ident(env, id);
604 if(get_entity_owner(ent) == get_tls_type()) {
605 if (get_entity_visibility(ent) == visibility_external_allocated) {
606 be_emit_cstring(env, "@INDNTPOFF");
608 be_emit_cstring(env, "@NTPOFF");
615 be_emit_irprintf(env->emit, "%+d", offs);
617 be_emit_irprintf(env->emit, "%d", offs);
621 if (has_base || has_index) {
622 be_emit_char(env, '(');
626 ia32_emit_source_register(env, node, 0);
629 /* emit index + scale */
632 be_emit_char(env, ',');
633 ia32_emit_source_register(env, node, 1);
635 scale = get_ia32_am_scale(node);
637 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
640 be_emit_char(env, ')');
644 /*************************************************
647 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
648 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
649 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
650 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
652 *************************************************/
655 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
658 * coding of conditions
660 struct cmp2conditon_t {
666 * positive conditions for signed compares
669 const struct cmp2conditon_t cmp2condition_s[] = {
670 { NULL, pn_Cmp_False }, /* always false */
671 { "e", pn_Cmp_Eq }, /* == */
672 { "l", pn_Cmp_Lt }, /* < */
673 { "le", pn_Cmp_Le }, /* <= */
674 { "g", pn_Cmp_Gt }, /* > */
675 { "ge", pn_Cmp_Ge }, /* >= */
676 { "ne", pn_Cmp_Lg }, /* != */
677 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
678 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
679 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
680 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
681 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
682 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
683 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
684 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
685 { NULL, pn_Cmp_True }, /* always true */
689 * positive conditions for unsigned compares
692 const struct cmp2conditon_t cmp2condition_u[] = {
693 { NULL, pn_Cmp_False }, /* always false */
694 { "e", pn_Cmp_Eq }, /* == */
695 { "b", pn_Cmp_Lt }, /* < */
696 { "be", pn_Cmp_Le }, /* <= */
697 { "a", pn_Cmp_Gt }, /* > */
698 { "ae", pn_Cmp_Ge }, /* >= */
699 { "ne", pn_Cmp_Lg }, /* != */
700 { NULL, pn_Cmp_True }, /* always true */
704 * returns the condition code
707 const char *get_cmp_suffix(pn_Cmp cmp_code)
709 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
710 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
712 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
713 return cmp2condition_u[cmp_code & 7].name;
715 return cmp2condition_s[cmp_code & 15].name;
719 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
721 be_emit_string(env, get_cmp_suffix(pnc));
726 * Returns the target block for a control flow node.
729 ir_node *get_cfop_target_block(const ir_node *irn) {
730 return get_irn_link(irn);
734 * Emits a block label for the given block.
737 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
739 be_emit_cstring(env, BLOCK_PREFIX);
740 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
744 * Emits the target label for a control flow node.
747 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
748 ir_node *block = get_cfop_target_block(node);
750 ia32_emit_block_name(env, block);
753 /** Return the next block in Block schedule */
754 static ir_node *next_blk_sched(const ir_node *block) {
755 return get_irn_link(block);
759 * Returns the Proj with projection number proj and NOT mode_M
762 ir_node *get_proj(const ir_node *node, long proj) {
763 const ir_edge_t *edge;
766 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
768 foreach_out_edge(node, edge) {
769 src = get_edge_src_irn(edge);
771 assert(is_Proj(src) && "Proj expected");
772 if (get_irn_mode(src) == mode_M)
775 if (get_Proj_proj(src) == proj)
782 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
785 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
787 const ir_node *proj_true;
788 const ir_node *proj_false;
789 const ir_node *block;
790 const ir_node *next_block;
793 /* get both Proj's */
794 proj_true = get_proj(node, pn_Cond_true);
795 assert(proj_true && "CondJmp without true Proj");
797 proj_false = get_proj(node, pn_Cond_false);
798 assert(proj_false && "CondJmp without false Proj");
800 /* for now, the code works for scheduled and non-schedules blocks */
801 block = get_nodes_block(node);
803 /* we have a block schedule */
804 next_block = next_blk_sched(block);
806 if (get_cfop_target_block(proj_true) == next_block) {
807 /* exchange both proj's so the second one can be omitted */
808 const ir_node *t = proj_true;
810 proj_true = proj_false;
813 pnc = get_negated_pnc(pnc, mode);
816 /* in case of unordered compare, check for parity */
817 if (pnc & pn_Cmp_Uo) {
818 be_emit_cstring(env, "\tjp ");
819 ia32_emit_cfop_target(env, proj_true);
820 be_emit_finish_line_gas(env, proj_true);
823 be_emit_cstring(env, "\tj");
824 ia32_emit_cmp_suffix(env, pnc);
825 be_emit_char(env, ' ');
826 ia32_emit_cfop_target(env, proj_true);
827 be_emit_finish_line_gas(env, proj_true);
829 /* the second Proj might be a fallthrough */
830 if (get_cfop_target_block(proj_false) != next_block) {
831 be_emit_cstring(env, "\tjmp ");
832 ia32_emit_cfop_target(env, proj_false);
833 be_emit_finish_line_gas(env, proj_false);
835 be_emit_cstring(env, "\t/* fallthrough to ");
836 ia32_emit_cfop_target(env, proj_false);
837 be_emit_cstring(env, " */");
838 be_emit_finish_line_gas(env, proj_false);
843 * Emits code for conditional jump.
846 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
847 be_emit_cstring(env, "\tcmp");
848 ia32_emit_mode_suffix(env, node);
849 be_emit_char(env, ' ');
850 ia32_emit_binop(env, node);
851 be_emit_finish_line_gas(env, node);
853 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
857 * Emits code for conditional jump with two variables.
860 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
861 CondJmp_emitter(env, node);
865 * Emits code for conditional test and jump.
868 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
869 be_emit_cstring(env, "\ttest");
870 ia32_emit_mode_suffix(env, node);
871 be_emit_char(env, ' ');
873 ia32_emit_binop(env, node);
874 be_emit_finish_line_gas(env, node);
876 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
880 * Emits code for conditional test and jump with two variables.
883 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
884 TestJmp_emitter(env, node);
888 * Emits code for conditional SSE floating point jump with two variables.
891 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
892 be_emit_cstring(env, "\tucomi");
893 ia32_emit_xmm_mode_suffix(env, node);
894 be_emit_char(env, ' ');
895 ia32_emit_binop(env, node);
896 be_emit_finish_line_gas(env, node);
898 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
902 * Emits code for conditional x87 floating point jump with two variables.
905 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
906 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
907 const char *reg = x87_attr->x87[1]->name;
908 long pnc = get_ia32_pncode(node);
910 switch (get_ia32_irn_opcode(node)) {
911 case iro_ia32_fcomrJmp:
912 pnc = get_inversed_pnc(pnc);
913 reg = x87_attr->x87[0]->name;
914 case iro_ia32_fcomJmp:
916 be_emit_cstring(env, "\tfucom ");
918 case iro_ia32_fcomrpJmp:
919 pnc = get_inversed_pnc(pnc);
920 reg = x87_attr->x87[0]->name;
921 case iro_ia32_fcompJmp:
922 be_emit_cstring(env, "\tfucomp ");
924 case iro_ia32_fcomrppJmp:
925 pnc = get_inversed_pnc(pnc);
926 case iro_ia32_fcomppJmp:
927 be_emit_cstring(env, "\tfucompp ");
933 be_emit_char(env, '%');
934 be_emit_string(env, reg);
936 be_emit_finish_line_gas(env, node);
938 be_emit_cstring(env, "\tfnstsw %ax");
939 be_emit_finish_line_gas(env, node);
940 be_emit_cstring(env, "\tsahf");
941 be_emit_finish_line_gas(env, node);
943 finish_CondJmp(env, node, mode_E, pnc);
947 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
949 const arch_register_t *in1, *in2, *out;
950 long pnc = get_ia32_pncode(node);
952 out = arch_get_irn_register(env->arch_env, node);
954 /* we have to emit the cmp first, because the destination register */
955 /* could be one of the compare registers */
956 if (is_ia32_xCmpCMov(node)) {
957 be_emit_cstring(env, "\tucomis");
958 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
959 be_emit_char(env, ' ');
960 ia32_emit_source_register(env, node, 1);
961 be_emit_cstring(env, ", ");
962 ia32_emit_source_register(env, node, 0);
964 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 2));
965 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 3));
967 if (is_ia32_CmpCMov(node)) {
968 be_emit_cstring(env, "\tcmp ");
970 assert(is_ia32_TestCMov(node));
971 be_emit_cstring(env, "\ttest ");
973 ia32_emit_binop(env, node);
975 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 5));
976 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 6));
978 be_emit_finish_line_gas(env, node);
981 /* best case: default in == out -> do nothing */
982 } else if(in2 == &ia32_gp_regs[REG_GP_UKNWN]) {
983 /* also nothign to do for unknown regs */
984 } else if (out == in1) {
985 const arch_register_t *t;
986 /* true in == out -> need complement compare and exchange true and
991 pnc = get_negated_pnc(pnc, get_irn_mode(node));
993 /* out is different from both ins: need copy default -> out */
994 be_emit_cstring(env, "\tmovl ");
995 ia32_emit_register(env, in2);
996 be_emit_cstring(env, ", ");
997 ia32_emit_register(env, out);
998 be_emit_finish_line_gas(env, node);
1001 be_emit_cstring(env, "\tcmov");
1002 ia32_emit_cmp_suffix(env, pnc);
1003 be_emit_cstring(env, "l ");
1004 ia32_emit_register(env, in1);
1005 be_emit_cstring(env, ", ");
1006 ia32_emit_register(env, out);
1008 be_emit_finish_line_gas(env, node);
1012 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
1014 CMov_emitter(env, node);
1018 void emit_ia32_TestCMov(ia32_emit_env_t *env, const ir_node *node)
1020 CMov_emitter(env, node);
1024 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
1026 CMov_emitter(env, node);
1030 void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
1032 long pnc = get_ia32_pncode(node);
1033 const char *reg8bit;
1034 const arch_register_t *out;
1036 out = arch_get_irn_register(env->arch_env, node);
1037 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1039 if(is_ia32_xCmpSet(node)) {
1040 be_emit_cstring(env, "\tucomis");
1041 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1042 be_emit_char(env, ' ');
1043 ia32_emit_binop(env, node);
1045 if (is_ia32_CmpSet(node)) {
1046 be_emit_cstring(env, "\tcmp ");
1048 assert(is_ia32_TestSet(node));
1049 be_emit_cstring(env, "\ttest ");
1051 ia32_emit_binop(env, node);
1053 be_emit_finish_line_gas(env, node);
1055 /* use mov to clear target because it doesn't affect the eflags */
1056 be_emit_cstring(env, "\tmovl $0, %");
1057 be_emit_string(env, arch_register_get_name(out));
1058 be_emit_finish_line_gas(env, node);
1060 be_emit_cstring(env, "\tset");
1061 ia32_emit_cmp_suffix(env, pnc);
1062 be_emit_cstring(env, " %");
1063 be_emit_string(env, reg8bit);
1064 be_emit_finish_line_gas(env, node);
1068 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1069 Set_emitter(env, node);
1073 void emit_ia32_TestSet(ia32_emit_env_t *env, const ir_node *node) {
1074 Set_emitter(env, node);
1078 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1079 Set_emitter(env, node);
1083 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1085 long pnc = get_ia32_pncode(node);
1086 long unord = pnc & pn_Cmp_Uo;
1088 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1091 case pn_Cmp_Leg: /* odered */
1094 case pn_Cmp_Uo: /* unordered */
1098 case pn_Cmp_Eq: /* == */
1102 case pn_Cmp_Lt: /* < */
1106 case pn_Cmp_Le: /* <= */
1110 case pn_Cmp_Gt: /* > */
1114 case pn_Cmp_Ge: /* >= */
1118 case pn_Cmp_Lg: /* != */
1123 assert(sse_pnc >= 0 && "unsupported compare");
1125 if (unord && sse_pnc != 3) {
1127 We need a separate compare against unordered.
1128 Quick and Dirty solution:
1129 - get some memory on stack
1133 - and result and stored result
1136 be_emit_cstring(env, "\tsubl $8, %esp");
1137 be_emit_finish_line_gas(env, node);
1139 be_emit_cstring(env, "\tcmpsd $3, ");
1140 ia32_emit_binop(env, node);
1141 be_emit_finish_line_gas(env, node);
1143 be_emit_cstring(env, "\tmovsd ");
1144 ia32_emit_dest_register(env, node, 0);
1145 be_emit_cstring(env, ", (%esp)");
1146 be_emit_finish_line_gas(env, node);
1149 be_emit_cstring(env, "\tcmpsd ");
1150 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1151 ia32_emit_binop(env, node);
1152 be_emit_finish_line_gas(env, node);
1154 if (unord && sse_pnc != 3) {
1155 be_emit_cstring(env, "\tandpd (%esp), ");
1156 ia32_emit_dest_register(env, node, 0);
1157 be_emit_finish_line_gas(env, node);
1159 be_emit_cstring(env, "\taddl $8, %esp");
1160 be_emit_finish_line_gas(env, node);
1164 /*********************************************************
1167 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1168 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1169 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1170 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1173 *********************************************************/
1175 /* jump table entry (target and corresponding number) */
1176 typedef struct _branch_t {
1181 /* jump table for switch generation */
1182 typedef struct _jmp_tbl_t {
1183 ir_node *defProj; /**< default target */
1184 long min_value; /**< smallest switch case */
1185 long max_value; /**< largest switch case */
1186 long num_branches; /**< number of jumps */
1187 char *label; /**< label of the jump table */
1188 branch_t *branches; /**< jump array */
1192 * Compare two variables of type branch_t. Used to sort all switch cases
1195 int ia32_cmp_branch_t(const void *a, const void *b) {
1196 branch_t *b1 = (branch_t *)a;
1197 branch_t *b2 = (branch_t *)b;
1199 if (b1->value <= b2->value)
1206 * Emits code for a SwitchJmp (creates a jump table if
1207 * possible otherwise a cmp-jmp cascade). Port from
1211 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1212 unsigned long interval;
1217 const ir_edge_t *edge;
1219 /* fill the table structure */
1220 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1221 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1223 tbl.num_branches = get_irn_n_edges(node);
1224 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1225 tbl.min_value = INT_MAX;
1226 tbl.max_value = INT_MIN;
1229 /* go over all proj's and collect them */
1230 foreach_out_edge(node, edge) {
1231 proj = get_edge_src_irn(edge);
1232 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1234 pnc = get_Proj_proj(proj);
1236 /* create branch entry */
1237 tbl.branches[i].target = proj;
1238 tbl.branches[i].value = pnc;
1240 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1241 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1243 /* check for default proj */
1244 if (pnc == get_ia32_pncode(node)) {
1245 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1252 /* sort the branches by their number */
1253 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1255 /* two-complement's magic make this work without overflow */
1256 interval = tbl.max_value - tbl.min_value;
1258 /* emit the table */
1259 be_emit_cstring(env, "\tcmpl $");
1260 be_emit_irprintf(env->emit, "%u, ", interval);
1261 ia32_emit_source_register(env, node, 0);
1262 be_emit_finish_line_gas(env, node);
1264 be_emit_cstring(env, "\tja ");
1265 ia32_emit_cfop_target(env, tbl.defProj);
1266 be_emit_finish_line_gas(env, node);
1268 if (tbl.num_branches > 1) {
1270 be_emit_cstring(env, "\tjmp *");
1271 be_emit_string(env, tbl.label);
1272 be_emit_cstring(env, "(,");
1273 ia32_emit_source_register(env, node, 0);
1274 be_emit_cstring(env, ",4)");
1275 be_emit_finish_line_gas(env, node);
1277 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1278 be_emit_cstring(env, "\t.align 4\n");
1279 be_emit_write_line(env);
1281 be_emit_string(env, tbl.label);
1282 be_emit_cstring(env, ":\n");
1283 be_emit_write_line(env);
1285 be_emit_cstring(env, ".long ");
1286 ia32_emit_cfop_target(env, tbl.branches[0].target);
1287 be_emit_finish_line_gas(env, NULL);
1289 last_value = tbl.branches[0].value;
1290 for (i = 1; i < tbl.num_branches; ++i) {
1291 while (++last_value < tbl.branches[i].value) {
1292 be_emit_cstring(env, ".long ");
1293 ia32_emit_cfop_target(env, tbl.defProj);
1294 be_emit_finish_line_gas(env, NULL);
1296 be_emit_cstring(env, ".long ");
1297 ia32_emit_cfop_target(env, tbl.branches[i].target);
1298 be_emit_finish_line_gas(env, NULL);
1300 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1302 /* one jump is enough */
1303 be_emit_cstring(env, "\tjmp ");
1304 ia32_emit_cfop_target(env, tbl.branches[0].target);
1305 be_emit_finish_line_gas(env, node);
1315 * Emits code for a unconditional jump.
1318 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1319 ir_node *block, *next_block;
1321 /* for now, the code works for scheduled and non-schedules blocks */
1322 block = get_nodes_block(node);
1324 /* we have a block schedule */
1325 next_block = next_blk_sched(block);
1326 if (get_cfop_target_block(node) != next_block) {
1327 be_emit_cstring(env, "\tjmp ");
1328 ia32_emit_cfop_target(env, node);
1330 be_emit_cstring(env, "\t/* fallthrough to ");
1331 ia32_emit_cfop_target(env, node);
1332 be_emit_cstring(env, " */");
1334 be_emit_finish_line_gas(env, node);
1338 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
1340 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1342 be_emit_char(env, '$');
1343 if(attr->symconst != NULL) {
1344 ident *id = get_entity_ld_ident(attr->symconst);
1346 if(attr->attr.data.am_sc_sign)
1347 be_emit_char(env, '-');
1348 be_emit_ident(env, id);
1350 if(attr->symconst == NULL || attr->offset != 0) {
1351 if(attr->symconst != NULL)
1352 be_emit_char(env, '+');
1353 be_emit_irprintf(env->emit, "%d", attr->offset);
1358 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1361 const arch_register_t *reg;
1362 const char *reg_name;
1366 const ia32_attr_t *attr;
1373 /* parse modifiers */
1376 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1377 be_emit_char(env, '%');
1380 be_emit_char(env, '%');
1400 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1401 "'%c' for asm op\n", node, c);
1407 sscanf(s, "%d%n", &num, &p);
1409 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1417 attr = get_ia32_attr_const(node);
1418 n_outs = ARR_LEN(attr->slots);
1420 reg = get_out_reg(env, node, num);
1423 int in = num - n_outs;
1424 if(in >= get_irn_arity(node)) {
1425 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1426 "op (%+F)\n", num, node);
1429 pred = get_irn_n(node, in);
1430 /* might be an immediate value */
1431 if(is_ia32_Immediate(pred)) {
1432 emit_ia32_Immediate(env, pred);
1435 reg = get_in_reg(env, node, in);
1438 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1439 "(%+F)\n", num, node);
1444 be_emit_char(env, '%');
1447 reg_name = arch_register_get_name(reg);
1450 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1453 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
1456 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1459 panic("Invalid asm op modifier");
1461 be_emit_string(env, reg_name);
1467 * Emits code for an ASM pseudo op.
1470 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1472 const void *gen_attr = get_irn_generic_attr_const(node);
1473 const ia32_asm_attr_t *attr
1474 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1475 ident *asm_text = attr->asm_text;
1476 const char *s = get_id_str(asm_text);
1478 be_emit_cstring(env, "# Begin ASM \t");
1479 be_emit_finish_line_gas(env, node);
1482 be_emit_char(env, '\t');
1486 s = emit_asm_operand(env, node, s);
1489 be_emit_char(env, *s);
1494 be_emit_char(env, '\n');
1495 be_emit_write_line(env);
1497 be_emit_cstring(env, "# End ASM\n");
1498 be_emit_write_line(env);
1501 /**********************************
1504 * | | ___ _ __ _ _| |_) |
1505 * | | / _ \| '_ \| | | | _ <
1506 * | |___| (_) | |_) | |_| | |_) |
1507 * \_____\___/| .__/ \__, |____/
1510 **********************************/
1513 * Emit movsb/w instructions to make mov count divideable by 4
1516 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1517 be_emit_cstring(env, "\tcld");
1518 be_emit_finish_line_gas(env, NULL);
1522 be_emit_cstring(env, "\tmovsb");
1523 be_emit_finish_line_gas(env, NULL);
1526 be_emit_cstring(env, "\tmovsw");
1527 be_emit_finish_line_gas(env, NULL);
1530 be_emit_cstring(env, "\tmovsb");
1531 be_emit_finish_line_gas(env, NULL);
1532 be_emit_cstring(env, "\tmovsw");
1533 be_emit_finish_line_gas(env, NULL);
1539 * Emit rep movsd instruction for memcopy.
1542 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1543 tarval *tv = get_ia32_Immop_tarval(node);
1544 int rem = get_tarval_long(tv);
1546 emit_CopyB_prolog(env, rem);
1548 be_emit_cstring(env, "\trep movsd");
1549 be_emit_finish_line_gas(env, node);
1553 * Emits unrolled memcopy.
1556 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1557 tarval *tv = get_ia32_Immop_tarval(node);
1558 int size = get_tarval_long(tv);
1560 emit_CopyB_prolog(env, size & 0x3);
1564 be_emit_cstring(env, "\tmovsd");
1565 be_emit_finish_line_gas(env, NULL);
1571 /***************************
1575 * | | / _ \| '_ \ \ / /
1576 * | |___| (_) | | | \ V /
1577 * \_____\___/|_| |_|\_/
1579 ***************************/
1582 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1585 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1586 ir_mode *ls_mode = get_ia32_ls_mode(node);
1587 int ls_bits = get_mode_size_bits(ls_mode);
1589 be_emit_cstring(env, "\tcvt");
1591 if(is_ia32_Conv_I2FP(node)) {
1593 be_emit_cstring(env, "si2ss");
1595 be_emit_cstring(env, "si2sd");
1597 } else if(is_ia32_Conv_FP2I(node)) {
1599 be_emit_cstring(env, "ss2si");
1601 be_emit_cstring(env, "sd2si");
1604 assert(is_ia32_Conv_FP2FP(node));
1606 be_emit_cstring(env, "sd2ss");
1608 be_emit_cstring(env, "ss2sd");
1611 be_emit_char(env, ' ');
1613 switch(get_ia32_op_type(node)) {
1615 ia32_emit_source_register(env, node, 2);
1616 be_emit_cstring(env, ", ");
1617 ia32_emit_dest_register(env, node, 0);
1619 case ia32_AddrModeS:
1620 ia32_emit_dest_register(env, node, 0);
1621 be_emit_cstring(env, ", ");
1622 ia32_emit_am(env, node);
1625 assert(0 && "unsupported op type for Conv");
1627 be_emit_finish_line_gas(env, node);
1631 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1632 emit_ia32_Conv_with_FP(env, node);
1636 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1637 emit_ia32_Conv_with_FP(env, node);
1641 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1642 emit_ia32_Conv_with_FP(env, node);
1646 * Emits code for an Int conversion.
1649 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1650 const char *sign_suffix;
1651 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1652 int smaller_bits = get_mode_size_bits(smaller_mode);
1654 const arch_register_t *in_reg, *out_reg;
1656 assert(!mode_is_float(smaller_mode));
1657 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1659 signed_mode = mode_is_signed(smaller_mode);
1660 if(smaller_bits == 32) {
1661 // this should not happen as it's no convert
1665 sign_suffix = signed_mode ? "s" : "z";
1668 switch(get_ia32_op_type(node)) {
1670 in_reg = get_in_reg(env, node, 2);
1671 out_reg = get_out_reg(env, node, 0);
1673 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1674 out_reg == &ia32_gp_regs[REG_EAX] &&
1678 /* argument and result are both in EAX and */
1679 /* signedness is ok: -> use the smaller cwtl opcode */
1680 be_emit_cstring(env, "\tcwtl");
1682 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1684 be_emit_cstring(env, "\tmov");
1685 be_emit_string(env, sign_suffix);
1686 ia32_emit_mode_suffix_mode(env, smaller_mode);
1687 be_emit_cstring(env, "l %");
1688 be_emit_string(env, sreg);
1689 be_emit_cstring(env, ", ");
1690 ia32_emit_dest_register(env, node, 0);
1693 case ia32_AddrModeS: {
1694 be_emit_cstring(env, "\tmov");
1695 be_emit_string(env, sign_suffix);
1696 ia32_emit_mode_suffix_mode(env, smaller_mode);
1697 be_emit_cstring(env, "l %");
1698 ia32_emit_am(env, node);
1699 be_emit_cstring(env, ", ");
1700 ia32_emit_dest_register(env, node, 0);
1704 assert(0 && "unsupported op type for Conv");
1706 be_emit_finish_line_gas(env, node);
1710 * Emits code for an 8Bit Int conversion.
1712 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1713 emit_ia32_Conv_I2I(env, node);
1717 /*******************************************
1720 * | |__ ___ _ __ ___ __| | ___ ___
1721 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1722 * | |_) | __/ | | | (_) | (_| | __/\__ \
1723 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1725 *******************************************/
1728 * Emits a backend call
1731 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1732 ir_entity *ent = be_Call_get_entity(node);
1734 be_emit_cstring(env, "\tcall ");
1736 set_entity_backend_marked(ent, 1);
1737 be_emit_string(env, get_entity_ld_name(ent));
1739 be_emit_char(env, '*');
1740 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1742 be_emit_finish_line_gas(env, node);
1746 * Emits code to increase stack pointer.
1749 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1750 int offs = be_get_IncSP_offset(node);
1756 be_emit_cstring(env, "\tsubl $");
1757 be_emit_irprintf(env->emit, "%u, ", offs);
1758 ia32_emit_source_register(env, node, 0);
1760 be_emit_cstring(env, "\taddl $");
1761 be_emit_irprintf(env->emit, "%u, ", -offs);
1762 ia32_emit_source_register(env, node, 0);
1764 be_emit_finish_line_gas(env, node);
1768 * Emits code to set stack pointer.
1771 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1772 be_emit_cstring(env, "\tmovl ");
1773 ia32_emit_source_register(env, node, 2);
1774 be_emit_cstring(env, ", ");
1775 ia32_emit_dest_register(env, node, 0);
1776 be_emit_finish_line_gas(env, node);
1780 * Emits code for Copy/CopyKeep.
1783 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1785 const arch_env_t *arch_env = env->arch_env;
1786 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1787 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1793 if(is_unknown_reg(in))
1795 /* copies of vf nodes aren't real... */
1796 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1799 mode = get_irn_mode(node);
1800 if (mode == mode_E) {
1801 be_emit_cstring(env, "\tmovsd ");
1802 ia32_emit_register(env, in);
1803 be_emit_cstring(env, ", ");
1804 ia32_emit_register(env, out);
1806 be_emit_cstring(env, "\tmovl ");
1807 ia32_emit_register(env, in);
1808 be_emit_cstring(env, ", ");
1809 ia32_emit_register(env, out);
1811 be_emit_finish_line_gas(env, node);
1815 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1816 Copy_emitter(env, node, be_get_Copy_op(node));
1820 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1821 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1825 * Emits code for exchange.
1828 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1829 const arch_register_t *in1, *in2;
1830 const arch_register_class_t *cls1, *cls2;
1832 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1833 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1835 cls1 = arch_register_get_class(in1);
1836 cls2 = arch_register_get_class(in2);
1838 assert(cls1 == cls2 && "Register class mismatch at Perm");
1840 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1841 be_emit_cstring(env, "\txchg ");
1842 ia32_emit_source_register(env, node, 1);
1843 be_emit_cstring(env, ", ");
1844 ia32_emit_source_register(env, node, 0);
1845 be_emit_finish_line_gas(env, node);
1846 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1847 be_emit_cstring(env, "\txorpd ");
1848 ia32_emit_source_register(env, node, 1);
1849 be_emit_cstring(env, ", ");
1850 ia32_emit_source_register(env, node, 0);
1851 be_emit_finish_line_gas(env, NULL);
1853 be_emit_cstring(env, "\txorpd ");
1854 ia32_emit_source_register(env, node, 0);
1855 be_emit_cstring(env, ", ");
1856 ia32_emit_source_register(env, node, 1);
1857 be_emit_finish_line_gas(env, NULL);
1859 be_emit_cstring(env, "\txorpd ");
1860 ia32_emit_source_register(env, node, 1);
1861 be_emit_cstring(env, ", ");
1862 ia32_emit_source_register(env, node, 0);
1863 be_emit_finish_line_gas(env, node);
1864 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1866 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1872 * Emits code for Constant loading.
1875 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1876 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1878 if (imm_tp == ia32_ImmSymConst) {
1879 be_emit_cstring(env, "\tmovl ");
1880 ia32_emit_immediate(env, node);
1881 be_emit_cstring(env, ", ");
1882 ia32_emit_dest_register(env, node, 0);
1884 tarval *tv = get_ia32_Immop_tarval(node);
1885 assert(get_irn_mode(node) == mode_Iu);
1886 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1887 if (tarval_is_null(tv)) {
1888 if (env->isa->opt_arch == arch_pentium_4) {
1889 /* P4 prefers sub r, r, others xor r, r */
1890 be_emit_cstring(env, "\tsubl ");
1892 be_emit_cstring(env, "\txorl ");
1894 ia32_emit_dest_register(env, node, 0);
1895 be_emit_cstring(env, ", ");
1896 ia32_emit_dest_register(env, node, 0);
1898 be_emit_cstring(env, "\tmovl ");
1899 ia32_emit_immediate(env, node);
1900 be_emit_cstring(env, ", ");
1901 ia32_emit_dest_register(env, node, 0);
1904 be_emit_finish_line_gas(env, node);
1908 * Emits code to load the TLS base
1911 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1912 be_emit_cstring(env, "\tmovl %gs:0, ");
1913 ia32_emit_dest_register(env, node, 0);
1914 be_emit_finish_line_gas(env, node);
1918 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
1920 be_emit_cstring(env, "\tret");
1921 be_emit_finish_line_gas(env, node);
1925 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
1932 /***********************************************************************************
1935 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1936 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1937 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1938 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1940 ***********************************************************************************/
1943 * Enters the emitter functions for handled nodes into the generic
1944 * pointer of an opcode.
1947 void ia32_register_emitters(void) {
1949 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1950 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1951 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1952 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1953 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1954 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1956 /* first clear the generic function pointer for all ops */
1957 clear_irp_opcodes_generic_func();
1959 /* register all emitter functions defined in spec */
1960 ia32_register_spec_emitters();
1962 /* other ia32 emitter functions */
1967 IA32_EMIT(TestCMov);
1970 IA32_EMIT(SwitchJmp);
1973 IA32_EMIT(Conv_I2FP);
1974 IA32_EMIT(Conv_FP2I);
1975 IA32_EMIT(Conv_FP2FP);
1976 IA32_EMIT(Conv_I2I);
1977 IA32_EMIT(Conv_I2I8Bit);
1982 IA32_EMIT(xCmpCMov);
1983 IA32_EMIT(xCondJmp);
1984 IA32_EMIT2(fcomJmp, x87CondJmp);
1985 IA32_EMIT2(fcompJmp, x87CondJmp);
1986 IA32_EMIT2(fcomppJmp, x87CondJmp);
1987 IA32_EMIT2(fcomrJmp, x87CondJmp);
1988 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1989 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1991 /* benode emitter */
2017 static const char *last_name = NULL;
2018 static unsigned last_line = -1;
2019 static unsigned num = -1;
2022 * Emit the debug support for node node.
2025 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
2026 dbg_info *db = get_irn_dbg_info(node);
2028 const char *fname = be_retrieve_dbg_info(db, &lineno);
2030 if (! env->cg->birg->main_env->options->stabs_debug_support)
2034 if (last_name != fname) {
2036 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2039 if (last_line != lineno) {
2042 snprintf(name, sizeof(name), ".LM%u", ++num);
2044 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2045 be_emit_string(env, name);
2046 be_emit_cstring(env, ":\n");
2047 be_emit_write_line(env);
2052 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2055 * Emits code for a node.
2058 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2059 ir_op *op = get_irn_op(node);
2061 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2063 if (op->ops.generic) {
2064 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2065 ia32_emit_dbg(env, node);
2066 (*func) (env, node);
2068 emit_Nothing(env, node);
2069 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
2075 * Emits gas alignment directives
2078 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2079 be_emit_cstring(env, "\t.p2align ");
2080 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2081 be_emit_write_line(env);
2085 * Emits gas alignment directives for Functions depended on cpu architecture.
2088 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2090 unsigned maximum_skip;
2105 maximum_skip = (1 << align) - 1;
2106 ia32_emit_alignment(env, align, maximum_skip);
2110 * Emits gas alignment directives for Labels depended on cpu architecture.
2113 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2114 unsigned align; unsigned maximum_skip;
2129 maximum_skip = (1 << align) - 1;
2130 ia32_emit_alignment(env, align, maximum_skip);
2134 * Test wether a block should be aligned.
2135 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2136 * 16 bytes. However we should only do that if the alignment nops before the
2137 * label aren't executed more often than we have jumps to the label.
2140 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2141 static const double DELTA = .0001;
2142 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2144 double prev_freq = 0; /**< execfreq of the fallthrough block */
2145 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2146 cpu_support cpu = env->isa->opt_arch;
2149 if(exec_freq == NULL)
2151 if(cpu == arch_i386 || cpu == arch_i486)
2154 block_freq = get_block_execfreq(exec_freq, block);
2155 if(block_freq < DELTA)
2158 n_cfgpreds = get_Block_n_cfgpreds(block);
2159 for(i = 0; i < n_cfgpreds; ++i) {
2160 ir_node *pred = get_Block_cfgpred_block(block, i);
2161 double pred_freq = get_block_execfreq(exec_freq, pred);
2164 prev_freq += pred_freq;
2166 jmp_freq += pred_freq;
2170 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2173 jmp_freq /= prev_freq;
2177 case arch_athlon_64:
2179 return jmp_freq > 3;
2181 return jmp_freq > 2;
2186 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2191 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2194 n_cfgpreds = get_Block_n_cfgpreds(block);
2195 if (n_cfgpreds == 0) {
2197 } else if (n_cfgpreds == 1) {
2198 ir_node *pred = get_Block_cfgpred(block, 0);
2199 ir_node *pred_block = get_nodes_block(pred);
2201 /* we don't need labels for fallthrough blocks, however switch-jmps
2202 * are no fallthroughs */
2203 if(pred_block == prev &&
2204 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2213 if (should_align_block(env, block, prev)) {
2215 ia32_emit_align_label(env, env->isa->opt_arch);
2219 ia32_emit_block_name(env, block);
2220 be_emit_char(env, ':');
2222 be_emit_pad_comment(env);
2223 be_emit_cstring(env, " /* preds:");
2225 /* emit list of pred blocks in comment */
2226 arity = get_irn_arity(block);
2227 for (i = 0; i < arity; ++i) {
2228 ir_node *predblock = get_Block_cfgpred_block(block, i);
2229 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2232 be_emit_cstring(env, "\t/* ");
2233 ia32_emit_block_name(env, block);
2234 be_emit_cstring(env, ": ");
2236 if (exec_freq != NULL) {
2237 be_emit_irprintf(env->emit, " freq: %f",
2238 get_block_execfreq(exec_freq, block));
2240 be_emit_cstring(env, " */\n");
2241 be_emit_write_line(env);
2245 * Walks over the nodes in a block connected by scheduling edges
2246 * and emits code for each node.
2249 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2251 const ir_node *node;
2253 ia32_emit_block_header(env, block, last_block);
2255 /* emit the contents of the block */
2256 ia32_emit_dbg(env, block);
2257 sched_foreach(block, node) {
2258 ia32_emit_node(env, node);
2263 * Emits code for function start.
2266 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2267 ir_entity *irg_ent = get_irg_entity(irg);
2268 const char *irg_name = get_entity_ld_name(irg_ent);
2269 cpu_support cpu = env->isa->opt_arch;
2270 const be_irg_t *birg = env->cg->birg;
2272 be_emit_write_line(env);
2273 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2274 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2275 ia32_emit_align_func(env, cpu);
2276 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2277 be_emit_cstring(env, ".global ");
2278 be_emit_string(env, irg_name);
2279 be_emit_char(env, '\n');
2280 be_emit_write_line(env);
2282 ia32_emit_function_object(env, irg_name);
2283 be_emit_string(env, irg_name);
2284 be_emit_cstring(env, ":\n");
2285 be_emit_write_line(env);
2289 * Emits code for function end
2292 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2293 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2294 const be_irg_t *birg = env->cg->birg;
2296 ia32_emit_function_size(env, irg_name);
2297 be_dbg_method_end(birg->main_env->db_handle);
2298 be_emit_char(env, '\n');
2299 be_emit_write_line(env);
2304 * Sets labels for control flow nodes (jump target)
2307 void ia32_gen_labels(ir_node *block, void *data)
2310 int n = get_Block_n_cfgpreds(block);
2313 for (n--; n >= 0; n--) {
2314 pred = get_Block_cfgpred(block, n);
2315 set_irn_link(pred, block);
2320 * Emit an exception label if the current instruction can fail.
2322 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2323 if (get_ia32_exc_label(node)) {
2324 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2325 be_emit_write_line(env);
2330 * Main driver. Emits the code for one routine.
2332 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2333 ia32_emit_env_t env;
2335 ir_node *last_block = NULL;
2338 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2339 env.emit = &env.isa->emit;
2340 env.arch_env = cg->arch_env;
2343 ia32_register_emitters();
2345 ia32_emit_func_prolog(&env, irg);
2346 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2348 n = ARR_LEN(cg->blk_sched);
2349 for (i = 0; i < n;) {
2352 block = cg->blk_sched[i];
2354 next_bl = i < n ? cg->blk_sched[i] : NULL;
2356 /* set here the link. the emitter expects to find the next block here */
2357 set_irn_link(block, next_bl);
2358 ia32_gen_block(&env, block, last_block);
2362 ia32_emit_func_epilog(&env, irg);
2365 void ia32_init_emitter(void)
2367 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");