2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
76 * Returns the register at in position pos.
78 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
81 const arch_register_t *reg = NULL;
83 assert(get_irn_arity(irn) > pos && "Invalid IN position");
85 /* The out register of the operator at position pos is the
86 in register we need. */
87 op = get_irn_n(irn, pos);
89 reg = arch_get_irn_register(arch_env, op);
91 assert(reg && "no in register found");
93 if(reg == &ia32_gp_regs[REG_GP_NOREG])
94 panic("trying to emit noreg for %+F input %d", irn, pos);
96 /* in case of unknown register: just return a valid register */
97 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
98 const arch_register_req_t *req;
100 /* ask for the requirements */
101 req = arch_get_register_req(arch_env, irn, pos);
103 if (arch_register_req_is(req, limited)) {
104 /* in case of limited requirements: get the first allowed register */
105 unsigned idx = rbitset_next(req->limited, 0, 1);
106 reg = arch_register_for_index(req->cls, idx);
108 /* otherwise get first register in class */
109 reg = arch_register_for_index(req->cls, 0);
117 * Returns the register at out position pos.
119 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
122 const arch_register_t *reg = NULL;
124 /* 1st case: irn is not of mode_T, so it has only */
125 /* one OUT register -> good */
126 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
127 /* Proj with the corresponding projnum for the register */
129 if (get_irn_mode(irn) != mode_T) {
131 reg = arch_get_irn_register(arch_env, irn);
132 } else if (is_ia32_irn(irn)) {
133 reg = get_ia32_out_reg(irn, pos);
135 const ir_edge_t *edge;
137 foreach_out_edge(irn, edge) {
138 proj = get_edge_src_irn(edge);
139 assert(is_Proj(proj) && "non-Proj from mode_T node");
140 if (get_Proj_proj(proj) == pos) {
141 reg = arch_get_irn_register(arch_env, proj);
147 assert(reg && "no out register found");
152 * Add a number to a prefix. This number will not be used a second time.
154 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
156 static unsigned long id = 0;
157 snprintf(buf, buflen, "%s%lu", prefix, ++id);
161 /*************************************************************
163 * (_) | | / _| | | | |
164 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
165 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
166 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
167 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
170 *************************************************************/
172 static void emit_8bit_register(const arch_register_t *reg)
174 const char *reg_name = arch_register_get_name(reg);
177 be_emit_char(reg_name[1]);
181 static void emit_16bit_register(const arch_register_t *reg)
183 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
186 be_emit_string(reg_name);
189 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
191 const char *reg_name;
194 int size = get_mode_size_bits(mode);
196 emit_8bit_register(reg);
198 } else if(size == 16) {
199 emit_16bit_register(reg);
202 assert(mode_is_float(mode) || size == 32);
206 reg_name = arch_register_get_name(reg);
209 be_emit_string(reg_name);
212 void ia32_emit_source_register(const ir_node *node, int pos)
214 const arch_register_t *reg = get_in_reg(node, pos);
216 emit_register(reg, NULL);
219 static void emit_ia32_Immediate(const ir_node *node);
221 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
223 const arch_register_t *reg;
224 ir_node *in = get_irn_n(node, pos);
225 if(is_ia32_Immediate(in)) {
226 emit_ia32_Immediate(in);
230 reg = get_in_reg(node, pos);
231 emit_8bit_register(reg);
234 void ia32_emit_dest_register(const ir_node *node, int pos)
236 const arch_register_t *reg = get_out_reg(node, pos);
238 emit_register(reg, NULL);
241 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
243 const arch_register_t *reg = get_out_reg(node, pos);
245 emit_register(reg, mode_Bu);
248 void ia32_emit_x87_register(const ir_node *node, int pos)
250 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
254 be_emit_string(attr->x87[pos]->name);
257 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
259 if(mode_is_float(mode)) {
260 switch(get_mode_size_bits(mode)) {
261 case 32: be_emit_char('s'); return;
262 case 64: be_emit_char('l'); return;
264 case 96: be_emit_char('t'); return;
267 assert(mode_is_int(mode) || mode_is_reference(mode));
268 switch(get_mode_size_bits(mode)) {
269 case 64: be_emit_cstring("ll"); return;
270 /* gas docu says q is the suffix but gcc, objdump and icc use
272 case 32: be_emit_char('l'); return;
273 case 16: be_emit_char('w'); return;
274 case 8: be_emit_char('b'); return;
277 panic("Can't output mode_suffix for %+F\n", mode);
280 void ia32_emit_mode_suffix(const ir_node *node)
282 ir_mode *mode = get_ia32_ls_mode(node);
286 ia32_emit_mode_suffix_mode(mode);
289 void ia32_emit_x87_mode_suffix(const ir_node *node)
291 ir_mode *mode = get_ia32_ls_mode(node);
292 assert(mode != NULL);
293 /* we only need to emit the mode on address mode */
294 if(get_ia32_op_type(node) != ia32_Normal)
295 ia32_emit_mode_suffix_mode(mode);
298 static char get_xmm_mode_suffix(ir_mode *mode)
300 assert(mode_is_float(mode));
301 switch(get_mode_size_bits(mode)) {
312 void ia32_emit_xmm_mode_suffix(const ir_node *node)
314 ir_mode *mode = get_ia32_ls_mode(node);
315 assert(mode != NULL);
317 be_emit_char(get_xmm_mode_suffix(mode));
320 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
322 ir_mode *mode = get_ia32_ls_mode(node);
323 assert(mode != NULL);
324 be_emit_char(get_xmm_mode_suffix(mode));
327 void ia32_emit_extend_suffix(const ir_mode *mode)
329 if(get_mode_size_bits(mode) == 32)
331 if(mode_is_signed(mode)) {
338 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
340 ir_node *in = get_irn_n(node, pos);
341 if(is_ia32_Immediate(in)) {
342 emit_ia32_Immediate(in);
344 const ir_mode *mode = get_ia32_ls_mode(node);
345 const arch_register_t *reg = get_in_reg(node, pos);
346 emit_register(reg, mode);
351 * Emits registers and/or address mode of a binary operation.
353 void ia32_emit_binop(const ir_node *node) {
354 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
355 const ir_mode *mode = get_ia32_ls_mode(node);
356 const arch_register_t *reg_left;
358 switch(get_ia32_op_type(node)) {
360 reg_left = get_in_reg(node, n_ia32_binary_left);
361 if(is_ia32_Immediate(right_op)) {
362 emit_ia32_Immediate(right_op);
363 be_emit_cstring(", ");
364 emit_register(reg_left, mode);
367 const arch_register_t *reg_right
368 = get_in_reg(node, n_ia32_binary_right);
369 emit_register(reg_right, mode);
370 be_emit_cstring(", ");
371 emit_register(reg_left, mode);
375 if(is_ia32_Immediate(right_op)) {
376 emit_ia32_Immediate(right_op);
377 be_emit_cstring(", ");
380 reg_left = get_in_reg(node, n_ia32_binary_left);
382 be_emit_cstring(", ");
383 emit_register(reg_left, mode);
387 panic("DestMode can't be output by %%binop anymore");
390 assert(0 && "unsupported op type");
395 * Emits registers and/or address mode of a binary operation.
397 void ia32_emit_x87_binop(const ir_node *node) {
398 switch(get_ia32_op_type(node)) {
401 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
402 const arch_register_t *in1 = x87_attr->x87[0];
403 const arch_register_t *in2 = x87_attr->x87[1];
404 const arch_register_t *out = x87_attr->x87[2];
405 const arch_register_t *in;
407 in = out ? ((out == in2) ? in1 : in2) : in2;
408 out = out ? out : in1;
411 be_emit_string(arch_register_get_name(in));
412 be_emit_cstring(", %");
413 be_emit_string(arch_register_get_name(out));
421 assert(0 && "unsupported op type");
425 void ia32_emit_am_or_dest_register(const ir_node *node,
427 if(get_ia32_op_type(node) == ia32_Normal) {
428 ia32_emit_dest_register(node, pos);
430 assert(get_ia32_op_type(node) == ia32_AddrModeD);
436 * Emits registers and/or address mode of a unary operation.
438 void ia32_emit_unop(const ir_node *node, int pos) {
441 switch(get_ia32_op_type(node)) {
443 op = get_irn_n(node, pos);
444 if (is_ia32_Immediate(op)) {
445 emit_ia32_Immediate(op);
447 ia32_emit_source_register(node, pos);
455 assert(0 && "unsupported op type");
459 static void ia32_emit_entity(ir_entity *entity)
463 set_entity_backend_marked(entity, 1);
464 id = get_entity_ld_ident(entity);
467 if(get_entity_owner(entity) == get_tls_type()) {
468 if (get_entity_visibility(entity) == visibility_external_allocated) {
469 be_emit_cstring("@INDNTPOFF");
471 be_emit_cstring("@NTPOFF");
477 * Emits address mode.
479 void ia32_emit_am(const ir_node *node) {
480 ir_entity *ent = get_ia32_am_sc(node);
481 int offs = get_ia32_am_offs_int(node);
482 ir_node *base = get_irn_n(node, 0);
483 int has_base = !is_ia32_NoReg_GP(base);
484 ir_node *index = get_irn_n(node, 1);
485 int has_index = !is_ia32_NoReg_GP(index);
487 /* just to be sure... */
488 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
492 if (is_ia32_am_sc_sign(node))
494 ia32_emit_entity(ent);
499 be_emit_irprintf("%+d", offs);
501 be_emit_irprintf("%d", offs);
505 if (has_base || has_index) {
510 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
511 emit_register(reg, NULL);
514 /* emit index + scale */
516 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
519 emit_register(reg, NULL);
521 scale = get_ia32_am_scale(node);
523 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
529 /* special case if nothing is set */
530 if(ent == NULL && offs == 0 && !has_base && !has_index) {
535 static void emit_ia32_IMul(const ir_node *node)
537 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
538 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
540 be_emit_cstring("\timul");
541 ia32_emit_mode_suffix(node);
544 ia32_emit_binop(node);
546 /* do we need the 3-address form? */
547 if(is_ia32_NoReg_GP(left) ||
548 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
549 be_emit_cstring(", ");
550 emit_register(out_reg, get_ia32_ls_mode(node));
552 be_emit_finish_line_gas(node);
555 /*************************************************
558 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
559 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
560 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
561 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
563 *************************************************/
566 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
569 * coding of conditions
571 struct cmp2conditon_t {
577 * positive conditions for signed compares
579 static const struct cmp2conditon_t cmp2condition_s[] = {
580 { NULL, pn_Cmp_False }, /* always false */
581 { "e", pn_Cmp_Eq }, /* == */
582 { "l", pn_Cmp_Lt }, /* < */
583 { "le", pn_Cmp_Le }, /* <= */
584 { "g", pn_Cmp_Gt }, /* > */
585 { "ge", pn_Cmp_Ge }, /* >= */
586 { "ne", pn_Cmp_Lg }, /* != */
587 { NULL, pn_Cmp_Leg}, /* always true */
591 * positive conditions for unsigned compares
593 static const struct cmp2conditon_t cmp2condition_u[] = {
594 { NULL, pn_Cmp_False }, /* always false */
595 { "e", pn_Cmp_Eq }, /* == */
596 { "b", pn_Cmp_Lt }, /* < */
597 { "be", pn_Cmp_Le }, /* <= */
598 { "a", pn_Cmp_Gt }, /* > */
599 { "ae", pn_Cmp_Ge }, /* >= */
600 { "ne", pn_Cmp_Lg }, /* != */
601 { NULL, pn_Cmp_Leg }, /* always true */
605 ia32_pn_Cmp_unsigned = 0x1000,
606 ia32_pn_Cmp_float = 0x2000,
610 * walks up a tree of copies/perms/spills/reloads to find the original value
611 * that is moved around
613 static ir_node *find_original_value(ir_node *node)
615 inc_irg_visited(current_ir_graph);
617 mark_irn_visited(node);
618 if(be_is_Copy(node)) {
619 node = be_get_Copy_op(node);
620 } else if(be_is_CopyKeep(node)) {
621 node = be_get_CopyKeep_op(node);
622 } else if(is_Proj(node)) {
623 ir_node *pred = get_Proj_pred(node);
624 if(be_is_Perm(pred)) {
625 node = get_irn_n(pred, get_Proj_proj(node));
626 } else if(be_is_MemPerm(pred)) {
627 node = get_irn_n(pred, get_Proj_proj(node) + 1);
628 } else if(is_ia32_Load(pred)) {
629 node = get_irn_n(pred, n_ia32_Load_mem);
633 } else if(is_ia32_Store(node)) {
634 node = get_irn_n(node, n_ia32_Store_val);
635 } else if(is_Phi(node)) {
637 arity = get_irn_arity(node);
638 for(i = 0; i < arity; ++i) {
639 ir_node *in = get_irn_n(node, i);
652 static int determine_final_pnc(const ir_node *node, int flags_pos,
655 ir_node *flags = get_irn_n(node, flags_pos);
656 const ia32_attr_t *flags_attr;
657 flags = skip_Proj(flags);
659 if(is_ia32_Sahf(flags)) {
660 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
661 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
662 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
663 cmp = find_original_value(cmp);
664 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
665 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
668 flags_attr = get_ia32_attr_const(cmp);
669 if(flags_attr->data.ins_permuted)
670 pnc = get_mirrored_pnc(pnc);
671 pnc |= ia32_pn_Cmp_float;
672 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
673 || is_ia32_Fucompi(flags)) {
674 flags_attr = get_ia32_attr_const(flags);
676 if(flags_attr->data.ins_permuted)
677 pnc = get_mirrored_pnc(pnc);
678 pnc |= ia32_pn_Cmp_float;
681 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
682 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
684 flags_attr = get_ia32_attr_const(flags);
686 if(flags_attr->data.ins_permuted)
687 pnc = get_mirrored_pnc(pnc);
688 if(flags_attr->data.cmp_unsigned)
689 pnc |= ia32_pn_Cmp_unsigned;
695 static void ia32_emit_cmp_suffix(int pnc)
699 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
701 assert(cmp2condition_u[pnc].num == pnc);
702 str = cmp2condition_u[pnc].name;
705 assert(cmp2condition_s[pnc].num == pnc);
706 str = cmp2condition_s[pnc].name;
712 void ia32_emit_cmp_suffix_node(const ir_node *node,
715 const ia32_attr_t *attr = get_ia32_attr_const(node);
717 pn_Cmp pnc = get_ia32_condcode(node);
719 pnc = determine_final_pnc(node, flags_pos, pnc);
720 if(attr->data.ins_permuted) {
721 if(pnc & ia32_pn_Cmp_float) {
722 pnc = get_negated_pnc(pnc, mode_F);
724 pnc = get_negated_pnc(pnc, mode_Iu);
728 ia32_emit_cmp_suffix(pnc);
732 * Returns the target block for a control flow node.
734 static ir_node *get_cfop_target_block(const ir_node *irn) {
735 return get_irn_link(irn);
739 * Emits a block label for the given block.
741 static void ia32_emit_block_name(const ir_node *block)
743 if (has_Block_label(block)) {
744 be_emit_string(be_gas_label_prefix());
745 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
747 be_emit_cstring(BLOCK_PREFIX);
748 be_emit_irprintf("%d", get_irn_node_nr(block));
753 * Emits the target label for a control flow node.
755 static void ia32_emit_cfop_target(const ir_node *node)
757 ir_node *block = get_cfop_target_block(node);
759 ia32_emit_block_name(block);
762 /** Return the next block in Block schedule */
763 static ir_node *next_blk_sched(const ir_node *block)
765 return get_irn_link(block);
769 * Returns the Proj with projection number proj and NOT mode_M
771 static ir_node *get_proj(const ir_node *node, long proj) {
772 const ir_edge_t *edge;
775 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
777 foreach_out_edge(node, edge) {
778 src = get_edge_src_irn(edge);
780 assert(is_Proj(src) && "Proj expected");
781 if (get_irn_mode(src) == mode_M)
784 if (get_Proj_proj(src) == proj)
791 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
793 static void emit_ia32_Jcc(const ir_node *node)
795 int need_parity_label = 0;
796 const ir_node *proj_true;
797 const ir_node *proj_false;
798 const ir_node *block;
799 const ir_node *next_block;
800 pn_Cmp pnc = get_ia32_condcode(node);
802 pnc = determine_final_pnc(node, 0, pnc);
805 proj_true = get_proj(node, pn_ia32_Jcc_true);
806 assert(proj_true && "Jcc without true Proj");
808 proj_false = get_proj(node, pn_ia32_Jcc_false);
809 assert(proj_false && "Jcc without false Proj");
811 block = get_nodes_block(node);
812 next_block = next_blk_sched(block);
814 if (get_cfop_target_block(proj_true) == next_block) {
815 /* exchange both proj's so the second one can be omitted */
816 const ir_node *t = proj_true;
818 proj_true = proj_false;
820 if(pnc & ia32_pn_Cmp_float) {
821 pnc = get_negated_pnc(pnc, mode_F);
823 pnc = get_negated_pnc(pnc, mode_Iu);
827 if (pnc & ia32_pn_Cmp_float) {
828 /* Some floating point comparisons require a test of the parity flag,
829 * which indicates that the result is unordered */
832 be_emit_cstring("\tjp ");
833 ia32_emit_cfop_target(proj_true);
834 be_emit_finish_line_gas(proj_true);
839 be_emit_cstring("\tjnp ");
840 ia32_emit_cfop_target(proj_true);
841 be_emit_finish_line_gas(proj_true);
847 /* we need a local label if the false proj is a fallthrough
848 * as the falseblock might have no label emitted then */
849 if (get_cfop_target_block(proj_false) == next_block) {
850 need_parity_label = 1;
851 be_emit_cstring("\tjp 1f");
853 be_emit_cstring("\tjp ");
854 ia32_emit_cfop_target(proj_false);
856 be_emit_finish_line_gas(proj_false);
862 be_emit_cstring("\tjp ");
863 ia32_emit_cfop_target(proj_true);
864 be_emit_finish_line_gas(proj_true);
872 be_emit_cstring("\tj");
873 ia32_emit_cmp_suffix(pnc);
875 ia32_emit_cfop_target(proj_true);
876 be_emit_finish_line_gas(proj_true);
879 if(need_parity_label) {
880 be_emit_cstring("1:");
881 be_emit_write_line();
884 /* the second Proj might be a fallthrough */
885 if (get_cfop_target_block(proj_false) != next_block) {
886 be_emit_cstring("\tjmp ");
887 ia32_emit_cfop_target(proj_false);
888 be_emit_finish_line_gas(proj_false);
890 be_emit_cstring("\t/* fallthrough to ");
891 ia32_emit_cfop_target(proj_false);
892 be_emit_cstring(" */");
893 be_emit_finish_line_gas(proj_false);
897 static void emit_ia32_CMov(const ir_node *node)
899 const ia32_attr_t *attr = get_ia32_attr_const(node);
900 int ins_permuted = attr->data.ins_permuted;
901 const arch_register_t *out = arch_get_irn_register(arch_env, node);
902 pn_Cmp pnc = get_ia32_condcode(node);
903 const arch_register_t *in_true;
904 const arch_register_t *in_false;
906 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
908 in_true = arch_get_irn_register(arch_env,
909 get_irn_n(node, n_ia32_CMov_val_true));
910 in_false = arch_get_irn_register(arch_env,
911 get_irn_n(node, n_ia32_CMov_val_false));
913 /* should be same constraint fullfilled? */
914 if(out == in_false) {
915 /* yes -> nothing to do */
916 } else if(out == in_true) {
917 const arch_register_t *tmp;
919 assert(get_ia32_op_type(node) == ia32_Normal);
921 ins_permuted = !ins_permuted;
928 be_emit_cstring("\tmovl ");
929 emit_register(in_false, NULL);
930 be_emit_cstring(", ");
931 emit_register(out, NULL);
932 be_emit_finish_line_gas(node);
936 if(pnc & ia32_pn_Cmp_float) {
937 pnc = get_negated_pnc(pnc, mode_F);
939 pnc = get_negated_pnc(pnc, mode_Iu);
943 /* TODO: handling of Nans isn't correct yet */
945 be_emit_cstring("\tcmov");
946 ia32_emit_cmp_suffix(pnc);
948 if(get_ia32_op_type(node) == ia32_AddrModeS) {
951 emit_register(in_true, get_ia32_ls_mode(node));
953 be_emit_cstring(", ");
954 emit_register(out, get_ia32_ls_mode(node));
955 be_emit_finish_line_gas(node);
958 /*********************************************************
961 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
962 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
963 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
964 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
967 *********************************************************/
969 /* jump table entry (target and corresponding number) */
970 typedef struct _branch_t {
975 /* jump table for switch generation */
976 typedef struct _jmp_tbl_t {
977 ir_node *defProj; /**< default target */
978 long min_value; /**< smallest switch case */
979 long max_value; /**< largest switch case */
980 long num_branches; /**< number of jumps */
981 char *label; /**< label of the jump table */
982 branch_t *branches; /**< jump array */
986 * Compare two variables of type branch_t. Used to sort all switch cases
988 static int ia32_cmp_branch_t(const void *a, const void *b) {
989 branch_t *b1 = (branch_t *)a;
990 branch_t *b2 = (branch_t *)b;
992 if (b1->value <= b2->value)
999 * Emits code for a SwitchJmp (creates a jump table if
1000 * possible otherwise a cmp-jmp cascade). Port from
1003 static void emit_ia32_SwitchJmp(const ir_node *node)
1005 unsigned long interval;
1011 const ir_edge_t *edge;
1013 /* fill the table structure */
1014 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1015 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1017 tbl.num_branches = get_irn_n_edges(node) - 1;
1018 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1019 tbl.min_value = INT_MAX;
1020 tbl.max_value = INT_MIN;
1022 default_pn = get_ia32_condcode(node);
1024 /* go over all proj's and collect them */
1025 foreach_out_edge(node, edge) {
1026 proj = get_edge_src_irn(edge);
1027 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1029 pnc = get_Proj_proj(proj);
1031 /* check for default proj */
1032 if (pnc == default_pn) {
1033 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1036 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1037 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1039 /* create branch entry */
1040 tbl.branches[i].target = proj;
1041 tbl.branches[i].value = pnc;
1046 assert(i == tbl.num_branches);
1048 /* sort the branches by their number */
1049 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1051 /* two-complement's magic make this work without overflow */
1052 interval = tbl.max_value - tbl.min_value;
1054 /* emit the table */
1055 be_emit_cstring("\tcmpl $");
1056 be_emit_irprintf("%u, ", interval);
1057 ia32_emit_source_register(node, 0);
1058 be_emit_finish_line_gas(node);
1060 be_emit_cstring("\tja ");
1061 ia32_emit_cfop_target(tbl.defProj);
1062 be_emit_finish_line_gas(node);
1064 if (tbl.num_branches > 1) {
1066 be_emit_cstring("\tjmp *");
1067 be_emit_string(tbl.label);
1068 be_emit_cstring("(,");
1069 ia32_emit_source_register(node, 0);
1070 be_emit_cstring(",4)");
1071 be_emit_finish_line_gas(node);
1073 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1074 be_emit_cstring("\t.align 4\n");
1075 be_emit_write_line();
1077 be_emit_string(tbl.label);
1078 be_emit_cstring(":\n");
1079 be_emit_write_line();
1081 be_emit_cstring(".long ");
1082 ia32_emit_cfop_target(tbl.branches[0].target);
1083 be_emit_finish_line_gas(NULL);
1085 last_value = tbl.branches[0].value;
1086 for (i = 1; i < tbl.num_branches; ++i) {
1087 while (++last_value < tbl.branches[i].value) {
1088 be_emit_cstring(".long ");
1089 ia32_emit_cfop_target(tbl.defProj);
1090 be_emit_finish_line_gas(NULL);
1092 be_emit_cstring(".long ");
1093 ia32_emit_cfop_target(tbl.branches[i].target);
1094 be_emit_finish_line_gas(NULL);
1096 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1098 /* one jump is enough */
1099 be_emit_cstring("\tjmp ");
1100 ia32_emit_cfop_target(tbl.branches[0].target);
1101 be_emit_finish_line_gas(node);
1111 * Emits code for a unconditional jump.
1113 static void emit_Jmp(const ir_node *node)
1115 ir_node *block, *next_block;
1117 /* for now, the code works for scheduled and non-schedules blocks */
1118 block = get_nodes_block(node);
1120 /* we have a block schedule */
1121 next_block = next_blk_sched(block);
1122 if (get_cfop_target_block(node) != next_block) {
1123 be_emit_cstring("\tjmp ");
1124 ia32_emit_cfop_target(node);
1126 be_emit_cstring("\t/* fallthrough to ");
1127 ia32_emit_cfop_target(node);
1128 be_emit_cstring(" */");
1130 be_emit_finish_line_gas(node);
1133 static void emit_ia32_Immediate(const ir_node *node)
1135 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1138 if(attr->symconst != NULL) {
1141 ia32_emit_entity(attr->symconst);
1143 if(attr->symconst == NULL || attr->offset != 0) {
1144 if(attr->symconst != NULL) {
1145 be_emit_irprintf("%+d", attr->offset);
1147 be_emit_irprintf("0x%X", attr->offset);
1153 * Emit an inline assembler operand.
1155 * @param node the ia32_ASM node
1156 * @param s points to the operand (a %c)
1158 * @return pointer to the first char in s NOT in the current operand
1160 static const char* emit_asm_operand(const ir_node *node, const char *s)
1162 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1163 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1165 const arch_register_t *reg;
1166 const ia32_asm_reg_t *asm_regs = attr->register_map;
1167 const ia32_asm_reg_t *asm_reg;
1168 const char *reg_name;
1177 /* parse modifiers */
1180 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1204 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1205 "'%c' for asm op\n", node, c);
1211 sscanf(s, "%d%n", &num, &p);
1213 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1220 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1221 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1222 "input/output (%+F)\n", node);
1225 asm_reg = & asm_regs[num];
1226 assert(asm_reg->valid);
1229 if(asm_reg->use_input == 0) {
1230 reg = get_out_reg(node, asm_reg->inout_pos);
1232 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1234 /* might be an immediate value */
1235 if(is_ia32_Immediate(pred)) {
1236 emit_ia32_Immediate(pred);
1239 reg = get_in_reg(node, asm_reg->inout_pos);
1242 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1243 "(%+F)\n", num, node);
1247 if(asm_reg->memory) {
1256 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1259 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1262 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1265 panic("Invalid asm op modifier");
1267 be_emit_string(reg_name);
1269 emit_register(reg, asm_reg->mode);
1272 if(asm_reg->memory) {
1280 * Emits code for an ASM pseudo op.
1282 static void emit_ia32_Asm(const ir_node *node)
1284 const void *gen_attr = get_irn_generic_attr_const(node);
1285 const ia32_asm_attr_t *attr
1286 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1287 ident *asm_text = attr->asm_text;
1288 const char *s = get_id_str(asm_text);
1290 be_emit_cstring("# Begin ASM \t");
1291 be_emit_finish_line_gas(node);
1298 s = emit_asm_operand(node, s);
1307 be_emit_write_line();
1309 be_emit_cstring("# End ASM\n");
1310 be_emit_write_line();
1313 /**********************************
1316 * | | ___ _ __ _ _| |_) |
1317 * | | / _ \| '_ \| | | | _ <
1318 * | |___| (_) | |_) | |_| | |_) |
1319 * \_____\___/| .__/ \__, |____/
1322 **********************************/
1325 * Emit movsb/w instructions to make mov count divideable by 4
1327 static void emit_CopyB_prolog(unsigned size) {
1328 be_emit_cstring("\tcld");
1329 be_emit_finish_line_gas(NULL);
1333 be_emit_cstring("\tmovsb");
1334 be_emit_finish_line_gas(NULL);
1337 be_emit_cstring("\tmovsw");
1338 be_emit_finish_line_gas(NULL);
1341 be_emit_cstring("\tmovsb");
1342 be_emit_finish_line_gas(NULL);
1343 be_emit_cstring("\tmovsw");
1344 be_emit_finish_line_gas(NULL);
1350 * Emit rep movsd instruction for memcopy.
1352 static void emit_ia32_CopyB(const ir_node *node)
1354 unsigned size = get_ia32_copyb_size(node);
1356 emit_CopyB_prolog(size);
1358 be_emit_cstring("\trep movsd");
1359 be_emit_finish_line_gas(node);
1363 * Emits unrolled memcopy.
1365 static void emit_ia32_CopyB_i(const ir_node *node)
1367 unsigned size = get_ia32_copyb_size(node);
1369 emit_CopyB_prolog(size & 0x3);
1373 be_emit_cstring("\tmovsd");
1374 be_emit_finish_line_gas(NULL);
1380 /***************************
1384 * | | / _ \| '_ \ \ / /
1385 * | |___| (_) | | | \ V /
1386 * \_____\___/|_| |_|\_/
1388 ***************************/
1391 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1393 static void emit_ia32_Conv_with_FP(const ir_node *node)
1395 ir_mode *ls_mode = get_ia32_ls_mode(node);
1396 int ls_bits = get_mode_size_bits(ls_mode);
1398 be_emit_cstring("\tcvt");
1400 if(is_ia32_Conv_I2FP(node)) {
1402 be_emit_cstring("si2ss");
1404 be_emit_cstring("si2sd");
1406 } else if(is_ia32_Conv_FP2I(node)) {
1408 be_emit_cstring("ss2si");
1410 be_emit_cstring("sd2si");
1413 assert(is_ia32_Conv_FP2FP(node));
1415 be_emit_cstring("sd2ss");
1417 be_emit_cstring("ss2sd");
1422 switch(get_ia32_op_type(node)) {
1424 ia32_emit_source_register(node, n_ia32_unary_op);
1426 case ia32_AddrModeS:
1430 assert(0 && "unsupported op type for Conv");
1432 be_emit_cstring(", ");
1433 ia32_emit_dest_register(node, 0);
1434 be_emit_finish_line_gas(node);
1437 static void emit_ia32_Conv_I2FP(const ir_node *node)
1439 emit_ia32_Conv_with_FP(node);
1442 static void emit_ia32_Conv_FP2I(const ir_node *node)
1444 emit_ia32_Conv_with_FP(node);
1447 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1449 emit_ia32_Conv_with_FP(node);
1453 * Emits code for an Int conversion.
1455 static void emit_ia32_Conv_I2I(const ir_node *node)
1457 const char *sign_suffix;
1458 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1459 int smaller_bits = get_mode_size_bits(smaller_mode);
1461 const arch_register_t *in_reg, *out_reg;
1463 assert(!mode_is_float(smaller_mode));
1464 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1466 signed_mode = mode_is_signed(smaller_mode);
1467 if(smaller_bits == 32) {
1468 // this should not happen as it's no convert
1472 sign_suffix = signed_mode ? "s" : "z";
1475 out_reg = get_out_reg(node, 0);
1477 switch(get_ia32_op_type(node)) {
1479 in_reg = get_in_reg(node, n_ia32_unary_op);
1481 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1482 out_reg == &ia32_gp_regs[REG_EAX] &&
1486 /* argument and result are both in EAX and */
1487 /* signedness is ok: -> use the smaller cwtl opcode */
1488 be_emit_cstring("\tcwtl");
1490 be_emit_cstring("\tmov");
1491 be_emit_string(sign_suffix);
1492 ia32_emit_mode_suffix_mode(smaller_mode);
1493 be_emit_cstring("l ");
1494 emit_register(in_reg, smaller_mode);
1495 be_emit_cstring(", ");
1496 emit_register(out_reg, NULL);
1499 case ia32_AddrModeS: {
1500 be_emit_cstring("\tmov");
1501 be_emit_string(sign_suffix);
1502 ia32_emit_mode_suffix_mode(smaller_mode);
1503 be_emit_cstring("l ");
1505 be_emit_cstring(", ");
1506 emit_register(out_reg, NULL);
1510 assert(0 && "unsupported op type for Conv");
1512 be_emit_finish_line_gas(node);
1516 /*******************************************
1519 * | |__ ___ _ __ ___ __| | ___ ___
1520 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1521 * | |_) | __/ | | | (_) | (_| | __/\__ \
1522 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1524 *******************************************/
1527 * Emits a backend call
1529 static void emit_be_Call(const ir_node *node)
1531 ir_entity *ent = be_Call_get_entity(node);
1533 be_emit_cstring("\tcall ");
1535 ia32_emit_entity(ent);
1537 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1539 emit_register(reg, NULL);
1541 be_emit_finish_line_gas(node);
1545 * Emits code to increase stack pointer.
1547 static void emit_be_IncSP(const ir_node *node)
1549 int offs = be_get_IncSP_offset(node);
1550 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1556 be_emit_cstring("\tsubl $");
1557 be_emit_irprintf("%u, ", offs);
1558 emit_register(reg, NULL);
1560 be_emit_cstring("\taddl $");
1561 be_emit_irprintf("%u, ", -offs);
1562 emit_register(reg, NULL);
1564 be_emit_finish_line_gas(node);
1568 * Emits code for Copy/CopyKeep.
1570 static void Copy_emitter(const ir_node *node, const ir_node *op)
1572 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1573 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1579 if(is_unknown_reg(in))
1581 /* copies of vf nodes aren't real... */
1582 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1585 mode = get_irn_mode(node);
1586 if (mode == mode_E) {
1587 be_emit_cstring("\tmovsd ");
1588 emit_register(in, NULL);
1589 be_emit_cstring(", ");
1590 emit_register(out, NULL);
1592 be_emit_cstring("\tmovl ");
1593 emit_register(in, NULL);
1594 be_emit_cstring(", ");
1595 emit_register(out, NULL);
1597 be_emit_finish_line_gas(node);
1600 static void emit_be_Copy(const ir_node *node)
1602 Copy_emitter(node, be_get_Copy_op(node));
1605 static void emit_be_CopyKeep(const ir_node *node)
1607 Copy_emitter(node, be_get_CopyKeep_op(node));
1611 * Emits code for exchange.
1613 static void emit_be_Perm(const ir_node *node)
1615 const arch_register_t *in0, *in1;
1616 const arch_register_class_t *cls0, *cls1;
1618 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1619 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1621 cls0 = arch_register_get_class(in0);
1622 cls1 = arch_register_get_class(in1);
1624 assert(cls0 == cls1 && "Register class mismatch at Perm");
1626 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1627 be_emit_cstring("\txchg ");
1628 emit_register(in1, NULL);
1629 be_emit_cstring(", ");
1630 emit_register(in0, NULL);
1631 be_emit_finish_line_gas(node);
1632 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1633 be_emit_cstring("\txorpd ");
1634 emit_register(in1, NULL);
1635 be_emit_cstring(", ");
1636 emit_register(in0, NULL);
1637 be_emit_finish_line_gas(NULL);
1639 be_emit_cstring("\txorpd ");
1640 emit_register(in0, NULL);
1641 be_emit_cstring(", ");
1642 emit_register(in1, NULL);
1643 be_emit_finish_line_gas(NULL);
1645 be_emit_cstring("\txorpd ");
1646 emit_register(in1, NULL);
1647 be_emit_cstring(", ");
1648 emit_register(in0, NULL);
1649 be_emit_finish_line_gas(node);
1650 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1652 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1655 panic("unexpected register class in be_Perm (%+F)\n", node);
1660 * Emits code for Constant loading.
1662 static void emit_ia32_Const(const ir_node *node)
1664 be_emit_cstring("\tmovl ");
1665 emit_ia32_Immediate(node);
1666 be_emit_cstring(", ");
1667 ia32_emit_dest_register(node, 0);
1669 be_emit_finish_line_gas(node);
1673 * Emits code to load the TLS base
1675 static void emit_ia32_LdTls(const ir_node *node)
1677 be_emit_cstring("\tmovl %gs:0, ");
1678 ia32_emit_dest_register(node, 0);
1679 be_emit_finish_line_gas(node);
1682 /* helper function for emit_ia32_Minus64Bit */
1683 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1685 be_emit_cstring("\tmovl ");
1686 emit_register(src, NULL);
1687 be_emit_cstring(", ");
1688 emit_register(dst, NULL);
1689 be_emit_finish_line_gas(node);
1692 /* helper function for emit_ia32_Minus64Bit */
1693 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1695 be_emit_cstring("\tnegl ");
1696 emit_register(reg, NULL);
1697 be_emit_finish_line_gas(node);
1700 /* helper function for emit_ia32_Minus64Bit */
1701 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1703 be_emit_cstring("\tsbbl $0, ");
1704 emit_register(reg, NULL);
1705 be_emit_finish_line_gas(node);
1708 /* helper function for emit_ia32_Minus64Bit */
1709 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1711 be_emit_cstring("\tsbbl ");
1712 emit_register(src, NULL);
1713 be_emit_cstring(", ");
1714 emit_register(dst, NULL);
1715 be_emit_finish_line_gas(node);
1718 /* helper function for emit_ia32_Minus64Bit */
1719 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1721 be_emit_cstring("\txchgl ");
1722 emit_register(src, NULL);
1723 be_emit_cstring(", ");
1724 emit_register(dst, NULL);
1725 be_emit_finish_line_gas(node);
1728 /* helper function for emit_ia32_Minus64Bit */
1729 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1731 be_emit_cstring("\txorl ");
1732 emit_register(reg, NULL);
1733 be_emit_cstring(", ");
1734 emit_register(reg, NULL);
1735 be_emit_finish_line_gas(node);
1738 static void emit_ia32_Minus64Bit(const ir_node *node)
1740 const arch_register_t *in_lo = get_in_reg(node, 0);
1741 const arch_register_t *in_hi = get_in_reg(node, 1);
1742 const arch_register_t *out_lo = get_out_reg(node, 0);
1743 const arch_register_t *out_hi = get_out_reg(node, 1);
1745 if (out_lo == in_lo) {
1746 if (out_hi != in_hi) {
1747 /* a -> a, b -> d */
1750 /* a -> a, b -> b */
1753 } else if (out_lo == in_hi) {
1754 if (out_hi == in_lo) {
1755 /* a -> b, b -> a */
1756 emit_xchg(node, in_lo, in_hi);
1759 /* a -> b, b -> d */
1760 emit_mov(node, in_hi, out_hi);
1761 emit_mov(node, in_lo, out_lo);
1765 if (out_hi == in_lo) {
1766 /* a -> c, b -> a */
1767 emit_mov(node, in_lo, out_lo);
1769 } else if (out_hi == in_hi) {
1770 /* a -> c, b -> b */
1771 emit_mov(node, in_lo, out_lo);
1774 /* a -> c, b -> d */
1775 emit_mov(node, in_lo, out_lo);
1781 emit_neg( node, out_hi);
1782 emit_neg( node, out_lo);
1783 emit_sbb0(node, out_hi);
1787 emit_zero(node, out_hi);
1788 emit_neg( node, out_lo);
1789 emit_sbb( node, in_hi, out_hi);
1792 static void emit_be_Return(const ir_node *node)
1795 be_emit_cstring("\tret");
1797 pop = be_Return_get_pop(node);
1799 be_emit_irprintf(" $%d", pop);
1801 be_emit_finish_line_gas(node);
1804 static void emit_Nothing(const ir_node *node)
1810 /***********************************************************************************
1813 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1814 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1815 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1816 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1818 ***********************************************************************************/
1821 * Enters the emitter functions for handled nodes into the generic
1822 * pointer of an opcode.
1824 static void ia32_register_emitters(void) {
1826 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1827 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1828 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1829 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1830 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1831 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1833 /* first clear the generic function pointer for all ops */
1834 clear_irp_opcodes_generic_func();
1836 /* register all emitter functions defined in spec */
1837 ia32_register_spec_emitters();
1839 /* other ia32 emitter functions */
1843 IA32_EMIT(SwitchJmp);
1846 IA32_EMIT(Conv_I2FP);
1847 IA32_EMIT(Conv_FP2I);
1848 IA32_EMIT(Conv_FP2FP);
1849 IA32_EMIT(Conv_I2I);
1850 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1853 IA32_EMIT(Minus64Bit);
1856 /* benode emitter */
1881 typedef void (*emit_func_ptr) (const ir_node *);
1884 * Emits code for a node.
1886 static void ia32_emit_node(const ir_node *node)
1888 ir_op *op = get_irn_op(node);
1890 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1892 if (op->ops.generic) {
1893 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1895 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1900 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1906 * Emits gas alignment directives
1908 static void ia32_emit_alignment(unsigned align, unsigned skip)
1910 be_emit_cstring("\t.p2align ");
1911 be_emit_irprintf("%u,,%u\n", align, skip);
1912 be_emit_write_line();
1916 * Emits gas alignment directives for Labels depended on cpu architecture.
1918 static void ia32_emit_align_label(void)
1920 unsigned align = ia32_cg_config.label_alignment;
1921 unsigned maximum_skip = (1 << align) - 1;
1922 ia32_emit_alignment(align, maximum_skip);
1926 * Test wether a block should be aligned.
1927 * For cpus in the P4/Athlon class it is useful to align jump labels to
1928 * 16 bytes. However we should only do that if the alignment nops before the
1929 * label aren't executed more often than we have jumps to the label.
1931 static int should_align_block(ir_node *block, ir_node *prev)
1933 static const double DELTA = .0001;
1934 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1936 double prev_freq = 0; /**< execfreq of the fallthrough block */
1937 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1940 if(exec_freq == NULL)
1942 if(ia32_cg_config.label_alignment_factor <= 0)
1945 block_freq = get_block_execfreq(exec_freq, block);
1946 if(block_freq < DELTA)
1949 n_cfgpreds = get_Block_n_cfgpreds(block);
1950 for(i = 0; i < n_cfgpreds; ++i) {
1951 ir_node *pred = get_Block_cfgpred_block(block, i);
1952 double pred_freq = get_block_execfreq(exec_freq, pred);
1955 prev_freq += pred_freq;
1957 jmp_freq += pred_freq;
1961 if(prev_freq < DELTA && !(jmp_freq < DELTA))
1964 jmp_freq /= prev_freq;
1966 return jmp_freq > ia32_cg_config.label_alignment_factor;
1969 static int can_omit_block_label(ir_node *cfgpred)
1973 if(!is_Proj(cfgpred))
1975 pred = get_Proj_pred(cfgpred);
1976 if(is_ia32_SwitchJmp(pred))
1982 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
1984 ir_graph *irg = current_ir_graph;
1988 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1990 if(block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
1993 n_cfgpreds = get_Block_n_cfgpreds(block);
1995 if(n_cfgpreds == 0) {
1997 } else if(n_cfgpreds == 1) {
1998 ir_node *cfgpred = get_Block_cfgpred(block, 0);
1999 if(get_nodes_block(cfgpred) == prev && can_omit_block_label(cfgpred)) {
2004 if (should_align_block(block, prev)) {
2005 ia32_emit_align_label();
2009 ia32_emit_block_name(block);
2012 be_emit_pad_comment();
2013 be_emit_cstring(" /* ");
2015 be_emit_cstring("\t/* ");
2016 ia32_emit_block_name(block);
2017 be_emit_cstring(": ");
2020 be_emit_cstring("preds:");
2022 /* emit list of pred blocks in comment */
2023 arity = get_irn_arity(block);
2024 for (i = 0; i < arity; ++i) {
2025 ir_node *predblock = get_Block_cfgpred_block(block, i);
2026 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2028 if (exec_freq != NULL) {
2029 be_emit_irprintf(" freq: %f",
2030 get_block_execfreq(exec_freq, block));
2032 be_emit_cstring(" */\n");
2033 be_emit_write_line();
2037 * Walks over the nodes in a block connected by scheduling edges
2038 * and emits code for each node.
2040 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2042 const ir_node *node;
2044 ia32_emit_block_header(block, last_block);
2046 /* emit the contents of the block */
2047 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2048 sched_foreach(block, node) {
2049 ia32_emit_node(node);
2055 * Sets labels for control flow nodes (jump target)
2057 static void ia32_gen_labels(ir_node *block, void *data)
2060 int n = get_Block_n_cfgpreds(block);
2063 for (n--; n >= 0; n--) {
2064 pred = get_Block_cfgpred(block, n);
2065 set_irn_link(pred, block);
2070 * Emit an exception label if the current instruction can fail.
2072 void ia32_emit_exc_label(const ir_node *node)
2074 if (get_ia32_exc_label(node)) {
2075 be_emit_irprintf(".EXL%u\n", 0);
2076 be_emit_write_line();
2081 * Main driver. Emits the code for one routine.
2083 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2086 ir_node *last_block = NULL;
2087 ir_entity *entity = get_irg_entity(irg);
2091 isa = (const ia32_isa_t*) cg->arch_env->isa;
2092 arch_env = cg->arch_env;
2094 ia32_register_emitters();
2096 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2097 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2099 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2101 n = ARR_LEN(cg->blk_sched);
2102 for (i = 0; i < n;) {
2105 block = cg->blk_sched[i];
2107 next_bl = i < n ? cg->blk_sched[i] : NULL;
2109 /* set here the link. the emitter expects to find the next block here */
2110 set_irn_link(block, next_bl);
2111 ia32_gen_block(block, last_block);
2115 be_gas_emit_function_epilog(entity);
2116 be_dbg_method_end();
2118 be_emit_write_line();
2121 void ia32_init_emitter(void)
2123 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");