2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 const char *reg_name = arch_register_get_name(reg);
157 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
158 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
161 be_emit_char(reg_name[1]); /* get the basic name of the register */
166 * Emit the name of the 8bit high register
168 static void emit_8bit_register_high(const arch_register_t *reg)
170 const char *reg_name = arch_register_get_name(reg);
171 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
172 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
175 be_emit_char(reg_name[1]); /* get the basic name of the register */
179 static void emit_16bit_register(const arch_register_t *reg)
181 const char *reg_name = arch_register_get_name(reg);
184 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
188 * emit a register, possible shortened by a mode
190 * @param reg the register
191 * @param mode the mode of the register or NULL for full register
193 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
195 const char *reg_name;
198 int size = get_mode_size_bits(mode);
200 case 8: emit_8bit_register(reg); return;
201 case 16: emit_16bit_register(reg); return;
203 assert(mode_is_float(mode) || size == 32);
206 reg_name = arch_register_get_name(reg);
209 be_emit_string(reg_name);
212 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
214 be_gas_emit_entity(entity);
216 if (get_entity_owner(entity) == get_tls_type()) {
217 if (!entity_has_definition(entity)) {
218 be_emit_cstring("@INDNTPOFF");
220 be_emit_cstring("@NTPOFF");
224 if (do_pic && !no_pic_adjust) {
226 be_emit_string(pic_base_label);
230 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
232 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
234 if (attr->symconst != NULL) {
237 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
239 if (attr->symconst == NULL || attr->offset != 0) {
240 if (attr->symconst != NULL) {
241 be_emit_irprintf("%+d", attr->offset);
243 be_emit_irprintf("0x%X", attr->offset);
248 static void emit_ia32_Immediate(const ir_node *node)
251 emit_ia32_Immediate_no_prefix(node);
254 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
256 assert(mode_is_int(mode) || mode_is_reference(mode));
257 switch (get_mode_size_bits(mode)) {
258 case 8: be_emit_char('b'); return;
259 case 16: be_emit_char('w'); return;
260 case 32: be_emit_char('l'); return;
261 /* gas docu says q is the suffix but gcc, objdump and icc use ll
263 case 64: be_emit_cstring("ll"); return;
265 panic("Can't output mode_suffix for %+F", mode);
268 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
272 /* we only need to emit the mode on address mode */
273 if (get_ia32_op_type(node) == ia32_Normal)
276 mode = get_ia32_ls_mode(node);
277 assert(mode != NULL);
279 if (mode_is_float(mode)) {
280 switch (get_mode_size_bits(mode)) {
281 case 32: be_emit_char('s'); return;
282 case 64: be_emit_char('l'); return;
283 /* long doubles have different sizes due to alignment on different
287 case 128: be_emit_char('t'); return;
290 assert(mode_is_int(mode) || mode_is_reference(mode));
291 switch (get_mode_size_bits(mode)) {
292 case 16: be_emit_char('s'); return;
293 case 32: be_emit_char('l'); return;
294 /* gas docu says q is the suffix but gcc, objdump and icc use ll
296 case 64: be_emit_cstring("ll"); return;
299 panic("Can't output mode_suffix for %+F", mode);
302 static char get_xmm_mode_suffix(ir_mode *mode)
304 assert(mode_is_float(mode));
305 switch (get_mode_size_bits(mode)) {
308 default: panic("Invalid XMM mode");
312 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
314 ir_mode *mode = get_ia32_ls_mode(node);
315 assert(mode != NULL);
316 be_emit_char(get_xmm_mode_suffix(mode));
320 * Returns the target block for a control flow node.
322 static ir_node *get_cfop_target_block(const ir_node *irn)
324 assert(get_irn_mode(irn) == mode_X);
325 return (ir_node*)get_irn_link(irn);
329 * Emits the target label for a control flow node.
331 static void ia32_emit_cfop_target(const ir_node *node)
333 ir_node *block = get_cfop_target_block(node);
334 be_gas_emit_block_name(block);
338 * Emit the suffix for a compare instruction.
340 static void ia32_emit_condition_code(ia32_condition_code_t cc)
343 case ia32_cc_overflow: be_emit_cstring("o"); return;
344 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
345 case ia32_cc_float_below:
346 case ia32_cc_float_unordered_below:
347 case ia32_cc_below: be_emit_cstring("b"); return;
348 case ia32_cc_float_above_equal:
349 case ia32_cc_float_unordered_above_equal:
350 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
351 case ia32_cc_float_equal:
352 case ia32_cc_equal: be_emit_cstring("e"); return;
353 case ia32_cc_float_not_equal:
354 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
355 case ia32_cc_float_below_equal:
356 case ia32_cc_float_unordered_below_equal:
357 case ia32_cc_below_equal: be_emit_cstring("be"); return;
358 case ia32_cc_float_above:
359 case ia32_cc_float_unordered_above:
360 case ia32_cc_above: be_emit_cstring("a"); return;
361 case ia32_cc_sign: be_emit_cstring("s"); return;
362 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
363 case ia32_cc_parity: be_emit_cstring("p"); return;
364 case ia32_cc_not_parity: be_emit_cstring("np"); return;
365 case ia32_cc_less: be_emit_cstring("l"); return;
366 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
367 case ia32_cc_less_equal: be_emit_cstring("le"); return;
368 case ia32_cc_greater: be_emit_cstring("g"); return;
369 case ia32_cc_float_parity_cases:
370 case ia32_cc_additional_float_cases:
373 panic("Invalid ia32 condition code");
376 typedef enum ia32_emit_mod_t {
378 EMIT_RESPECT_LS = 1U << 0,
379 EMIT_ALTERNATE_AM = 1U << 1,
381 EMIT_HIGH_REG = 1U << 3,
382 EMIT_LOW_REG = 1U << 4,
383 EMIT_16BIT_REG = 1U << 5
385 ENUM_BITSET(ia32_emit_mod_t)
388 * Emits address mode.
390 static void ia32_emit_am(ir_node const *const node)
392 ir_entity *ent = get_ia32_am_sc(node);
393 int offs = get_ia32_am_offs_int(node);
394 ir_node *base = get_irn_n(node, n_ia32_base);
395 int has_base = !is_ia32_NoReg_GP(base);
396 ir_node *idx = get_irn_n(node, n_ia32_index);
397 int has_index = !is_ia32_NoReg_GP(idx);
399 /* just to be sure... */
400 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
402 if (get_ia32_am_tls_segment(node))
403 be_emit_cstring("%gs:");
407 const ia32_attr_t *attr = get_ia32_attr_const(node);
408 if (is_ia32_am_sc_sign(node))
410 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
413 /* also handle special case if nothing is set */
414 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
416 be_emit_irprintf("%+d", offs);
418 be_emit_irprintf("%d", offs);
422 if (has_base || has_index) {
427 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
428 emit_register(reg, NULL);
431 /* emit index + scale */
433 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
436 emit_register(reg, NULL);
438 scale = get_ia32_am_scale(node);
440 be_emit_irprintf(",%d", 1 << scale);
447 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
449 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
456 const char *start = fmt;
457 ia32_emit_mod_t mod = EMIT_NONE;
459 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
462 be_emit_string_len(start, fmt - start);
467 be_emit_write_line();
481 case '*': mod |= EMIT_ALTERNATE_AM; break;
482 case '#': mod |= EMIT_RESPECT_LS; break;
483 case 'l': mod |= EMIT_LONG; break;
484 case '>': mod |= EMIT_HIGH_REG; break;
485 case '<': mod |= EMIT_LOW_REG; break;
486 case '^': mod |= EMIT_16BIT_REG; break;
495 arch_register_t const *reg;
505 if (get_ia32_op_type(node) == ia32_AddrModeS) {
508 assert(get_ia32_op_type(node) == ia32_Normal);
509 ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
510 arch_register_t const *const out = x87_attr->x87[2];
511 arch_register_t const * in = x87_attr->x87[1];
513 in = x87_attr->x87[0];
514 be_emit_irprintf("%%%s, %%%s", arch_register_get_name(in), arch_register_get_name(out));
520 if (mod & EMIT_ALTERNATE_AM)
526 reg = va_arg(ap, const arch_register_t*);
527 if (get_ia32_op_type(node) == ia32_AddrModeS) {
534 if (get_ia32_op_type(node) == ia32_AddrModeS) {
538 assert(get_ia32_op_type(node) == ia32_Normal);
542 default: goto unknown;
548 imm = get_irn_n(node, n_ia32_binary_right);
549 if (is_ia32_Immediate(imm)) {
550 emit_ia32_Immediate(imm);
551 be_emit_cstring(", ");
552 if (get_ia32_op_type(node) == ia32_AddrModeS) {
555 assert(get_ia32_op_type(node) == ia32_Normal);
556 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
557 emit_register(reg, get_ia32_ls_mode(node));
560 if (get_ia32_op_type(node) == ia32_AddrModeS) {
563 assert(get_ia32_op_type(node) == ia32_Normal);
564 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
565 emit_register(reg, get_ia32_ls_mode(node));
567 be_emit_cstring(", ");
568 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
569 emit_register(reg, get_ia32_ls_mode(node));
574 if (*fmt < '0' || '9' < *fmt)
576 reg = arch_get_irn_register_out(node, *fmt++ - '0');
582 ia32_emit_x87_mode_suffix(node);
583 } else if (*fmt == 'X') {
585 ia32_emit_xmm_mode_suffix(node);
586 } else if ('0' <= *fmt && *fmt <= '2') {
587 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
589 be_emit_string(attr->x87[*fmt++ - '0']->name);
598 if (!(mod & EMIT_ALTERNATE_AM))
600 emit_ia32_Immediate_no_prefix(imm);
604 ia32_emit_cfop_target(node);
608 ir_mode *mode = get_ia32_ls_mode(node);
611 if (mod & EMIT_RESPECT_LS) {
612 if (get_mode_size_bits(mode) == 32)
614 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
616 ia32_emit_mode_suffix_mode(mode);
621 ia32_condition_code_t cc;
624 cc = (ia32_condition_code_t)va_arg(ap, int);
625 } else if ('0' <= *fmt && *fmt <= '9') {
626 cc = get_ia32_condcode(node);
627 cc = determine_final_cc(node, *fmt - '0', cc);
632 ia32_emit_condition_code(cc);
637 reg = va_arg(ap, const arch_register_t*);
639 if (mod & EMIT_ALTERNATE_AM)
641 if (mod & EMIT_HIGH_REG) {
642 emit_8bit_register_high(reg);
643 } else if (mod & EMIT_LOW_REG) {
644 emit_8bit_register(reg);
645 } else if (mod & EMIT_16BIT_REG) {
646 emit_16bit_register(reg);
648 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
656 if (*fmt < '0' || '9' < *fmt)
660 imm = get_irn_n(node, pos);
661 if (is_ia32_Immediate(imm)) {
664 reg = arch_get_irn_register_in(node, pos);
670 const char *str = va_arg(ap, const char*);
676 if (mod & EMIT_LONG) {
677 unsigned long num = va_arg(ap, unsigned long);
678 be_emit_irprintf("%lu", num);
680 unsigned num = va_arg(ap, unsigned);
681 be_emit_irprintf("%u", num);
686 if (mod & EMIT_LONG) {
687 long num = va_arg(ap, long);
688 be_emit_irprintf("%ld", num);
690 int num = va_arg(ap, int);
691 be_emit_irprintf("%d", num);
697 panic("unknown format conversion");
701 be_emit_finish_line_gas(node);
705 static void emit_ia32_IMul(const ir_node *node)
707 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
708 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
710 /* do we need the 3-address form? */
711 if (is_ia32_NoReg_GP(left) ||
712 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
713 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
715 ia32_emitf(node, "imul%M %#AS4, %#S3");
720 * walks up a tree of copies/perms/spills/reloads to find the original value
721 * that is moved around
723 static ir_node *find_original_value(ir_node *node)
725 if (irn_visited(node))
728 mark_irn_visited(node);
729 if (be_is_Copy(node)) {
730 return find_original_value(be_get_Copy_op(node));
731 } else if (be_is_CopyKeep(node)) {
732 return find_original_value(be_get_CopyKeep_op(node));
733 } else if (is_Proj(node)) {
734 ir_node *pred = get_Proj_pred(node);
735 if (be_is_Perm(pred)) {
736 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
737 } else if (be_is_MemPerm(pred)) {
738 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
739 } else if (is_ia32_Load(pred)) {
740 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
741 } else if (is_ia32_Store(pred)) {
742 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
746 } else if (is_Phi(node)) {
748 arity = get_irn_arity(node);
749 for (i = 0; i < arity; ++i) {
750 ir_node *in = get_irn_n(node, i);
751 ir_node *res = find_original_value(in);
762 static ia32_condition_code_t determine_final_cc(const ir_node *node,
763 int flags_pos, ia32_condition_code_t cc)
765 ir_node *flags = get_irn_n(node, flags_pos);
766 const ia32_attr_t *flags_attr;
767 flags = skip_Proj(flags);
769 if (is_ia32_Sahf(flags)) {
770 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
771 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
772 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
773 inc_irg_visited(current_ir_graph);
774 cmp = find_original_value(cmp);
776 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
777 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
780 flags_attr = get_ia32_attr_const(cmp);
782 flags_attr = get_ia32_attr_const(flags);
785 if (flags_attr->data.ins_permuted)
786 cc = ia32_invert_condition_code(cc);
791 * Emits an exception label for a given node.
793 static void ia32_emit_exc_label(const ir_node *node)
795 be_emit_string(be_gas_insn_label_prefix());
796 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
800 * Returns the Proj with projection number proj and NOT mode_M
802 static ir_node *get_proj(const ir_node *node, long proj)
806 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
808 foreach_out_edge(node, edge) {
809 src = get_edge_src_irn(edge);
811 assert(is_Proj(src) && "Proj expected");
812 if (get_irn_mode(src) == mode_M)
815 if (get_Proj_proj(src) == proj)
821 static int can_be_fallthrough(const ir_node *node)
823 ir_node *target_block = get_cfop_target_block(node);
824 ir_node *block = get_nodes_block(node);
825 return get_prev_block_sched(target_block) == block;
829 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
831 static void emit_ia32_Jcc(const ir_node *node)
833 int need_parity_label = 0;
834 ia32_condition_code_t cc = get_ia32_condcode(node);
835 const ir_node *proj_true;
836 const ir_node *proj_false;
838 cc = determine_final_cc(node, 0, cc);
841 proj_true = get_proj(node, pn_ia32_Jcc_true);
842 assert(proj_true && "Jcc without true Proj");
844 proj_false = get_proj(node, pn_ia32_Jcc_false);
845 assert(proj_false && "Jcc without false Proj");
847 if (can_be_fallthrough(proj_true)) {
848 /* exchange both proj's so the second one can be omitted */
849 const ir_node *t = proj_true;
851 proj_true = proj_false;
853 cc = ia32_negate_condition_code(cc);
856 if (cc & ia32_cc_float_parity_cases) {
857 /* Some floating point comparisons require a test of the parity flag,
858 * which indicates that the result is unordered */
859 if (cc & ia32_cc_negated) {
860 ia32_emitf(proj_true, "jp %L");
862 /* we need a local label if the false proj is a fallthrough
863 * as the falseblock might have no label emitted then */
864 if (can_be_fallthrough(proj_false)) {
865 need_parity_label = 1;
866 ia32_emitf(proj_false, "jp 1f");
868 ia32_emitf(proj_false, "jp %L");
872 ia32_emitf(proj_true, "j%PX %L", (int)cc);
873 if (need_parity_label) {
874 be_emit_cstring("1:\n");
875 be_emit_write_line();
878 /* the second Proj might be a fallthrough */
879 if (can_be_fallthrough(proj_false)) {
880 if (be_options.verbose_asm)
881 ia32_emitf(proj_false, "/* fallthrough to %L */");
883 ia32_emitf(proj_false, "jmp %L");
888 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
891 static void emit_ia32_Setcc(const ir_node *node)
893 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
895 ia32_condition_code_t cc = get_ia32_condcode(node);
896 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
897 if (cc & ia32_cc_float_parity_cases) {
898 if (cc & ia32_cc_negated) {
899 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
900 ia32_emitf(node, "setp %>R", dreg);
901 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
903 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
904 ia32_emitf(node, "setnp %>R", dreg);
905 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
908 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
912 static void emit_ia32_CMovcc(const ir_node *node)
914 const ia32_attr_t *attr = get_ia32_attr_const(node);
915 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
916 ia32_condition_code_t cc = get_ia32_condcode(node);
917 const arch_register_t *in_true;
918 const arch_register_t *in_false;
920 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
921 /* although you can't set ins_permuted in the constructor it might still
922 * be set by memory operand folding
923 * Permuting inputs of a cmov means the condition is negated!
925 if (attr->data.ins_permuted)
926 cc = ia32_negate_condition_code(cc);
928 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
929 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
931 /* should be same constraint fullfilled? */
932 if (out == in_false) {
933 /* yes -> nothing to do */
934 } else if (out == in_true) {
935 const arch_register_t *tmp;
937 assert(get_ia32_op_type(node) == ia32_Normal);
939 cc = ia32_negate_condition_code(cc);
946 ia32_emitf(node, "movl %R, %R", in_false, out);
949 if (cc & ia32_cc_float_parity_cases) {
950 panic("CMov with floatingpoint compare/parity not supported yet");
953 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
957 * Emits code for a SwitchJmp
959 static void emit_ia32_SwitchJmp(const ir_node *node)
961 ir_entity *jump_table = get_ia32_am_sc(node);
962 const ir_switch_table *table = get_ia32_switch_table(node);
964 ia32_emitf(node, "jmp %*AM");
965 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
969 * Emits code for a unconditional jump.
971 static void emit_ia32_Jmp(const ir_node *node)
973 /* we have a block schedule */
974 if (can_be_fallthrough(node)) {
975 if (be_options.verbose_asm)
976 ia32_emitf(node, "/* fallthrough to %L */");
978 ia32_emitf(node, "jmp %L");
983 * Emit an inline assembler operand.
985 * @param node the ia32_ASM node
986 * @param s points to the operand (a %c)
988 * @return pointer to the first char in s NOT in the current operand
990 static const char* emit_asm_operand(const ir_node *node, const char *s)
992 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
993 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
995 const arch_register_t *reg;
996 const ia32_asm_reg_t *asm_regs = attr->register_map;
997 const ia32_asm_reg_t *asm_reg;
1006 /* parse modifiers */
1009 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1034 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1041 if (sscanf(s, "%d%n", &num, &p) != 1) {
1042 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1049 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1051 "Error: Custom assembler references invalid input/output (%+F)\n",
1055 asm_reg = & asm_regs[num];
1056 assert(asm_reg->valid);
1059 if (asm_reg->use_input == 0) {
1060 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1062 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1064 /* might be an immediate value */
1065 if (is_ia32_Immediate(pred)) {
1066 emit_ia32_Immediate(pred);
1069 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1073 "Warning: no register assigned for %d asm op (%+F)\n",
1078 if (asm_reg->memory) {
1083 if (modifier != 0) {
1086 emit_8bit_register(reg);
1089 emit_8bit_register_high(reg);
1092 emit_16bit_register(reg);
1095 panic("Invalid asm op modifier");
1098 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1101 if (asm_reg->memory) {
1109 * Emits code for an ASM pseudo op.
1111 static void emit_ia32_Asm(const ir_node *node)
1113 const void *gen_attr = get_irn_generic_attr_const(node);
1114 const ia32_asm_attr_t *attr
1115 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1116 ident *asm_text = attr->asm_text;
1117 const char *s = get_id_str(asm_text);
1119 be_emit_cstring("#APP\n");
1120 be_emit_write_line();
1127 s = emit_asm_operand(node, s);
1133 be_emit_cstring("\n#NO_APP\n");
1134 be_emit_write_line();
1139 * Emit movsb/w instructions to make mov count divideable by 4
1141 static void emit_CopyB_prolog(unsigned size)
1144 ia32_emitf(NULL, "movsb");
1146 ia32_emitf(NULL, "movsw");
1150 * Emit rep movsd instruction for memcopy.
1152 static void emit_ia32_CopyB(const ir_node *node)
1154 unsigned size = get_ia32_copyb_size(node);
1156 emit_CopyB_prolog(size);
1157 ia32_emitf(node, "rep movsd");
1161 * Emits unrolled memcopy.
1163 static void emit_ia32_CopyB_i(const ir_node *node)
1165 unsigned size = get_ia32_copyb_size(node);
1167 emit_CopyB_prolog(size);
1171 ia32_emitf(NULL, "movsd");
1177 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1179 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1182 ir_mode *ls_mode = get_ia32_ls_mode(node);
1183 int ls_bits = get_mode_size_bits(ls_mode);
1184 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1186 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1189 static void emit_ia32_Conv_I2FP(const ir_node *node)
1191 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1194 static void emit_ia32_Conv_FP2I(const ir_node *node)
1196 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1199 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1201 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1205 * Emits code to increase stack pointer.
1207 static void emit_be_IncSP(const ir_node *node)
1209 int offs = be_get_IncSP_offset(node);
1215 ia32_emitf(node, "subl $%u, %D0", offs);
1217 ia32_emitf(node, "addl $%u, %D0", -offs);
1222 * Emits code for Copy/CopyKeep.
1224 static void Copy_emitter(const ir_node *node, const ir_node *op)
1226 const arch_register_t *in = arch_get_irn_register(op);
1227 const arch_register_t *out = arch_get_irn_register(node);
1232 /* copies of vf nodes aren't real... */
1233 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1236 ia32_emitf(node, "movl %R, %R", in, out);
1239 static void emit_be_Copy(const ir_node *node)
1241 Copy_emitter(node, be_get_Copy_op(node));
1244 static void emit_be_CopyKeep(const ir_node *node)
1246 Copy_emitter(node, be_get_CopyKeep_op(node));
1250 * Emits code for exchange.
1252 static void emit_be_Perm(const ir_node *node)
1254 const arch_register_t *in0, *in1;
1255 const arch_register_class_t *cls0, *cls1;
1257 in0 = arch_get_irn_register(get_irn_n(node, 0));
1258 in1 = arch_get_irn_register(get_irn_n(node, 1));
1260 cls0 = arch_register_get_class(in0);
1261 cls1 = arch_register_get_class(in1);
1263 assert(cls0 == cls1 && "Register class mismatch at Perm");
1265 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1266 ia32_emitf(node, "xchg %R, %R", in1, in0);
1267 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1268 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1269 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1270 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1271 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1273 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1276 panic("unexpected register class in be_Perm (%+F)", node);
1280 /* helper function for emit_ia32_Minus64Bit */
1281 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1283 ia32_emitf(node, "movl %R, %R", src, dst);
1286 /* helper function for emit_ia32_Minus64Bit */
1287 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1289 ia32_emitf(node, "negl %R", reg);
1292 /* helper function for emit_ia32_Minus64Bit */
1293 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1295 ia32_emitf(node, "sbbl $0, %R", reg);
1298 /* helper function for emit_ia32_Minus64Bit */
1299 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1301 ia32_emitf(node, "sbbl %R, %R", src, dst);
1304 /* helper function for emit_ia32_Minus64Bit */
1305 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1307 ia32_emitf(node, "xchgl %R, %R", src, dst);
1310 /* helper function for emit_ia32_Minus64Bit */
1311 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1313 ia32_emitf(node, "xorl %R, %R", reg, reg);
1316 static void emit_ia32_Minus64Bit(const ir_node *node)
1318 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1319 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1320 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1321 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1323 if (out_lo == in_lo) {
1324 if (out_hi != in_hi) {
1325 /* a -> a, b -> d */
1328 /* a -> a, b -> b */
1331 } else if (out_lo == in_hi) {
1332 if (out_hi == in_lo) {
1333 /* a -> b, b -> a */
1334 emit_xchg(node, in_lo, in_hi);
1337 /* a -> b, b -> d */
1338 emit_mov(node, in_hi, out_hi);
1339 emit_mov(node, in_lo, out_lo);
1343 if (out_hi == in_lo) {
1344 /* a -> c, b -> a */
1345 emit_mov(node, in_lo, out_lo);
1347 } else if (out_hi == in_hi) {
1348 /* a -> c, b -> b */
1349 emit_mov(node, in_lo, out_lo);
1352 /* a -> c, b -> d */
1353 emit_mov(node, in_lo, out_lo);
1359 emit_neg( node, out_hi);
1360 emit_neg( node, out_lo);
1361 emit_sbb0(node, out_hi);
1365 emit_zero(node, out_hi);
1366 emit_neg( node, out_lo);
1367 emit_sbb( node, in_hi, out_hi);
1370 static void emit_ia32_GetEIP(const ir_node *node)
1372 ia32_emitf(node, "call %s", pic_base_label);
1373 be_emit_irprintf("%s:\n", pic_base_label);
1374 be_emit_write_line();
1375 ia32_emitf(node, "popl %D0");
1378 static void emit_ia32_ClimbFrame(const ir_node *node)
1380 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1382 ia32_emitf(node, "movl %S0, %D0");
1383 ia32_emitf(node, "movl $%u, %S1", attr->count);
1384 be_gas_emit_block_name(node);
1385 be_emit_cstring(":\n");
1386 be_emit_write_line();
1387 ia32_emitf(node, "movl (%D0), %D0");
1388 ia32_emitf(node, "dec %S1");
1389 be_emit_cstring("\tjnz ");
1390 be_gas_emit_block_name(node);
1391 be_emit_finish_line_gas(node);
1394 static void emit_be_Return(const ir_node *node)
1396 unsigned pop = be_Return_get_pop(node);
1398 if (pop > 0 || be_Return_get_emit_pop(node)) {
1399 ia32_emitf(node, "ret $%u", pop);
1401 ia32_emitf(node, "ret");
1405 static void emit_Nothing(const ir_node *node)
1412 * Enters the emitter functions for handled nodes into the generic
1413 * pointer of an opcode.
1415 static void ia32_register_emitters(void)
1417 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1418 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1419 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1420 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1421 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1423 /* first clear the generic function pointer for all ops */
1424 ir_clear_opcodes_generic_func();
1426 /* register all emitter functions defined in spec */
1427 ia32_register_spec_emitters();
1429 /* other ia32 emitter functions */
1432 IA32_EMIT(Conv_FP2FP);
1433 IA32_EMIT(Conv_FP2I);
1434 IA32_EMIT(Conv_I2FP);
1441 IA32_EMIT(Minus64Bit);
1442 IA32_EMIT(SwitchJmp);
1443 IA32_EMIT(ClimbFrame);
1446 /* benode emitter */
1465 typedef void (*emit_func_ptr) (const ir_node *);
1468 * Assign and emit an exception label if the current instruction can fail.
1470 static void ia32_assign_exc_label(ir_node *node)
1472 /* assign a new ID to the instruction */
1473 set_ia32_exc_label_id(node, ++exc_label_id);
1475 ia32_emit_exc_label(node);
1477 be_emit_pad_comment();
1478 be_emit_cstring("/* exception to Block ");
1479 ia32_emit_cfop_target(node);
1480 be_emit_cstring(" */\n");
1481 be_emit_write_line();
1485 * Emits code for a node.
1487 static void ia32_emit_node(ir_node *node)
1489 ir_op *op = get_irn_op(node);
1491 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1493 if (is_ia32_irn(node)) {
1494 if (get_ia32_exc_label(node)) {
1495 /* emit the exception label of this instruction */
1496 ia32_assign_exc_label(node);
1498 if (mark_spill_reload) {
1499 if (is_ia32_is_spill(node)) {
1500 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1502 if (is_ia32_is_reload(node)) {
1503 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1505 if (is_ia32_is_remat(node)) {
1506 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1510 if (op->ops.generic) {
1511 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1513 be_dwarf_location(get_irn_dbg_info(node));
1518 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1523 int sp_change = arch_get_sp_bias(node);
1524 if (sp_change != 0) {
1525 assert(sp_change != SP_BIAS_RESET);
1526 callframe_offset += sp_change;
1527 be_dwarf_callframe_offset(callframe_offset);
1533 * Emits gas alignment directives
1535 static void ia32_emit_alignment(unsigned align, unsigned skip)
1537 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1541 * Emits gas alignment directives for Labels depended on cpu architecture.
1543 static void ia32_emit_align_label(void)
1545 unsigned align = ia32_cg_config.label_alignment;
1546 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1547 ia32_emit_alignment(align, maximum_skip);
1551 * Test whether a block should be aligned.
1552 * For cpus in the P4/Athlon class it is useful to align jump labels to
1553 * 16 bytes. However we should only do that if the alignment nops before the
1554 * label aren't executed more often than we have jumps to the label.
1556 static int should_align_block(const ir_node *block)
1558 static const double DELTA = .0001;
1559 ir_node *prev = get_prev_block_sched(block);
1560 double prev_freq = 0; /**< execfreq of the fallthrough block */
1561 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1565 if (ia32_cg_config.label_alignment_factor <= 0)
1568 block_freq = get_block_execfreq(block);
1569 if (block_freq < DELTA)
1572 n_cfgpreds = get_Block_n_cfgpreds(block);
1573 for (i = 0; i < n_cfgpreds; ++i) {
1574 const ir_node *pred = get_Block_cfgpred_block(block, i);
1575 double pred_freq = get_block_execfreq(pred);
1578 prev_freq += pred_freq;
1580 jmp_freq += pred_freq;
1584 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1587 jmp_freq /= prev_freq;
1589 return jmp_freq > ia32_cg_config.label_alignment_factor;
1593 * Emit the block header for a block.
1595 * @param block the block
1596 * @param prev_block the previous block
1598 static void ia32_emit_block_header(ir_node *block)
1600 ir_graph *irg = current_ir_graph;
1601 int need_label = block_needs_label(block);
1603 if (block == get_irg_end_block(irg))
1606 if (ia32_cg_config.label_alignment > 0) {
1607 /* align the current block if:
1608 * a) if should be aligned due to its execution frequency
1609 * b) there is no fall-through here
1611 if (should_align_block(block)) {
1612 ia32_emit_align_label();
1614 /* if the predecessor block has no fall-through,
1615 we can always align the label. */
1617 int has_fallthrough = 0;
1619 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1620 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1621 if (can_be_fallthrough(cfg_pred)) {
1622 has_fallthrough = 1;
1627 if (!has_fallthrough)
1628 ia32_emit_align_label();
1632 be_gas_begin_block(block, need_label);
1636 * Walks over the nodes in a block connected by scheduling edges
1637 * and emits code for each node.
1639 static void ia32_gen_block(ir_node *block)
1641 ia32_emit_block_header(block);
1644 ir_graph *irg = get_irn_irg(block);
1645 callframe_offset = 4; /* 4 bytes for the return address */
1646 /* ESP guessing, TODO perform a real ESP simulation */
1647 if (block != get_irg_start_block(irg)) {
1648 callframe_offset += frame_type_size;
1650 be_dwarf_callframe_offset(callframe_offset);
1653 /* emit the contents of the block */
1654 be_dwarf_location(get_irn_dbg_info(block));
1655 sched_foreach(block, node) {
1656 ia32_emit_node(node);
1660 typedef struct exc_entry {
1661 ir_node *exc_instr; /** The instruction that can issue an exception. */
1662 ir_node *block; /** The block to call then. */
1667 * Sets labels for control flow nodes (jump target).
1668 * Links control predecessors to there destination blocks.
1670 static void ia32_gen_labels(ir_node *block, void *data)
1672 exc_entry **exc_list = (exc_entry**)data;
1676 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1677 pred = get_Block_cfgpred(block, n);
1678 set_irn_link(pred, block);
1680 pred = skip_Proj(pred);
1681 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1686 ARR_APP1(exc_entry, *exc_list, e);
1687 set_irn_link(pred, block);
1693 * Compare two exception_entries.
1695 static int cmp_exc_entry(const void *a, const void *b)
1697 const exc_entry *ea = (const exc_entry*)a;
1698 const exc_entry *eb = (const exc_entry*)b;
1700 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1705 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1707 ir_entity *entity = get_irg_entity(irg);
1708 ir_type *type = get_entity_type(entity);
1709 size_t n_params = get_method_n_params(type);
1710 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1711 ir_type *arg_type = layout->arg_type;
1712 size_t n_members = get_compound_n_members(arg_type);
1713 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1716 for (i = 0; i < n_members; ++i) {
1717 ir_entity *member = get_compound_member(arg_type, i);
1719 if (!is_parameter_entity(member))
1721 param = get_entity_parameter_number(member);
1722 if (param == IR_VA_START_PARAMETER_NUMBER)
1724 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1725 infos[param].reg = NULL;
1726 infos[param].entity = member;
1733 * Main driver. Emits the code for one routine.
1735 void ia32_gen_routine(ir_graph *irg)
1737 ir_entity *entity = get_irg_entity(irg);
1738 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1739 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1740 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1741 ir_node **blk_sched = irg_data->blk_sched;
1742 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1743 parameter_dbg_info_t *infos;
1746 isa = (ia32_isa_t*) arch_env;
1747 do_pic = be_options.pic;
1749 be_gas_elf_type_char = '@';
1751 ia32_register_emitters();
1753 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1755 infos = construct_parameter_infos(irg);
1756 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1760 sp_relative = layout->sp_relative;
1761 if (layout->sp_relative) {
1762 ir_type *frame_type = get_irg_frame_type(irg);
1763 frame_type_size = get_type_size_bytes(frame_type);
1764 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1766 /* well not entirely correct here, we should emit this after the
1767 * "movl esp, ebp" */
1768 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1769 /* TODO: do not hardcode the following */
1770 be_dwarf_callframe_offset(8);
1771 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1774 /* we use links to point to target blocks */
1775 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1776 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1778 /* initialize next block links */
1779 n = ARR_LEN(blk_sched);
1780 for (i = 0; i < n; ++i) {
1781 ir_node *block = blk_sched[i];
1782 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1784 set_irn_link(block, prev);
1787 for (i = 0; i < n; ++i) {
1788 ir_node *block = blk_sched[i];
1790 ia32_gen_block(block);
1793 be_gas_emit_function_epilog(entity);
1795 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1797 /* Sort the exception table using the exception label id's.
1798 Those are ascending with ascending addresses. */
1799 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1803 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1804 be_emit_cstring("\t.long ");
1805 ia32_emit_exc_label(exc_list[e].exc_instr);
1807 be_emit_cstring("\t.long ");
1808 be_gas_emit_block_name(exc_list[e].block);
1812 DEL_ARR_F(exc_list);
1815 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1816 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1820 /* ==== Experimental binary emitter ==== */
1822 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1823 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1824 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1826 static void build_reg_map(void)
1828 reg_gp_map[REG_GP_EAX] = 0x0;
1829 reg_gp_map[REG_GP_ECX] = 0x1;
1830 reg_gp_map[REG_GP_EDX] = 0x2;
1831 reg_gp_map[REG_GP_EBX] = 0x3;
1832 reg_gp_map[REG_GP_ESP] = 0x4;
1833 reg_gp_map[REG_GP_EBP] = 0x5;
1834 reg_gp_map[REG_GP_ESI] = 0x6;
1835 reg_gp_map[REG_GP_EDI] = 0x7;
1838 /** Returns the encoding for a pnc field. */
1839 static unsigned char pnc2cc(ia32_condition_code_t cc)
1844 /** Sign extension bit values for binops */
1846 UNSIGNED_IMM = 0, /**< unsigned immediate */
1847 SIGNEXT_IMM = 2, /**< sign extended immediate */
1850 /** The mod encoding of the ModR/M */
1852 MOD_IND = 0x00, /**< [reg1] */
1853 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1854 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1855 MOD_REG = 0xC0 /**< reg1 */
1858 /** create R/M encoding for ModR/M */
1859 #define ENC_RM(x) (x)
1860 /** create REG encoding for ModR/M */
1861 #define ENC_REG(x) ((x) << 3)
1863 /** create encoding for a SIB byte */
1864 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1866 /* Node: The following routines are supposed to append bytes, words, dwords
1867 to the output stream.
1868 Currently the implementation is stupid in that it still creates output
1869 for an "assembler" in the form of .byte, .long
1870 We will change this when enough infrastructure is there to create complete
1871 machine code in memory/object files */
1873 static void bemit8(const unsigned char byte)
1875 be_emit_irprintf("\t.byte 0x%x\n", byte);
1876 be_emit_write_line();
1879 static void bemit16(const unsigned short u16)
1881 be_emit_irprintf("\t.word 0x%x\n", u16);
1882 be_emit_write_line();
1885 static void bemit32(const unsigned u32)
1887 be_emit_irprintf("\t.long 0x%x\n", u32);
1888 be_emit_write_line();
1892 * Emit address of an entity. If @p is_relative is true then a relative
1893 * offset from behind the address to the entity is created.
1895 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1898 if (entity == NULL) {
1903 /* the final version should remember the position in the bytestream
1904 and patch it with the correct address at linktime... */
1905 be_emit_cstring("\t.long ");
1908 be_gas_emit_entity(entity);
1910 if (get_entity_owner(entity) == get_tls_type()) {
1911 if (!entity_has_definition(entity)) {
1912 be_emit_cstring("@INDNTPOFF");
1914 be_emit_cstring("@NTPOFF");
1919 be_emit_cstring("-.");
1924 be_emit_irprintf("%+d", offset);
1927 be_emit_write_line();
1930 static void bemit_jmp_destination(const ir_node *dest_block)
1932 be_emit_cstring("\t.long ");
1933 be_gas_emit_block_name(dest_block);
1934 be_emit_cstring(" - . - 4\n");
1935 be_emit_write_line();
1938 /* end emit routines, all emitters following here should only use the functions
1941 typedef enum reg_modifier {
1946 /** Create a ModR/M byte for src1,src2 registers */
1947 static void bemit_modrr(const arch_register_t *src1,
1948 const arch_register_t *src2)
1950 unsigned char modrm = MOD_REG;
1951 modrm |= ENC_RM(reg_gp_map[src1->index]);
1952 modrm |= ENC_REG(reg_gp_map[src2->index]);
1956 /** Create a ModR/M8 byte for src1,src2 registers */
1957 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1958 reg_modifier_t high_part2, const arch_register_t *src2)
1960 unsigned char modrm = MOD_REG;
1961 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1962 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1966 /** Create a ModR/M byte for one register and extension */
1967 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1969 unsigned char modrm = MOD_REG;
1971 modrm |= ENC_RM(reg_gp_map[reg->index]);
1972 modrm |= ENC_REG(ext);
1976 /** Create a ModR/M8 byte for one register */
1977 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1979 unsigned char modrm = MOD_REG;
1980 assert(reg_gp_map[reg->index] < 4);
1981 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1987 * Calculate the size of an signed immediate in bytes.
1989 * @param offset an offset
1991 static unsigned get_signed_imm_size(int offset)
1993 if (-128 <= offset && offset < 128) {
1995 } else if (-32768 <= offset && offset < 32768) {
2003 * Emit an address mode.
2005 * @param reg content of the reg field: either a register index or an opcode extension
2006 * @param node the node
2008 static void bemit_mod_am(unsigned reg, const ir_node *node)
2010 ir_entity *ent = get_ia32_am_sc(node);
2011 int offs = get_ia32_am_offs_int(node);
2012 ir_node *base = get_irn_n(node, n_ia32_base);
2013 int has_base = !is_ia32_NoReg_GP(base);
2014 ir_node *idx = get_irn_n(node, n_ia32_index);
2015 int has_index = !is_ia32_NoReg_GP(idx);
2018 unsigned emitoffs = 0;
2019 bool emitsib = false;
2022 /* set the mod part depending on displacement */
2024 modrm |= MOD_IND_WORD_OFS;
2026 } else if (offs == 0) {
2029 } else if (-128 <= offs && offs < 128) {
2030 modrm |= MOD_IND_BYTE_OFS;
2033 modrm |= MOD_IND_WORD_OFS;
2038 const arch_register_t *base_reg = arch_get_irn_register(base);
2039 base_enc = reg_gp_map[base_reg->index];
2041 /* Use the EBP encoding + MOD_IND if NO base register. There is
2042 * always a 32bit offset present in this case. */
2048 /* Determine if we need a SIB byte. */
2050 const arch_register_t *reg_index = arch_get_irn_register(idx);
2051 int scale = get_ia32_am_scale(node);
2053 /* R/M set to ESP means SIB in 32bit mode. */
2054 modrm |= ENC_RM(0x04);
2055 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2057 } else if (base_enc == 0x04) {
2058 /* for the above reason we are forced to emit a SIB when base is ESP.
2059 * Only the base is used, index must be ESP too, which means no index.
2061 modrm |= ENC_RM(0x04);
2062 sib = ENC_SIB(0, 0x04, 0x04);
2065 modrm |= ENC_RM(base_enc);
2068 /* We are forced to emit an 8bit offset as EBP base without offset is a
2069 * special case for SIB without base register. */
2070 if (base_enc == 0x05 && emitoffs == 0) {
2071 modrm |= MOD_IND_BYTE_OFS;
2075 modrm |= ENC_REG(reg);
2081 /* emit displacement */
2082 if (emitoffs == 8) {
2083 bemit8((unsigned) offs);
2084 } else if (emitoffs == 32) {
2085 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2090 * Emit a binop with a immediate operand.
2092 * @param node the node to emit
2093 * @param opcode_eax the opcode for the op eax, imm variant
2094 * @param opcode the opcode for the reg, imm variant
2095 * @param ruval the opcode extension for opcode
2097 static void bemit_binop_with_imm(
2098 const ir_node *node,
2099 unsigned char opcode_ax,
2100 unsigned char opcode, unsigned char ruval)
2102 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2103 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2104 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2107 /* Some instructions (test) have no short form with 32bit value + 8bit
2109 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2112 /* check for sign extension */
2113 size = get_signed_imm_size(attr->offset);
2118 bemit8(opcode | SIGNEXT_IMM);
2119 /* cmp has this special mode */
2120 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2121 bemit_mod_am(ruval, node);
2123 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2124 bemit_modru(reg, ruval);
2126 bemit8((unsigned char)attr->offset);
2130 /* check for eax variant: this variant is shorter for 32bit immediates only */
2131 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2133 bemit_mod_am(ruval, node);
2135 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2136 if (reg->index == REG_GP_EAX) {
2140 bemit_modru(reg, ruval);
2143 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2146 panic("invalid imm size?!?");
2152 static void bemit_binop_2(const ir_node *node, unsigned code)
2154 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2156 if (get_ia32_op_type(node) == ia32_Normal) {
2157 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2158 bemit_modrr(op2, out);
2160 bemit_mod_am(reg_gp_map[out->index], node);
2167 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2169 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2170 if (is_ia32_Immediate(right)) {
2171 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2173 bemit_binop_2(node, opcodes[0]);
2180 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2183 if (get_ia32_op_type(node) == ia32_Normal) {
2184 const arch_register_t *in = arch_get_irn_register_in(node, input);
2185 bemit_modru(in, ext);
2187 bemit_mod_am(ext, node);
2191 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2193 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2194 bemit_unop(node, code, reg_gp_map[out->index], input);
2197 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2199 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2202 bemit8(size == 8 ? code : code + 1);
2203 bemit_mod_am(ext, node);
2206 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2209 bemit_unop_reg(node, code, input);
2212 static void bemit_immediate(const ir_node *node, bool relative)
2214 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2215 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2218 static void bemit_copy(const ir_node *copy)
2220 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2221 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2225 /* copies of vf nodes aren't real... */
2226 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2229 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2231 bemit_modrr(in, out);
2234 static void bemit_perm(const ir_node *node)
2236 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2237 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2238 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2240 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2242 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2243 if (in0->index == REG_GP_EAX) {
2244 bemit8(0x90 + reg_gp_map[in1->index]);
2245 } else if (in1->index == REG_GP_EAX) {
2246 bemit8(0x90 + reg_gp_map[in0->index]);
2249 bemit_modrr(in0, in1);
2251 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2252 panic("unimplemented"); // TODO implement
2253 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2254 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2255 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2256 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2258 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2261 panic("unexpected register class in be_Perm (%+F)", node);
2265 static void bemit_xor0(const ir_node *node)
2267 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2269 bemit_modrr(out, out);
2272 static void bemit_mov_const(const ir_node *node)
2274 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2275 bemit8(0xB8 + reg_gp_map[out->index]);
2276 bemit_immediate(node, false);
2280 * Creates a function for a Binop with 3 possible encodings.
2282 #define BINOP(op, op0, op1, op2, op2_ext) \
2283 static void bemit_ ## op(const ir_node *node) { \
2284 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2285 bemit_binop(node, op ## _codes); \
2288 /* insn def eax,imm imm */
2289 BINOP(add, 0x03, 0x05, 0x81, 0)
2290 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2291 BINOP(adc, 0x13, 0x15, 0x81, 2)
2292 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2293 BINOP(and, 0x23, 0x25, 0x81, 4)
2294 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2295 BINOP(xor, 0x33, 0x35, 0x81, 6)
2296 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2298 #define BINOPMEM(op, ext) \
2299 static void bemit_##op(const ir_node *node) \
2302 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2305 val = get_irn_n(node, n_ia32_unary_op); \
2306 if (is_ia32_Immediate(val)) { \
2307 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2308 int offset = attr->offset; \
2309 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2311 bemit_mod_am(ext, node); \
2315 bemit_mod_am(ext, node); \
2319 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2323 bemit8(ext << 3 | 1); \
2324 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2328 static void bemit_##op##8bit(const ir_node *node) \
2330 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2331 if (is_ia32_Immediate(val)) { \
2333 bemit_mod_am(ext, node); \
2334 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2337 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2349 * Creates a function for an Unop with code /ext encoding.
2351 #define UNOP(op, code, ext, input) \
2352 static void bemit_ ## op(const ir_node *node) { \
2353 bemit_unop(node, code, ext, input); \
2356 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2357 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2358 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2359 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2360 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2361 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2363 /* TODO: am support for IJmp */
2364 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2366 #define SHIFT(op, ext) \
2367 static void bemit_##op(const ir_node *node) \
2369 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2370 ir_node *count = get_irn_n(node, 1); \
2371 if (is_ia32_Immediate(count)) { \
2372 int offset = get_ia32_immediate_attr_const(count)->offset; \
2373 if (offset == 1) { \
2375 bemit_modru(out, ext); \
2378 bemit_modru(out, ext); \
2383 bemit_modru(out, ext); \
2387 static void bemit_##op##mem(const ir_node *node) \
2390 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2393 count = get_irn_n(node, 1); \
2394 if (is_ia32_Immediate(count)) { \
2395 int offset = get_ia32_immediate_attr_const(count)->offset; \
2396 if (offset == 1) { \
2397 bemit8(size == 8 ? 0xD0 : 0xD1); \
2398 bemit_mod_am(ext, node); \
2400 bemit8(size == 8 ? 0xC0 : 0xC1); \
2401 bemit_mod_am(ext, node); \
2405 bemit8(size == 8 ? 0xD2 : 0xD3); \
2406 bemit_mod_am(ext, node); \
2416 static void bemit_shld(const ir_node *node)
2418 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2419 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2420 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2422 if (is_ia32_Immediate(count)) {
2424 bemit_modrr(out, in);
2425 bemit8(get_ia32_immediate_attr_const(count)->offset);
2428 bemit_modrr(out, in);
2432 static void bemit_shrd(const ir_node *node)
2434 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2435 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2436 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2438 if (is_ia32_Immediate(count)) {
2440 bemit_modrr(out, in);
2441 bemit8(get_ia32_immediate_attr_const(count)->offset);
2444 bemit_modrr(out, in);
2448 static void bemit_sbb0(ir_node const *const node)
2450 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2451 unsigned char const reg = reg_gp_map[out->index];
2453 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2457 * binary emitter for setcc.
2459 static void bemit_setcc(const ir_node *node)
2461 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2463 ia32_condition_code_t cc = get_ia32_condcode(node);
2464 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2465 if (cc & ia32_cc_float_parity_cases) {
2466 if (cc & ia32_cc_negated) {
2469 bemit8(0x90 | pnc2cc(cc));
2470 bemit_modrm8(REG_LOW, dreg);
2475 bemit_modrm8(REG_HIGH, dreg);
2477 /* orb %>dreg, %<dreg */
2479 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2483 bemit8(0x90 | pnc2cc(cc));
2484 bemit_modrm8(REG_LOW, dreg);
2489 bemit_modrm8(REG_HIGH, dreg);
2491 /* andb %>dreg, %<dreg */
2493 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2498 bemit8(0x90 | pnc2cc(cc));
2499 bemit_modrm8(REG_LOW, dreg);
2503 static void bemit_bsf(ir_node const *const node)
2505 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2508 static void bemit_bsr(ir_node const *const node)
2510 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2513 static void bemit_bswap(ir_node const *const node)
2516 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2519 static void bemit_bt(ir_node const *const node)
2522 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2523 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2524 if (is_ia32_Immediate(right)) {
2525 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2526 int const offset = attr->offset;
2527 assert(!attr->symconst);
2528 assert(get_signed_imm_size(offset) == 1);
2530 bemit_modru(lreg, 4);
2534 bemit_modrr(lreg, arch_get_irn_register(right));
2538 static void bemit_cmovcc(const ir_node *node)
2540 const ia32_attr_t *attr = get_ia32_attr_const(node);
2541 int ins_permuted = attr->data.ins_permuted;
2542 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2543 ia32_condition_code_t cc = get_ia32_condcode(node);
2544 const arch_register_t *in_true;
2545 const arch_register_t *in_false;
2547 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2549 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2550 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2552 /* should be same constraint fullfilled? */
2553 if (out == in_false) {
2554 /* yes -> nothing to do */
2555 } else if (out == in_true) {
2556 assert(get_ia32_op_type(node) == ia32_Normal);
2557 ins_permuted = !ins_permuted;
2561 bemit8(0x8B); // mov %in_false, %out
2562 bemit_modrr(in_false, out);
2566 cc = ia32_negate_condition_code(cc);
2568 if (cc & ia32_cc_float_parity_cases)
2569 panic("cmov can't handle parity float cases");
2572 bemit8(0x40 | pnc2cc(cc));
2573 if (get_ia32_op_type(node) == ia32_Normal) {
2574 bemit_modrr(in_true, out);
2576 bemit_mod_am(reg_gp_map[out->index], node);
2580 static void bemit_cmp(const ir_node *node)
2582 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2588 right = get_irn_n(node, n_ia32_binary_right);
2589 if (is_ia32_Immediate(right)) {
2590 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2591 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2592 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2595 if (attr->symconst != NULL) {
2598 /* check for sign extension */
2599 size = get_signed_imm_size(attr->offset);
2604 bemit8(0x81 | SIGNEXT_IMM);
2605 /* cmp has this special mode */
2606 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2607 bemit_mod_am(7, node);
2609 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2610 bemit_modru(reg, 7);
2612 bemit8((unsigned char)attr->offset);
2616 /* check for eax variant: this variant is shorter for 32bit immediates only */
2617 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2619 bemit_mod_am(7, node);
2621 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2622 if (reg->index == REG_GP_EAX) {
2626 bemit_modru(reg, 7);
2629 if (ls_size == 16) {
2630 bemit16(attr->offset);
2632 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2636 panic("invalid imm size?!?");
2638 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2640 if (get_ia32_op_type(node) == ia32_Normal) {
2641 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2642 bemit_modrr(op2, out);
2644 bemit_mod_am(reg_gp_map[out->index], node);
2649 static void bemit_cmp8bit(const ir_node *node)
2651 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2652 if (is_ia32_Immediate(right)) {
2653 if (get_ia32_op_type(node) == ia32_Normal) {
2654 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2655 if (out->index == REG_GP_EAX) {
2659 bemit_modru(out, 7);
2663 bemit_mod_am(7, node);
2665 bemit8(get_ia32_immediate_attr_const(right)->offset);
2667 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2669 if (get_ia32_op_type(node) == ia32_Normal) {
2670 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2671 bemit_modrr(out, in);
2673 bemit_mod_am(reg_gp_map[out->index], node);
2678 static void bemit_test8bit(const ir_node *node)
2680 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2681 if (is_ia32_Immediate(right)) {
2682 if (get_ia32_op_type(node) == ia32_Normal) {
2683 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2684 if (out->index == REG_GP_EAX) {
2688 bemit_modru(out, 0);
2692 bemit_mod_am(0, node);
2694 bemit8(get_ia32_immediate_attr_const(right)->offset);
2696 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2698 if (get_ia32_op_type(node) == ia32_Normal) {
2699 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2700 bemit_modrr(out, in);
2702 bemit_mod_am(reg_gp_map[out->index], node);
2707 static void bemit_imul(const ir_node *node)
2709 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2710 /* Do we need the immediate form? */
2711 if (is_ia32_Immediate(right)) {
2712 int imm = get_ia32_immediate_attr_const(right)->offset;
2713 if (get_signed_imm_size(imm) == 1) {
2714 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2717 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2721 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2725 static void bemit_dec(const ir_node *node)
2727 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2728 bemit8(0x48 + reg_gp_map[out->index]);
2731 static void bemit_inc(const ir_node *node)
2733 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2734 bemit8(0x40 + reg_gp_map[out->index]);
2737 #define UNOPMEM(op, code, ext) \
2738 static void bemit_##op(const ir_node *node) \
2740 bemit_unop_mem(node, code, ext); \
2743 UNOPMEM(notmem, 0xF6, 2)
2744 UNOPMEM(negmem, 0xF6, 3)
2745 UNOPMEM(incmem, 0xFE, 0)
2746 UNOPMEM(decmem, 0xFE, 1)
2748 static void bemit_ldtls(const ir_node *node)
2750 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2752 bemit8(0x65); // gs:
2753 if (out->index == REG_GP_EAX) {
2754 bemit8(0xA1); // movl 0, %eax
2756 bemit8(0x8B); // movl 0, %reg
2757 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2765 static void bemit_lea(const ir_node *node)
2767 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2769 bemit_mod_am(reg_gp_map[out->index], node);
2772 /* helper function for bemit_minus64bit */
2773 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2775 bemit8(0x8B); // movl %src, %dst
2776 bemit_modrr(src, dst);
2779 /* helper function for bemit_minus64bit */
2780 static void bemit_helper_neg(const arch_register_t *reg)
2782 bemit8(0xF7); // negl %reg
2783 bemit_modru(reg, 3);
2786 /* helper function for bemit_minus64bit */
2787 static void bemit_helper_sbb0(const arch_register_t *reg)
2789 bemit8(0x83); // sbbl $0, %reg
2790 bemit_modru(reg, 3);
2794 /* helper function for bemit_minus64bit */
2795 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2797 bemit8(0x1B); // sbbl %src, %dst
2798 bemit_modrr(src, dst);
2801 /* helper function for bemit_minus64bit */
2802 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2804 if (src->index == REG_GP_EAX) {
2805 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2806 } else if (dst->index == REG_GP_EAX) {
2807 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2809 bemit8(0x87); // xchgl %src, %dst
2810 bemit_modrr(src, dst);
2814 /* helper function for bemit_minus64bit */
2815 static void bemit_helper_zero(const arch_register_t *reg)
2817 bemit8(0x33); // xorl %reg, %reg
2818 bemit_modrr(reg, reg);
2821 static void bemit_minus64bit(const ir_node *node)
2823 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2824 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2825 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2826 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2828 if (out_lo == in_lo) {
2829 if (out_hi != in_hi) {
2830 /* a -> a, b -> d */
2833 /* a -> a, b -> b */
2836 } else if (out_lo == in_hi) {
2837 if (out_hi == in_lo) {
2838 /* a -> b, b -> a */
2839 bemit_helper_xchg(in_lo, in_hi);
2842 /* a -> b, b -> d */
2843 bemit_helper_mov(in_hi, out_hi);
2844 bemit_helper_mov(in_lo, out_lo);
2848 if (out_hi == in_lo) {
2849 /* a -> c, b -> a */
2850 bemit_helper_mov(in_lo, out_lo);
2852 } else if (out_hi == in_hi) {
2853 /* a -> c, b -> b */
2854 bemit_helper_mov(in_lo, out_lo);
2857 /* a -> c, b -> d */
2858 bemit_helper_mov(in_lo, out_lo);
2864 bemit_helper_neg( out_hi);
2865 bemit_helper_neg( out_lo);
2866 bemit_helper_sbb0(out_hi);
2870 bemit_helper_zero(out_hi);
2871 bemit_helper_neg( out_lo);
2872 bemit_helper_sbb( in_hi, out_hi);
2876 * Emit a single opcode.
2878 #define EMIT_SINGLEOP(op, code) \
2879 static void bemit_ ## op(const ir_node *node) { \
2884 //EMIT_SINGLEOP(daa, 0x27)
2885 //EMIT_SINGLEOP(das, 0x2F)
2886 //EMIT_SINGLEOP(aaa, 0x37)
2887 //EMIT_SINGLEOP(aas, 0x3F)
2888 //EMIT_SINGLEOP(nop, 0x90)
2889 EMIT_SINGLEOP(cwtl, 0x98)
2890 EMIT_SINGLEOP(cltd, 0x99)
2891 //EMIT_SINGLEOP(fwait, 0x9B)
2892 EMIT_SINGLEOP(sahf, 0x9E)
2893 //EMIT_SINGLEOP(popf, 0x9D)
2894 EMIT_SINGLEOP(leave, 0xC9)
2895 EMIT_SINGLEOP(int3, 0xCC)
2896 //EMIT_SINGLEOP(iret, 0xCF)
2897 //EMIT_SINGLEOP(xlat, 0xD7)
2898 //EMIT_SINGLEOP(lock, 0xF0)
2899 EMIT_SINGLEOP(rep, 0xF3)
2900 //EMIT_SINGLEOP(halt, 0xF4)
2901 EMIT_SINGLEOP(cmc, 0xF5)
2902 EMIT_SINGLEOP(stc, 0xF9)
2903 //EMIT_SINGLEOP(cli, 0xFA)
2904 //EMIT_SINGLEOP(sti, 0xFB)
2905 //EMIT_SINGLEOP(std, 0xFD)
2908 * Emits a MOV out, [MEM].
2910 static void bemit_load(const ir_node *node)
2912 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2914 if (out->index == REG_GP_EAX) {
2915 ir_node *base = get_irn_n(node, n_ia32_base);
2916 int has_base = !is_ia32_NoReg_GP(base);
2917 ir_node *idx = get_irn_n(node, n_ia32_index);
2918 int has_index = !is_ia32_NoReg_GP(idx);
2919 if (!has_base && !has_index) {
2920 ir_entity *ent = get_ia32_am_sc(node);
2921 int offs = get_ia32_am_offs_int(node);
2922 /* load from constant address to EAX can be encoded
2925 bemit_entity(ent, 0, offs, false);
2930 bemit_mod_am(reg_gp_map[out->index], node);
2934 * Emits a MOV [mem], in.
2936 static void bemit_store(const ir_node *node)
2938 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2939 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2941 if (is_ia32_Immediate(value)) {
2944 bemit_mod_am(0, node);
2945 bemit8(get_ia32_immediate_attr_const(value)->offset);
2946 } else if (size == 16) {
2949 bemit_mod_am(0, node);
2950 bemit16(get_ia32_immediate_attr_const(value)->offset);
2953 bemit_mod_am(0, node);
2954 bemit_immediate(value, false);
2957 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2959 if (in->index == REG_GP_EAX) {
2960 ir_node *base = get_irn_n(node, n_ia32_base);
2961 int has_base = !is_ia32_NoReg_GP(base);
2962 ir_node *idx = get_irn_n(node, n_ia32_index);
2963 int has_index = !is_ia32_NoReg_GP(idx);
2964 if (!has_base && !has_index) {
2965 ir_entity *ent = get_ia32_am_sc(node);
2966 int offs = get_ia32_am_offs_int(node);
2967 /* store to constant address from EAX can be encoded as
2968 * 0xA2/0xA3 [offset]*/
2976 bemit_entity(ent, 0, offs, false);
2988 bemit_mod_am(reg_gp_map[in->index], node);
2992 static void bemit_conv_i2i(const ir_node *node)
2997 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
2998 unsigned opcode = 0xB6;
2999 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3000 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3001 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3004 static void bemit_popcnt(ir_node const *const node)
3007 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
3013 static void bemit_push(const ir_node *node)
3015 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3017 if (is_ia32_Immediate(value)) {
3018 const ia32_immediate_attr_t *attr
3019 = get_ia32_immediate_attr_const(value);
3020 unsigned size = get_signed_imm_size(attr->offset);
3026 bemit8((unsigned char)attr->offset);
3031 bemit_immediate(value, false);
3034 } else if (is_ia32_NoReg_GP(value)) {
3036 bemit_mod_am(6, node);
3038 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3039 bemit8(0x50 + reg_gp_map[reg->index]);
3046 static void bemit_pop(const ir_node *node)
3048 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3049 bemit8(0x58 + reg_gp_map[reg->index]);
3052 static void bemit_popmem(const ir_node *node)
3055 bemit_mod_am(0, node);
3058 static void bemit_call(const ir_node *node)
3060 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3062 if (is_ia32_Immediate(proc)) {
3064 bemit_immediate(proc, true);
3066 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3070 static void bemit_jmp(const ir_node *dest_block)
3073 bemit_jmp_destination(dest_block);
3076 static void bemit_jump(const ir_node *node)
3078 if (can_be_fallthrough(node))
3081 bemit_jmp(get_cfop_target_block(node));
3084 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3086 unsigned char cc = pnc2cc(pnc);
3089 bemit_jmp_destination(dest_block);
3092 static void bemit_jp(bool odd, const ir_node *dest_block)
3096 bemit_jmp_destination(dest_block);
3099 static void bemit_ia32_jcc(const ir_node *node)
3101 ia32_condition_code_t cc = get_ia32_condcode(node);
3102 const ir_node *proj_true;
3103 const ir_node *proj_false;
3104 const ir_node *dest_true;
3105 const ir_node *dest_false;
3107 cc = determine_final_cc(node, 0, cc);
3109 /* get both Projs */
3110 proj_true = get_proj(node, pn_ia32_Jcc_true);
3111 assert(proj_true && "Jcc without true Proj");
3113 proj_false = get_proj(node, pn_ia32_Jcc_false);
3114 assert(proj_false && "Jcc without false Proj");
3116 if (can_be_fallthrough(proj_true)) {
3117 /* exchange both proj's so the second one can be omitted */
3118 const ir_node *t = proj_true;
3120 proj_true = proj_false;
3122 cc = ia32_negate_condition_code(cc);
3125 dest_true = get_cfop_target_block(proj_true);
3126 dest_false = get_cfop_target_block(proj_false);
3128 if (cc & ia32_cc_float_parity_cases) {
3129 /* Some floating point comparisons require a test of the parity flag,
3130 * which indicates that the result is unordered */
3131 if (cc & ia32_cc_negated) {
3132 bemit_jp(false, dest_true);
3134 /* we need a local label if the false proj is a fallthrough
3135 * as the falseblock might have no label emitted then */
3136 if (can_be_fallthrough(proj_false)) {
3138 bemit8(0x06); // jp + 6
3140 bemit_jp(false, dest_false);
3144 bemit_jcc(cc, dest_true);
3146 /* the second Proj might be a fallthrough */
3147 if (can_be_fallthrough(proj_false)) {
3148 /* it's a fallthrough */
3150 bemit_jmp(dest_false);
3154 static void bemit_switchjmp(const ir_node *node)
3156 ir_entity *jump_table = get_ia32_am_sc(node);
3157 const ir_switch_table *table = get_ia32_switch_table(node);
3159 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3160 bemit_mod_am(0x05, node);
3162 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3168 static void bemit_return(const ir_node *node)
3170 unsigned pop = be_Return_get_pop(node);
3171 if (pop > 0 || be_Return_get_emit_pop(node)) {
3173 assert(pop <= 0xffff);
3180 static void bemit_subsp(const ir_node *node)
3182 const arch_register_t *out;
3185 /* mov %esp, %out */
3187 out = arch_get_irn_register_out(node, 1);
3188 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3191 static void bemit_incsp(const ir_node *node)
3194 const arch_register_t *reg;
3198 offs = be_get_IncSP_offset(node);
3209 size = get_signed_imm_size(offs);
3210 bemit8(size == 1 ? 0x83 : 0x81);
3212 reg = arch_get_irn_register_out(node, 0);
3213 bemit_modru(reg, ext);
3222 static void bemit_copybi(const ir_node *node)
3224 unsigned size = get_ia32_copyb_size(node);
3226 bemit8(0xA4); // movsb
3229 bemit8(0xA5); // movsw
3233 bemit8(0xA5); // movsl
3237 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3239 if (get_ia32_op_type(node) == ia32_Normal) {
3240 ia32_x87_attr_t const *const x87_attr = get_ia32_x87_attr_const(node);
3241 arch_register_t const *const out = x87_attr->x87[2];
3242 arch_register_t const * in = x87_attr->x87[1];
3244 in = x87_attr->x87[0];
3246 if (out->index == 0) {
3248 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3251 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3254 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3259 bemit_mod_am(code, node);
3263 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3265 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3266 const arch_register_t *out = x87_attr->x87[2];
3268 bemit8(code + out->index);
3271 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3274 bemit8(op1 + get_ia32_x87_attr_const(node)->x87[0]->index);
3277 static void bemit_fabs(const ir_node *node)
3285 static void bemit_fadd(const ir_node *node)
3287 bemit_fbinop(node, 0, 0);
3290 static void bemit_faddp(const ir_node *node)
3292 bemit_fbinopp(node, 0xC0);
3295 static void bemit_fchs(const ir_node *node)
3303 static void bemit_fdiv(const ir_node *node)
3305 bemit_fbinop(node, 6, 7);
3308 static void bemit_fdivp(const ir_node *node)
3310 bemit_fbinopp(node, 0xF8);
3313 static void bemit_fdivr(const ir_node *node)
3315 bemit_fbinop(node, 7, 6);
3318 static void bemit_fdivrp(const ir_node *node)
3320 bemit_fbinopp(node, 0xF0);
3323 static void bemit_ffreep(ir_node const *const node)
3325 bemit_fop_reg(node, 0xDF, 0xC0);
3328 static void bemit_fild(const ir_node *node)
3330 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3332 bemit8(0xDF); // filds
3333 bemit_mod_am(0, node);
3337 bemit8(0xDB); // fildl
3338 bemit_mod_am(0, node);
3342 bemit8(0xDF); // fildll
3343 bemit_mod_am(5, node);
3347 panic("invalid mode size");
3351 static void bemit_fist(const ir_node *node)
3353 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3355 bemit8(0xDF); // fists
3359 bemit8(0xDB); // fistl
3363 panic("invalid mode size");
3365 bemit_mod_am(2, node);
3368 static void bemit_fistp(const ir_node *node)
3370 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3372 bemit8(0xDF); // fistps
3373 bemit_mod_am(3, node);
3377 bemit8(0xDB); // fistpl
3378 bemit_mod_am(3, node);
3382 bemit8(0xDF); // fistpll
3383 bemit_mod_am(7, node);
3387 panic("invalid mode size");
3391 static void bemit_fisttp(ir_node const *const node)
3393 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3394 case 16: bemit8(0xDF); break; // fisttps
3395 case 32: bemit8(0xDB); break; // fisttpl
3396 case 64: bemit8(0xDD); break; // fisttpll
3397 default: panic("Invalid mode size");
3399 bemit_mod_am(1, node);
3402 static void bemit_fld(const ir_node *node)
3404 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3406 bemit8(0xD9); // flds
3407 bemit_mod_am(0, node);
3411 bemit8(0xDD); // fldl
3412 bemit_mod_am(0, node);
3417 bemit8(0xDB); // fldt
3418 bemit_mod_am(5, node);
3422 panic("invalid mode size");
3426 static void bemit_fld1(const ir_node *node)
3430 bemit8(0xE8); // fld1
3433 static void bemit_fldcw(const ir_node *node)
3435 bemit8(0xD9); // fldcw
3436 bemit_mod_am(5, node);
3439 static void bemit_fldz(const ir_node *node)
3443 bemit8(0xEE); // fldz
3446 static void bemit_fmul(const ir_node *node)
3448 bemit_fbinop(node, 1, 1);
3451 static void bemit_fmulp(const ir_node *node)
3453 bemit_fbinopp(node, 0xC8);
3456 static void bemit_fpop(const ir_node *node)
3458 bemit_fop_reg(node, 0xDD, 0xD8);
3461 static void bemit_fpush(const ir_node *node)
3463 bemit_fop_reg(node, 0xD9, 0xC0);
3466 static void bemit_fpushcopy(const ir_node *node)
3468 bemit_fop_reg(node, 0xD9, 0xC0);
3471 static void bemit_fst(const ir_node *node)
3473 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3475 bemit8(0xD9); // fsts
3479 bemit8(0xDD); // fstl
3483 panic("invalid mode size");
3485 bemit_mod_am(2, node);
3488 static void bemit_fstp(const ir_node *node)
3490 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3492 bemit8(0xD9); // fstps
3493 bemit_mod_am(3, node);
3497 bemit8(0xDD); // fstpl
3498 bemit_mod_am(3, node);
3503 bemit8(0xDB); // fstpt
3504 bemit_mod_am(7, node);
3508 panic("invalid mode size");
3512 static void bemit_fsub(const ir_node *node)
3514 bemit_fbinop(node, 4, 5);
3517 static void bemit_fsubp(const ir_node *node)
3519 bemit_fbinopp(node, 0xE8);
3522 static void bemit_fsubr(const ir_node *node)
3524 bemit_fbinop(node, 5, 4);
3527 static void bemit_fsubrp(const ir_node *node)
3529 bemit_fbinopp(node, 0xE0);
3532 static void bemit_fnstcw(const ir_node *node)
3534 bemit8(0xD9); // fnstcw
3535 bemit_mod_am(7, node);
3538 static void bemit_fnstsw(void)
3540 bemit8(0xDF); // fnstsw %ax
3544 static void bemit_ftstfnstsw(const ir_node *node)
3548 bemit8(0xD9); // ftst
3553 static void bemit_fucomi(const ir_node *node)
3555 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3556 bemit8(0xDB); // fucomi
3557 bemit8(0xE8 + attr->x87[1]->index);
3560 static void bemit_fucomip(const ir_node *node)
3562 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3563 bemit8(0xDF); // fucomip
3564 bemit8(0xE8 + attr->x87[1]->index);
3567 static void bemit_fucomfnstsw(const ir_node *node)
3569 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3570 bemit8(0xDD); // fucom
3571 bemit8(0xE0 + attr->x87[1]->index);
3575 static void bemit_fucompfnstsw(const ir_node *node)
3577 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3578 bemit8(0xDD); // fucomp
3579 bemit8(0xE8 + attr->x87[1]->index);
3583 static void bemit_fucomppfnstsw(const ir_node *node)
3587 bemit8(0xDA); // fucompp
3592 static void bemit_fxch(const ir_node *node)
3594 bemit_fop_reg(node, 0xD9, 0xC8);
3598 * The type of a emitter function.
3600 typedef void (*emit_func) (const ir_node *);
3603 * Set a node emitter. Make it a bit more type safe.
3605 static void register_emitter(ir_op *op, emit_func func)
3607 op->ops.generic = (op_func) func;
3610 static void ia32_register_binary_emitters(void)
3612 /* first clear the generic function pointer for all ops */
3613 ir_clear_opcodes_generic_func();
3615 /* benode emitter */
3616 register_emitter(op_be_Copy, bemit_copy);
3617 register_emitter(op_be_CopyKeep, bemit_copy);
3618 register_emitter(op_be_IncSP, bemit_incsp);
3619 register_emitter(op_be_Perm, bemit_perm);
3620 register_emitter(op_be_Return, bemit_return);
3621 register_emitter(op_ia32_Adc, bemit_adc);
3622 register_emitter(op_ia32_Add, bemit_add);
3623 register_emitter(op_ia32_AddMem, bemit_addmem);
3624 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3625 register_emitter(op_ia32_And, bemit_and);
3626 register_emitter(op_ia32_AndMem, bemit_andmem);
3627 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3628 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3629 register_emitter(op_ia32_Breakpoint, bemit_int3);
3630 register_emitter(op_ia32_Bsf, bemit_bsf);
3631 register_emitter(op_ia32_Bsr, bemit_bsr);
3632 register_emitter(op_ia32_Bswap, bemit_bswap);
3633 register_emitter(op_ia32_Bt, bemit_bt);
3634 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3635 register_emitter(op_ia32_Call, bemit_call);
3636 register_emitter(op_ia32_Cltd, bemit_cltd);
3637 register_emitter(op_ia32_Cmc, bemit_cmc);
3638 register_emitter(op_ia32_Cmp, bemit_cmp);
3639 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3640 register_emitter(op_ia32_Const, bemit_mov_const);
3641 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3642 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3643 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3644 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3645 register_emitter(op_ia32_Dec, bemit_dec);
3646 register_emitter(op_ia32_DecMem, bemit_decmem);
3647 register_emitter(op_ia32_Div, bemit_div);
3648 register_emitter(op_ia32_FldCW, bemit_fldcw);
3649 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3650 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3651 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3652 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3653 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3654 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3655 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3656 register_emitter(op_ia32_IDiv, bemit_idiv);
3657 register_emitter(op_ia32_IJmp, bemit_ijmp);
3658 register_emitter(op_ia32_IMul, bemit_imul);
3659 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3660 register_emitter(op_ia32_Inc, bemit_inc);
3661 register_emitter(op_ia32_IncMem, bemit_incmem);
3662 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3663 register_emitter(op_ia32_Jmp, bemit_jump);
3664 register_emitter(op_ia32_LdTls, bemit_ldtls);
3665 register_emitter(op_ia32_Lea, bemit_lea);
3666 register_emitter(op_ia32_Leave, bemit_leave);
3667 register_emitter(op_ia32_Load, bemit_load);
3668 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3669 register_emitter(op_ia32_Mul, bemit_mul);
3670 register_emitter(op_ia32_Neg, bemit_neg);
3671 register_emitter(op_ia32_NegMem, bemit_negmem);
3672 register_emitter(op_ia32_Not, bemit_not);
3673 register_emitter(op_ia32_NotMem, bemit_notmem);
3674 register_emitter(op_ia32_Or, bemit_or);
3675 register_emitter(op_ia32_OrMem, bemit_ormem);
3676 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3677 register_emitter(op_ia32_Pop, bemit_pop);
3678 register_emitter(op_ia32_PopEbp, bemit_pop);
3679 register_emitter(op_ia32_PopMem, bemit_popmem);
3680 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3681 register_emitter(op_ia32_Push, bemit_push);
3682 register_emitter(op_ia32_RepPrefix, bemit_rep);
3683 register_emitter(op_ia32_Rol, bemit_rol);
3684 register_emitter(op_ia32_RolMem, bemit_rolmem);
3685 register_emitter(op_ia32_Ror, bemit_ror);
3686 register_emitter(op_ia32_RorMem, bemit_rormem);
3687 register_emitter(op_ia32_Sahf, bemit_sahf);
3688 register_emitter(op_ia32_Sar, bemit_sar);
3689 register_emitter(op_ia32_SarMem, bemit_sarmem);
3690 register_emitter(op_ia32_Sbb, bemit_sbb);
3691 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3692 register_emitter(op_ia32_Setcc, bemit_setcc);
3693 register_emitter(op_ia32_Shl, bemit_shl);
3694 register_emitter(op_ia32_ShlD, bemit_shld);
3695 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3696 register_emitter(op_ia32_Shr, bemit_shr);
3697 register_emitter(op_ia32_ShrD, bemit_shrd);
3698 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3699 register_emitter(op_ia32_Stc, bemit_stc);
3700 register_emitter(op_ia32_Store, bemit_store);
3701 register_emitter(op_ia32_Store8Bit, bemit_store);
3702 register_emitter(op_ia32_Sub, bemit_sub);
3703 register_emitter(op_ia32_SubMem, bemit_submem);
3704 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3705 register_emitter(op_ia32_SubSP, bemit_subsp);
3706 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3707 register_emitter(op_ia32_Test, bemit_test);
3708 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3709 register_emitter(op_ia32_Xor, bemit_xor);
3710 register_emitter(op_ia32_Xor0, bemit_xor0);
3711 register_emitter(op_ia32_XorMem, bemit_xormem);
3712 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3713 register_emitter(op_ia32_fabs, bemit_fabs);
3714 register_emitter(op_ia32_fadd, bemit_fadd);
3715 register_emitter(op_ia32_faddp, bemit_faddp);
3716 register_emitter(op_ia32_fchs, bemit_fchs);
3717 register_emitter(op_ia32_fdiv, bemit_fdiv);
3718 register_emitter(op_ia32_fdivp, bemit_fdivp);
3719 register_emitter(op_ia32_fdivr, bemit_fdivr);
3720 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3721 register_emitter(op_ia32_ffreep, bemit_ffreep);
3722 register_emitter(op_ia32_fild, bemit_fild);
3723 register_emitter(op_ia32_fist, bemit_fist);
3724 register_emitter(op_ia32_fistp, bemit_fistp);
3725 register_emitter(op_ia32_fisttp, bemit_fisttp);
3726 register_emitter(op_ia32_fld, bemit_fld);
3727 register_emitter(op_ia32_fld1, bemit_fld1);
3728 register_emitter(op_ia32_fldz, bemit_fldz);
3729 register_emitter(op_ia32_fmul, bemit_fmul);
3730 register_emitter(op_ia32_fmulp, bemit_fmulp);
3731 register_emitter(op_ia32_fpop, bemit_fpop);
3732 register_emitter(op_ia32_fpush, bemit_fpush);
3733 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3734 register_emitter(op_ia32_fst, bemit_fst);
3735 register_emitter(op_ia32_fstp, bemit_fstp);
3736 register_emitter(op_ia32_fsub, bemit_fsub);
3737 register_emitter(op_ia32_fsubp, bemit_fsubp);
3738 register_emitter(op_ia32_fsubr, bemit_fsubr);
3739 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3740 register_emitter(op_ia32_fxch, bemit_fxch);
3742 /* ignore the following nodes */
3743 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3744 register_emitter(op_ia32_Unknown, emit_Nothing);
3745 register_emitter(op_be_Keep, emit_Nothing);
3746 register_emitter(op_be_Start, emit_Nothing);
3747 register_emitter(op_Phi, emit_Nothing);
3748 register_emitter(op_Start, emit_Nothing);
3751 static void gen_binary_block(ir_node *block)
3753 ia32_emit_block_header(block);
3755 /* emit the contents of the block */
3756 sched_foreach(block, node) {
3757 ia32_emit_node(node);
3761 void ia32_gen_binary_routine(ir_graph *irg)
3763 ir_entity *entity = get_irg_entity(irg);
3764 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3765 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3766 ir_node **blk_sched = irg_data->blk_sched;
3768 parameter_dbg_info_t *infos;
3770 isa = (ia32_isa_t*) arch_env;
3772 ia32_register_binary_emitters();
3774 infos = construct_parameter_infos(irg);
3775 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3779 /* we use links to point to target blocks */
3780 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3781 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3783 /* initialize next block links */
3784 n = ARR_LEN(blk_sched);
3785 for (i = 0; i < n; ++i) {
3786 ir_node *block = blk_sched[i];
3787 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3789 set_irn_link(block, prev);
3792 for (i = 0; i < n; ++i) {
3793 ir_node *block = blk_sched[i];
3794 gen_binary_block(block);
3797 be_gas_emit_function_epilog(entity);
3799 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3803 void ia32_init_emitter(void)
3805 lc_opt_entry_t *be_grp;
3806 lc_opt_entry_t *ia32_grp;
3808 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3809 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3811 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3815 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");