2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
72 #include "ia32_emitter.h"
73 #include "ia32_common_transform.h"
74 #include "gen_ia32_emitter.h"
75 #include "gen_ia32_regalloc_if.h"
76 #include "ia32_nodes_attr.h"
77 #include "ia32_new_nodes.h"
78 #include "ia32_architecture.h"
79 #include "bearch_ia32_t.h"
81 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
83 static const ia32_isa_t *isa;
84 static char pic_base_label[128];
85 static ir_label_t exc_label_id;
86 static int mark_spill_reload = 0;
89 static bool sp_relative;
90 static int frame_type_size;
91 static int callframe_offset;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (get_Block_entity(block) != NULL)
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Add a number to a prefix. This number will not be used a second time.
143 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
145 static unsigned long id = 0;
146 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
151 * Emit the name of the 8bit low register
153 static void emit_8bit_register(const arch_register_t *reg)
155 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
156 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
159 be_emit_char(reg->name[1]); /* get the basic name of the register */
164 * Emit the name of the 8bit high register
166 static void emit_8bit_register_high(const arch_register_t *reg)
168 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
169 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
172 be_emit_char(reg->name[1]); /* get the basic name of the register */
176 static void emit_16bit_register(const arch_register_t *reg)
179 be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
183 * emit a register, possible shortened by a mode
185 * @param reg the register
186 * @param mode the mode of the register or NULL for full register
188 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
191 int size = get_mode_size_bits(mode);
193 case 8: emit_8bit_register(reg); return;
194 case 16: emit_16bit_register(reg); return;
196 assert(mode_is_float(mode) || size == 32);
200 be_emit_string(reg->name);
203 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
205 be_gas_emit_entity(entity);
207 if (get_entity_owner(entity) == get_tls_type()) {
208 if (!entity_has_definition(entity)) {
209 be_emit_cstring("@INDNTPOFF");
211 be_emit_cstring("@NTPOFF");
215 if (do_pic && !no_pic_adjust) {
217 be_emit_string(pic_base_label);
221 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
223 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
225 if (attr->symconst != NULL) {
228 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
230 if (attr->symconst == NULL || attr->offset != 0) {
231 if (attr->symconst != NULL) {
232 be_emit_irprintf("%+d", attr->offset);
234 be_emit_irprintf("0x%X", attr->offset);
239 static void emit_ia32_Immediate(const ir_node *node)
242 emit_ia32_Immediate_no_prefix(node);
245 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
247 assert(mode_is_int(mode) || mode_is_reference(mode));
248 switch (get_mode_size_bits(mode)) {
249 case 8: be_emit_char('b'); return;
250 case 16: be_emit_char('w'); return;
251 case 32: be_emit_char('l'); return;
252 /* gas docu says q is the suffix but gcc, objdump and icc use ll
254 case 64: be_emit_cstring("ll"); return;
256 panic("Can't output mode_suffix for %+F", mode);
259 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
263 /* we only need to emit the mode on address mode */
264 if (get_ia32_op_type(node) == ia32_Normal)
267 mode = get_ia32_ls_mode(node);
268 assert(mode != NULL);
270 if (mode_is_float(mode)) {
271 switch (get_mode_size_bits(mode)) {
272 case 32: be_emit_char('s'); return;
273 case 64: be_emit_char('l'); return;
274 /* long doubles have different sizes due to alignment on different
278 case 128: be_emit_char('t'); return;
281 assert(mode_is_int(mode) || mode_is_reference(mode));
282 switch (get_mode_size_bits(mode)) {
283 case 16: be_emit_char('s'); return;
284 case 32: be_emit_char('l'); return;
285 /* gas docu says q is the suffix but gcc, objdump and icc use ll
287 case 64: be_emit_cstring("ll"); return;
290 panic("Can't output mode_suffix for %+F", mode);
293 static char get_xmm_mode_suffix(ir_mode *mode)
295 assert(mode_is_float(mode));
296 switch (get_mode_size_bits(mode)) {
299 default: panic("Invalid XMM mode");
303 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
305 ir_mode *mode = get_ia32_ls_mode(node);
306 assert(mode != NULL);
307 be_emit_char(get_xmm_mode_suffix(mode));
311 * Returns the target block for a control flow node.
313 static ir_node *get_cfop_target_block(const ir_node *irn)
315 assert(get_irn_mode(irn) == mode_X);
316 return (ir_node*)get_irn_link(irn);
320 * Emits the target label for a control flow node.
322 static void ia32_emit_cfop_target(const ir_node *node)
324 ir_node *block = get_cfop_target_block(node);
325 be_gas_emit_block_name(block);
329 * Emit the suffix for a compare instruction.
331 static void ia32_emit_condition_code(ia32_condition_code_t cc)
334 case ia32_cc_overflow: be_emit_cstring("o"); return;
335 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
336 case ia32_cc_float_below:
337 case ia32_cc_float_unordered_below:
338 case ia32_cc_below: be_emit_cstring("b"); return;
339 case ia32_cc_float_above_equal:
340 case ia32_cc_float_unordered_above_equal:
341 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
342 case ia32_cc_float_equal:
343 case ia32_cc_equal: be_emit_cstring("e"); return;
344 case ia32_cc_float_not_equal:
345 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
346 case ia32_cc_float_below_equal:
347 case ia32_cc_float_unordered_below_equal:
348 case ia32_cc_below_equal: be_emit_cstring("be"); return;
349 case ia32_cc_float_above:
350 case ia32_cc_float_unordered_above:
351 case ia32_cc_above: be_emit_cstring("a"); return;
352 case ia32_cc_sign: be_emit_cstring("s"); return;
353 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
354 case ia32_cc_parity: be_emit_cstring("p"); return;
355 case ia32_cc_not_parity: be_emit_cstring("np"); return;
356 case ia32_cc_less: be_emit_cstring("l"); return;
357 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
358 case ia32_cc_less_equal: be_emit_cstring("le"); return;
359 case ia32_cc_greater: be_emit_cstring("g"); return;
360 case ia32_cc_float_parity_cases:
361 case ia32_cc_additional_float_cases:
364 panic("Invalid ia32 condition code");
367 typedef enum ia32_emit_mod_t {
369 EMIT_RESPECT_LS = 1U << 0,
370 EMIT_ALTERNATE_AM = 1U << 1,
372 EMIT_HIGH_REG = 1U << 3,
373 EMIT_LOW_REG = 1U << 4,
374 EMIT_16BIT_REG = 1U << 5
376 ENUM_BITSET(ia32_emit_mod_t)
379 * Emits address mode.
381 static void ia32_emit_am(ir_node const *const node)
383 ir_entity *ent = get_ia32_am_sc(node);
384 int offs = get_ia32_am_offs_int(node);
385 ir_node *base = get_irn_n(node, n_ia32_base);
386 int has_base = !is_ia32_NoReg_GP(base);
387 ir_node *idx = get_irn_n(node, n_ia32_index);
388 int has_index = !is_ia32_NoReg_GP(idx);
390 /* just to be sure... */
391 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
393 if (get_ia32_am_tls_segment(node))
394 be_emit_cstring("%gs:");
398 const ia32_attr_t *attr = get_ia32_attr_const(node);
399 if (is_ia32_am_sc_sign(node))
401 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
404 /* also handle special case if nothing is set */
405 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
407 be_emit_irprintf("%+d", offs);
409 be_emit_irprintf("%d", offs);
413 if (has_base || has_index) {
418 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
419 emit_register(reg, NULL);
422 /* emit index + scale */
424 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
427 emit_register(reg, NULL);
429 scale = get_ia32_am_scale(node);
431 be_emit_irprintf(",%d", 1 << scale);
438 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
440 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
447 const char *start = fmt;
448 ia32_emit_mod_t mod = EMIT_NONE;
450 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
453 be_emit_string_len(start, fmt - start);
458 be_emit_write_line();
472 case '*': mod |= EMIT_ALTERNATE_AM; break;
473 case '#': mod |= EMIT_RESPECT_LS; break;
474 case 'l': mod |= EMIT_LONG; break;
475 case '>': mod |= EMIT_HIGH_REG; break;
476 case '<': mod |= EMIT_LOW_REG; break;
477 case '^': mod |= EMIT_16BIT_REG; break;
486 arch_register_t const *reg;
496 if (get_ia32_op_type(node) == ia32_AddrModeS) {
499 assert(get_ia32_op_type(node) == ia32_Normal);
500 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
501 char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
502 be_emit_irprintf(fmt, attr->reg->name);
508 if (mod & EMIT_ALTERNATE_AM)
514 reg = va_arg(ap, const arch_register_t*);
515 if (get_ia32_op_type(node) == ia32_AddrModeS) {
522 if (get_ia32_op_type(node) == ia32_AddrModeS) {
526 assert(get_ia32_op_type(node) == ia32_Normal);
530 default: goto unknown;
536 imm = get_irn_n(node, n_ia32_binary_right);
537 if (is_ia32_Immediate(imm)) {
538 emit_ia32_Immediate(imm);
539 be_emit_cstring(", ");
540 if (get_ia32_op_type(node) == ia32_AddrModeS) {
543 assert(get_ia32_op_type(node) == ia32_Normal);
544 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
545 emit_register(reg, get_ia32_ls_mode(node));
548 if (get_ia32_op_type(node) == ia32_AddrModeS) {
551 assert(get_ia32_op_type(node) == ia32_Normal);
552 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
553 emit_register(reg, get_ia32_ls_mode(node));
555 be_emit_cstring(", ");
556 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
557 emit_register(reg, get_ia32_ls_mode(node));
562 if (*fmt < '0' || '9' < *fmt)
564 reg = arch_get_irn_register_out(node, *fmt++ - '0');
569 ia32_emit_x87_mode_suffix(node);
570 } else if (*fmt == 'P') {
571 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
574 } else if (*fmt == 'R') {
575 /* NOTE: Work around a gas quirk for non-commutative operations if the
576 * destination register is not %st0. In this case r/non-r is swapped.
577 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
578 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
579 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
580 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
581 * In fact this corresponds to the encoding of the instruction:
582 * - The r suffix selects whether %st0 is on the left (no r) or on the
583 * right (r) side of the executed operation.
584 * - The placement of %st0 selects whether the result is written to
585 * %st0 (right) or the other register (left).
586 * This means that it is sufficient to test whether the operands are
587 * permuted. In particular it is not necessary to consider wether the
588 * result is to be placed into the explicit register operand. */
589 if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
591 } else if (*fmt == 'X') {
592 ia32_emit_xmm_mode_suffix(node);
593 } else if (*fmt == '0') {
595 be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
605 if (!(mod & EMIT_ALTERNATE_AM))
607 emit_ia32_Immediate_no_prefix(imm);
611 ia32_emit_cfop_target(node);
615 ir_mode *mode = get_ia32_ls_mode(node);
618 if (mod & EMIT_RESPECT_LS) {
619 if (get_mode_size_bits(mode) == 32)
621 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
623 ia32_emit_mode_suffix_mode(mode);
628 ia32_condition_code_t cc;
631 cc = (ia32_condition_code_t)va_arg(ap, int);
632 } else if ('0' <= *fmt && *fmt <= '9') {
633 cc = get_ia32_condcode(node);
634 cc = determine_final_cc(node, *fmt - '0', cc);
639 ia32_emit_condition_code(cc);
644 reg = va_arg(ap, const arch_register_t*);
646 if (mod & EMIT_ALTERNATE_AM)
648 if (mod & EMIT_HIGH_REG) {
649 emit_8bit_register_high(reg);
650 } else if (mod & EMIT_LOW_REG) {
651 emit_8bit_register(reg);
652 } else if (mod & EMIT_16BIT_REG) {
653 emit_16bit_register(reg);
655 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
663 if (*fmt < '0' || '9' < *fmt)
667 imm = get_irn_n(node, pos);
668 if (is_ia32_Immediate(imm)) {
671 reg = arch_get_irn_register_in(node, pos);
677 const char *str = va_arg(ap, const char*);
683 if (mod & EMIT_LONG) {
684 unsigned long num = va_arg(ap, unsigned long);
685 be_emit_irprintf("%lu", num);
687 unsigned num = va_arg(ap, unsigned);
688 be_emit_irprintf("%u", num);
693 if (mod & EMIT_LONG) {
694 long num = va_arg(ap, long);
695 be_emit_irprintf("%ld", num);
697 int num = va_arg(ap, int);
698 be_emit_irprintf("%d", num);
704 panic("unknown format conversion");
708 be_emit_finish_line_gas(node);
712 static void emit_ia32_IMul(const ir_node *node)
714 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
715 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
717 /* do we need the 3-address form? */
718 if (is_ia32_NoReg_GP(left) ||
719 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
720 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
722 ia32_emitf(node, "imul%M %#AS4, %#S3");
727 * walks up a tree of copies/perms/spills/reloads to find the original value
728 * that is moved around
730 static ir_node *find_original_value(ir_node *node)
732 if (irn_visited(node))
735 mark_irn_visited(node);
736 if (be_is_Copy(node)) {
737 return find_original_value(be_get_Copy_op(node));
738 } else if (be_is_CopyKeep(node)) {
739 return find_original_value(be_get_CopyKeep_op(node));
740 } else if (is_Proj(node)) {
741 ir_node *pred = get_Proj_pred(node);
742 if (be_is_Perm(pred)) {
743 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
744 } else if (be_is_MemPerm(pred)) {
745 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
746 } else if (is_ia32_Load(pred)) {
747 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
748 } else if (is_ia32_Store(pred)) {
749 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
753 } else if (is_Phi(node)) {
755 arity = get_irn_arity(node);
756 for (i = 0; i < arity; ++i) {
757 ir_node *in = get_irn_n(node, i);
758 ir_node *res = find_original_value(in);
769 static ia32_condition_code_t determine_final_cc(const ir_node *node,
770 int flags_pos, ia32_condition_code_t cc)
772 ir_node *flags = get_irn_n(node, flags_pos);
773 const ia32_attr_t *flags_attr;
774 flags = skip_Proj(flags);
776 if (is_ia32_Sahf(flags)) {
777 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
778 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
779 inc_irg_visited(current_ir_graph);
780 cmp = find_original_value(cmp);
782 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
785 flags_attr = get_ia32_attr_const(cmp);
787 flags_attr = get_ia32_attr_const(flags);
790 if (flags_attr->data.ins_permuted)
791 cc = ia32_invert_condition_code(cc);
796 * Emits an exception label for a given node.
798 static void ia32_emit_exc_label(const ir_node *node)
800 be_emit_string(be_gas_insn_label_prefix());
801 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
805 * Returns the Proj with projection number proj and NOT mode_M
807 static ir_node *get_proj(const ir_node *node, long proj)
811 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
813 foreach_out_edge(node, edge) {
814 src = get_edge_src_irn(edge);
816 assert(is_Proj(src) && "Proj expected");
817 if (get_irn_mode(src) == mode_M)
820 if (get_Proj_proj(src) == proj)
826 static int can_be_fallthrough(const ir_node *node)
828 ir_node *target_block = get_cfop_target_block(node);
829 ir_node *block = get_nodes_block(node);
830 return get_prev_block_sched(target_block) == block;
834 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
836 static void emit_ia32_Jcc(const ir_node *node)
838 int need_parity_label = 0;
839 ia32_condition_code_t cc = get_ia32_condcode(node);
840 const ir_node *proj_true;
841 const ir_node *proj_false;
843 cc = determine_final_cc(node, 0, cc);
846 proj_true = get_proj(node, pn_ia32_Jcc_true);
847 assert(proj_true && "Jcc without true Proj");
849 proj_false = get_proj(node, pn_ia32_Jcc_false);
850 assert(proj_false && "Jcc without false Proj");
852 if (can_be_fallthrough(proj_true)) {
853 /* exchange both proj's so the second one can be omitted */
854 const ir_node *t = proj_true;
856 proj_true = proj_false;
858 cc = ia32_negate_condition_code(cc);
861 if (cc & ia32_cc_float_parity_cases) {
862 /* Some floating point comparisons require a test of the parity flag,
863 * which indicates that the result is unordered */
864 if (cc & ia32_cc_negated) {
865 ia32_emitf(proj_true, "jp %L");
867 /* we need a local label if the false proj is a fallthrough
868 * as the falseblock might have no label emitted then */
869 if (can_be_fallthrough(proj_false)) {
870 need_parity_label = 1;
871 ia32_emitf(proj_false, "jp 1f");
873 ia32_emitf(proj_false, "jp %L");
877 ia32_emitf(proj_true, "j%PX %L", (int)cc);
878 if (need_parity_label) {
879 be_emit_cstring("1:\n");
880 be_emit_write_line();
883 /* the second Proj might be a fallthrough */
884 if (can_be_fallthrough(proj_false)) {
885 if (be_options.verbose_asm)
886 ia32_emitf(proj_false, "/* fallthrough to %L */");
888 ia32_emitf(proj_false, "jmp %L");
893 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
896 static void emit_ia32_Setcc(const ir_node *node)
898 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
900 ia32_condition_code_t cc = get_ia32_condcode(node);
901 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
902 if (cc & ia32_cc_float_parity_cases) {
903 if (cc & ia32_cc_negated) {
904 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
905 ia32_emitf(node, "setp %>R", dreg);
906 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
908 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
909 ia32_emitf(node, "setnp %>R", dreg);
910 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
913 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
917 static void emit_ia32_CMovcc(const ir_node *node)
919 const ia32_attr_t *attr = get_ia32_attr_const(node);
920 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
921 ia32_condition_code_t cc = get_ia32_condcode(node);
922 const arch_register_t *in_true;
923 const arch_register_t *in_false;
925 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
926 /* although you can't set ins_permuted in the constructor it might still
927 * be set by memory operand folding
928 * Permuting inputs of a cmov means the condition is negated!
930 if (attr->data.ins_permuted)
931 cc = ia32_negate_condition_code(cc);
933 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
934 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
936 /* should be same constraint fullfilled? */
937 if (out == in_false) {
938 /* yes -> nothing to do */
939 } else if (out == in_true) {
940 const arch_register_t *tmp;
942 assert(get_ia32_op_type(node) == ia32_Normal);
944 cc = ia32_negate_condition_code(cc);
951 ia32_emitf(node, "movl %R, %R", in_false, out);
954 if (cc & ia32_cc_float_parity_cases) {
955 panic("CMov with floatingpoint compare/parity not supported yet");
958 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
962 * Emits code for a SwitchJmp
964 static void emit_ia32_SwitchJmp(const ir_node *node)
966 ir_entity *jump_table = get_ia32_am_sc(node);
967 const ir_switch_table *table = get_ia32_switch_table(node);
969 ia32_emitf(node, "jmp %*AM");
970 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
974 * Emits code for a unconditional jump.
976 static void emit_ia32_Jmp(const ir_node *node)
978 /* we have a block schedule */
979 if (can_be_fallthrough(node)) {
980 if (be_options.verbose_asm)
981 ia32_emitf(node, "/* fallthrough to %L */");
983 ia32_emitf(node, "jmp %L");
988 * Emit an inline assembler operand.
990 * @param node the ia32_ASM node
991 * @param s points to the operand (a %c)
993 * @return pointer to the first char in s NOT in the current operand
995 static const char* emit_asm_operand(const ir_node *node, const char *s)
997 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
998 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1000 const arch_register_t *reg;
1001 const ia32_asm_reg_t *asm_regs = attr->register_map;
1002 const ia32_asm_reg_t *asm_reg;
1011 /* parse modifiers */
1014 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1039 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1046 if (sscanf(s, "%d%n", &num, &p) != 1) {
1047 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1054 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1056 "Error: Custom assembler references invalid input/output (%+F)\n",
1060 asm_reg = & asm_regs[num];
1061 assert(asm_reg->valid);
1064 if (asm_reg->use_input == 0) {
1065 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1067 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1069 /* might be an immediate value */
1070 if (is_ia32_Immediate(pred)) {
1071 emit_ia32_Immediate(pred);
1074 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1078 "Warning: no register assigned for %d asm op (%+F)\n",
1083 if (asm_reg->memory) {
1088 if (modifier != 0) {
1091 emit_8bit_register(reg);
1094 emit_8bit_register_high(reg);
1097 emit_16bit_register(reg);
1100 panic("Invalid asm op modifier");
1103 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1106 if (asm_reg->memory) {
1114 * Emits code for an ASM pseudo op.
1116 static void emit_ia32_Asm(const ir_node *node)
1118 const void *gen_attr = get_irn_generic_attr_const(node);
1119 const ia32_asm_attr_t *attr
1120 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1121 ident *asm_text = attr->asm_text;
1122 const char *s = get_id_str(asm_text);
1124 be_emit_cstring("#APP\n");
1125 be_emit_write_line();
1132 s = emit_asm_operand(node, s);
1138 be_emit_cstring("\n#NO_APP\n");
1139 be_emit_write_line();
1144 * Emit movsb/w instructions to make mov count divideable by 4
1146 static void emit_CopyB_prolog(unsigned size)
1149 ia32_emitf(NULL, "movsb");
1151 ia32_emitf(NULL, "movsw");
1155 * Emit rep movsd instruction for memcopy.
1157 static void emit_ia32_CopyB(const ir_node *node)
1159 unsigned size = get_ia32_copyb_size(node);
1161 emit_CopyB_prolog(size);
1162 ia32_emitf(node, "rep movsd");
1166 * Emits unrolled memcopy.
1168 static void emit_ia32_CopyB_i(const ir_node *node)
1170 unsigned size = get_ia32_copyb_size(node);
1172 emit_CopyB_prolog(size);
1176 ia32_emitf(NULL, "movsd");
1182 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1184 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1187 ir_mode *ls_mode = get_ia32_ls_mode(node);
1188 int ls_bits = get_mode_size_bits(ls_mode);
1189 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1191 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1194 static void emit_ia32_Conv_I2FP(const ir_node *node)
1196 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1199 static void emit_ia32_Conv_FP2I(const ir_node *node)
1201 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1204 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1206 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1210 * Emits code to increase stack pointer.
1212 static void emit_be_IncSP(const ir_node *node)
1214 int offs = be_get_IncSP_offset(node);
1220 ia32_emitf(node, "subl $%u, %D0", offs);
1222 ia32_emitf(node, "addl $%u, %D0", -offs);
1227 * Emits code for Copy/CopyKeep.
1229 static void Copy_emitter(const ir_node *node, const ir_node *op)
1231 const arch_register_t *in = arch_get_irn_register(op);
1232 const arch_register_t *out = arch_get_irn_register(node);
1237 /* copies of fp nodes aren't real... */
1238 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
1241 ia32_emitf(node, "movl %R, %R", in, out);
1244 static void emit_be_Copy(const ir_node *node)
1246 Copy_emitter(node, be_get_Copy_op(node));
1249 static void emit_be_CopyKeep(const ir_node *node)
1251 Copy_emitter(node, be_get_CopyKeep_op(node));
1255 * Emits code for exchange.
1257 static void emit_be_Perm(const ir_node *node)
1259 const arch_register_t *in0, *in1;
1261 in0 = arch_get_irn_register(get_irn_n(node, 0));
1262 in1 = arch_get_irn_register(get_irn_n(node, 1));
1264 arch_register_class_t const *const cls0 = in0->reg_class;
1265 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
1267 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1268 ia32_emitf(node, "xchg %R, %R", in1, in0);
1269 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1270 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1271 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1272 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1273 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
1276 panic("unexpected register class in be_Perm (%+F)", node);
1280 /* helper function for emit_ia32_Minus64Bit */
1281 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1283 ia32_emitf(node, "movl %R, %R", src, dst);
1286 /* helper function for emit_ia32_Minus64Bit */
1287 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1289 ia32_emitf(node, "negl %R", reg);
1292 /* helper function for emit_ia32_Minus64Bit */
1293 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1295 ia32_emitf(node, "sbbl $0, %R", reg);
1298 /* helper function for emit_ia32_Minus64Bit */
1299 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1301 ia32_emitf(node, "sbbl %R, %R", src, dst);
1304 /* helper function for emit_ia32_Minus64Bit */
1305 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1307 ia32_emitf(node, "xchgl %R, %R", src, dst);
1310 /* helper function for emit_ia32_Minus64Bit */
1311 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1313 ia32_emitf(node, "xorl %R, %R", reg, reg);
1316 static void emit_ia32_Minus64Bit(const ir_node *node)
1318 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1319 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1320 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1321 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1323 if (out_lo == in_lo) {
1324 if (out_hi != in_hi) {
1325 /* a -> a, b -> d */
1328 /* a -> a, b -> b */
1331 } else if (out_lo == in_hi) {
1332 if (out_hi == in_lo) {
1333 /* a -> b, b -> a */
1334 emit_xchg(node, in_lo, in_hi);
1337 /* a -> b, b -> d */
1338 emit_mov(node, in_hi, out_hi);
1339 emit_mov(node, in_lo, out_lo);
1343 if (out_hi == in_lo) {
1344 /* a -> c, b -> a */
1345 emit_mov(node, in_lo, out_lo);
1347 } else if (out_hi == in_hi) {
1348 /* a -> c, b -> b */
1349 emit_mov(node, in_lo, out_lo);
1352 /* a -> c, b -> d */
1353 emit_mov(node, in_lo, out_lo);
1359 emit_neg( node, out_hi);
1360 emit_neg( node, out_lo);
1361 emit_sbb0(node, out_hi);
1365 emit_zero(node, out_hi);
1366 emit_neg( node, out_lo);
1367 emit_sbb( node, in_hi, out_hi);
1370 static void emit_ia32_GetEIP(const ir_node *node)
1372 ia32_emitf(node, "call %s", pic_base_label);
1373 be_emit_irprintf("%s:\n", pic_base_label);
1374 be_emit_write_line();
1375 ia32_emitf(node, "popl %D0");
1378 static void emit_ia32_ClimbFrame(const ir_node *node)
1380 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1382 ia32_emitf(node, "movl %S0, %D0");
1383 ia32_emitf(node, "movl $%u, %S1", attr->count);
1384 be_gas_emit_block_name(node);
1385 be_emit_cstring(":\n");
1386 be_emit_write_line();
1387 ia32_emitf(node, "movl (%D0), %D0");
1388 ia32_emitf(node, "dec %S1");
1389 be_emit_cstring("\tjnz ");
1390 be_gas_emit_block_name(node);
1391 be_emit_finish_line_gas(node);
1394 static void emit_be_Return(const ir_node *node)
1396 unsigned pop = be_Return_get_pop(node);
1398 if (pop > 0 || be_Return_get_emit_pop(node)) {
1399 ia32_emitf(node, "ret $%u", pop);
1401 ia32_emitf(node, "ret");
1405 static void emit_Nothing(const ir_node *node)
1412 * Enters the emitter functions for handled nodes into the generic
1413 * pointer of an opcode.
1415 static void ia32_register_emitters(void)
1417 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1418 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1419 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1420 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1421 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1423 /* first clear the generic function pointer for all ops */
1424 ir_clear_opcodes_generic_func();
1426 /* register all emitter functions defined in spec */
1427 ia32_register_spec_emitters();
1429 /* other ia32 emitter functions */
1432 IA32_EMIT(Conv_FP2FP);
1433 IA32_EMIT(Conv_FP2I);
1434 IA32_EMIT(Conv_I2FP);
1441 IA32_EMIT(Minus64Bit);
1442 IA32_EMIT(SwitchJmp);
1443 IA32_EMIT(ClimbFrame);
1446 /* benode emitter */
1465 typedef void (*emit_func_ptr) (const ir_node *);
1468 * Assign and emit an exception label if the current instruction can fail.
1470 static void ia32_assign_exc_label(ir_node *node)
1472 /* assign a new ID to the instruction */
1473 set_ia32_exc_label_id(node, ++exc_label_id);
1475 ia32_emit_exc_label(node);
1477 be_emit_pad_comment();
1478 be_emit_cstring("/* exception to Block ");
1479 ia32_emit_cfop_target(node);
1480 be_emit_cstring(" */\n");
1481 be_emit_write_line();
1485 * Emits code for a node.
1487 static void ia32_emit_node(ir_node *node)
1489 ir_op *op = get_irn_op(node);
1491 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1493 if (is_ia32_irn(node)) {
1494 if (get_ia32_exc_label(node)) {
1495 /* emit the exception label of this instruction */
1496 ia32_assign_exc_label(node);
1498 if (mark_spill_reload) {
1499 if (is_ia32_is_spill(node)) {
1500 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1502 if (is_ia32_is_reload(node)) {
1503 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1505 if (is_ia32_is_remat(node)) {
1506 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1510 if (op->ops.generic) {
1511 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1513 be_dwarf_location(get_irn_dbg_info(node));
1518 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1523 int sp_change = arch_get_sp_bias(node);
1524 if (sp_change != 0) {
1525 assert(sp_change != SP_BIAS_RESET);
1526 callframe_offset += sp_change;
1527 be_dwarf_callframe_offset(callframe_offset);
1533 * Emits gas alignment directives
1535 static void ia32_emit_alignment(unsigned align, unsigned skip)
1537 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1541 * Emits gas alignment directives for Labels depended on cpu architecture.
1543 static void ia32_emit_align_label(void)
1545 unsigned align = ia32_cg_config.label_alignment;
1546 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1547 ia32_emit_alignment(align, maximum_skip);
1551 * Test whether a block should be aligned.
1552 * For cpus in the P4/Athlon class it is useful to align jump labels to
1553 * 16 bytes. However we should only do that if the alignment nops before the
1554 * label aren't executed more often than we have jumps to the label.
1556 static int should_align_block(const ir_node *block)
1558 static const double DELTA = .0001;
1559 ir_node *prev = get_prev_block_sched(block);
1560 double prev_freq = 0; /**< execfreq of the fallthrough block */
1561 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1565 if (ia32_cg_config.label_alignment_factor <= 0)
1568 block_freq = get_block_execfreq(block);
1569 if (block_freq < DELTA)
1572 n_cfgpreds = get_Block_n_cfgpreds(block);
1573 for (i = 0; i < n_cfgpreds; ++i) {
1574 const ir_node *pred = get_Block_cfgpred_block(block, i);
1575 double pred_freq = get_block_execfreq(pred);
1578 prev_freq += pred_freq;
1580 jmp_freq += pred_freq;
1584 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1587 jmp_freq /= prev_freq;
1589 return jmp_freq > ia32_cg_config.label_alignment_factor;
1593 * Emit the block header for a block.
1595 * @param block the block
1596 * @param prev_block the previous block
1598 static void ia32_emit_block_header(ir_node *block)
1600 ir_graph *irg = current_ir_graph;
1601 int need_label = block_needs_label(block);
1603 if (block == get_irg_end_block(irg))
1606 if (ia32_cg_config.label_alignment > 0) {
1607 /* align the current block if:
1608 * a) if should be aligned due to its execution frequency
1609 * b) there is no fall-through here
1611 if (should_align_block(block)) {
1612 ia32_emit_align_label();
1614 /* if the predecessor block has no fall-through,
1615 we can always align the label. */
1617 int has_fallthrough = 0;
1619 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1620 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1621 if (can_be_fallthrough(cfg_pred)) {
1622 has_fallthrough = 1;
1627 if (!has_fallthrough)
1628 ia32_emit_align_label();
1632 be_gas_begin_block(block, need_label);
1636 * Walks over the nodes in a block connected by scheduling edges
1637 * and emits code for each node.
1639 static void ia32_gen_block(ir_node *block)
1641 ia32_emit_block_header(block);
1644 ir_graph *irg = get_irn_irg(block);
1645 callframe_offset = 4; /* 4 bytes for the return address */
1646 /* ESP guessing, TODO perform a real ESP simulation */
1647 if (block != get_irg_start_block(irg)) {
1648 callframe_offset += frame_type_size;
1650 be_dwarf_callframe_offset(callframe_offset);
1653 /* emit the contents of the block */
1654 be_dwarf_location(get_irn_dbg_info(block));
1655 sched_foreach(block, node) {
1656 ia32_emit_node(node);
1660 typedef struct exc_entry {
1661 ir_node *exc_instr; /** The instruction that can issue an exception. */
1662 ir_node *block; /** The block to call then. */
1667 * Sets labels for control flow nodes (jump target).
1668 * Links control predecessors to there destination blocks.
1670 static void ia32_gen_labels(ir_node *block, void *data)
1672 exc_entry **exc_list = (exc_entry**)data;
1676 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1677 pred = get_Block_cfgpred(block, n);
1678 set_irn_link(pred, block);
1680 pred = skip_Proj(pred);
1681 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1686 ARR_APP1(exc_entry, *exc_list, e);
1687 set_irn_link(pred, block);
1693 * Compare two exception_entries.
1695 static int cmp_exc_entry(const void *a, const void *b)
1697 const exc_entry *ea = (const exc_entry*)a;
1698 const exc_entry *eb = (const exc_entry*)b;
1700 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1705 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1707 ir_entity *entity = get_irg_entity(irg);
1708 ir_type *type = get_entity_type(entity);
1709 size_t n_params = get_method_n_params(type);
1710 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1711 ir_type *arg_type = layout->arg_type;
1712 size_t n_members = get_compound_n_members(arg_type);
1713 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1716 for (i = 0; i < n_members; ++i) {
1717 ir_entity *member = get_compound_member(arg_type, i);
1719 if (!is_parameter_entity(member))
1721 param = get_entity_parameter_number(member);
1722 if (param == IR_VA_START_PARAMETER_NUMBER)
1724 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1725 infos[param].reg = NULL;
1726 infos[param].entity = member;
1733 * Main driver. Emits the code for one routine.
1735 void ia32_gen_routine(ir_graph *irg)
1737 ir_entity *entity = get_irg_entity(irg);
1738 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1739 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1740 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1741 ir_node **blk_sched = irg_data->blk_sched;
1742 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1743 parameter_dbg_info_t *infos;
1746 isa = (ia32_isa_t*) arch_env;
1747 do_pic = be_options.pic;
1749 be_gas_elf_type_char = '@';
1751 ia32_register_emitters();
1753 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1755 infos = construct_parameter_infos(irg);
1756 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1760 sp_relative = layout->sp_relative;
1761 if (layout->sp_relative) {
1762 ir_type *frame_type = get_irg_frame_type(irg);
1763 frame_type_size = get_type_size_bytes(frame_type);
1764 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1766 /* well not entirely correct here, we should emit this after the
1767 * "movl esp, ebp" */
1768 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1769 /* TODO: do not hardcode the following */
1770 be_dwarf_callframe_offset(8);
1771 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1774 /* we use links to point to target blocks */
1775 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1776 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1778 /* initialize next block links */
1779 n = ARR_LEN(blk_sched);
1780 for (i = 0; i < n; ++i) {
1781 ir_node *block = blk_sched[i];
1782 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1784 set_irn_link(block, prev);
1787 for (i = 0; i < n; ++i) {
1788 ir_node *block = blk_sched[i];
1790 ia32_gen_block(block);
1793 be_gas_emit_function_epilog(entity);
1795 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1797 /* Sort the exception table using the exception label id's.
1798 Those are ascending with ascending addresses. */
1799 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1803 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1804 be_emit_cstring("\t.long ");
1805 ia32_emit_exc_label(exc_list[e].exc_instr);
1807 be_emit_cstring("\t.long ");
1808 be_gas_emit_block_name(exc_list[e].block);
1812 DEL_ARR_F(exc_list);
1815 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1816 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1820 /* ==== Experimental binary emitter ==== */
1822 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1823 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1824 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1826 static void build_reg_map(void)
1828 reg_gp_map[REG_GP_EAX] = 0x0;
1829 reg_gp_map[REG_GP_ECX] = 0x1;
1830 reg_gp_map[REG_GP_EDX] = 0x2;
1831 reg_gp_map[REG_GP_EBX] = 0x3;
1832 reg_gp_map[REG_GP_ESP] = 0x4;
1833 reg_gp_map[REG_GP_EBP] = 0x5;
1834 reg_gp_map[REG_GP_ESI] = 0x6;
1835 reg_gp_map[REG_GP_EDI] = 0x7;
1838 /** Returns the encoding for a pnc field. */
1839 static unsigned char pnc2cc(ia32_condition_code_t cc)
1844 /** Sign extension bit values for binops */
1846 UNSIGNED_IMM = 0, /**< unsigned immediate */
1847 SIGNEXT_IMM = 2, /**< sign extended immediate */
1850 /** The mod encoding of the ModR/M */
1852 MOD_IND = 0x00, /**< [reg1] */
1853 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1854 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1855 MOD_REG = 0xC0 /**< reg1 */
1858 /** create R/M encoding for ModR/M */
1859 #define ENC_RM(x) (x)
1860 /** create REG encoding for ModR/M */
1861 #define ENC_REG(x) ((x) << 3)
1863 /** create encoding for a SIB byte */
1864 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1866 /* Node: The following routines are supposed to append bytes, words, dwords
1867 to the output stream.
1868 Currently the implementation is stupid in that it still creates output
1869 for an "assembler" in the form of .byte, .long
1870 We will change this when enough infrastructure is there to create complete
1871 machine code in memory/object files */
1873 static void bemit8(const unsigned char byte)
1875 be_emit_irprintf("\t.byte 0x%x\n", byte);
1876 be_emit_write_line();
1879 static void bemit16(const unsigned short u16)
1881 be_emit_irprintf("\t.word 0x%x\n", u16);
1882 be_emit_write_line();
1885 static void bemit32(const unsigned u32)
1887 be_emit_irprintf("\t.long 0x%x\n", u32);
1888 be_emit_write_line();
1892 * Emit address of an entity. If @p is_relative is true then a relative
1893 * offset from behind the address to the entity is created.
1895 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1898 if (entity == NULL) {
1903 /* the final version should remember the position in the bytestream
1904 and patch it with the correct address at linktime... */
1905 be_emit_cstring("\t.long ");
1908 be_gas_emit_entity(entity);
1910 if (get_entity_owner(entity) == get_tls_type()) {
1911 if (!entity_has_definition(entity)) {
1912 be_emit_cstring("@INDNTPOFF");
1914 be_emit_cstring("@NTPOFF");
1919 be_emit_cstring("-.");
1924 be_emit_irprintf("%+d", offset);
1927 be_emit_write_line();
1930 static void bemit_jmp_destination(const ir_node *dest_block)
1932 be_emit_cstring("\t.long ");
1933 be_gas_emit_block_name(dest_block);
1934 be_emit_cstring(" - . - 4\n");
1935 be_emit_write_line();
1938 /* end emit routines, all emitters following here should only use the functions
1941 typedef enum reg_modifier {
1946 /** Create a ModR/M byte for src1,src2 registers */
1947 static void bemit_modrr(const arch_register_t *src1,
1948 const arch_register_t *src2)
1950 unsigned char modrm = MOD_REG;
1951 modrm |= ENC_RM(reg_gp_map[src1->index]);
1952 modrm |= ENC_REG(reg_gp_map[src2->index]);
1956 /** Create a ModR/M8 byte for src1,src2 registers */
1957 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1958 reg_modifier_t high_part2, const arch_register_t *src2)
1960 unsigned char modrm = MOD_REG;
1961 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1962 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1966 /** Create a ModR/M byte for one register and extension */
1967 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1969 unsigned char modrm = MOD_REG;
1971 modrm |= ENC_RM(reg_gp_map[reg->index]);
1972 modrm |= ENC_REG(ext);
1976 /** Create a ModR/M8 byte for one register */
1977 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1979 unsigned char modrm = MOD_REG;
1980 assert(reg_gp_map[reg->index] < 4);
1981 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1987 * Calculate the size of an signed immediate in bytes.
1989 * @param offset an offset
1991 static unsigned get_signed_imm_size(int offset)
1993 if (-128 <= offset && offset < 128) {
1995 } else if (-32768 <= offset && offset < 32768) {
2003 * Emit an address mode.
2005 * @param reg content of the reg field: either a register index or an opcode extension
2006 * @param node the node
2008 static void bemit_mod_am(unsigned reg, const ir_node *node)
2010 ir_entity *ent = get_ia32_am_sc(node);
2011 int offs = get_ia32_am_offs_int(node);
2012 ir_node *base = get_irn_n(node, n_ia32_base);
2013 int has_base = !is_ia32_NoReg_GP(base);
2014 ir_node *idx = get_irn_n(node, n_ia32_index);
2015 int has_index = !is_ia32_NoReg_GP(idx);
2018 unsigned emitoffs = 0;
2019 bool emitsib = false;
2022 /* set the mod part depending on displacement */
2024 modrm |= MOD_IND_WORD_OFS;
2026 } else if (offs == 0) {
2029 } else if (-128 <= offs && offs < 128) {
2030 modrm |= MOD_IND_BYTE_OFS;
2033 modrm |= MOD_IND_WORD_OFS;
2038 const arch_register_t *base_reg = arch_get_irn_register(base);
2039 base_enc = reg_gp_map[base_reg->index];
2041 /* Use the EBP encoding + MOD_IND if NO base register. There is
2042 * always a 32bit offset present in this case. */
2048 /* Determine if we need a SIB byte. */
2050 const arch_register_t *reg_index = arch_get_irn_register(idx);
2051 int scale = get_ia32_am_scale(node);
2053 /* R/M set to ESP means SIB in 32bit mode. */
2054 modrm |= ENC_RM(0x04);
2055 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2057 } else if (base_enc == 0x04) {
2058 /* for the above reason we are forced to emit a SIB when base is ESP.
2059 * Only the base is used, index must be ESP too, which means no index.
2061 modrm |= ENC_RM(0x04);
2062 sib = ENC_SIB(0, 0x04, 0x04);
2065 modrm |= ENC_RM(base_enc);
2068 /* We are forced to emit an 8bit offset as EBP base without offset is a
2069 * special case for SIB without base register. */
2070 if (base_enc == 0x05 && emitoffs == 0) {
2071 modrm |= MOD_IND_BYTE_OFS;
2075 modrm |= ENC_REG(reg);
2081 /* emit displacement */
2082 if (emitoffs == 8) {
2083 bemit8((unsigned) offs);
2084 } else if (emitoffs == 32) {
2085 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2090 * Emit a binop with a immediate operand.
2092 * @param node the node to emit
2093 * @param opcode_eax the opcode for the op eax, imm variant
2094 * @param opcode the opcode for the reg, imm variant
2095 * @param ruval the opcode extension for opcode
2097 static void bemit_binop_with_imm(
2098 const ir_node *node,
2099 unsigned char opcode_ax,
2100 unsigned char opcode, unsigned char ruval)
2102 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2103 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2104 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2107 /* Some instructions (test) have no short form with 32bit value + 8bit
2109 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2112 /* check for sign extension */
2113 size = get_signed_imm_size(attr->offset);
2118 bemit8(opcode | SIGNEXT_IMM);
2119 /* cmp has this special mode */
2120 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2121 bemit_mod_am(ruval, node);
2123 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2124 bemit_modru(reg, ruval);
2126 bemit8((unsigned char)attr->offset);
2130 /* check for eax variant: this variant is shorter for 32bit immediates only */
2131 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2133 bemit_mod_am(ruval, node);
2135 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2136 if (reg->index == REG_GP_EAX) {
2140 bemit_modru(reg, ruval);
2143 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2146 panic("invalid imm size?!?");
2152 static void bemit_binop_2(const ir_node *node, unsigned code)
2154 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2156 if (get_ia32_op_type(node) == ia32_Normal) {
2157 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2158 bemit_modrr(op2, out);
2160 bemit_mod_am(reg_gp_map[out->index], node);
2167 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2169 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2170 if (is_ia32_Immediate(right)) {
2171 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2173 bemit_binop_2(node, opcodes[0]);
2180 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2183 if (get_ia32_op_type(node) == ia32_Normal) {
2184 const arch_register_t *in = arch_get_irn_register_in(node, input);
2185 bemit_modru(in, ext);
2187 bemit_mod_am(ext, node);
2191 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2193 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2194 bemit_unop(node, code, reg_gp_map[out->index], input);
2197 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2199 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2202 bemit8(size == 8 ? code : code + 1);
2203 bemit_mod_am(ext, node);
2206 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2209 bemit_unop_reg(node, code, input);
2212 static void bemit_immediate(const ir_node *node, bool relative)
2214 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2215 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2218 static void bemit_copy(const ir_node *copy)
2220 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2221 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2225 /* copies of fp nodes aren't real... */
2226 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_fp])
2229 assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
2231 bemit_modrr(in, out);
2234 static void bemit_perm(const ir_node *node)
2236 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2237 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2238 const arch_register_class_t *cls0 = in0->reg_class;
2240 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
2242 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2243 if (in0->index == REG_GP_EAX) {
2244 bemit8(0x90 + reg_gp_map[in1->index]);
2245 } else if (in1->index == REG_GP_EAX) {
2246 bemit8(0x90 + reg_gp_map[in0->index]);
2249 bemit_modrr(in0, in1);
2251 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2252 panic("unimplemented"); // TODO implement
2253 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2254 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2255 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2256 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_fp]) {
2259 panic("unexpected register class in be_Perm (%+F)", node);
2263 static void bemit_xor0(const ir_node *node)
2265 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2267 bemit_modrr(out, out);
2270 static void bemit_mov_const(const ir_node *node)
2272 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2273 bemit8(0xB8 + reg_gp_map[out->index]);
2274 bemit_immediate(node, false);
2278 * Creates a function for a Binop with 3 possible encodings.
2280 #define BINOP(op, op0, op1, op2, op2_ext) \
2281 static void bemit_ ## op(const ir_node *node) { \
2282 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2283 bemit_binop(node, op ## _codes); \
2286 /* insn def eax,imm imm */
2287 BINOP(add, 0x03, 0x05, 0x81, 0)
2288 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2289 BINOP(adc, 0x13, 0x15, 0x81, 2)
2290 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2291 BINOP(and, 0x23, 0x25, 0x81, 4)
2292 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2293 BINOP(xor, 0x33, 0x35, 0x81, 6)
2294 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2296 #define BINOPMEM(op, ext) \
2297 static void bemit_##op(const ir_node *node) \
2300 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2303 val = get_irn_n(node, n_ia32_unary_op); \
2304 if (is_ia32_Immediate(val)) { \
2305 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2306 int offset = attr->offset; \
2307 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2309 bemit_mod_am(ext, node); \
2313 bemit_mod_am(ext, node); \
2317 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2321 bemit8(ext << 3 | 1); \
2322 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2326 static void bemit_##op##8bit(const ir_node *node) \
2328 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2329 if (is_ia32_Immediate(val)) { \
2331 bemit_mod_am(ext, node); \
2332 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2335 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2347 * Creates a function for an Unop with code /ext encoding.
2349 #define UNOP(op, code, ext, input) \
2350 static void bemit_ ## op(const ir_node *node) { \
2351 bemit_unop(node, code, ext, input); \
2354 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2355 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2356 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2357 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2358 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2359 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2361 /* TODO: am support for IJmp */
2362 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2364 #define SHIFT(op, ext) \
2365 static void bemit_##op(const ir_node *node) \
2367 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2368 ir_node *count = get_irn_n(node, 1); \
2369 if (is_ia32_Immediate(count)) { \
2370 int offset = get_ia32_immediate_attr_const(count)->offset; \
2371 if (offset == 1) { \
2373 bemit_modru(out, ext); \
2376 bemit_modru(out, ext); \
2381 bemit_modru(out, ext); \
2385 static void bemit_##op##mem(const ir_node *node) \
2388 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2391 count = get_irn_n(node, 1); \
2392 if (is_ia32_Immediate(count)) { \
2393 int offset = get_ia32_immediate_attr_const(count)->offset; \
2394 if (offset == 1) { \
2395 bemit8(size == 8 ? 0xD0 : 0xD1); \
2396 bemit_mod_am(ext, node); \
2398 bemit8(size == 8 ? 0xC0 : 0xC1); \
2399 bemit_mod_am(ext, node); \
2403 bemit8(size == 8 ? 0xD2 : 0xD3); \
2404 bemit_mod_am(ext, node); \
2414 static void bemit_shld(const ir_node *node)
2416 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2417 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2418 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2420 if (is_ia32_Immediate(count)) {
2422 bemit_modrr(out, in);
2423 bemit8(get_ia32_immediate_attr_const(count)->offset);
2426 bemit_modrr(out, in);
2430 static void bemit_shrd(const ir_node *node)
2432 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2433 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2434 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2436 if (is_ia32_Immediate(count)) {
2438 bemit_modrr(out, in);
2439 bemit8(get_ia32_immediate_attr_const(count)->offset);
2442 bemit_modrr(out, in);
2446 static void bemit_sbb0(ir_node const *const node)
2448 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2449 unsigned char const reg = reg_gp_map[out->index];
2451 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2455 * binary emitter for setcc.
2457 static void bemit_setcc(const ir_node *node)
2459 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2461 ia32_condition_code_t cc = get_ia32_condcode(node);
2462 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2463 if (cc & ia32_cc_float_parity_cases) {
2464 if (cc & ia32_cc_negated) {
2467 bemit8(0x90 | pnc2cc(cc));
2468 bemit_modrm8(REG_LOW, dreg);
2473 bemit_modrm8(REG_HIGH, dreg);
2475 /* orb %>dreg, %<dreg */
2477 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2481 bemit8(0x90 | pnc2cc(cc));
2482 bemit_modrm8(REG_LOW, dreg);
2487 bemit_modrm8(REG_HIGH, dreg);
2489 /* andb %>dreg, %<dreg */
2491 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2496 bemit8(0x90 | pnc2cc(cc));
2497 bemit_modrm8(REG_LOW, dreg);
2501 static void bemit_bsf(ir_node const *const node)
2503 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2506 static void bemit_bsr(ir_node const *const node)
2508 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2511 static void bemit_bswap(ir_node const *const node)
2514 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2517 static void bemit_bt(ir_node const *const node)
2520 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2521 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2522 if (is_ia32_Immediate(right)) {
2523 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2524 int const offset = attr->offset;
2525 assert(!attr->symconst);
2526 assert(get_signed_imm_size(offset) == 1);
2528 bemit_modru(lreg, 4);
2532 bemit_modrr(lreg, arch_get_irn_register(right));
2536 static void bemit_cmovcc(const ir_node *node)
2538 const ia32_attr_t *attr = get_ia32_attr_const(node);
2539 int ins_permuted = attr->data.ins_permuted;
2540 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2541 ia32_condition_code_t cc = get_ia32_condcode(node);
2542 const arch_register_t *in_true;
2543 const arch_register_t *in_false;
2545 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2547 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2548 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2550 /* should be same constraint fullfilled? */
2551 if (out == in_false) {
2552 /* yes -> nothing to do */
2553 } else if (out == in_true) {
2554 assert(get_ia32_op_type(node) == ia32_Normal);
2555 ins_permuted = !ins_permuted;
2559 bemit8(0x8B); // mov %in_false, %out
2560 bemit_modrr(in_false, out);
2564 cc = ia32_negate_condition_code(cc);
2566 if (cc & ia32_cc_float_parity_cases)
2567 panic("cmov can't handle parity float cases");
2570 bemit8(0x40 | pnc2cc(cc));
2571 if (get_ia32_op_type(node) == ia32_Normal) {
2572 bemit_modrr(in_true, out);
2574 bemit_mod_am(reg_gp_map[out->index], node);
2578 static void bemit_cmp(const ir_node *node)
2580 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2586 right = get_irn_n(node, n_ia32_binary_right);
2587 if (is_ia32_Immediate(right)) {
2588 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2589 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2590 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2593 if (attr->symconst != NULL) {
2596 /* check for sign extension */
2597 size = get_signed_imm_size(attr->offset);
2602 bemit8(0x81 | SIGNEXT_IMM);
2603 /* cmp has this special mode */
2604 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2605 bemit_mod_am(7, node);
2607 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2608 bemit_modru(reg, 7);
2610 bemit8((unsigned char)attr->offset);
2614 /* check for eax variant: this variant is shorter for 32bit immediates only */
2615 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2617 bemit_mod_am(7, node);
2619 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2620 if (reg->index == REG_GP_EAX) {
2624 bemit_modru(reg, 7);
2627 if (ls_size == 16) {
2628 bemit16(attr->offset);
2630 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2634 panic("invalid imm size?!?");
2636 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2638 if (get_ia32_op_type(node) == ia32_Normal) {
2639 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2640 bemit_modrr(op2, out);
2642 bemit_mod_am(reg_gp_map[out->index], node);
2647 static void bemit_cmp8bit(const ir_node *node)
2649 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2650 if (is_ia32_Immediate(right)) {
2651 if (get_ia32_op_type(node) == ia32_Normal) {
2652 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2653 if (out->index == REG_GP_EAX) {
2657 bemit_modru(out, 7);
2661 bemit_mod_am(7, node);
2663 bemit8(get_ia32_immediate_attr_const(right)->offset);
2665 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2667 if (get_ia32_op_type(node) == ia32_Normal) {
2668 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2669 bemit_modrr(out, in);
2671 bemit_mod_am(reg_gp_map[out->index], node);
2676 static void bemit_test8bit(const ir_node *node)
2678 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2679 if (is_ia32_Immediate(right)) {
2680 if (get_ia32_op_type(node) == ia32_Normal) {
2681 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2682 if (out->index == REG_GP_EAX) {
2686 bemit_modru(out, 0);
2690 bemit_mod_am(0, node);
2692 bemit8(get_ia32_immediate_attr_const(right)->offset);
2694 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2696 if (get_ia32_op_type(node) == ia32_Normal) {
2697 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2698 bemit_modrr(out, in);
2700 bemit_mod_am(reg_gp_map[out->index], node);
2705 static void bemit_imul(const ir_node *node)
2707 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2708 /* Do we need the immediate form? */
2709 if (is_ia32_Immediate(right)) {
2710 int imm = get_ia32_immediate_attr_const(right)->offset;
2711 if (get_signed_imm_size(imm) == 1) {
2712 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2715 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2719 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2723 static void bemit_dec(const ir_node *node)
2725 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2726 bemit8(0x48 + reg_gp_map[out->index]);
2729 static void bemit_inc(const ir_node *node)
2731 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2732 bemit8(0x40 + reg_gp_map[out->index]);
2735 #define UNOPMEM(op, code, ext) \
2736 static void bemit_##op(const ir_node *node) \
2738 bemit_unop_mem(node, code, ext); \
2741 UNOPMEM(notmem, 0xF6, 2)
2742 UNOPMEM(negmem, 0xF6, 3)
2743 UNOPMEM(incmem, 0xFE, 0)
2744 UNOPMEM(decmem, 0xFE, 1)
2746 static void bemit_ldtls(const ir_node *node)
2748 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2750 bemit8(0x65); // gs:
2751 if (out->index == REG_GP_EAX) {
2752 bemit8(0xA1); // movl 0, %eax
2754 bemit8(0x8B); // movl 0, %reg
2755 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2763 static void bemit_lea(const ir_node *node)
2765 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2767 bemit_mod_am(reg_gp_map[out->index], node);
2770 /* helper function for bemit_minus64bit */
2771 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2773 bemit8(0x8B); // movl %src, %dst
2774 bemit_modrr(src, dst);
2777 /* helper function for bemit_minus64bit */
2778 static void bemit_helper_neg(const arch_register_t *reg)
2780 bemit8(0xF7); // negl %reg
2781 bemit_modru(reg, 3);
2784 /* helper function for bemit_minus64bit */
2785 static void bemit_helper_sbb0(const arch_register_t *reg)
2787 bemit8(0x83); // sbbl $0, %reg
2788 bemit_modru(reg, 3);
2792 /* helper function for bemit_minus64bit */
2793 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2795 bemit8(0x1B); // sbbl %src, %dst
2796 bemit_modrr(src, dst);
2799 /* helper function for bemit_minus64bit */
2800 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2802 if (src->index == REG_GP_EAX) {
2803 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2804 } else if (dst->index == REG_GP_EAX) {
2805 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2807 bemit8(0x87); // xchgl %src, %dst
2808 bemit_modrr(src, dst);
2812 /* helper function for bemit_minus64bit */
2813 static void bemit_helper_zero(const arch_register_t *reg)
2815 bemit8(0x33); // xorl %reg, %reg
2816 bemit_modrr(reg, reg);
2819 static void bemit_minus64bit(const ir_node *node)
2821 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2822 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2823 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2824 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2826 if (out_lo == in_lo) {
2827 if (out_hi != in_hi) {
2828 /* a -> a, b -> d */
2831 /* a -> a, b -> b */
2834 } else if (out_lo == in_hi) {
2835 if (out_hi == in_lo) {
2836 /* a -> b, b -> a */
2837 bemit_helper_xchg(in_lo, in_hi);
2840 /* a -> b, b -> d */
2841 bemit_helper_mov(in_hi, out_hi);
2842 bemit_helper_mov(in_lo, out_lo);
2846 if (out_hi == in_lo) {
2847 /* a -> c, b -> a */
2848 bemit_helper_mov(in_lo, out_lo);
2850 } else if (out_hi == in_hi) {
2851 /* a -> c, b -> b */
2852 bemit_helper_mov(in_lo, out_lo);
2855 /* a -> c, b -> d */
2856 bemit_helper_mov(in_lo, out_lo);
2862 bemit_helper_neg( out_hi);
2863 bemit_helper_neg( out_lo);
2864 bemit_helper_sbb0(out_hi);
2868 bemit_helper_zero(out_hi);
2869 bemit_helper_neg( out_lo);
2870 bemit_helper_sbb( in_hi, out_hi);
2874 * Emit a single opcode.
2876 #define EMIT_SINGLEOP(op, code) \
2877 static void bemit_ ## op(const ir_node *node) { \
2882 //EMIT_SINGLEOP(daa, 0x27)
2883 //EMIT_SINGLEOP(das, 0x2F)
2884 //EMIT_SINGLEOP(aaa, 0x37)
2885 //EMIT_SINGLEOP(aas, 0x3F)
2886 //EMIT_SINGLEOP(nop, 0x90)
2887 EMIT_SINGLEOP(cwtl, 0x98)
2888 EMIT_SINGLEOP(cltd, 0x99)
2889 //EMIT_SINGLEOP(fwait, 0x9B)
2890 EMIT_SINGLEOP(sahf, 0x9E)
2891 //EMIT_SINGLEOP(popf, 0x9D)
2892 EMIT_SINGLEOP(leave, 0xC9)
2893 EMIT_SINGLEOP(int3, 0xCC)
2894 //EMIT_SINGLEOP(iret, 0xCF)
2895 //EMIT_SINGLEOP(xlat, 0xD7)
2896 //EMIT_SINGLEOP(lock, 0xF0)
2897 EMIT_SINGLEOP(rep, 0xF3)
2898 //EMIT_SINGLEOP(halt, 0xF4)
2899 EMIT_SINGLEOP(cmc, 0xF5)
2900 EMIT_SINGLEOP(stc, 0xF9)
2901 //EMIT_SINGLEOP(cli, 0xFA)
2902 //EMIT_SINGLEOP(sti, 0xFB)
2903 //EMIT_SINGLEOP(std, 0xFD)
2906 * Emits a MOV out, [MEM].
2908 static void bemit_load(const ir_node *node)
2910 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2912 if (out->index == REG_GP_EAX) {
2913 ir_node *base = get_irn_n(node, n_ia32_base);
2914 int has_base = !is_ia32_NoReg_GP(base);
2915 ir_node *idx = get_irn_n(node, n_ia32_index);
2916 int has_index = !is_ia32_NoReg_GP(idx);
2917 if (!has_base && !has_index) {
2918 ir_entity *ent = get_ia32_am_sc(node);
2919 int offs = get_ia32_am_offs_int(node);
2920 /* load from constant address to EAX can be encoded
2923 bemit_entity(ent, 0, offs, false);
2928 bemit_mod_am(reg_gp_map[out->index], node);
2932 * Emits a MOV [mem], in.
2934 static void bemit_store(const ir_node *node)
2936 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2937 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2939 if (is_ia32_Immediate(value)) {
2942 bemit_mod_am(0, node);
2943 bemit8(get_ia32_immediate_attr_const(value)->offset);
2944 } else if (size == 16) {
2947 bemit_mod_am(0, node);
2948 bemit16(get_ia32_immediate_attr_const(value)->offset);
2951 bemit_mod_am(0, node);
2952 bemit_immediate(value, false);
2955 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2957 if (in->index == REG_GP_EAX) {
2958 ir_node *base = get_irn_n(node, n_ia32_base);
2959 int has_base = !is_ia32_NoReg_GP(base);
2960 ir_node *idx = get_irn_n(node, n_ia32_index);
2961 int has_index = !is_ia32_NoReg_GP(idx);
2962 if (!has_base && !has_index) {
2963 ir_entity *ent = get_ia32_am_sc(node);
2964 int offs = get_ia32_am_offs_int(node);
2965 /* store to constant address from EAX can be encoded as
2966 * 0xA2/0xA3 [offset]*/
2974 bemit_entity(ent, 0, offs, false);
2986 bemit_mod_am(reg_gp_map[in->index], node);
2990 static void bemit_conv_i2i(const ir_node *node)
2995 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
2996 unsigned opcode = 0xB6;
2997 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
2998 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
2999 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3002 static void bemit_popcnt(ir_node const *const node)
3005 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
3011 static void bemit_push(const ir_node *node)
3013 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3015 if (is_ia32_Immediate(value)) {
3016 const ia32_immediate_attr_t *attr
3017 = get_ia32_immediate_attr_const(value);
3018 unsigned size = get_signed_imm_size(attr->offset);
3024 bemit8((unsigned char)attr->offset);
3029 bemit_immediate(value, false);
3032 } else if (is_ia32_NoReg_GP(value)) {
3034 bemit_mod_am(6, node);
3036 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3037 bemit8(0x50 + reg_gp_map[reg->index]);
3044 static void bemit_pop(const ir_node *node)
3046 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3047 bemit8(0x58 + reg_gp_map[reg->index]);
3050 static void bemit_popmem(const ir_node *node)
3053 bemit_mod_am(0, node);
3056 static void bemit_call(const ir_node *node)
3058 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3060 if (is_ia32_Immediate(proc)) {
3062 bemit_immediate(proc, true);
3064 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3068 static void bemit_jmp(const ir_node *dest_block)
3071 bemit_jmp_destination(dest_block);
3074 static void bemit_jump(const ir_node *node)
3076 if (can_be_fallthrough(node))
3079 bemit_jmp(get_cfop_target_block(node));
3082 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3084 unsigned char cc = pnc2cc(pnc);
3087 bemit_jmp_destination(dest_block);
3090 static void bemit_jp(bool odd, const ir_node *dest_block)
3094 bemit_jmp_destination(dest_block);
3097 static void bemit_ia32_jcc(const ir_node *node)
3099 ia32_condition_code_t cc = get_ia32_condcode(node);
3100 const ir_node *proj_true;
3101 const ir_node *proj_false;
3102 const ir_node *dest_true;
3103 const ir_node *dest_false;
3105 cc = determine_final_cc(node, 0, cc);
3107 /* get both Projs */
3108 proj_true = get_proj(node, pn_ia32_Jcc_true);
3109 assert(proj_true && "Jcc without true Proj");
3111 proj_false = get_proj(node, pn_ia32_Jcc_false);
3112 assert(proj_false && "Jcc without false Proj");
3114 if (can_be_fallthrough(proj_true)) {
3115 /* exchange both proj's so the second one can be omitted */
3116 const ir_node *t = proj_true;
3118 proj_true = proj_false;
3120 cc = ia32_negate_condition_code(cc);
3123 dest_true = get_cfop_target_block(proj_true);
3124 dest_false = get_cfop_target_block(proj_false);
3126 if (cc & ia32_cc_float_parity_cases) {
3127 /* Some floating point comparisons require a test of the parity flag,
3128 * which indicates that the result is unordered */
3129 if (cc & ia32_cc_negated) {
3130 bemit_jp(false, dest_true);
3132 /* we need a local label if the false proj is a fallthrough
3133 * as the falseblock might have no label emitted then */
3134 if (can_be_fallthrough(proj_false)) {
3136 bemit8(0x06); // jp + 6
3138 bemit_jp(false, dest_false);
3142 bemit_jcc(cc, dest_true);
3144 /* the second Proj might be a fallthrough */
3145 if (can_be_fallthrough(proj_false)) {
3146 /* it's a fallthrough */
3148 bemit_jmp(dest_false);
3152 static void bemit_switchjmp(const ir_node *node)
3154 ir_entity *jump_table = get_ia32_am_sc(node);
3155 const ir_switch_table *table = get_ia32_switch_table(node);
3157 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3158 bemit_mod_am(0x05, node);
3160 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3166 static void bemit_return(const ir_node *node)
3168 unsigned pop = be_Return_get_pop(node);
3169 if (pop > 0 || be_Return_get_emit_pop(node)) {
3171 assert(pop <= 0xffff);
3178 static void bemit_subsp(const ir_node *node)
3180 const arch_register_t *out;
3183 /* mov %esp, %out */
3185 out = arch_get_irn_register_out(node, 1);
3186 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3189 static void bemit_incsp(const ir_node *node)
3192 const arch_register_t *reg;
3196 offs = be_get_IncSP_offset(node);
3207 size = get_signed_imm_size(offs);
3208 bemit8(size == 1 ? 0x83 : 0x81);
3210 reg = arch_get_irn_register_out(node, 0);
3211 bemit_modru(reg, ext);
3220 static void bemit_copybi(const ir_node *node)
3222 unsigned size = get_ia32_copyb_size(node);
3224 bemit8(0xA4); // movsb
3227 bemit8(0xA5); // movsw
3231 bemit8(0xA5); // movsl
3235 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3237 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3238 unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
3239 if (get_ia32_op_type(node) == ia32_Normal) {
3240 assert(!attr->pop || attr->res_in_reg);
3242 unsigned char op0 = 0xD8;
3243 if (attr->res_in_reg) op0 |= 0x04;
3244 if (attr->pop) op0 |= 0x02;
3247 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
3252 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3253 bemit8(size == 32 ? 0xD8 : 0xDC);
3254 bemit_mod_am(op, node);
3258 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3261 bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
3264 static void bemit_fabs(const ir_node *node)
3272 static void bemit_fadd(const ir_node *node)
3274 bemit_fbinop(node, 0, 0);
3277 static void bemit_fchs(const ir_node *node)
3285 static void bemit_fdiv(const ir_node *node)
3287 bemit_fbinop(node, 6, 7);
3290 static void bemit_ffreep(ir_node const *const node)
3292 bemit_fop_reg(node, 0xDF, 0xC0);
3295 static void bemit_fild(const ir_node *node)
3297 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3299 bemit8(0xDF); // filds
3300 bemit_mod_am(0, node);
3304 bemit8(0xDB); // fildl
3305 bemit_mod_am(0, node);
3309 bemit8(0xDF); // fildll
3310 bemit_mod_am(5, node);
3314 panic("invalid mode size");
3318 static void bemit_fist(const ir_node *node)
3321 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3323 case 16: bemit8(0xDF); op = 2; break; // fist[p]s
3324 case 32: bemit8(0xDB); op = 2; break; // fist[p]l
3325 case 64: bemit8(0xDF); op = 6; break; // fistpll
3326 default: panic("invalid mode size");
3328 if (get_ia32_x87_attr_const(node)->pop)
3330 // There is only a pop variant for 64 bit integer store.
3331 assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
3332 bemit_mod_am(op, node);
3335 static void bemit_fisttp(ir_node const *const node)
3337 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3338 case 16: bemit8(0xDF); break; // fisttps
3339 case 32: bemit8(0xDB); break; // fisttpl
3340 case 64: bemit8(0xDD); break; // fisttpll
3341 default: panic("Invalid mode size");
3343 bemit_mod_am(1, node);
3346 static void bemit_fld(const ir_node *node)
3348 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3350 bemit8(0xD9); // flds
3351 bemit_mod_am(0, node);
3355 bemit8(0xDD); // fldl
3356 bemit_mod_am(0, node);
3361 bemit8(0xDB); // fldt
3362 bemit_mod_am(5, node);
3366 panic("invalid mode size");
3370 static void bemit_fld1(const ir_node *node)
3374 bemit8(0xE8); // fld1
3377 static void bemit_fldcw(const ir_node *node)
3379 bemit8(0xD9); // fldcw
3380 bemit_mod_am(5, node);
3383 static void bemit_fldz(const ir_node *node)
3387 bemit8(0xEE); // fldz
3390 static void bemit_fmul(const ir_node *node)
3392 bemit_fbinop(node, 1, 1);
3395 static void bemit_fpop(const ir_node *node)
3397 bemit_fop_reg(node, 0xDD, 0xD8);
3400 static void bemit_fpush(const ir_node *node)
3402 bemit_fop_reg(node, 0xD9, 0xC0);
3405 static void bemit_fpushcopy(const ir_node *node)
3407 bemit_fop_reg(node, 0xD9, 0xC0);
3410 static void bemit_fst(const ir_node *node)
3413 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3415 case 32: bemit8(0xD9); op = 2; break; // fst[p]s
3416 case 64: bemit8(0xDD); op = 2; break; // fst[p]l
3418 case 96: bemit8(0xDB); op = 6; break; // fstpt
3419 default: panic("invalid mode size");
3421 if (get_ia32_x87_attr_const(node)->pop)
3423 // There is only a pop variant for long double store.
3424 assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
3425 bemit_mod_am(op, node);
3428 static void bemit_fsub(const ir_node *node)
3430 bemit_fbinop(node, 4, 5);
3433 static void bemit_fnstcw(const ir_node *node)
3435 bemit8(0xD9); // fnstcw
3436 bemit_mod_am(7, node);
3439 static void bemit_fnstsw(void)
3441 bemit8(0xDF); // fnstsw %ax
3445 static void bemit_ftstfnstsw(const ir_node *node)
3449 bemit8(0xD9); // ftst
3454 static void bemit_fucomi(const ir_node *node)
3456 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3457 bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
3458 bemit8(0xE8 + attr->reg->index);
3461 static void bemit_fucomfnstsw(const ir_node *node)
3463 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3464 bemit8(0xDD); // fucom[p]
3465 bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
3469 static void bemit_fucomppfnstsw(const ir_node *node)
3473 bemit8(0xDA); // fucompp
3478 static void bemit_fxch(const ir_node *node)
3480 bemit_fop_reg(node, 0xD9, 0xC8);
3484 * The type of a emitter function.
3486 typedef void (*emit_func) (const ir_node *);
3489 * Set a node emitter. Make it a bit more type safe.
3491 static void register_emitter(ir_op *op, emit_func func)
3493 op->ops.generic = (op_func) func;
3496 static void ia32_register_binary_emitters(void)
3498 /* first clear the generic function pointer for all ops */
3499 ir_clear_opcodes_generic_func();
3501 /* benode emitter */
3502 register_emitter(op_be_Copy, bemit_copy);
3503 register_emitter(op_be_CopyKeep, bemit_copy);
3504 register_emitter(op_be_IncSP, bemit_incsp);
3505 register_emitter(op_be_Perm, bemit_perm);
3506 register_emitter(op_be_Return, bemit_return);
3507 register_emitter(op_ia32_Adc, bemit_adc);
3508 register_emitter(op_ia32_Add, bemit_add);
3509 register_emitter(op_ia32_AddMem, bemit_addmem);
3510 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3511 register_emitter(op_ia32_And, bemit_and);
3512 register_emitter(op_ia32_AndMem, bemit_andmem);
3513 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3514 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3515 register_emitter(op_ia32_Breakpoint, bemit_int3);
3516 register_emitter(op_ia32_Bsf, bemit_bsf);
3517 register_emitter(op_ia32_Bsr, bemit_bsr);
3518 register_emitter(op_ia32_Bswap, bemit_bswap);
3519 register_emitter(op_ia32_Bt, bemit_bt);
3520 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3521 register_emitter(op_ia32_Call, bemit_call);
3522 register_emitter(op_ia32_Cltd, bemit_cltd);
3523 register_emitter(op_ia32_Cmc, bemit_cmc);
3524 register_emitter(op_ia32_Cmp, bemit_cmp);
3525 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3526 register_emitter(op_ia32_Const, bemit_mov_const);
3527 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3528 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3529 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3530 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3531 register_emitter(op_ia32_Dec, bemit_dec);
3532 register_emitter(op_ia32_DecMem, bemit_decmem);
3533 register_emitter(op_ia32_Div, bemit_div);
3534 register_emitter(op_ia32_FldCW, bemit_fldcw);
3535 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3536 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3537 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3538 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3539 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3540 register_emitter(op_ia32_IDiv, bemit_idiv);
3541 register_emitter(op_ia32_IJmp, bemit_ijmp);
3542 register_emitter(op_ia32_IMul, bemit_imul);
3543 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3544 register_emitter(op_ia32_Inc, bemit_inc);
3545 register_emitter(op_ia32_IncMem, bemit_incmem);
3546 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3547 register_emitter(op_ia32_Jmp, bemit_jump);
3548 register_emitter(op_ia32_LdTls, bemit_ldtls);
3549 register_emitter(op_ia32_Lea, bemit_lea);
3550 register_emitter(op_ia32_Leave, bemit_leave);
3551 register_emitter(op_ia32_Load, bemit_load);
3552 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3553 register_emitter(op_ia32_Mul, bemit_mul);
3554 register_emitter(op_ia32_Neg, bemit_neg);
3555 register_emitter(op_ia32_NegMem, bemit_negmem);
3556 register_emitter(op_ia32_Not, bemit_not);
3557 register_emitter(op_ia32_NotMem, bemit_notmem);
3558 register_emitter(op_ia32_Or, bemit_or);
3559 register_emitter(op_ia32_OrMem, bemit_ormem);
3560 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3561 register_emitter(op_ia32_Pop, bemit_pop);
3562 register_emitter(op_ia32_PopEbp, bemit_pop);
3563 register_emitter(op_ia32_PopMem, bemit_popmem);
3564 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3565 register_emitter(op_ia32_Push, bemit_push);
3566 register_emitter(op_ia32_RepPrefix, bemit_rep);
3567 register_emitter(op_ia32_Rol, bemit_rol);
3568 register_emitter(op_ia32_RolMem, bemit_rolmem);
3569 register_emitter(op_ia32_Ror, bemit_ror);
3570 register_emitter(op_ia32_RorMem, bemit_rormem);
3571 register_emitter(op_ia32_Sahf, bemit_sahf);
3572 register_emitter(op_ia32_Sar, bemit_sar);
3573 register_emitter(op_ia32_SarMem, bemit_sarmem);
3574 register_emitter(op_ia32_Sbb, bemit_sbb);
3575 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3576 register_emitter(op_ia32_Setcc, bemit_setcc);
3577 register_emitter(op_ia32_Shl, bemit_shl);
3578 register_emitter(op_ia32_ShlD, bemit_shld);
3579 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3580 register_emitter(op_ia32_Shr, bemit_shr);
3581 register_emitter(op_ia32_ShrD, bemit_shrd);
3582 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3583 register_emitter(op_ia32_Stc, bemit_stc);
3584 register_emitter(op_ia32_Store, bemit_store);
3585 register_emitter(op_ia32_Store8Bit, bemit_store);
3586 register_emitter(op_ia32_Sub, bemit_sub);
3587 register_emitter(op_ia32_SubMem, bemit_submem);
3588 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3589 register_emitter(op_ia32_SubSP, bemit_subsp);
3590 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3591 register_emitter(op_ia32_Test, bemit_test);
3592 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3593 register_emitter(op_ia32_Xor, bemit_xor);
3594 register_emitter(op_ia32_Xor0, bemit_xor0);
3595 register_emitter(op_ia32_XorMem, bemit_xormem);
3596 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3597 register_emitter(op_ia32_fabs, bemit_fabs);
3598 register_emitter(op_ia32_fadd, bemit_fadd);
3599 register_emitter(op_ia32_fchs, bemit_fchs);
3600 register_emitter(op_ia32_fdiv, bemit_fdiv);
3601 register_emitter(op_ia32_ffreep, bemit_ffreep);
3602 register_emitter(op_ia32_fild, bemit_fild);
3603 register_emitter(op_ia32_fist, bemit_fist);
3604 register_emitter(op_ia32_fisttp, bemit_fisttp);
3605 register_emitter(op_ia32_fld, bemit_fld);
3606 register_emitter(op_ia32_fld1, bemit_fld1);
3607 register_emitter(op_ia32_fldz, bemit_fldz);
3608 register_emitter(op_ia32_fmul, bemit_fmul);
3609 register_emitter(op_ia32_fpop, bemit_fpop);
3610 register_emitter(op_ia32_fpush, bemit_fpush);
3611 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3612 register_emitter(op_ia32_fst, bemit_fst);
3613 register_emitter(op_ia32_fsub, bemit_fsub);
3614 register_emitter(op_ia32_fxch, bemit_fxch);
3616 /* ignore the following nodes */
3617 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3618 register_emitter(op_ia32_Unknown, emit_Nothing);
3619 register_emitter(op_be_Keep, emit_Nothing);
3620 register_emitter(op_be_Start, emit_Nothing);
3621 register_emitter(op_Phi, emit_Nothing);
3622 register_emitter(op_Start, emit_Nothing);
3625 static void gen_binary_block(ir_node *block)
3627 ia32_emit_block_header(block);
3629 /* emit the contents of the block */
3630 sched_foreach(block, node) {
3631 ia32_emit_node(node);
3635 void ia32_gen_binary_routine(ir_graph *irg)
3637 ir_entity *entity = get_irg_entity(irg);
3638 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3639 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3640 ir_node **blk_sched = irg_data->blk_sched;
3642 parameter_dbg_info_t *infos;
3644 isa = (ia32_isa_t*) arch_env;
3646 ia32_register_binary_emitters();
3648 infos = construct_parameter_infos(irg);
3649 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3653 /* we use links to point to target blocks */
3654 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3655 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3657 /* initialize next block links */
3658 n = ARR_LEN(blk_sched);
3659 for (i = 0; i < n; ++i) {
3660 ir_node *block = blk_sched[i];
3661 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3663 set_irn_link(block, prev);
3666 for (i = 0; i < n; ++i) {
3667 ir_node *block = blk_sched[i];
3668 gen_binary_block(block);
3671 be_gas_emit_function_epilog(entity);
3673 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3677 void ia32_init_emitter(void)
3679 lc_opt_entry_t *be_grp;
3680 lc_opt_entry_t *ia32_grp;
3682 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3683 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3685 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3689 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");