2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
76 static ir_label_t exc_label_id;
79 * Returns the register at in position pos.
81 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
84 const arch_register_t *reg = NULL;
86 assert(get_irn_arity(irn) > pos && "Invalid IN position");
88 /* The out register of the operator at position pos is the
89 in register we need. */
90 op = get_irn_n(irn, pos);
92 reg = arch_get_irn_register(arch_env, op);
94 assert(reg && "no in register found");
96 if(reg == &ia32_gp_regs[REG_GP_NOREG])
97 panic("trying to emit noreg for %+F input %d", irn, pos);
99 /* in case of unknown register: just return a valid register */
100 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
101 const arch_register_req_t *req;
103 /* ask for the requirements */
104 req = arch_get_register_req(arch_env, irn, pos);
106 if (arch_register_req_is(req, limited)) {
107 /* in case of limited requirements: get the first allowed register */
108 unsigned idx = rbitset_next(req->limited, 0, 1);
109 reg = arch_register_for_index(req->cls, idx);
111 /* otherwise get first register in class */
112 reg = arch_register_for_index(req->cls, 0);
120 * Returns the register at out position pos.
122 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
125 const arch_register_t *reg = NULL;
127 /* 1st case: irn is not of mode_T, so it has only */
128 /* one OUT register -> good */
129 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
130 /* Proj with the corresponding projnum for the register */
132 if (get_irn_mode(irn) != mode_T) {
134 reg = arch_get_irn_register(arch_env, irn);
135 } else if (is_ia32_irn(irn)) {
136 reg = get_ia32_out_reg(irn, pos);
138 const ir_edge_t *edge;
140 foreach_out_edge(irn, edge) {
141 proj = get_edge_src_irn(edge);
142 assert(is_Proj(proj) && "non-Proj from mode_T node");
143 if (get_Proj_proj(proj) == pos) {
144 reg = arch_get_irn_register(arch_env, proj);
150 assert(reg && "no out register found");
155 * Add a number to a prefix. This number will not be used a second time.
157 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
159 static unsigned long id = 0;
160 snprintf(buf, buflen, "%s%lu", prefix, ++id);
164 /*************************************************************
166 * (_) | | / _| | | | |
167 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
168 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
169 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
170 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
173 *************************************************************/
175 static void emit_8bit_register(const arch_register_t *reg)
177 const char *reg_name = arch_register_get_name(reg);
180 be_emit_char(reg_name[1]);
184 static void emit_16bit_register(const arch_register_t *reg)
186 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
189 be_emit_string(reg_name);
192 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
194 const char *reg_name;
197 int size = get_mode_size_bits(mode);
199 emit_8bit_register(reg);
201 } else if(size == 16) {
202 emit_16bit_register(reg);
205 assert(mode_is_float(mode) || size == 32);
209 reg_name = arch_register_get_name(reg);
212 be_emit_string(reg_name);
215 void ia32_emit_source_register(const ir_node *node, int pos)
217 const arch_register_t *reg = get_in_reg(node, pos);
219 emit_register(reg, NULL);
222 static void emit_ia32_Immediate(const ir_node *node);
224 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
226 const arch_register_t *reg;
227 ir_node *in = get_irn_n(node, pos);
228 if(is_ia32_Immediate(in)) {
229 emit_ia32_Immediate(in);
233 reg = get_in_reg(node, pos);
234 emit_8bit_register(reg);
237 void ia32_emit_dest_register(const ir_node *node, int pos)
239 const arch_register_t *reg = get_out_reg(node, pos);
241 emit_register(reg, NULL);
244 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
246 const arch_register_t *reg = get_out_reg(node, pos);
248 emit_register(reg, mode_Bu);
251 void ia32_emit_x87_register(const ir_node *node, int pos)
253 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
257 be_emit_string(attr->x87[pos]->name);
260 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
262 if(mode_is_float(mode)) {
263 switch(get_mode_size_bits(mode)) {
264 case 32: be_emit_char('s'); return;
265 case 64: be_emit_char('l'); return;
267 case 96: be_emit_char('t'); return;
270 assert(mode_is_int(mode) || mode_is_reference(mode));
271 switch(get_mode_size_bits(mode)) {
272 case 64: be_emit_cstring("ll"); return;
273 /* gas docu says q is the suffix but gcc, objdump and icc use
275 case 32: be_emit_char('l'); return;
276 case 16: be_emit_char('w'); return;
277 case 8: be_emit_char('b'); return;
280 panic("Can't output mode_suffix for %+F\n", mode);
283 void ia32_emit_mode_suffix(const ir_node *node)
285 ir_mode *mode = get_ia32_ls_mode(node);
289 ia32_emit_mode_suffix_mode(mode);
292 void ia32_emit_x87_mode_suffix(const ir_node *node)
294 ir_mode *mode = get_ia32_ls_mode(node);
295 assert(mode != NULL);
296 /* we only need to emit the mode on address mode */
297 if(get_ia32_op_type(node) != ia32_Normal)
298 ia32_emit_mode_suffix_mode(mode);
301 static char get_xmm_mode_suffix(ir_mode *mode)
303 assert(mode_is_float(mode));
304 switch(get_mode_size_bits(mode)) {
315 void ia32_emit_xmm_mode_suffix(const ir_node *node)
317 ir_mode *mode = get_ia32_ls_mode(node);
318 assert(mode != NULL);
320 be_emit_char(get_xmm_mode_suffix(mode));
323 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
325 ir_mode *mode = get_ia32_ls_mode(node);
326 assert(mode != NULL);
327 be_emit_char(get_xmm_mode_suffix(mode));
330 void ia32_emit_extend_suffix(const ir_mode *mode)
332 if(get_mode_size_bits(mode) == 32)
334 if(mode_is_signed(mode)) {
341 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
343 ir_node *in = get_irn_n(node, pos);
344 if(is_ia32_Immediate(in)) {
345 emit_ia32_Immediate(in);
347 const ir_mode *mode = get_ia32_ls_mode(node);
348 const arch_register_t *reg = get_in_reg(node, pos);
349 emit_register(reg, mode);
354 * Emits registers and/or address mode of a binary operation.
356 void ia32_emit_binop(const ir_node *node) {
357 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
358 const ir_mode *mode = get_ia32_ls_mode(node);
359 const arch_register_t *reg_left;
361 switch(get_ia32_op_type(node)) {
363 reg_left = get_in_reg(node, n_ia32_binary_left);
364 if(is_ia32_Immediate(right_op)) {
365 emit_ia32_Immediate(right_op);
366 be_emit_cstring(", ");
367 emit_register(reg_left, mode);
370 const arch_register_t *reg_right
371 = get_in_reg(node, n_ia32_binary_right);
372 emit_register(reg_right, mode);
373 be_emit_cstring(", ");
374 emit_register(reg_left, mode);
378 if(is_ia32_Immediate(right_op)) {
379 emit_ia32_Immediate(right_op);
380 be_emit_cstring(", ");
383 reg_left = get_in_reg(node, n_ia32_binary_left);
385 be_emit_cstring(", ");
386 emit_register(reg_left, mode);
390 panic("DestMode can't be output by %%binop anymore");
393 assert(0 && "unsupported op type");
398 * Emits registers and/or address mode of a binary operation.
400 void ia32_emit_x87_binop(const ir_node *node) {
401 switch(get_ia32_op_type(node)) {
404 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
405 const arch_register_t *in1 = x87_attr->x87[0];
406 const arch_register_t *in2 = x87_attr->x87[1];
407 const arch_register_t *out = x87_attr->x87[2];
408 const arch_register_t *in;
410 in = out ? ((out == in2) ? in1 : in2) : in2;
411 out = out ? out : in1;
414 be_emit_string(arch_register_get_name(in));
415 be_emit_cstring(", %");
416 be_emit_string(arch_register_get_name(out));
424 assert(0 && "unsupported op type");
429 * Emits registers and/or address mode of a unary operation.
431 void ia32_emit_unop(const ir_node *node, int pos) {
434 switch(get_ia32_op_type(node)) {
436 op = get_irn_n(node, pos);
437 if (is_ia32_Immediate(op)) {
438 emit_ia32_Immediate(op);
440 ia32_emit_source_register(node, pos);
448 assert(0 && "unsupported op type");
452 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
456 set_entity_backend_marked(entity, 1);
457 id = get_entity_ld_ident(entity);
460 if (get_entity_owner(entity) == get_tls_type()) {
461 if (get_entity_visibility(entity) == visibility_external_allocated) {
462 be_emit_cstring("@INDNTPOFF");
464 be_emit_cstring("@NTPOFF");
468 if (!no_pic_adjust && do_pic) {
469 /* TODO: only do this when necessary */
471 be_emit_string(pic_base_label);
476 * Emits address mode.
478 void ia32_emit_am(const ir_node *node) {
479 ir_entity *ent = get_ia32_am_sc(node);
480 int offs = get_ia32_am_offs_int(node);
481 ir_node *base = get_irn_n(node, 0);
482 int has_base = !is_ia32_NoReg_GP(base);
483 ir_node *index = get_irn_n(node, 1);
484 int has_index = !is_ia32_NoReg_GP(index);
486 /* just to be sure... */
487 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
491 if (is_ia32_am_sc_sign(node))
493 ia32_emit_entity(ent, 0);
498 be_emit_irprintf("%+d", offs);
500 be_emit_irprintf("%d", offs);
504 if (has_base || has_index) {
509 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
510 emit_register(reg, NULL);
513 /* emit index + scale */
515 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
518 emit_register(reg, NULL);
520 scale = get_ia32_am_scale(node);
522 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
528 /* special case if nothing is set */
529 if(ent == NULL && offs == 0 && !has_base && !has_index) {
534 static void emit_ia32_IMul(const ir_node *node)
536 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
537 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
539 be_emit_cstring("\timul");
540 ia32_emit_mode_suffix(node);
543 ia32_emit_binop(node);
545 /* do we need the 3-address form? */
546 if(is_ia32_NoReg_GP(left) ||
547 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
548 be_emit_cstring(", ");
549 emit_register(out_reg, get_ia32_ls_mode(node));
551 be_emit_finish_line_gas(node);
554 /*************************************************
557 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
558 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
559 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
560 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
562 *************************************************/
565 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
568 * coding of conditions
570 struct cmp2conditon_t {
576 * positive conditions for signed compares
578 static const struct cmp2conditon_t cmp2condition_s[] = {
579 { NULL, pn_Cmp_False }, /* always false */
580 { "e", pn_Cmp_Eq }, /* == */
581 { "l", pn_Cmp_Lt }, /* < */
582 { "le", pn_Cmp_Le }, /* <= */
583 { "g", pn_Cmp_Gt }, /* > */
584 { "ge", pn_Cmp_Ge }, /* >= */
585 { "ne", pn_Cmp_Lg }, /* != */
586 { NULL, pn_Cmp_Leg}, /* always true */
590 * positive conditions for unsigned compares
592 static const struct cmp2conditon_t cmp2condition_u[] = {
593 { NULL, pn_Cmp_False }, /* always false */
594 { "e", pn_Cmp_Eq }, /* == */
595 { "b", pn_Cmp_Lt }, /* < */
596 { "be", pn_Cmp_Le }, /* <= */
597 { "a", pn_Cmp_Gt }, /* > */
598 { "ae", pn_Cmp_Ge }, /* >= */
599 { "ne", pn_Cmp_Lg }, /* != */
600 { NULL, pn_Cmp_Leg }, /* always true */
604 * walks up a tree of copies/perms/spills/reloads to find the original value
605 * that is moved around
607 static ir_node *find_original_value(ir_node *node)
609 inc_irg_visited(current_ir_graph);
611 mark_irn_visited(node);
612 if(be_is_Copy(node)) {
613 node = be_get_Copy_op(node);
614 } else if(be_is_CopyKeep(node)) {
615 node = be_get_CopyKeep_op(node);
616 } else if(is_Proj(node)) {
617 ir_node *pred = get_Proj_pred(node);
618 if(be_is_Perm(pred)) {
619 node = get_irn_n(pred, get_Proj_proj(node));
620 } else if(be_is_MemPerm(pred)) {
621 node = get_irn_n(pred, get_Proj_proj(node) + 1);
622 } else if(is_ia32_Load(pred)) {
623 node = get_irn_n(pred, n_ia32_Load_mem);
627 } else if(is_ia32_Store(node)) {
628 node = get_irn_n(node, n_ia32_Store_val);
629 } else if(is_Phi(node)) {
631 arity = get_irn_arity(node);
632 for(i = 0; i < arity; ++i) {
633 ir_node *in = get_irn_n(node, i);
646 static int determine_final_pnc(const ir_node *node, int flags_pos,
649 ir_node *flags = get_irn_n(node, flags_pos);
650 const ia32_attr_t *flags_attr;
651 flags = skip_Proj(flags);
653 if(is_ia32_Sahf(flags)) {
654 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
655 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
656 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
657 cmp = find_original_value(cmp);
658 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
659 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
662 flags_attr = get_ia32_attr_const(cmp);
663 if(flags_attr->data.ins_permuted)
664 pnc = get_mirrored_pnc(pnc);
665 pnc |= ia32_pn_Cmp_float;
666 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
667 || is_ia32_Fucompi(flags)) {
668 flags_attr = get_ia32_attr_const(flags);
670 if(flags_attr->data.ins_permuted)
671 pnc = get_mirrored_pnc(pnc);
672 pnc |= ia32_pn_Cmp_float;
675 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
676 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
678 flags_attr = get_ia32_attr_const(flags);
680 if(flags_attr->data.ins_permuted)
681 pnc = get_mirrored_pnc(pnc);
682 if(flags_attr->data.cmp_unsigned)
683 pnc |= ia32_pn_Cmp_unsigned;
689 static void ia32_emit_cmp_suffix(int pnc)
693 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
695 assert(cmp2condition_u[pnc].num == pnc);
696 str = cmp2condition_u[pnc].name;
699 assert(cmp2condition_s[pnc].num == pnc);
700 str = cmp2condition_s[pnc].name;
706 void ia32_emit_cmp_suffix_node(const ir_node *node,
709 const ia32_attr_t *attr = get_ia32_attr_const(node);
711 pn_Cmp pnc = get_ia32_condcode(node);
713 pnc = determine_final_pnc(node, flags_pos, pnc);
714 if(attr->data.ins_permuted) {
715 if(pnc & ia32_pn_Cmp_float) {
716 pnc = get_negated_pnc(pnc, mode_F);
718 pnc = get_negated_pnc(pnc, mode_Iu);
722 ia32_emit_cmp_suffix(pnc);
726 * Returns the target block for a control flow node.
728 static ir_node *get_cfop_target_block(const ir_node *irn) {
729 return get_irn_link(irn);
733 * Emits a block label for the given block.
735 static void ia32_emit_block_name(const ir_node *block)
737 if (has_Block_label(block)) {
738 be_emit_string(be_gas_block_label_prefix());
739 be_emit_irprintf("%lu", get_Block_label(block));
741 be_emit_cstring(BLOCK_PREFIX);
742 be_emit_irprintf("%ld", get_irn_node_nr(block));
747 * Emits an exception label for a given node.
749 static void ia32_emit_exc_label(const ir_node *node)
751 be_emit_string(be_gas_insn_label_prefix());
752 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
756 * Emits the target label for a control flow node.
758 static void ia32_emit_cfop_target(const ir_node *node)
760 ir_node *block = get_cfop_target_block(node);
762 ia32_emit_block_name(block);
765 /** Return the next block in Block schedule */
766 static ir_node *next_blk_sched(const ir_node *block)
768 return get_irn_link(block);
772 * Returns the Proj with projection number proj and NOT mode_M
774 static ir_node *get_proj(const ir_node *node, long proj) {
775 const ir_edge_t *edge;
778 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
780 foreach_out_edge(node, edge) {
781 src = get_edge_src_irn(edge);
783 assert(is_Proj(src) && "Proj expected");
784 if (get_irn_mode(src) == mode_M)
787 if (get_Proj_proj(src) == proj)
794 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
796 static void emit_ia32_Jcc(const ir_node *node)
798 int need_parity_label = 0;
799 const ir_node *proj_true;
800 const ir_node *proj_false;
801 const ir_node *block;
802 const ir_node *next_block;
803 pn_Cmp pnc = get_ia32_condcode(node);
805 pnc = determine_final_pnc(node, 0, pnc);
808 proj_true = get_proj(node, pn_ia32_Jcc_true);
809 assert(proj_true && "Jcc without true Proj");
811 proj_false = get_proj(node, pn_ia32_Jcc_false);
812 assert(proj_false && "Jcc without false Proj");
814 block = get_nodes_block(node);
815 next_block = next_blk_sched(block);
817 if (get_cfop_target_block(proj_true) == next_block) {
818 /* exchange both proj's so the second one can be omitted */
819 const ir_node *t = proj_true;
821 proj_true = proj_false;
823 if(pnc & ia32_pn_Cmp_float) {
824 pnc = get_negated_pnc(pnc, mode_F);
826 pnc = get_negated_pnc(pnc, mode_Iu);
830 if (pnc & ia32_pn_Cmp_float) {
831 /* Some floating point comparisons require a test of the parity flag,
832 * which indicates that the result is unordered */
835 be_emit_cstring("\tjp ");
836 ia32_emit_cfop_target(proj_true);
837 be_emit_finish_line_gas(proj_true);
842 be_emit_cstring("\tjnp ");
843 ia32_emit_cfop_target(proj_true);
844 be_emit_finish_line_gas(proj_true);
850 /* we need a local label if the false proj is a fallthrough
851 * as the falseblock might have no label emitted then */
852 if (get_cfop_target_block(proj_false) == next_block) {
853 need_parity_label = 1;
854 be_emit_cstring("\tjp 1f");
856 be_emit_cstring("\tjp ");
857 ia32_emit_cfop_target(proj_false);
859 be_emit_finish_line_gas(proj_false);
865 be_emit_cstring("\tjp ");
866 ia32_emit_cfop_target(proj_true);
867 be_emit_finish_line_gas(proj_true);
875 be_emit_cstring("\tj");
876 ia32_emit_cmp_suffix(pnc);
878 ia32_emit_cfop_target(proj_true);
879 be_emit_finish_line_gas(proj_true);
882 if(need_parity_label) {
883 be_emit_cstring("1:");
884 be_emit_write_line();
887 /* the second Proj might be a fallthrough */
888 if (get_cfop_target_block(proj_false) != next_block) {
889 be_emit_cstring("\tjmp ");
890 ia32_emit_cfop_target(proj_false);
891 be_emit_finish_line_gas(proj_false);
893 be_emit_cstring("\t/* fallthrough to ");
894 ia32_emit_cfop_target(proj_false);
895 be_emit_cstring(" */");
896 be_emit_finish_line_gas(proj_false);
900 static void emit_ia32_CMov(const ir_node *node)
902 const ia32_attr_t *attr = get_ia32_attr_const(node);
903 int ins_permuted = attr->data.ins_permuted;
904 const arch_register_t *out = arch_get_irn_register(arch_env, node);
905 pn_Cmp pnc = get_ia32_condcode(node);
906 const arch_register_t *in_true;
907 const arch_register_t *in_false;
909 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
911 in_true = arch_get_irn_register(arch_env,
912 get_irn_n(node, n_ia32_CMov_val_true));
913 in_false = arch_get_irn_register(arch_env,
914 get_irn_n(node, n_ia32_CMov_val_false));
916 /* should be same constraint fullfilled? */
917 if(out == in_false) {
918 /* yes -> nothing to do */
919 } else if(out == in_true) {
920 const arch_register_t *tmp;
922 assert(get_ia32_op_type(node) == ia32_Normal);
924 ins_permuted = !ins_permuted;
931 be_emit_cstring("\tmovl ");
932 emit_register(in_false, NULL);
933 be_emit_cstring(", ");
934 emit_register(out, NULL);
935 be_emit_finish_line_gas(node);
939 if(pnc & ia32_pn_Cmp_float) {
940 pnc = get_negated_pnc(pnc, mode_F);
942 pnc = get_negated_pnc(pnc, mode_Iu);
946 /* TODO: handling of Nans isn't correct yet */
948 be_emit_cstring("\tcmov");
949 ia32_emit_cmp_suffix(pnc);
951 if(get_ia32_op_type(node) == ia32_AddrModeS) {
954 emit_register(in_true, get_ia32_ls_mode(node));
956 be_emit_cstring(", ");
957 emit_register(out, get_ia32_ls_mode(node));
958 be_emit_finish_line_gas(node);
961 /*********************************************************
964 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
965 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
966 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
967 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
970 *********************************************************/
972 /* jump table entry (target and corresponding number) */
973 typedef struct _branch_t {
978 /* jump table for switch generation */
979 typedef struct _jmp_tbl_t {
980 ir_node *defProj; /**< default target */
981 long min_value; /**< smallest switch case */
982 long max_value; /**< largest switch case */
983 long num_branches; /**< number of jumps */
984 char *label; /**< label of the jump table */
985 branch_t *branches; /**< jump array */
989 * Compare two variables of type branch_t. Used to sort all switch cases
991 static int ia32_cmp_branch_t(const void *a, const void *b) {
992 branch_t *b1 = (branch_t *)a;
993 branch_t *b2 = (branch_t *)b;
995 if (b1->value <= b2->value)
1002 * Emits code for a SwitchJmp (creates a jump table if
1003 * possible otherwise a cmp-jmp cascade). Port from
1006 static void emit_ia32_SwitchJmp(const ir_node *node)
1008 unsigned long interval;
1014 const ir_edge_t *edge;
1016 /* fill the table structure */
1017 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1018 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1020 tbl.num_branches = get_irn_n_edges(node) - 1;
1021 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1022 tbl.min_value = INT_MAX;
1023 tbl.max_value = INT_MIN;
1025 default_pn = get_ia32_condcode(node);
1027 /* go over all proj's and collect them */
1028 foreach_out_edge(node, edge) {
1029 proj = get_edge_src_irn(edge);
1030 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1032 pnc = get_Proj_proj(proj);
1034 /* check for default proj */
1035 if (pnc == default_pn) {
1036 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1039 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1040 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1042 /* create branch entry */
1043 tbl.branches[i].target = proj;
1044 tbl.branches[i].value = pnc;
1049 assert(i == tbl.num_branches);
1051 /* sort the branches by their number */
1052 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1054 /* two-complement's magic make this work without overflow */
1055 interval = tbl.max_value - tbl.min_value;
1057 /* emit the table */
1058 be_emit_cstring("\tcmpl $");
1059 be_emit_irprintf("%u, ", interval);
1060 ia32_emit_source_register(node, 0);
1061 be_emit_finish_line_gas(node);
1063 be_emit_cstring("\tja ");
1064 ia32_emit_cfop_target(tbl.defProj);
1065 be_emit_finish_line_gas(node);
1067 if (tbl.num_branches > 1) {
1069 be_emit_cstring("\tjmp *");
1070 be_emit_string(tbl.label);
1071 be_emit_cstring("(,");
1072 ia32_emit_source_register(node, 0);
1073 be_emit_cstring(",4)");
1074 be_emit_finish_line_gas(node);
1076 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1077 be_emit_cstring("\t.align 4\n");
1078 be_emit_write_line();
1080 be_emit_string(tbl.label);
1081 be_emit_cstring(":\n");
1082 be_emit_write_line();
1084 be_emit_cstring(".long ");
1085 ia32_emit_cfop_target(tbl.branches[0].target);
1086 be_emit_finish_line_gas(NULL);
1088 last_value = tbl.branches[0].value;
1089 for (i = 1; i < tbl.num_branches; ++i) {
1090 while (++last_value < tbl.branches[i].value) {
1091 be_emit_cstring(".long ");
1092 ia32_emit_cfop_target(tbl.defProj);
1093 be_emit_finish_line_gas(NULL);
1095 be_emit_cstring(".long ");
1096 ia32_emit_cfop_target(tbl.branches[i].target);
1097 be_emit_finish_line_gas(NULL);
1099 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1101 /* one jump is enough */
1102 be_emit_cstring("\tjmp ");
1103 ia32_emit_cfop_target(tbl.branches[0].target);
1104 be_emit_finish_line_gas(node);
1114 * Emits code for a unconditional jump.
1116 static void emit_Jmp(const ir_node *node)
1118 ir_node *block, *next_block;
1120 /* for now, the code works for scheduled and non-schedules blocks */
1121 block = get_nodes_block(node);
1123 /* we have a block schedule */
1124 next_block = next_blk_sched(block);
1125 if (get_cfop_target_block(node) != next_block) {
1126 be_emit_cstring("\tjmp ");
1127 ia32_emit_cfop_target(node);
1129 be_emit_cstring("\t/* fallthrough to ");
1130 ia32_emit_cfop_target(node);
1131 be_emit_cstring(" */");
1133 be_emit_finish_line_gas(node);
1136 static void emit_ia32_Immediate(const ir_node *node)
1138 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1141 if(attr->symconst != NULL) {
1144 ia32_emit_entity(attr->symconst, 0);
1146 if(attr->symconst == NULL || attr->offset != 0) {
1147 if(attr->symconst != NULL) {
1148 be_emit_irprintf("%+d", attr->offset);
1150 be_emit_irprintf("0x%X", attr->offset);
1156 * Emit an inline assembler operand.
1158 * @param node the ia32_ASM node
1159 * @param s points to the operand (a %c)
1161 * @return pointer to the first char in s NOT in the current operand
1163 static const char* emit_asm_operand(const ir_node *node, const char *s)
1165 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1166 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1168 const arch_register_t *reg;
1169 const ia32_asm_reg_t *asm_regs = attr->register_map;
1170 const ia32_asm_reg_t *asm_reg;
1171 const char *reg_name;
1180 /* parse modifiers */
1183 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1207 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1208 "'%c' for asm op\n", node, c);
1214 sscanf(s, "%d%n", &num, &p);
1216 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1223 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1224 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1225 "input/output (%+F)\n", node);
1228 asm_reg = & asm_regs[num];
1229 assert(asm_reg->valid);
1232 if(asm_reg->use_input == 0) {
1233 reg = get_out_reg(node, asm_reg->inout_pos);
1235 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1237 /* might be an immediate value */
1238 if(is_ia32_Immediate(pred)) {
1239 emit_ia32_Immediate(pred);
1242 reg = get_in_reg(node, asm_reg->inout_pos);
1245 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1246 "(%+F)\n", num, node);
1250 if(asm_reg->memory) {
1259 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1262 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1265 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1268 panic("Invalid asm op modifier");
1270 be_emit_string(reg_name);
1272 emit_register(reg, asm_reg->mode);
1275 if(asm_reg->memory) {
1283 * Emits code for an ASM pseudo op.
1285 static void emit_ia32_Asm(const ir_node *node)
1287 const void *gen_attr = get_irn_generic_attr_const(node);
1288 const ia32_asm_attr_t *attr
1289 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1290 ident *asm_text = attr->asm_text;
1291 const char *s = get_id_str(asm_text);
1293 be_emit_cstring("# Begin ASM \t");
1294 be_emit_finish_line_gas(node);
1301 s = emit_asm_operand(node, s);
1310 be_emit_write_line();
1312 be_emit_cstring("# End ASM\n");
1313 be_emit_write_line();
1316 /**********************************
1319 * | | ___ _ __ _ _| |_) |
1320 * | | / _ \| '_ \| | | | _ <
1321 * | |___| (_) | |_) | |_| | |_) |
1322 * \_____\___/| .__/ \__, |____/
1325 **********************************/
1328 * Emit movsb/w instructions to make mov count divideable by 4
1330 static void emit_CopyB_prolog(unsigned size) {
1331 be_emit_cstring("\tcld");
1332 be_emit_finish_line_gas(NULL);
1336 be_emit_cstring("\tmovsb");
1337 be_emit_finish_line_gas(NULL);
1340 be_emit_cstring("\tmovsw");
1341 be_emit_finish_line_gas(NULL);
1344 be_emit_cstring("\tmovsb");
1345 be_emit_finish_line_gas(NULL);
1346 be_emit_cstring("\tmovsw");
1347 be_emit_finish_line_gas(NULL);
1353 * Emit rep movsd instruction for memcopy.
1355 static void emit_ia32_CopyB(const ir_node *node)
1357 unsigned size = get_ia32_copyb_size(node);
1359 emit_CopyB_prolog(size);
1361 be_emit_cstring("\trep movsd");
1362 be_emit_finish_line_gas(node);
1366 * Emits unrolled memcopy.
1368 static void emit_ia32_CopyB_i(const ir_node *node)
1370 unsigned size = get_ia32_copyb_size(node);
1372 emit_CopyB_prolog(size & 0x3);
1376 be_emit_cstring("\tmovsd");
1377 be_emit_finish_line_gas(NULL);
1383 /***************************
1387 * | | / _ \| '_ \ \ / /
1388 * | |___| (_) | | | \ V /
1389 * \_____\___/|_| |_|\_/
1391 ***************************/
1394 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1396 static void emit_ia32_Conv_with_FP(const ir_node *node)
1398 ir_mode *ls_mode = get_ia32_ls_mode(node);
1399 int ls_bits = get_mode_size_bits(ls_mode);
1401 be_emit_cstring("\tcvt");
1403 if(is_ia32_Conv_I2FP(node)) {
1405 be_emit_cstring("si2ss");
1407 be_emit_cstring("si2sd");
1409 } else if(is_ia32_Conv_FP2I(node)) {
1411 be_emit_cstring("ss2si");
1413 be_emit_cstring("sd2si");
1416 assert(is_ia32_Conv_FP2FP(node));
1418 be_emit_cstring("sd2ss");
1420 be_emit_cstring("ss2sd");
1425 switch(get_ia32_op_type(node)) {
1427 ia32_emit_source_register(node, n_ia32_unary_op);
1429 case ia32_AddrModeS:
1433 assert(0 && "unsupported op type for Conv");
1435 be_emit_cstring(", ");
1436 ia32_emit_dest_register(node, 0);
1437 be_emit_finish_line_gas(node);
1440 static void emit_ia32_Conv_I2FP(const ir_node *node)
1442 emit_ia32_Conv_with_FP(node);
1445 static void emit_ia32_Conv_FP2I(const ir_node *node)
1447 emit_ia32_Conv_with_FP(node);
1450 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1452 emit_ia32_Conv_with_FP(node);
1456 * Emits code for an Int conversion.
1458 static void emit_ia32_Conv_I2I(const ir_node *node)
1460 const char *sign_suffix;
1461 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1462 int smaller_bits = get_mode_size_bits(smaller_mode);
1464 const arch_register_t *in_reg, *out_reg;
1466 assert(!mode_is_float(smaller_mode));
1467 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1469 signed_mode = mode_is_signed(smaller_mode);
1470 if(smaller_bits == 32) {
1471 // this should not happen as it's no convert
1475 sign_suffix = signed_mode ? "s" : "z";
1478 out_reg = get_out_reg(node, 0);
1480 switch(get_ia32_op_type(node)) {
1482 in_reg = get_in_reg(node, n_ia32_unary_op);
1484 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1485 out_reg == &ia32_gp_regs[REG_EAX] &&
1489 /* argument and result are both in EAX and */
1490 /* signedness is ok: -> use the smaller cwtl opcode */
1491 be_emit_cstring("\tcwtl");
1493 be_emit_cstring("\tmov");
1494 be_emit_string(sign_suffix);
1495 ia32_emit_mode_suffix_mode(smaller_mode);
1496 be_emit_cstring("l ");
1497 emit_register(in_reg, smaller_mode);
1498 be_emit_cstring(", ");
1499 emit_register(out_reg, NULL);
1502 case ia32_AddrModeS: {
1503 be_emit_cstring("\tmov");
1504 be_emit_string(sign_suffix);
1505 ia32_emit_mode_suffix_mode(smaller_mode);
1506 be_emit_cstring("l ");
1508 be_emit_cstring(", ");
1509 emit_register(out_reg, NULL);
1513 assert(0 && "unsupported op type for Conv");
1515 be_emit_finish_line_gas(node);
1519 /*******************************************
1522 * | |__ ___ _ __ ___ __| | ___ ___
1523 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1524 * | |_) | __/ | | | (_) | (_| | __/\__ \
1525 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1527 *******************************************/
1530 * Emits a backend call
1532 static void emit_be_Call(const ir_node *node)
1534 ir_entity *ent = be_Call_get_entity(node);
1536 be_emit_cstring("\tcall ");
1538 ia32_emit_entity(ent, 1);
1540 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1542 emit_register(reg, NULL);
1544 be_emit_finish_line_gas(node);
1548 * Emits code to increase stack pointer.
1550 static void emit_be_IncSP(const ir_node *node)
1552 int offs = be_get_IncSP_offset(node);
1553 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1559 be_emit_cstring("\tsubl $");
1560 be_emit_irprintf("%u, ", offs);
1561 emit_register(reg, NULL);
1563 be_emit_cstring("\taddl $");
1564 be_emit_irprintf("%u, ", -offs);
1565 emit_register(reg, NULL);
1567 be_emit_finish_line_gas(node);
1571 * Emits code for Copy/CopyKeep.
1573 static void Copy_emitter(const ir_node *node, const ir_node *op)
1575 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1576 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1582 if(is_unknown_reg(in))
1584 /* copies of vf nodes aren't real... */
1585 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1588 mode = get_irn_mode(node);
1589 if (mode == mode_E) {
1590 be_emit_cstring("\tmovsd ");
1591 emit_register(in, NULL);
1592 be_emit_cstring(", ");
1593 emit_register(out, NULL);
1595 be_emit_cstring("\tmovl ");
1596 emit_register(in, NULL);
1597 be_emit_cstring(", ");
1598 emit_register(out, NULL);
1600 be_emit_finish_line_gas(node);
1603 static void emit_be_Copy(const ir_node *node)
1605 Copy_emitter(node, be_get_Copy_op(node));
1608 static void emit_be_CopyKeep(const ir_node *node)
1610 Copy_emitter(node, be_get_CopyKeep_op(node));
1614 * Emits code for exchange.
1616 static void emit_be_Perm(const ir_node *node)
1618 const arch_register_t *in0, *in1;
1619 const arch_register_class_t *cls0, *cls1;
1621 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1622 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1624 cls0 = arch_register_get_class(in0);
1625 cls1 = arch_register_get_class(in1);
1627 assert(cls0 == cls1 && "Register class mismatch at Perm");
1629 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1630 be_emit_cstring("\txchg ");
1631 emit_register(in1, NULL);
1632 be_emit_cstring(", ");
1633 emit_register(in0, NULL);
1634 be_emit_finish_line_gas(node);
1635 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1636 be_emit_cstring("\txorpd ");
1637 emit_register(in1, NULL);
1638 be_emit_cstring(", ");
1639 emit_register(in0, NULL);
1640 be_emit_finish_line_gas(NULL);
1642 be_emit_cstring("\txorpd ");
1643 emit_register(in0, NULL);
1644 be_emit_cstring(", ");
1645 emit_register(in1, NULL);
1646 be_emit_finish_line_gas(NULL);
1648 be_emit_cstring("\txorpd ");
1649 emit_register(in1, NULL);
1650 be_emit_cstring(", ");
1651 emit_register(in0, NULL);
1652 be_emit_finish_line_gas(node);
1653 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1655 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1658 panic("unexpected register class in be_Perm (%+F)\n", node);
1663 * Emits code for Constant loading.
1665 static void emit_ia32_Const(const ir_node *node)
1667 be_emit_cstring("\tmovl ");
1668 emit_ia32_Immediate(node);
1669 be_emit_cstring(", ");
1670 ia32_emit_dest_register(node, 0);
1672 be_emit_finish_line_gas(node);
1676 * Emits code to load the TLS base
1678 static void emit_ia32_LdTls(const ir_node *node)
1680 be_emit_cstring("\tmovl %gs:0, ");
1681 ia32_emit_dest_register(node, 0);
1682 be_emit_finish_line_gas(node);
1685 /* helper function for emit_ia32_Minus64Bit */
1686 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1688 be_emit_cstring("\tmovl ");
1689 emit_register(src, NULL);
1690 be_emit_cstring(", ");
1691 emit_register(dst, NULL);
1692 be_emit_finish_line_gas(node);
1695 /* helper function for emit_ia32_Minus64Bit */
1696 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1698 be_emit_cstring("\tnegl ");
1699 emit_register(reg, NULL);
1700 be_emit_finish_line_gas(node);
1703 /* helper function for emit_ia32_Minus64Bit */
1704 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1706 be_emit_cstring("\tsbbl $0, ");
1707 emit_register(reg, NULL);
1708 be_emit_finish_line_gas(node);
1711 /* helper function for emit_ia32_Minus64Bit */
1712 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1714 be_emit_cstring("\tsbbl ");
1715 emit_register(src, NULL);
1716 be_emit_cstring(", ");
1717 emit_register(dst, NULL);
1718 be_emit_finish_line_gas(node);
1721 /* helper function for emit_ia32_Minus64Bit */
1722 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1724 be_emit_cstring("\txchgl ");
1725 emit_register(src, NULL);
1726 be_emit_cstring(", ");
1727 emit_register(dst, NULL);
1728 be_emit_finish_line_gas(node);
1731 /* helper function for emit_ia32_Minus64Bit */
1732 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1734 be_emit_cstring("\txorl ");
1735 emit_register(reg, NULL);
1736 be_emit_cstring(", ");
1737 emit_register(reg, NULL);
1738 be_emit_finish_line_gas(node);
1741 static void emit_ia32_Minus64Bit(const ir_node *node)
1743 const arch_register_t *in_lo = get_in_reg(node, 0);
1744 const arch_register_t *in_hi = get_in_reg(node, 1);
1745 const arch_register_t *out_lo = get_out_reg(node, 0);
1746 const arch_register_t *out_hi = get_out_reg(node, 1);
1748 if (out_lo == in_lo) {
1749 if (out_hi != in_hi) {
1750 /* a -> a, b -> d */
1753 /* a -> a, b -> b */
1756 } else if (out_lo == in_hi) {
1757 if (out_hi == in_lo) {
1758 /* a -> b, b -> a */
1759 emit_xchg(node, in_lo, in_hi);
1762 /* a -> b, b -> d */
1763 emit_mov(node, in_hi, out_hi);
1764 emit_mov(node, in_lo, out_lo);
1768 if (out_hi == in_lo) {
1769 /* a -> c, b -> a */
1770 emit_mov(node, in_lo, out_lo);
1772 } else if (out_hi == in_hi) {
1773 /* a -> c, b -> b */
1774 emit_mov(node, in_lo, out_lo);
1777 /* a -> c, b -> d */
1778 emit_mov(node, in_lo, out_lo);
1784 emit_neg( node, out_hi);
1785 emit_neg( node, out_lo);
1786 emit_sbb0(node, out_hi);
1790 emit_zero(node, out_hi);
1791 emit_neg( node, out_lo);
1792 emit_sbb( node, in_hi, out_hi);
1795 static void emit_ia32_GetEIP(const ir_node *node)
1797 be_emit_cstring("\tcall ");
1798 be_emit_string(pic_base_label);
1799 be_emit_finish_line_gas(node);
1801 be_emit_string(pic_base_label);
1802 be_emit_cstring(":\n");
1803 be_emit_write_line();
1805 be_emit_cstring("\tpopl ");
1806 ia32_emit_dest_register(node, 0);
1808 be_emit_write_line();
1811 static void emit_be_Return(const ir_node *node)
1814 be_emit_cstring("\tret");
1816 pop = be_Return_get_pop(node);
1817 if (pop > 0 || be_Return_get_emit_pop(node)) {
1818 be_emit_irprintf(" $%d", pop);
1820 be_emit_finish_line_gas(node);
1823 static void emit_Nothing(const ir_node *node)
1829 /***********************************************************************************
1832 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1833 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1834 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1835 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1837 ***********************************************************************************/
1840 * Enters the emitter functions for handled nodes into the generic
1841 * pointer of an opcode.
1843 static void ia32_register_emitters(void) {
1845 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1846 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1847 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1848 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1849 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1850 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1852 /* first clear the generic function pointer for all ops */
1853 clear_irp_opcodes_generic_func();
1855 /* register all emitter functions defined in spec */
1856 ia32_register_spec_emitters();
1858 /* other ia32 emitter functions */
1862 IA32_EMIT(SwitchJmp);
1865 IA32_EMIT(Conv_I2FP);
1866 IA32_EMIT(Conv_FP2I);
1867 IA32_EMIT(Conv_FP2FP);
1868 IA32_EMIT(Conv_I2I);
1869 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1872 IA32_EMIT(Minus64Bit);
1876 /* benode emitter */
1901 typedef void (*emit_func_ptr) (const ir_node *);
1904 * Emits code for a node.
1906 static void ia32_emit_node(ir_node *node)
1908 ir_op *op = get_irn_op(node);
1910 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1912 if (is_ia32_irn(node) && get_ia32_exc_label(node)) {
1913 /* emit the exception label of this instruction */
1914 ia32_assign_exc_label(node);
1916 if (op->ops.generic) {
1917 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1919 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1924 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1930 * Emits gas alignment directives
1932 static void ia32_emit_alignment(unsigned align, unsigned skip)
1934 be_emit_cstring("\t.p2align ");
1935 be_emit_irprintf("%u,,%u\n", align, skip);
1936 be_emit_write_line();
1940 * Emits gas alignment directives for Labels depended on cpu architecture.
1942 static void ia32_emit_align_label(void)
1944 unsigned align = ia32_cg_config.label_alignment;
1945 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1946 ia32_emit_alignment(align, maximum_skip);
1950 * Test whether a block should be aligned.
1951 * For cpus in the P4/Athlon class it is useful to align jump labels to
1952 * 16 bytes. However we should only do that if the alignment nops before the
1953 * label aren't executed more often than we have jumps to the label.
1955 static int should_align_block(ir_node *block, ir_node *prev)
1957 static const double DELTA = .0001;
1958 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1960 double prev_freq = 0; /**< execfreq of the fallthrough block */
1961 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1964 if(exec_freq == NULL)
1966 if(ia32_cg_config.label_alignment_factor <= 0)
1969 block_freq = get_block_execfreq(exec_freq, block);
1970 if(block_freq < DELTA)
1973 n_cfgpreds = get_Block_n_cfgpreds(block);
1974 for(i = 0; i < n_cfgpreds; ++i) {
1975 ir_node *pred = get_Block_cfgpred_block(block, i);
1976 double pred_freq = get_block_execfreq(exec_freq, pred);
1979 prev_freq += pred_freq;
1981 jmp_freq += pred_freq;
1985 if(prev_freq < DELTA && !(jmp_freq < DELTA))
1988 jmp_freq /= prev_freq;
1990 return jmp_freq > ia32_cg_config.label_alignment_factor;
1994 * Return non-zero, if a instruction in a fall-through.
1996 static int is_fallthrough(ir_node *cfgpred)
2000 if(!is_Proj(cfgpred))
2002 pred = get_Proj_pred(cfgpred);
2003 if(is_ia32_SwitchJmp(pred))
2010 * Emit the block header for a block.
2012 * @param block the block
2013 * @param prev_block the previous block
2015 static void ia32_emit_block_header(ir_node *block, ir_node *prev_block)
2017 ir_graph *irg = current_ir_graph;
2021 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2023 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2026 n_cfgpreds = get_Block_n_cfgpreds(block);
2028 if (n_cfgpreds == 0) {
2030 } else if (n_cfgpreds == 1) {
2031 ir_node *cfgpred = get_Block_cfgpred(block, 0);
2032 if (get_nodes_block(cfgpred) == prev_block && is_fallthrough(cfgpred)) {
2037 if (ia32_cg_config.label_alignment > 0) {
2038 /* align the current block if:
2039 * a) if should be aligned due to its execution frequency
2040 * b) there is no fall-through here
2042 if (should_align_block(block, prev_block)) {
2043 ia32_emit_align_label();
2045 /* if the predecessor block has no fall-through,
2046 we can always align the label. */
2048 ir_node *check_node = NULL;
2050 for (i = n_cfgpreds - 1; i >= 0; --i) {
2051 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2053 if (get_nodes_block(skip_Proj(cfg_pred)) == prev_block) {
2054 check_node = cfg_pred;
2058 if (check_node == NULL || !is_fallthrough(check_node))
2059 ia32_emit_align_label();
2063 if (need_label || has_Block_label(block)) {
2064 ia32_emit_block_name(block);
2067 be_emit_pad_comment();
2068 be_emit_cstring(" /* ");
2070 be_emit_cstring("\t/* ");
2071 ia32_emit_block_name(block);
2072 be_emit_cstring(": ");
2075 be_emit_cstring("preds:");
2077 /* emit list of pred blocks in comment */
2078 arity = get_irn_arity(block);
2079 for (i = 0; i < arity; ++i) {
2080 ir_node *predblock = get_Block_cfgpred_block(block, i);
2081 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2083 if (exec_freq != NULL) {
2084 be_emit_irprintf(" freq: %f",
2085 get_block_execfreq(exec_freq, block));
2087 be_emit_cstring(" */\n");
2088 be_emit_write_line();
2092 * Walks over the nodes in a block connected by scheduling edges
2093 * and emits code for each node.
2095 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2099 ia32_emit_block_header(block, last_block);
2101 /* emit the contents of the block */
2102 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2103 sched_foreach(block, node) {
2104 ia32_emit_node(node);
2108 typedef struct exc_entry {
2109 ir_node *exc_instr; /** The instruction that can issue an exception. */
2110 ir_node *block; /** The block to call then. */
2115 * Sets labels for control flow nodes (jump target).
2116 * Links control predecessors to there destination blocks.
2118 static void ia32_gen_labels(ir_node *block, void *data)
2120 exc_entry **exc_list = data;
2124 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2125 pred = get_Block_cfgpred(block, n);
2126 set_irn_link(pred, block);
2128 pred = skip_Proj(pred);
2129 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2134 ARR_APP1(exc_entry, *exc_list, e);
2135 set_irn_link(pred, block);
2141 * Assign and emit an exception label if the current instruction can fail.
2143 void ia32_assign_exc_label(ir_node *node)
2145 if (get_ia32_exc_label(node)) {
2146 /* assign a new ID to the instruction */
2147 set_ia32_exc_label_id(node, ++exc_label_id);
2149 ia32_emit_exc_label(node);
2151 be_emit_pad_comment();
2152 be_emit_cstring("/* exception to Block ");
2153 ia32_emit_cfop_target(node);
2154 be_emit_cstring(" */\n");
2155 be_emit_write_line();
2160 * Compare two exception_entries.
2162 static int cmp_exc_entry(const void *a, const void *b) {
2163 const exc_entry *ea = a;
2164 const exc_entry *eb = b;
2166 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2172 * Main driver. Emits the code for one routine.
2174 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2177 ir_node *last_block = NULL;
2178 ir_entity *entity = get_irg_entity(irg);
2179 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2183 isa = (const ia32_isa_t*) cg->arch_env;
2184 arch_env = cg->arch_env;
2185 do_pic = cg->birg->main_env->options->pic;
2187 ia32_register_emitters();
2189 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2191 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2192 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2194 /* we use links to point to target blocks */
2195 set_using_irn_link(irg);
2196 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2198 n = ARR_LEN(cg->blk_sched);
2199 for (i = 0; i < n;) {
2202 block = cg->blk_sched[i];
2204 next_bl = i < n ? cg->blk_sched[i] : NULL;
2206 /* set here the link. the emitter expects to find the next block here */
2207 set_irn_link(block, next_bl);
2208 ia32_gen_block(block, last_block);
2212 be_gas_emit_function_epilog(entity);
2213 be_dbg_method_end();
2215 be_emit_write_line();
2217 clear_using_irn_link(irg);
2219 /* Sort the exception table using the exception label id's.
2220 Those are ascending with ascending addresses. */
2221 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2225 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2226 be_emit_cstring("\t.long ");
2227 ia32_emit_exc_label(exc_list[i].exc_instr);
2229 be_emit_cstring("\t.long ");
2230 ia32_emit_block_name(exc_list[i].block);
2234 DEL_ARR_F(exc_list);
2237 void ia32_init_emitter(void)
2239 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");