2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
68 static const arch_env_t *arch_env;
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
73 * Returns the register at in position pos.
75 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
78 const arch_register_t *reg = NULL;
80 assert(get_irn_arity(irn) > pos && "Invalid IN position");
82 /* The out register of the operator at position pos is the
83 in register we need. */
84 op = get_irn_n(irn, pos);
86 reg = arch_get_irn_register(arch_env, op);
88 assert(reg && "no in register found");
90 if(reg == &ia32_gp_regs[REG_GP_NOREG])
91 panic("trying to emit noreg for %+F input %d", irn, pos);
93 /* in case of unknown register: just return a valid register */
94 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
95 const arch_register_req_t *req;
97 /* ask for the requirements */
98 req = arch_get_register_req(arch_env, irn, pos);
100 if (arch_register_req_is(req, limited)) {
101 /* in case of limited requirements: get the first allowed register */
102 unsigned idx = rbitset_next(req->limited, 0, 1);
103 reg = arch_register_for_index(req->cls, idx);
105 /* otherwise get first register in class */
106 reg = arch_register_for_index(req->cls, 0);
114 * Returns the register at out position pos.
116 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
119 const arch_register_t *reg = NULL;
121 /* 1st case: irn is not of mode_T, so it has only */
122 /* one OUT register -> good */
123 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
124 /* Proj with the corresponding projnum for the register */
126 if (get_irn_mode(irn) != mode_T) {
127 reg = arch_get_irn_register(arch_env, irn);
128 } else if (is_ia32_irn(irn)) {
129 reg = get_ia32_out_reg(irn, pos);
131 const ir_edge_t *edge;
133 foreach_out_edge(irn, edge) {
134 proj = get_edge_src_irn(edge);
135 assert(is_Proj(proj) && "non-Proj from mode_T node");
136 if (get_Proj_proj(proj) == pos) {
137 reg = arch_get_irn_register(arch_env, proj);
143 assert(reg && "no out register found");
148 * Determine the gnu assembler suffix that indicates a mode
150 static char get_mode_suffix(const ir_mode *mode)
152 if(mode_is_float(mode)) {
153 switch(get_mode_size_bits(mode)) {
163 assert(mode_is_int(mode) || mode_is_reference(mode));
164 switch(get_mode_size_bits(mode)) {
175 panic("Can't output mode_suffix for %+F\n", mode);
179 * Add a number to a prefix. This number will not be used a second time.
181 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
183 static unsigned long id = 0;
184 snprintf(buf, buflen, "%s%lu", prefix, ++id);
188 /*************************************************************
190 * (_) | | / _| | | | |
191 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
192 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
193 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
194 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
197 *************************************************************/
199 static void emit_8bit_register(const arch_register_t *reg)
201 const char *reg_name = arch_register_get_name(reg);
204 be_emit_char(reg_name[1]);
208 static void emit_16bit_register(const arch_register_t *reg)
210 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
213 be_emit_string(reg_name);
216 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
218 const char *reg_name;
221 int size = get_mode_size_bits(mode);
223 emit_8bit_register(reg);
225 } else if(size == 16) {
226 emit_16bit_register(reg);
233 reg_name = arch_register_get_name(reg);
236 be_emit_string(reg_name);
239 void ia32_emit_source_register(const ir_node *node, int pos)
241 const arch_register_t *reg = get_in_reg(node, pos);
243 emit_register(reg, NULL);
246 static void emit_ia32_Immediate(const ir_node *node);
248 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
250 const arch_register_t *reg;
251 ir_node *in = get_irn_n(node, pos);
252 if(is_ia32_Immediate(in)) {
253 emit_ia32_Immediate(in);
257 reg = get_in_reg(node, pos);
258 emit_8bit_register(reg);
261 void ia32_emit_dest_register(const ir_node *node, int pos)
263 const arch_register_t *reg = get_out_reg(node, pos);
265 emit_register(reg, NULL);
268 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
270 const arch_register_t *reg = get_out_reg(node, pos);
272 emit_register(reg, mode_Bu);
275 void ia32_emit_x87_register(const ir_node *node, int pos)
277 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
281 be_emit_string(attr->x87[pos]->name);
285 void ia32_emit_mode_suffix_mode(const ir_mode *mode)
287 be_emit_char(get_mode_suffix(mode));
290 void ia32_emit_mode_suffix(const ir_node *node)
292 ir_mode *mode = get_ia32_ls_mode(node);
296 ia32_emit_mode_suffix_mode(mode);
299 void ia32_emit_x87_mode_suffix(const ir_node *node)
301 ir_mode *mode = get_ia32_ls_mode(node);
303 ia32_emit_mode_suffix_mode(mode);
307 char get_xmm_mode_suffix(ir_mode *mode)
309 assert(mode_is_float(mode));
310 switch(get_mode_size_bits(mode)) {
321 void ia32_emit_xmm_mode_suffix(const ir_node *node)
323 ir_mode *mode = get_ia32_ls_mode(node);
324 assert(mode != NULL);
326 be_emit_char(get_xmm_mode_suffix(mode));
329 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
331 ir_mode *mode = get_ia32_ls_mode(node);
332 assert(mode != NULL);
333 be_emit_char(get_xmm_mode_suffix(mode));
336 void ia32_emit_extend_suffix(const ir_mode *mode)
338 if(get_mode_size_bits(mode) == 32)
340 if(mode_is_signed(mode)) {
348 void ia32_emit_function_object(const char *name)
350 switch (be_gas_flavour) {
351 case GAS_FLAVOUR_NORMAL:
352 be_emit_cstring("\t.type\t");
353 be_emit_string(name);
354 be_emit_cstring(", @function\n");
355 be_emit_write_line();
357 case GAS_FLAVOUR_MINGW:
358 be_emit_cstring("\t.def\t");
359 be_emit_string(name);
360 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
361 be_emit_write_line();
369 void ia32_emit_function_size(const char *name)
371 switch (be_gas_flavour) {
372 case GAS_FLAVOUR_NORMAL:
373 be_emit_cstring("\t.size\t");
374 be_emit_string(name);
375 be_emit_cstring(", .-");
376 be_emit_string(name);
378 be_emit_write_line();
386 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
388 ir_node *in = get_irn_n(node, pos);
389 if(is_ia32_Immediate(in)) {
390 emit_ia32_Immediate(in);
392 const ir_mode *mode = get_ia32_ls_mode(node);
393 const arch_register_t *reg = get_in_reg(node, pos);
394 emit_register(reg, mode);
399 * Emits registers and/or address mode of a binary operation.
401 void ia32_emit_binop(const ir_node *node, int produces_result) {
402 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
403 const ir_mode *mode = get_ia32_ls_mode(node);
404 const arch_register_t *reg_left;
406 switch(get_ia32_op_type(node)) {
408 reg_left = get_in_reg(node, n_ia32_binary_left);
409 if(is_ia32_Immediate(right_op)) {
410 emit_ia32_Immediate(right_op);
411 be_emit_cstring(", ");
412 emit_register(reg_left, mode);
415 const arch_register_t *reg_right
416 = get_in_reg(node, n_ia32_binary_right);
417 emit_register(reg_right, mode);
418 be_emit_cstring(", ");
419 emit_register(reg_left, mode);
423 if(is_ia32_Immediate(right_op)) {
424 assert(!produces_result && "Source AM with Const must not produce result");
426 emit_ia32_Immediate(right_op);
427 be_emit_cstring(", ");
430 reg_left = get_in_reg(node, n_ia32_binary_left);
432 be_emit_cstring(", ");
433 emit_register(reg_left, mode);
437 panic("DestMode can't be output by %%binop anymore");
440 assert(0 && "unsupported op type");
445 * Emits registers and/or address mode of a binary operation.
447 void ia32_emit_x87_binop(const ir_node *node) {
448 switch(get_ia32_op_type(node)) {
451 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
452 const arch_register_t *in1 = x87_attr->x87[0];
453 const arch_register_t *in2 = x87_attr->x87[1];
454 const arch_register_t *out = x87_attr->x87[2];
455 const arch_register_t *in;
457 in = out ? ((out == in2) ? in1 : in2) : in2;
458 out = out ? out : in1;
461 be_emit_string(arch_register_get_name(in));
462 be_emit_cstring(", %");
463 be_emit_string(arch_register_get_name(out));
471 assert(0 && "unsupported op type");
475 void ia32_emit_am_or_dest_register(const ir_node *node,
477 if(get_ia32_op_type(node) == ia32_Normal) {
478 ia32_emit_dest_register(node, pos);
480 assert(get_ia32_op_type(node) == ia32_AddrModeD);
486 * Emits registers and/or address mode of a unary operation.
488 void ia32_emit_unop(const ir_node *node, int pos) {
491 switch(get_ia32_op_type(node)) {
493 op = get_irn_n(node, pos);
494 if (is_ia32_Immediate(op)) {
495 emit_ia32_Immediate(op);
497 ia32_emit_source_register(node, pos);
505 assert(0 && "unsupported op type");
510 * Emits address mode.
512 void ia32_emit_am(const ir_node *node) {
513 ir_entity *ent = get_ia32_am_sc(node);
514 int offs = get_ia32_am_offs_int(node);
515 ir_node *base = get_irn_n(node, 0);
516 int has_base = !is_ia32_NoReg_GP(base);
517 ir_node *index = get_irn_n(node, 1);
518 int has_index = !is_ia32_NoReg_GP(index);
520 /* just to be sure... */
521 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
527 set_entity_backend_marked(ent, 1);
528 id = get_entity_ld_ident(ent);
529 if (is_ia32_am_sc_sign(node))
533 if(get_entity_owner(ent) == get_tls_type()) {
534 if (get_entity_visibility(ent) == visibility_external_allocated) {
535 be_emit_cstring("@INDNTPOFF");
537 be_emit_cstring("@NTPOFF");
544 be_emit_irprintf("%+d", offs);
546 be_emit_irprintf("%d", offs);
550 if (has_base || has_index) {
555 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
556 emit_register(reg, NULL);
559 /* emit index + scale */
561 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
564 emit_register(reg, NULL);
566 scale = get_ia32_am_scale(node);
568 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
574 /* special case if nothing is set */
575 if(ent == NULL && offs == 0 && !has_base && !has_index) {
580 /*************************************************
583 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
584 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
585 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
586 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
588 *************************************************/
591 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
594 * coding of conditions
596 struct cmp2conditon_t {
602 * positive conditions for signed compares
604 static const struct cmp2conditon_t cmp2condition_s[] = {
605 { NULL, pn_Cmp_False }, /* always false */
606 { "e", pn_Cmp_Eq }, /* == */
607 { "l", pn_Cmp_Lt }, /* < */
608 { "le", pn_Cmp_Le }, /* <= */
609 { "g", pn_Cmp_Gt }, /* > */
610 { "ge", pn_Cmp_Ge }, /* >= */
611 { "ne", pn_Cmp_Lg }, /* != */
612 { NULL, pn_Cmp_Leg}, /* always true */
616 * positive conditions for unsigned compares
618 static const struct cmp2conditon_t cmp2condition_u[] = {
619 { NULL, pn_Cmp_False }, /* always false */
620 { "e", pn_Cmp_Eq }, /* == */
621 { "b", pn_Cmp_Lt }, /* < */
622 { "be", pn_Cmp_Le }, /* <= */
623 { "a", pn_Cmp_Gt }, /* > */
624 { "ae", pn_Cmp_Ge }, /* >= */
625 { "ne", pn_Cmp_Lg }, /* != */
626 { NULL, pn_Cmp_Leg }, /* always true */
630 ia32_pn_Cmp_unsigned = 0x1000,
631 ia32_pn_Cmp_float = 0x2000,
635 * walks up a tree of copies/perms/spills/reloads to find the original value
636 * that is moved around
638 static ir_node *find_original_value(ir_node *node)
640 inc_irg_visited(current_ir_graph);
642 mark_irn_visited(node);
643 if(be_is_Copy(node)) {
644 node = be_get_Copy_op(node);
645 } else if(be_is_CopyKeep(node)) {
646 node = be_get_CopyKeep_op(node);
647 } else if(is_Proj(node)) {
648 ir_node *pred = get_Proj_pred(node);
649 if(be_is_Perm(pred)) {
650 node = get_irn_n(pred, get_Proj_proj(node));
651 } else if(be_is_MemPerm(pred)) {
652 node = get_irn_n(pred, get_Proj_proj(node) + 1);
653 } else if(is_ia32_Load(pred)) {
654 node = get_irn_n(pred, n_ia32_Load_mem);
658 } else if(is_ia32_Store(node)) {
659 node = get_irn_n(node, n_ia32_Store_val);
660 } else if(is_Phi(node)) {
662 arity = get_irn_arity(node);
663 for(i = 0; i < arity; ++i) {
664 ir_node *in = get_irn_n(node, i);
677 static int determine_final_pnc(const ir_node *node, int flags_pos,
680 ir_node *flags = get_irn_n(node, flags_pos);
681 const ia32_attr_t *flags_attr;
682 flags = skip_Proj(flags);
684 if(is_ia32_Sahf(flags)) {
685 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
686 if(!is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
687 || is_ia32_FucomppFnstsw(cmp)) {
688 cmp = find_original_value(cmp);
689 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
690 || is_ia32_FucomppFnstsw(cmp));
693 flags_attr = get_ia32_attr_const(cmp);
694 if(flags_attr->data.cmp_flipped)
695 pnc = get_mirrored_pnc(pnc);
696 pnc |= ia32_pn_Cmp_float;
697 } else if(is_ia32_Ucomi(flags)) {
698 flags_attr = get_ia32_attr_const(flags);
700 if(flags_attr->data.cmp_flipped)
701 pnc = get_mirrored_pnc(pnc);
702 pnc |= ia32_pn_Cmp_float;
704 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
705 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
706 flags_attr = get_ia32_attr_const(flags);
708 if(flags_attr->data.cmp_flipped)
709 pnc = get_mirrored_pnc(pnc);
710 if(flags_attr->data.cmp_unsigned)
711 pnc |= ia32_pn_Cmp_unsigned;
717 static void ia32_emit_cmp_suffix(int pnc)
721 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
723 assert(cmp2condition_u[pnc].num == pnc);
724 str = cmp2condition_u[pnc].name;
727 assert(cmp2condition_s[pnc].num == pnc);
728 str = cmp2condition_s[pnc].name;
734 void ia32_emit_cmp_suffix_node(const ir_node *node,
737 pn_Cmp pnc = get_ia32_pncode(node);
739 pnc = determine_final_pnc(node, flags_pos, pnc);
740 ia32_emit_cmp_suffix(pnc);
744 * Returns the target block for a control flow node.
747 ir_node *get_cfop_target_block(const ir_node *irn) {
748 return get_irn_link(irn);
752 * Emits a block label for the given block.
755 void ia32_emit_block_name(const ir_node *block)
757 if (has_Block_label(block)) {
758 be_emit_string(be_gas_label_prefix());
759 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
761 be_emit_cstring(BLOCK_PREFIX);
762 be_emit_irprintf("%d", get_irn_node_nr(block));
767 * Emits the target label for a control flow node.
769 static void ia32_emit_cfop_target(const ir_node *node)
771 ir_node *block = get_cfop_target_block(node);
773 ia32_emit_block_name(block);
776 /** Return the next block in Block schedule */
777 static ir_node *next_blk_sched(const ir_node *block)
779 return get_irn_link(block);
783 * Returns the Proj with projection number proj and NOT mode_M
785 static ir_node *get_proj(const ir_node *node, long proj) {
786 const ir_edge_t *edge;
789 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
791 foreach_out_edge(node, edge) {
792 src = get_edge_src_irn(edge);
794 assert(is_Proj(src) && "Proj expected");
795 if (get_irn_mode(src) == mode_M)
798 if (get_Proj_proj(src) == proj)
805 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
807 static void emit_ia32_Jcc(const ir_node *node)
809 const ir_node *proj_true;
810 const ir_node *proj_false;
811 const ir_node *block;
812 const ir_node *next_block;
813 pn_Cmp pnc = get_ia32_pncode(node);
815 pnc = determine_final_pnc(node, 0, pnc);
818 proj_true = get_proj(node, pn_ia32_Jcc_true);
819 assert(proj_true && "Jcc without true Proj");
821 proj_false = get_proj(node, pn_ia32_Jcc_false);
822 assert(proj_false && "Jcc without false Proj");
824 block = get_nodes_block(node);
825 next_block = next_blk_sched(block);
827 if (get_cfop_target_block(proj_true) == next_block) {
828 /* exchange both proj's so the second one can be omitted */
829 const ir_node *t = proj_true;
831 proj_true = proj_false;
833 if(pnc & ia32_pn_Cmp_float) {
834 pnc = get_negated_pnc(pnc, mode_F);
836 pnc = get_negated_pnc(pnc, mode_Iu);
840 if (pnc & ia32_pn_Cmp_float) {
841 /* Some floating point comparisons require a test of the parity flag,
842 * which indicates that the result is unordered */
845 be_emit_cstring("\tjp ");
846 ia32_emit_cfop_target(proj_true);
847 be_emit_finish_line_gas(proj_true);
851 be_emit_cstring("\tjnp ");
852 ia32_emit_cfop_target(proj_true);
853 be_emit_finish_line_gas(proj_true);
859 be_emit_cstring("\tjp ");
860 ia32_emit_cfop_target(proj_false);
861 be_emit_finish_line_gas(proj_false);
867 be_emit_cstring("\tjp ");
868 ia32_emit_cfop_target(proj_true);
869 be_emit_finish_line_gas(proj_true);
877 be_emit_cstring("\tj");
878 ia32_emit_cmp_suffix(pnc);
880 ia32_emit_cfop_target(proj_true);
881 be_emit_finish_line_gas(proj_true);
884 /* the second Proj might be a fallthrough */
885 if (get_cfop_target_block(proj_false) != next_block) {
886 be_emit_cstring("\tjmp ");
887 ia32_emit_cfop_target(proj_false);
888 be_emit_finish_line_gas(proj_false);
890 be_emit_cstring("\t/* fallthrough to ");
891 ia32_emit_cfop_target(proj_false);
892 be_emit_cstring(" */");
893 be_emit_finish_line_gas(proj_false);
897 static void emit_ia32_CMov(const ir_node *node)
899 const arch_register_t *out = arch_get_irn_register(arch_env, node);
900 const arch_register_t *in_true;
901 const arch_register_t *in_false;
902 pn_Cmp pnc = get_ia32_pncode(node);
904 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
906 in_true = arch_get_irn_register(arch_env,
907 get_irn_n(node, n_ia32_CMov_val_true));
908 in_false = arch_get_irn_register(arch_env,
909 get_irn_n(node, n_ia32_CMov_val_false));
911 /* should be same constraint fullfilled? */
912 if(out == in_false) {
913 /* yes -> nothing to do */
914 } else if(out == in_true) {
915 const arch_register_t *tmp;
917 /* swap left/right and negate pnc */
918 pnc = get_negated_pnc(pnc, mode_Iu);
925 be_emit_cstring("\tmovl ");
926 emit_register(in_false, NULL);
927 be_emit_cstring(", ");
928 emit_register(out, NULL);
929 be_emit_finish_line_gas(node);
932 be_emit_cstring("\tcmov");
933 ia32_emit_cmp_suffix(pnc);
935 if(get_ia32_op_type(node) == ia32_AddrModeS) {
938 emit_register(in_true, get_ia32_ls_mode(node));
940 be_emit_cstring(", ");
941 emit_register(out, get_ia32_ls_mode(node));
942 be_emit_finish_line_gas(node);
945 /*********************************************************
948 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
949 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
950 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
951 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
954 *********************************************************/
956 /* jump table entry (target and corresponding number) */
957 typedef struct _branch_t {
962 /* jump table for switch generation */
963 typedef struct _jmp_tbl_t {
964 ir_node *defProj; /**< default target */
965 long min_value; /**< smallest switch case */
966 long max_value; /**< largest switch case */
967 long num_branches; /**< number of jumps */
968 char *label; /**< label of the jump table */
969 branch_t *branches; /**< jump array */
973 * Compare two variables of type branch_t. Used to sort all switch cases
976 int ia32_cmp_branch_t(const void *a, const void *b) {
977 branch_t *b1 = (branch_t *)a;
978 branch_t *b2 = (branch_t *)b;
980 if (b1->value <= b2->value)
987 * Emits code for a SwitchJmp (creates a jump table if
988 * possible otherwise a cmp-jmp cascade). Port from
992 void emit_ia32_SwitchJmp(const ir_node *node) {
993 unsigned long interval;
998 const ir_edge_t *edge;
1000 /* fill the table structure */
1001 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1002 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1004 tbl.num_branches = get_irn_n_edges(node);
1005 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1006 tbl.min_value = INT_MAX;
1007 tbl.max_value = INT_MIN;
1010 /* go over all proj's and collect them */
1011 foreach_out_edge(node, edge) {
1012 proj = get_edge_src_irn(edge);
1013 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1015 pnc = get_Proj_proj(proj);
1017 /* create branch entry */
1018 tbl.branches[i].target = proj;
1019 tbl.branches[i].value = pnc;
1021 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1022 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1024 /* check for default proj */
1025 if (pnc == get_ia32_pncode(node)) {
1026 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1033 /* sort the branches by their number */
1034 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1036 /* two-complement's magic make this work without overflow */
1037 interval = tbl.max_value - tbl.min_value;
1039 /* emit the table */
1040 be_emit_cstring("\tcmpl $");
1041 be_emit_irprintf("%u, ", interval);
1042 ia32_emit_source_register(node, 0);
1043 be_emit_finish_line_gas(node);
1045 be_emit_cstring("\tja ");
1046 ia32_emit_cfop_target(tbl.defProj);
1047 be_emit_finish_line_gas(node);
1049 if (tbl.num_branches > 1) {
1051 be_emit_cstring("\tjmp *");
1052 be_emit_string(tbl.label);
1053 be_emit_cstring("(,");
1054 ia32_emit_source_register(node, 0);
1055 be_emit_cstring(",4)");
1056 be_emit_finish_line_gas(node);
1058 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1059 be_emit_cstring("\t.align 4\n");
1060 be_emit_write_line();
1062 be_emit_string(tbl.label);
1063 be_emit_cstring(":\n");
1064 be_emit_write_line();
1066 be_emit_cstring(".long ");
1067 ia32_emit_cfop_target(tbl.branches[0].target);
1068 be_emit_finish_line_gas(NULL);
1070 last_value = tbl.branches[0].value;
1071 for (i = 1; i < tbl.num_branches; ++i) {
1072 while (++last_value < tbl.branches[i].value) {
1073 be_emit_cstring(".long ");
1074 ia32_emit_cfop_target(tbl.defProj);
1075 be_emit_finish_line_gas(NULL);
1077 be_emit_cstring(".long ");
1078 ia32_emit_cfop_target(tbl.branches[i].target);
1079 be_emit_finish_line_gas(NULL);
1081 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1083 /* one jump is enough */
1084 be_emit_cstring("\tjmp ");
1085 ia32_emit_cfop_target(tbl.branches[0].target);
1086 be_emit_finish_line_gas(node);
1096 * Emits code for a unconditional jump.
1098 static void emit_Jmp(const ir_node *node)
1100 ir_node *block, *next_block;
1102 /* for now, the code works for scheduled and non-schedules blocks */
1103 block = get_nodes_block(node);
1105 /* we have a block schedule */
1106 next_block = next_blk_sched(block);
1107 if (get_cfop_target_block(node) != next_block) {
1108 be_emit_cstring("\tjmp ");
1109 ia32_emit_cfop_target(node);
1111 be_emit_cstring("\t/* fallthrough to ");
1112 ia32_emit_cfop_target(node);
1113 be_emit_cstring(" */");
1115 be_emit_finish_line_gas(node);
1118 static void emit_ia32_Immediate(const ir_node *node)
1120 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1123 if(attr->symconst != NULL) {
1124 ident *id = get_entity_ld_ident(attr->symconst);
1126 if(attr->attr.data.am_sc_sign)
1130 if(attr->symconst == NULL || attr->offset != 0) {
1131 if(attr->symconst != NULL) {
1132 be_emit_irprintf("%+d", attr->offset);
1134 be_emit_irprintf("0x%X", attr->offset);
1139 static const char* emit_asm_operand(const ir_node *node, const char *s)
1141 const arch_register_t *reg;
1142 const char *reg_name;
1146 const ia32_attr_t *attr;
1153 /* parse modifiers */
1156 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1180 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1181 "'%c' for asm op\n", node, c);
1187 sscanf(s, "%d%n", &num, &p);
1189 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1197 attr = get_ia32_attr_const(node);
1198 n_outs = ARR_LEN(attr->slots);
1200 reg = get_out_reg(node, num);
1203 int in = num - n_outs;
1204 if(in >= get_irn_arity(node)) {
1205 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1206 "op (%+F)\n", num, node);
1209 pred = get_irn_n(node, in);
1210 /* might be an immediate value */
1211 if(is_ia32_Immediate(pred)) {
1212 emit_ia32_Immediate(pred);
1215 reg = get_in_reg(node, in);
1218 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1219 "(%+F)\n", num, node);
1227 reg_name = arch_register_get_name(reg);
1230 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1233 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1236 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1239 panic("Invalid asm op modifier");
1241 be_emit_string(reg_name);
1247 * Emits code for an ASM pseudo op.
1249 static void emit_ia32_Asm(const ir_node *node)
1251 const void *gen_attr = get_irn_generic_attr_const(node);
1252 const ia32_asm_attr_t *attr
1253 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1254 ident *asm_text = attr->asm_text;
1255 const char *s = get_id_str(asm_text);
1257 be_emit_cstring("# Begin ASM \t");
1258 be_emit_finish_line_gas(node);
1265 s = emit_asm_operand(node, s);
1274 be_emit_write_line();
1276 be_emit_cstring("# End ASM\n");
1277 be_emit_write_line();
1280 /**********************************
1283 * | | ___ _ __ _ _| |_) |
1284 * | | / _ \| '_ \| | | | _ <
1285 * | |___| (_) | |_) | |_| | |_) |
1286 * \_____\___/| .__/ \__, |____/
1289 **********************************/
1292 * Emit movsb/w instructions to make mov count divideable by 4
1294 static void emit_CopyB_prolog(int rem) {
1295 be_emit_cstring("\tcld");
1296 be_emit_finish_line_gas(NULL);
1300 be_emit_cstring("\tmovsb");
1301 be_emit_finish_line_gas(NULL);
1304 be_emit_cstring("\tmovsw");
1305 be_emit_finish_line_gas(NULL);
1308 be_emit_cstring("\tmovsb");
1309 be_emit_finish_line_gas(NULL);
1310 be_emit_cstring("\tmovsw");
1311 be_emit_finish_line_gas(NULL);
1317 * Emit rep movsd instruction for memcopy.
1319 static void emit_ia32_CopyB(const ir_node *node)
1321 int rem = get_ia32_pncode(node);
1323 emit_CopyB_prolog(rem);
1325 be_emit_cstring("\trep movsd");
1326 be_emit_finish_line_gas(node);
1330 * Emits unrolled memcopy.
1332 static void emit_ia32_CopyB_i(const ir_node *node)
1334 int size = get_ia32_pncode(node);
1336 emit_CopyB_prolog(size & 0x3);
1340 be_emit_cstring("\tmovsd");
1341 be_emit_finish_line_gas(NULL);
1347 /***************************
1351 * | | / _ \| '_ \ \ / /
1352 * | |___| (_) | | | \ V /
1353 * \_____\___/|_| |_|\_/
1355 ***************************/
1358 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1360 static void emit_ia32_Conv_with_FP(const ir_node *node)
1362 ir_mode *ls_mode = get_ia32_ls_mode(node);
1363 int ls_bits = get_mode_size_bits(ls_mode);
1365 be_emit_cstring("\tcvt");
1367 if(is_ia32_Conv_I2FP(node)) {
1369 be_emit_cstring("si2ss");
1371 be_emit_cstring("si2sd");
1373 } else if(is_ia32_Conv_FP2I(node)) {
1375 be_emit_cstring("ss2si");
1377 be_emit_cstring("sd2si");
1380 assert(is_ia32_Conv_FP2FP(node));
1382 be_emit_cstring("sd2ss");
1384 be_emit_cstring("ss2sd");
1389 switch(get_ia32_op_type(node)) {
1391 ia32_emit_source_register(node, n_ia32_unary_op);
1392 be_emit_cstring(", ");
1393 ia32_emit_dest_register(node, 0);
1395 case ia32_AddrModeS:
1396 ia32_emit_dest_register(node, 0);
1397 be_emit_cstring(", ");
1401 assert(0 && "unsupported op type for Conv");
1403 be_emit_finish_line_gas(node);
1406 static void emit_ia32_Conv_I2FP(const ir_node *node)
1408 emit_ia32_Conv_with_FP(node);
1411 static void emit_ia32_Conv_FP2I(const ir_node *node)
1413 emit_ia32_Conv_with_FP(node);
1416 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1418 emit_ia32_Conv_with_FP(node);
1422 * Emits code for an Int conversion.
1424 static void emit_ia32_Conv_I2I(const ir_node *node)
1426 const char *sign_suffix;
1427 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1428 int smaller_bits = get_mode_size_bits(smaller_mode);
1430 const arch_register_t *in_reg, *out_reg;
1432 assert(!mode_is_float(smaller_mode));
1433 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1435 signed_mode = mode_is_signed(smaller_mode);
1436 if(smaller_bits == 32) {
1437 // this should not happen as it's no convert
1441 sign_suffix = signed_mode ? "s" : "z";
1444 out_reg = get_out_reg(node, 0);
1446 switch(get_ia32_op_type(node)) {
1448 in_reg = get_in_reg(node, n_ia32_unary_op);
1450 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1451 out_reg == &ia32_gp_regs[REG_EAX] &&
1455 /* argument and result are both in EAX and */
1456 /* signedness is ok: -> use the smaller cwtl opcode */
1457 be_emit_cstring("\tcwtl");
1459 be_emit_cstring("\tmov");
1460 be_emit_string(sign_suffix);
1461 ia32_emit_mode_suffix_mode(smaller_mode);
1462 be_emit_cstring("l ");
1463 emit_register(in_reg, smaller_mode);
1464 be_emit_cstring(", ");
1465 emit_register(out_reg, NULL);
1468 case ia32_AddrModeS: {
1469 be_emit_cstring("\tmov");
1470 be_emit_string(sign_suffix);
1471 ia32_emit_mode_suffix_mode(smaller_mode);
1472 be_emit_cstring("l ");
1474 be_emit_cstring(", ");
1475 emit_register(out_reg, NULL);
1479 assert(0 && "unsupported op type for Conv");
1481 be_emit_finish_line_gas(node);
1485 * Emits code for an 8Bit Int conversion.
1487 static void emit_ia32_Conv_I2I8Bit(const ir_node *node)
1489 emit_ia32_Conv_I2I(node);
1493 /*******************************************
1496 * | |__ ___ _ __ ___ __| | ___ ___
1497 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1498 * | |_) | __/ | | | (_) | (_| | __/\__ \
1499 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1501 *******************************************/
1504 * Emits a backend call
1506 static void emit_be_Call(const ir_node *node)
1508 ir_entity *ent = be_Call_get_entity(node);
1510 be_emit_cstring("\tcall ");
1512 set_entity_backend_marked(ent, 1);
1513 be_emit_string(get_entity_ld_name(ent));
1515 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1517 emit_register(reg, NULL);
1519 be_emit_finish_line_gas(node);
1523 * Emits code to increase stack pointer.
1525 static void emit_be_IncSP(const ir_node *node)
1527 int offs = be_get_IncSP_offset(node);
1528 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1534 be_emit_cstring("\tsubl $");
1535 be_emit_irprintf("%u, ", offs);
1536 emit_register(reg, NULL);
1538 be_emit_cstring("\taddl $");
1539 be_emit_irprintf("%u, ", -offs);
1540 emit_register(reg, NULL);
1542 be_emit_finish_line_gas(node);
1546 * Emits code for Copy/CopyKeep.
1548 static void Copy_emitter(const ir_node *node, const ir_node *op)
1550 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1551 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1557 if(is_unknown_reg(in))
1559 /* copies of vf nodes aren't real... */
1560 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1563 mode = get_irn_mode(node);
1564 if (mode == mode_E) {
1565 be_emit_cstring("\tmovsd ");
1566 emit_register(in, NULL);
1567 be_emit_cstring(", ");
1568 emit_register(out, NULL);
1570 be_emit_cstring("\tmovl ");
1571 emit_register(in, NULL);
1572 be_emit_cstring(", ");
1573 emit_register(out, NULL);
1575 be_emit_finish_line_gas(node);
1578 static void emit_be_Copy(const ir_node *node)
1580 Copy_emitter(node, be_get_Copy_op(node));
1583 static void emit_be_CopyKeep(const ir_node *node)
1585 Copy_emitter(node, be_get_CopyKeep_op(node));
1589 * Emits code for exchange.
1591 static void emit_be_Perm(const ir_node *node)
1593 const arch_register_t *in0, *in1;
1594 const arch_register_class_t *cls0, *cls1;
1596 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1597 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1599 cls0 = arch_register_get_class(in0);
1600 cls1 = arch_register_get_class(in1);
1602 assert(cls0 == cls1 && "Register class mismatch at Perm");
1604 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1605 be_emit_cstring("\txchg ");
1606 emit_register(in1, NULL);
1607 be_emit_cstring(", ");
1608 emit_register(in0, NULL);
1609 be_emit_finish_line_gas(node);
1610 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1611 be_emit_cstring("\txorpd ");
1612 emit_register(in1, NULL);
1613 be_emit_cstring(", ");
1614 emit_register(in0, NULL);
1615 be_emit_finish_line_gas(NULL);
1617 be_emit_cstring("\txorpd ");
1618 emit_register(in0, NULL);
1619 be_emit_cstring(", ");
1620 emit_register(in1, NULL);
1621 be_emit_finish_line_gas(NULL);
1623 be_emit_cstring("\txorpd ");
1624 emit_register(in1, NULL);
1625 be_emit_cstring(", ");
1626 emit_register(in0, NULL);
1627 be_emit_finish_line_gas(node);
1628 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1630 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1633 panic("unexpected register class in be_Perm (%+F)\n", node);
1638 * Emits code for Constant loading.
1640 static void emit_ia32_Const(const ir_node *node)
1642 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1645 if(attr->symconst == NULL && attr->offset == 0) {
1646 assert(get_ia32_flags(node) & arch_irn_flags_modify_flags);
1647 be_emit_cstring("\txorl ");
1648 ia32_emit_dest_register(node, 0);
1649 be_emit_cstring(", ");
1650 ia32_emit_dest_register(node, 0);
1652 be_emit_cstring("\tmovl ");
1653 emit_ia32_Immediate(node);
1654 be_emit_cstring(", ");
1655 ia32_emit_dest_register(node, 0);
1658 be_emit_finish_line_gas(node);
1662 * Emits code to load the TLS base
1664 static void emit_ia32_LdTls(const ir_node *node)
1666 be_emit_cstring("\tmovl %gs:0, ");
1667 ia32_emit_dest_register(node, 0);
1668 be_emit_finish_line_gas(node);
1671 /* helper function for emit_ia32_Minus64Bit */
1672 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1674 be_emit_cstring("\tmovl ");
1675 emit_register(src, NULL);
1676 be_emit_cstring(", ");
1677 emit_register(dst, NULL);
1678 be_emit_finish_line_gas(node);
1681 /* helper function for emit_ia32_Minus64Bit */
1682 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1684 be_emit_cstring("\tnegl ");
1685 emit_register(reg, NULL);
1686 be_emit_finish_line_gas(node);
1689 /* helper function for emit_ia32_Minus64Bit */
1690 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1692 be_emit_cstring("\tsbbl $0, ");
1693 emit_register(reg, NULL);
1694 be_emit_finish_line_gas(node);
1697 /* helper function for emit_ia32_Minus64Bit */
1698 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1700 be_emit_cstring("\tsbbl ");
1701 emit_register(src, NULL);
1702 be_emit_cstring(", ");
1703 emit_register(dst, NULL);
1704 be_emit_finish_line_gas(node);
1707 /* helper function for emit_ia32_Minus64Bit */
1708 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1710 be_emit_cstring("\txchgl ");
1711 emit_register(src, NULL);
1712 be_emit_cstring(", ");
1713 emit_register(dst, NULL);
1714 be_emit_finish_line_gas(node);
1717 /* helper function for emit_ia32_Minus64Bit */
1718 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1720 be_emit_cstring("\txorl ");
1721 emit_register(reg, NULL);
1722 be_emit_cstring(", ");
1723 emit_register(reg, NULL);
1724 be_emit_finish_line_gas(node);
1727 static void emit_ia32_Minus64Bit(const ir_node *node)
1729 const arch_register_t *in_lo = get_in_reg(node, 0);
1730 const arch_register_t *in_hi = get_in_reg(node, 1);
1731 const arch_register_t *out_lo = get_out_reg(node, 0);
1732 const arch_register_t *out_hi = get_out_reg(node, 1);
1734 if (out_lo == in_lo) {
1735 if (out_hi != in_hi) {
1736 /* a -> a, b -> d */
1739 /* a -> a, b -> b */
1742 } else if (out_lo == in_hi) {
1743 if (out_hi == in_lo) {
1744 /* a -> b, b -> a */
1745 emit_xchg(node, in_lo, in_hi);
1748 /* a -> b, b -> d */
1749 emit_mov(node, in_hi, out_hi);
1750 emit_mov(node, in_lo, out_lo);
1754 if (out_hi == in_lo) {
1755 /* a -> c, b -> a */
1756 emit_mov(node, in_lo, out_lo);
1758 } else if (out_hi == in_hi) {
1759 /* a -> c, b -> b */
1760 emit_mov(node, in_lo, out_lo);
1763 /* a -> c, b -> d */
1764 emit_mov(node, in_lo, out_lo);
1770 emit_neg( node, out_hi);
1771 emit_neg( node, out_lo);
1772 emit_sbb0(node, out_hi);
1776 emit_zero(node, out_hi);
1777 emit_neg( node, out_lo);
1778 emit_sbb( node, in_hi, out_hi);
1781 static void emit_be_Return(const ir_node *node)
1783 be_emit_cstring("\tret");
1784 be_emit_finish_line_gas(node);
1787 static void emit_Nothing(const ir_node *node)
1793 /***********************************************************************************
1796 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1797 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1798 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1799 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1801 ***********************************************************************************/
1804 * Enters the emitter functions for handled nodes into the generic
1805 * pointer of an opcode.
1808 void ia32_register_emitters(void) {
1810 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1811 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1812 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1813 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1814 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1815 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1817 /* first clear the generic function pointer for all ops */
1818 clear_irp_opcodes_generic_func();
1820 /* register all emitter functions defined in spec */
1821 ia32_register_spec_emitters();
1823 /* other ia32 emitter functions */
1826 IA32_EMIT(SwitchJmp);
1829 IA32_EMIT(Conv_I2FP);
1830 IA32_EMIT(Conv_FP2I);
1831 IA32_EMIT(Conv_FP2FP);
1832 IA32_EMIT(Conv_I2I);
1833 IA32_EMIT(Conv_I2I8Bit);
1836 IA32_EMIT(Minus64Bit);
1839 /* benode emitter */
1864 static const char *last_name = NULL;
1865 static unsigned last_line = -1;
1866 static unsigned num = -1;
1869 * Emit the debug support for node node.
1871 static void ia32_emit_dbg(const ir_node *node)
1873 dbg_info *db = get_irn_dbg_info(node);
1875 const char *fname = be_retrieve_dbg_info(db, &lineno);
1877 if (! cg->birg->main_env->options->stabs_debug_support)
1881 if (last_name != fname) {
1883 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1886 if (last_line != lineno) {
1889 snprintf(name, sizeof(name), ".LM%u", ++num);
1891 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1892 be_emit_string(name);
1893 be_emit_cstring(":\n");
1894 be_emit_write_line();
1899 typedef void (*emit_func_ptr) (const ir_node *);
1902 * Emits code for a node.
1904 static void ia32_emit_node(const ir_node *node)
1906 ir_op *op = get_irn_op(node);
1908 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1910 if (op->ops.generic) {
1911 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1912 ia32_emit_dbg(node);
1916 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1922 * Emits gas alignment directives
1924 static void ia32_emit_alignment(unsigned align, unsigned skip)
1926 be_emit_cstring("\t.p2align ");
1927 be_emit_irprintf("%u,,%u\n", align, skip);
1928 be_emit_write_line();
1932 * Emits gas alignment directives for Functions depended on cpu architecture.
1934 static void ia32_emit_align_func(cpu_support cpu)
1937 unsigned maximum_skip;
1952 maximum_skip = (1 << align) - 1;
1953 ia32_emit_alignment(align, maximum_skip);
1957 * Emits gas alignment directives for Labels depended on cpu architecture.
1959 static void ia32_emit_align_label(cpu_support cpu)
1961 unsigned align; unsigned maximum_skip;
1976 maximum_skip = (1 << align) - 1;
1977 ia32_emit_alignment(align, maximum_skip);
1981 * Test wether a block should be aligned.
1982 * For cpus in the P4/Athlon class it is usefull to align jump labels to
1983 * 16 bytes. However we should only do that if the alignment nops before the
1984 * label aren't executed more often than we have jumps to the label.
1986 static int should_align_block(ir_node *block, ir_node *prev)
1988 static const double DELTA = .0001;
1989 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1991 double prev_freq = 0; /**< execfreq of the fallthrough block */
1992 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1993 cpu_support cpu = isa->opt_arch;
1996 if(exec_freq == NULL)
1998 if(cpu == arch_i386 || cpu == arch_i486)
2001 block_freq = get_block_execfreq(exec_freq, block);
2002 if(block_freq < DELTA)
2005 n_cfgpreds = get_Block_n_cfgpreds(block);
2006 for(i = 0; i < n_cfgpreds; ++i) {
2007 ir_node *pred = get_Block_cfgpred_block(block, i);
2008 double pred_freq = get_block_execfreq(exec_freq, pred);
2011 prev_freq += pred_freq;
2013 jmp_freq += pred_freq;
2017 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2020 jmp_freq /= prev_freq;
2024 case arch_athlon_64:
2026 return jmp_freq > 3;
2028 return jmp_freq > 2;
2032 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2037 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2039 n_cfgpreds = get_Block_n_cfgpreds(block);
2040 need_label = (n_cfgpreds != 0);
2042 if (should_align_block(block, prev)) {
2044 ia32_emit_align_label(isa->opt_arch);
2048 ia32_emit_block_name(block);
2051 be_emit_pad_comment();
2052 be_emit_cstring(" /* preds:");
2054 /* emit list of pred blocks in comment */
2055 arity = get_irn_arity(block);
2056 for (i = 0; i < arity; ++i) {
2057 ir_node *predblock = get_Block_cfgpred_block(block, i);
2058 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2061 be_emit_cstring("\t/* ");
2062 ia32_emit_block_name(block);
2063 be_emit_cstring(": ");
2065 if (exec_freq != NULL) {
2066 be_emit_irprintf(" freq: %f",
2067 get_block_execfreq(exec_freq, block));
2069 be_emit_cstring(" */\n");
2070 be_emit_write_line();
2074 * Walks over the nodes in a block connected by scheduling edges
2075 * and emits code for each node.
2077 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2079 const ir_node *node;
2081 ia32_emit_block_header(block, last_block);
2083 /* emit the contents of the block */
2084 ia32_emit_dbg(block);
2085 sched_foreach(block, node) {
2086 ia32_emit_node(node);
2091 * Emits code for function start.
2093 static void ia32_emit_func_prolog(ir_graph *irg)
2095 ir_entity *irg_ent = get_irg_entity(irg);
2096 const char *irg_name = get_entity_ld_name(irg_ent);
2097 cpu_support cpu = isa->opt_arch;
2098 const be_irg_t *birg = cg->birg;
2100 be_emit_write_line();
2101 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2102 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2103 ia32_emit_align_func(cpu);
2104 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2105 be_emit_cstring(".global ");
2106 be_emit_string(irg_name);
2108 be_emit_write_line();
2110 ia32_emit_function_object(irg_name);
2111 be_emit_string(irg_name);
2112 be_emit_cstring(":\n");
2113 be_emit_write_line();
2117 * Emits code for function end
2119 static void ia32_emit_func_epilog(ir_graph *irg)
2121 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2122 const be_irg_t *birg = cg->birg;
2124 ia32_emit_function_size(irg_name);
2125 be_dbg_method_end(birg->main_env->db_handle);
2127 be_emit_write_line();
2132 * Sets labels for control flow nodes (jump target)
2134 static void ia32_gen_labels(ir_node *block, void *data)
2137 int n = get_Block_n_cfgpreds(block);
2140 for (n--; n >= 0; n--) {
2141 pred = get_Block_cfgpred(block, n);
2142 set_irn_link(pred, block);
2147 * Emit an exception label if the current instruction can fail.
2149 void ia32_emit_exc_label(const ir_node *node)
2151 if (get_ia32_exc_label(node)) {
2152 be_emit_irprintf(".EXL%u\n", 0);
2153 be_emit_write_line();
2158 * Main driver. Emits the code for one routine.
2160 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2163 ir_node *last_block = NULL;
2167 isa = (const ia32_isa_t*) cg->arch_env->isa;
2168 arch_env = cg->arch_env;
2170 ia32_register_emitters();
2172 ia32_emit_func_prolog(irg);
2173 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2175 n = ARR_LEN(cg->blk_sched);
2176 for (i = 0; i < n;) {
2179 block = cg->blk_sched[i];
2181 next_bl = i < n ? cg->blk_sched[i] : NULL;
2183 /* set here the link. the emitter expects to find the next block here */
2184 set_irn_link(block, next_bl);
2185 ia32_gen_block(block, last_block);
2189 ia32_emit_func_epilog(irg);
2192 void ia32_init_emitter(void)
2194 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");