2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
33 * pnc_Leg => NP (ordered)
55 #include "iredges_t.h"
59 #include "raw_bitset.h"
63 #include "../besched.h"
64 #include "../benode.h"
66 #include "../be_dbgout.h"
67 #include "../beemitter.h"
68 #include "../begnuas.h"
70 #include "../be_dbgout.h"
72 #include "ia32_emitter.h"
73 #include "ia32_common_transform.h"
74 #include "gen_ia32_emitter.h"
75 #include "gen_ia32_regalloc_if.h"
76 #include "ia32_nodes_attr.h"
77 #include "ia32_new_nodes.h"
78 #include "ia32_map_regs.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 #define SNPRINTF_BUF_LEN 128
86 static const ia32_isa_t *isa;
87 static ia32_code_gen_t *cg;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
146 const arch_register_t *reg = NULL;
148 assert(get_irn_arity(irn) > pos && "Invalid IN position");
150 /* The out register of the operator at position pos is the
151 in register we need. */
152 op = get_irn_n(irn, pos);
154 reg = arch_get_irn_register(op);
156 assert(reg && "no in register found");
158 if (reg == &ia32_gp_regs[REG_GP_NOREG])
159 panic("trying to emit noreg for %+F input %d", irn, pos);
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
170 const arch_register_t *reg = NULL;
172 /* 1st case: irn is not of mode_T, so it has only */
173 /* one OUT register -> good */
174 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
175 /* Proj with the corresponding projnum for the register */
177 if (get_irn_mode(irn) != mode_T) {
179 reg = arch_get_irn_register(irn);
180 } else if (is_ia32_irn(irn)) {
181 reg = arch_irn_get_register(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(proj);
195 assert(reg && "no out register found");
200 * Add a number to a prefix. This number will not be used a second time.
202 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
204 static unsigned long id = 0;
205 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
211 * Emit the name of the 8bit low register
213 static void emit_8bit_register(const arch_register_t *reg)
215 const char *reg_name = arch_register_get_name(reg);
218 be_emit_char(reg_name[1]);
223 * Emit the name of the 8bit high register
225 static void emit_8bit_register_high(const arch_register_t *reg)
227 const char *reg_name = arch_register_get_name(reg);
230 be_emit_char(reg_name[1]);
234 static void emit_16bit_register(const arch_register_t *reg)
236 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
239 be_emit_string(reg_name);
243 * emit a register, possible shortened by a mode
245 * @param reg the register
246 * @param mode the mode of the register or NULL for full register
248 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
250 const char *reg_name;
253 int size = get_mode_size_bits(mode);
255 case 8: emit_8bit_register(reg); return;
256 case 16: emit_16bit_register(reg); return;
258 assert(mode_is_float(mode) || size == 32);
261 reg_name = arch_register_get_name(reg);
264 be_emit_string(reg_name);
267 void ia32_emit_source_register(const ir_node *node, int pos)
269 const arch_register_t *reg = get_in_reg(node, pos);
271 emit_register(reg, NULL);
274 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
276 be_gas_emit_entity(entity);
278 if (get_entity_owner(entity) == get_tls_type()) {
279 if (get_entity_visibility(entity) == ir_visibility_external) {
280 be_emit_cstring("@INDNTPOFF");
282 be_emit_cstring("@NTPOFF");
286 if (do_pic && !no_pic_adjust) {
288 be_emit_string(pic_base_label);
292 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
294 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
296 if (attr->symconst != NULL) {
299 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
301 if (attr->symconst == NULL || attr->offset != 0) {
302 if (attr->symconst != NULL) {
303 be_emit_irprintf("%+d", attr->offset);
305 be_emit_irprintf("0x%X", attr->offset);
310 static void emit_ia32_Immediate(const ir_node *node)
313 emit_ia32_Immediate_no_prefix(node);
316 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
318 const arch_register_t *reg;
319 const ir_node *in = get_irn_n(node, pos);
320 if (is_ia32_Immediate(in)) {
321 emit_ia32_Immediate(in);
325 reg = get_in_reg(node, pos);
326 emit_8bit_register(reg);
329 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
331 const arch_register_t *reg = get_in_reg(node, pos);
332 emit_8bit_register_high(reg);
335 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
337 const arch_register_t *reg;
338 const ir_node *in = get_irn_n(node, pos);
339 if (is_ia32_Immediate(in)) {
340 emit_ia32_Immediate(in);
344 reg = get_in_reg(node, pos);
345 emit_16bit_register(reg);
348 void ia32_emit_dest_register(const ir_node *node, int pos)
350 const arch_register_t *reg = get_out_reg(node, pos);
352 emit_register(reg, NULL);
355 void ia32_emit_dest_register_size(const ir_node *node, int pos)
357 const arch_register_t *reg = get_out_reg(node, pos);
359 emit_register(reg, get_ia32_ls_mode(node));
362 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
364 const arch_register_t *reg = get_out_reg(node, pos);
366 emit_register(reg, mode_Bu);
369 void ia32_emit_x87_register(const ir_node *node, int pos)
371 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
375 be_emit_string(attr->x87[pos]->name);
378 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
380 assert(mode_is_int(mode) || mode_is_reference(mode));
381 switch (get_mode_size_bits(mode)) {
382 case 8: be_emit_char('b'); return;
383 case 16: be_emit_char('w'); return;
384 case 32: be_emit_char('l'); return;
385 /* gas docu says q is the suffix but gcc, objdump and icc use ll
387 case 64: be_emit_cstring("ll"); return;
389 panic("Can't output mode_suffix for %+F", mode);
392 void ia32_emit_mode_suffix(const ir_node *node)
394 ir_mode *mode = get_ia32_ls_mode(node);
398 ia32_emit_mode_suffix_mode(mode);
401 void ia32_emit_x87_mode_suffix(const ir_node *node)
405 /* we only need to emit the mode on address mode */
406 if (get_ia32_op_type(node) == ia32_Normal)
409 mode = get_ia32_ls_mode(node);
410 assert(mode != NULL);
412 if (mode_is_float(mode)) {
413 switch (get_mode_size_bits(mode)) {
414 case 32: be_emit_char('s'); return;
415 case 64: be_emit_char('l'); return;
416 /* long doubles have different sizes due to alignment on different
420 case 128: be_emit_char('t'); return;
423 assert(mode_is_int(mode) || mode_is_reference(mode));
424 switch (get_mode_size_bits(mode)) {
425 case 16: be_emit_char('s'); return;
426 case 32: be_emit_char('l'); return;
427 /* gas docu says q is the suffix but gcc, objdump and icc use ll
429 case 64: be_emit_cstring("ll"); return;
432 panic("Can't output mode_suffix for %+F", mode);
435 static char get_xmm_mode_suffix(ir_mode *mode)
437 assert(mode_is_float(mode));
438 switch (get_mode_size_bits(mode)) {
441 default: panic("Invalid XMM mode");
445 void ia32_emit_xmm_mode_suffix(const ir_node *node)
447 ir_mode *mode = get_ia32_ls_mode(node);
448 assert(mode != NULL);
450 be_emit_char(get_xmm_mode_suffix(mode));
453 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
455 ir_mode *mode = get_ia32_ls_mode(node);
456 assert(mode != NULL);
457 be_emit_char(get_xmm_mode_suffix(mode));
460 void ia32_emit_extend_suffix(const ir_node *node)
462 ir_mode *mode = get_ia32_ls_mode(node);
463 if (get_mode_size_bits(mode) == 32)
465 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
466 ia32_emit_mode_suffix_mode(mode);
469 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
471 ir_node *in = get_irn_n(node, pos);
472 if (is_ia32_Immediate(in)) {
473 emit_ia32_Immediate(in);
475 const ir_mode *mode = get_ia32_ls_mode(node);
476 const arch_register_t *reg = get_in_reg(node, pos);
477 emit_register(reg, mode);
482 * Returns the target block for a control flow node.
484 static ir_node *get_cfop_target_block(const ir_node *irn)
486 assert(get_irn_mode(irn) == mode_X);
487 return get_irn_link(irn);
491 * Emits the target label for a control flow node.
493 static void ia32_emit_cfop_target(const ir_node *node)
495 ir_node *block = get_cfop_target_block(node);
496 be_gas_emit_block_name(block);
500 * positive conditions for signed compares
502 static const char *const cmp2condition_s[] = {
503 NULL, /* always false */
510 NULL /* always true */
514 * positive conditions for unsigned compares
516 static const char *const cmp2condition_u[] = {
517 NULL, /* always false */
524 NULL /* always true */
528 * Emit the suffix for a compare instruction.
530 static void ia32_emit_cmp_suffix(int pnc)
534 if (pnc == ia32_pn_Cmp_parity) {
539 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
540 str = cmp2condition_u[pnc & 7];
542 str = cmp2condition_s[pnc & 7];
548 typedef enum ia32_emit_mod_t {
549 EMIT_RESPECT_LS = 1U << 0,
550 EMIT_ALTERNATE_AM = 1U << 1,
552 EMIT_HIGH_REG = 1U << 3,
553 EMIT_LOW_REG = 1U << 4
557 * Emits address mode.
559 void ia32_emit_am(const ir_node *node)
561 ir_entity *ent = get_ia32_am_sc(node);
562 int offs = get_ia32_am_offs_int(node);
563 ir_node *base = get_irn_n(node, n_ia32_base);
564 int has_base = !is_ia32_NoReg_GP(base);
565 ir_node *index = get_irn_n(node, n_ia32_index);
566 int has_index = !is_ia32_NoReg_GP(index);
568 /* just to be sure... */
569 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
573 const ia32_attr_t *attr = get_ia32_attr_const(node);
574 if (is_ia32_am_sc_sign(node))
576 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
579 /* also handle special case if nothing is set */
580 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
582 be_emit_irprintf("%+d", offs);
584 be_emit_irprintf("%d", offs);
588 if (has_base || has_index) {
593 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
594 emit_register(reg, NULL);
597 /* emit index + scale */
599 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
602 emit_register(reg, NULL);
604 scale = get_ia32_am_scale(node);
606 be_emit_irprintf(",%d", 1 << scale);
614 * fmt parameter output
615 * ---- ---------------------- ---------------------------------------------
617 * %AM <node> address mode of the node
618 * %AR const arch_register_t* address mode of the node or register
619 * %ASx <node> address mode of the node or source register x
620 * %Dx <node> destination register x
621 * %I <node> immediate of the node
622 * %L <node> control flow target of the node
623 * %M <node> mode suffix of the node
624 * %P int condition code
625 * %R const arch_register_t* register
626 * %Sx <node> source register x
627 * %s const char* string
628 * %u unsigned int unsigned int
629 * %d signed int signed int
632 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
633 * * modifier does not prefix immediates with $, but AM with *
634 * l modifier for %lu and %ld
635 * > modifier to output high 8bit register (ah, bh)
636 * < modifier to output low 8bit register (al, bl)
638 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
644 const char *start = fmt;
645 ia32_emit_mod_t mod = 0;
647 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
650 be_emit_string_len(start, fmt - start);
654 be_emit_finish_line_gas(node);
667 case '*': mod |= EMIT_ALTERNATE_AM; break;
668 case '#': mod |= EMIT_RESPECT_LS; break;
669 case 'l': mod |= EMIT_LONG; break;
670 case '>': mod |= EMIT_HIGH_REG; break;
671 case '<': mod |= EMIT_LOW_REG; break;
688 if (mod & EMIT_ALTERNATE_AM)
694 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
695 if (get_ia32_op_type(node) == ia32_AddrModeS) {
698 if (mod & EMIT_ALTERNATE_AM)
700 emit_register(reg, NULL);
706 if (get_ia32_op_type(node) == ia32_AddrModeS) {
710 assert(get_ia32_op_type(node) == ia32_Normal);
715 default: goto unknown;
722 const arch_register_t *reg;
724 if (*fmt < '0' || '9' <= *fmt)
728 reg = get_out_reg(node, pos);
729 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
734 if (!(mod & EMIT_ALTERNATE_AM))
736 emit_ia32_Immediate_no_prefix(node);
740 ia32_emit_cfop_target(node);
744 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
749 int pnc = va_arg(ap, int);
750 ia32_emit_cmp_suffix(pnc);
755 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
756 if (mod & EMIT_HIGH_REG) {
757 emit_8bit_register_high(reg);
758 } else if (mod & EMIT_LOW_REG) {
759 emit_8bit_register(reg);
761 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
771 if (*fmt < '0' || '9' <= *fmt)
775 in = get_irn_n(node, pos);
776 if (is_ia32_Immediate(in)) {
777 if (!(mod & EMIT_ALTERNATE_AM))
779 emit_ia32_Immediate_no_prefix(in);
781 const arch_register_t *reg;
783 if (mod & EMIT_ALTERNATE_AM)
785 reg = get_in_reg(node, pos);
786 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
792 const char *str = va_arg(ap, const char*);
798 if (mod & EMIT_LONG) {
799 unsigned long num = va_arg(ap, unsigned long);
800 be_emit_irprintf("%lu", num);
802 unsigned num = va_arg(ap, unsigned);
803 be_emit_irprintf("%u", num);
808 if (mod & EMIT_LONG) {
809 long num = va_arg(ap, long);
810 be_emit_irprintf("%ld", num);
812 int num = va_arg(ap, int);
813 be_emit_irprintf("%d", num);
819 panic("unknown format conversion in ia32_emitf()");
827 * Emits registers and/or address mode of a binary operation.
829 void ia32_emit_binop(const ir_node *node)
831 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
832 ia32_emitf(node, "%#S4, %#AS3");
834 ia32_emitf(node, "%#AS4, %#S3");
839 * Emits registers and/or address mode of a binary operation.
841 void ia32_emit_x87_binop(const ir_node *node)
843 switch (get_ia32_op_type(node)) {
846 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
847 const arch_register_t *in1 = x87_attr->x87[0];
848 const arch_register_t *in = x87_attr->x87[1];
849 const arch_register_t *out = x87_attr->x87[2];
853 } else if (out == in) {
858 be_emit_string(arch_register_get_name(in));
859 be_emit_cstring(", %");
860 be_emit_string(arch_register_get_name(out));
868 assert(0 && "unsupported op type");
873 * Emits registers and/or address mode of a unary operation.
875 void ia32_emit_unop(const ir_node *node, int pos)
879 ia32_emitf(node, fmt);
882 static void emit_ia32_IMul(const ir_node *node)
884 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
885 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
887 /* do we need the 3-address form? */
888 if (is_ia32_NoReg_GP(left) ||
889 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
890 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
892 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
897 * walks up a tree of copies/perms/spills/reloads to find the original value
898 * that is moved around
900 static ir_node *find_original_value(ir_node *node)
902 if (irn_visited(node))
905 mark_irn_visited(node);
906 if (be_is_Copy(node)) {
907 return find_original_value(be_get_Copy_op(node));
908 } else if (be_is_CopyKeep(node)) {
909 return find_original_value(be_get_CopyKeep_op(node));
910 } else if (is_Proj(node)) {
911 ir_node *pred = get_Proj_pred(node);
912 if (be_is_Perm(pred)) {
913 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
914 } else if (be_is_MemPerm(pred)) {
915 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
916 } else if (is_ia32_Load(pred)) {
917 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
921 } else if (is_ia32_Store(node)) {
922 return find_original_value(get_irn_n(node, n_ia32_Store_val));
923 } else if (is_Phi(node)) {
925 arity = get_irn_arity(node);
926 for (i = 0; i < arity; ++i) {
927 ir_node *in = get_irn_n(node, i);
928 ir_node *res = find_original_value(in);
939 static int determine_final_pnc(const ir_node *node, int flags_pos, int pnc)
941 ir_node *flags = get_irn_n(node, flags_pos);
942 const ia32_attr_t *flags_attr;
943 flags = skip_Proj(flags);
945 if (is_ia32_Sahf(flags)) {
946 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
947 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
948 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
949 inc_irg_visited(current_ir_graph);
950 cmp = find_original_value(cmp);
952 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
953 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
956 flags_attr = get_ia32_attr_const(cmp);
957 if (flags_attr->data.ins_permuted)
958 pnc = get_mirrored_pnc(pnc);
959 pnc |= ia32_pn_Cmp_float;
960 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
961 || is_ia32_Fucompi(flags)) {
962 flags_attr = get_ia32_attr_const(flags);
964 if (flags_attr->data.ins_permuted)
965 pnc = get_mirrored_pnc(pnc);
966 pnc |= ia32_pn_Cmp_float;
968 flags_attr = get_ia32_attr_const(flags);
970 if (flags_attr->data.ins_permuted)
971 pnc = get_mirrored_pnc(pnc);
972 if (flags_attr->data.cmp_unsigned)
973 pnc |= ia32_pn_Cmp_unsigned;
979 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
981 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
982 return get_negated_pnc(pnc, mode);
985 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
987 pn_Cmp pnc = get_ia32_condcode(node);
988 pnc = determine_final_pnc(node, flags_pos, pnc);
990 ia32_emit_cmp_suffix(pnc);
994 * Emits an exception label for a given node.
996 static void ia32_emit_exc_label(const ir_node *node)
998 be_emit_string(be_gas_insn_label_prefix());
999 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1003 * Returns the Proj with projection number proj and NOT mode_M
1005 static ir_node *get_proj(const ir_node *node, long proj)
1007 const ir_edge_t *edge;
1010 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1012 foreach_out_edge(node, edge) {
1013 src = get_edge_src_irn(edge);
1015 assert(is_Proj(src) && "Proj expected");
1016 if (get_irn_mode(src) == mode_M)
1019 if (get_Proj_proj(src) == proj)
1025 static int can_be_fallthrough(const ir_node *node)
1027 ir_node *target_block = get_cfop_target_block(node);
1028 ir_node *block = get_nodes_block(node);
1029 return get_prev_block_sched(target_block) == block;
1033 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1035 static void emit_ia32_Jcc(const ir_node *node)
1037 int need_parity_label = 0;
1038 const ir_node *proj_true;
1039 const ir_node *proj_false;
1040 pn_Cmp pnc = get_ia32_condcode(node);
1042 pnc = determine_final_pnc(node, 0, pnc);
1044 /* get both Projs */
1045 proj_true = get_proj(node, pn_ia32_Jcc_true);
1046 assert(proj_true && "Jcc without true Proj");
1048 proj_false = get_proj(node, pn_ia32_Jcc_false);
1049 assert(proj_false && "Jcc without false Proj");
1051 if (can_be_fallthrough(proj_true)) {
1052 /* exchange both proj's so the second one can be omitted */
1053 const ir_node *t = proj_true;
1055 proj_true = proj_false;
1057 pnc = ia32_get_negated_pnc(pnc);
1060 if (pnc & ia32_pn_Cmp_float) {
1061 /* Some floating point comparisons require a test of the parity flag,
1062 * which indicates that the result is unordered */
1063 switch (pnc & 0x0f) {
1065 ia32_emitf(proj_true, "\tjp %L\n");
1070 ia32_emitf(proj_true, "\tjnp %L\n");
1076 /* we need a local label if the false proj is a fallthrough
1077 * as the falseblock might have no label emitted then */
1078 if (can_be_fallthrough(proj_false)) {
1079 need_parity_label = 1;
1080 ia32_emitf(proj_false, "\tjp 1f\n");
1082 ia32_emitf(proj_false, "\tjp %L\n");
1089 ia32_emitf(proj_true, "\tjp %L\n");
1097 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1100 if (need_parity_label) {
1101 ia32_emitf(NULL, "1:\n");
1104 /* the second Proj might be a fallthrough */
1105 if (can_be_fallthrough(proj_false)) {
1106 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1108 ia32_emitf(proj_false, "\tjmp %L\n");
1113 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1116 static void emit_ia32_Setcc(const ir_node *node)
1118 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1120 pn_Cmp pnc = get_ia32_condcode(node);
1121 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1122 if (pnc & ia32_pn_Cmp_float) {
1123 switch (pnc & 0x0f) {
1125 ia32_emitf(node, "\tsetp %#R\n", dreg);
1129 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1135 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1136 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1137 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1143 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1144 ia32_emitf(node, "\tsetp %>R\n", dreg);
1145 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1152 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1155 static void emit_ia32_CMovcc(const ir_node *node)
1157 const ia32_attr_t *attr = get_ia32_attr_const(node);
1158 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1159 pn_Cmp pnc = get_ia32_condcode(node);
1160 const arch_register_t *in_true;
1161 const arch_register_t *in_false;
1163 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1164 /* although you can't set ins_permuted in the constructor it might still
1165 * be set by memory operand folding
1166 * Permuting inputs of a cmov means the condition is negated!
1168 if (attr->data.ins_permuted)
1169 pnc = ia32_get_negated_pnc(pnc);
1171 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1172 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1174 /* should be same constraint fullfilled? */
1175 if (out == in_false) {
1176 /* yes -> nothing to do */
1177 } else if (out == in_true) {
1178 const arch_register_t *tmp;
1180 assert(get_ia32_op_type(node) == ia32_Normal);
1182 pnc = ia32_get_negated_pnc(pnc);
1189 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1192 /* TODO: handling of Nans isn't correct yet */
1193 if (pnc & ia32_pn_Cmp_float) {
1194 switch (pnc & 0x0f) {
1203 panic("CMov with floatingpoint compare/parity not supported yet");
1207 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1211 /* jump table entry (target and corresponding number) */
1212 typedef struct branch_t {
1217 /* jump table for switch generation */
1218 typedef struct jmp_tbl_t {
1219 ir_node *defProj; /**< default target */
1220 long min_value; /**< smallest switch case */
1221 long max_value; /**< largest switch case */
1222 long num_branches; /**< number of jumps */
1223 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1224 branch_t *branches; /**< jump array */
1228 * Compare two variables of type branch_t. Used to sort all switch cases
1230 static int ia32_cmp_branch_t(const void *a, const void *b)
1232 branch_t *b1 = (branch_t *)a;
1233 branch_t *b2 = (branch_t *)b;
1235 if (b1->value <= b2->value)
1241 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1247 const ir_edge_t *edge;
1249 /* fill the table structure */
1250 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1251 tbl->defProj = NULL;
1252 tbl->num_branches = get_irn_n_edges(node) - 1;
1253 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1254 tbl->min_value = LONG_MAX;
1255 tbl->max_value = LONG_MIN;
1257 default_pn = get_ia32_condcode(node);
1259 /* go over all proj's and collect them */
1260 foreach_out_edge(node, edge) {
1261 proj = get_edge_src_irn(edge);
1262 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1264 pnc = get_Proj_proj(proj);
1266 /* check for default proj */
1267 if (pnc == default_pn) {
1268 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1269 tbl->defProj = proj;
1271 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1272 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1274 /* create branch entry */
1275 tbl->branches[i].target = proj;
1276 tbl->branches[i].value = pnc;
1281 assert(i == tbl->num_branches);
1283 /* sort the branches by their number */
1284 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1288 * Emits code for a SwitchJmp (creates a jump table if
1289 * possible otherwise a cmp-jmp cascade). Port from
1292 static void emit_ia32_SwitchJmp(const ir_node *node)
1294 unsigned long interval;
1298 /* fill the table structure */
1299 generate_jump_table(&tbl, node);
1301 /* two-complement's magic make this work without overflow */
1302 interval = tbl.max_value - tbl.min_value;
1304 /* emit the table */
1305 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1306 ia32_emitf(tbl.defProj, "\tja %L\n");
1308 if (tbl.num_branches > 1) {
1310 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1312 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1313 ia32_emitf(NULL, "\t.align 4\n");
1314 ia32_emitf(NULL, "%s:\n", tbl.label);
1316 last_value = tbl.branches[0].value;
1317 for (i = 0; i != tbl.num_branches; ++i) {
1318 while (last_value != tbl.branches[i].value) {
1319 ia32_emitf(tbl.defProj, ".long %L\n");
1322 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1325 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1327 /* one jump is enough */
1328 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1335 * Emits code for a unconditional jump.
1337 static void emit_ia32_Jmp(const ir_node *node)
1341 /* for now, the code works for scheduled and non-schedules blocks */
1342 block = get_nodes_block(node);
1344 /* we have a block schedule */
1345 if (can_be_fallthrough(node)) {
1346 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1348 ia32_emitf(node, "\tjmp %L\n");
1353 * Emit an inline assembler operand.
1355 * @param node the ia32_ASM node
1356 * @param s points to the operand (a %c)
1358 * @return pointer to the first char in s NOT in the current operand
1360 static const char* emit_asm_operand(const ir_node *node, const char *s)
1362 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1363 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1365 const arch_register_t *reg;
1366 const ia32_asm_reg_t *asm_regs = attr->register_map;
1367 const ia32_asm_reg_t *asm_reg;
1368 const char *reg_name;
1377 /* parse modifiers */
1380 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1405 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1412 sscanf(s, "%d%n", &num, &p);
1414 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1421 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1423 "Error: Custom assembler references invalid input/output (%+F)\n",
1427 asm_reg = & asm_regs[num];
1428 assert(asm_reg->valid);
1431 if (asm_reg->use_input == 0) {
1432 reg = get_out_reg(node, asm_reg->inout_pos);
1434 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1436 /* might be an immediate value */
1437 if (is_ia32_Immediate(pred)) {
1438 emit_ia32_Immediate(pred);
1441 reg = get_in_reg(node, asm_reg->inout_pos);
1445 "Warning: no register assigned for %d asm op (%+F)\n",
1450 if (asm_reg->memory) {
1455 if (modifier != 0) {
1459 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1462 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1465 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1468 panic("Invalid asm op modifier");
1470 be_emit_string(reg_name);
1472 emit_register(reg, asm_reg->mode);
1475 if (asm_reg->memory) {
1483 * Emits code for an ASM pseudo op.
1485 static void emit_ia32_Asm(const ir_node *node)
1487 const void *gen_attr = get_irn_generic_attr_const(node);
1488 const ia32_asm_attr_t *attr
1489 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1490 ident *asm_text = attr->asm_text;
1491 const char *s = get_id_str(asm_text);
1493 ia32_emitf(node, "#APP\t\n");
1500 s = emit_asm_operand(node, s);
1506 ia32_emitf(NULL, "\n#NO_APP\n");
1511 * Emit movsb/w instructions to make mov count divideable by 4
1513 static void emit_CopyB_prolog(unsigned size)
1516 ia32_emitf(NULL, "\tmovsb\n");
1518 ia32_emitf(NULL, "\tmovsw\n");
1522 * Emit rep movsd instruction for memcopy.
1524 static void emit_ia32_CopyB(const ir_node *node)
1526 unsigned size = get_ia32_copyb_size(node);
1528 emit_CopyB_prolog(size);
1529 ia32_emitf(node, "\trep movsd\n");
1533 * Emits unrolled memcopy.
1535 static void emit_ia32_CopyB_i(const ir_node *node)
1537 unsigned size = get_ia32_copyb_size(node);
1539 emit_CopyB_prolog(size);
1543 ia32_emitf(NULL, "\tmovsd\n");
1549 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1551 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1554 ir_mode *ls_mode = get_ia32_ls_mode(node);
1555 int ls_bits = get_mode_size_bits(ls_mode);
1556 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1558 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1561 static void emit_ia32_Conv_I2FP(const ir_node *node)
1563 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1566 static void emit_ia32_Conv_FP2I(const ir_node *node)
1568 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1571 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1573 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1577 * Emits code for an Int conversion.
1579 static void emit_ia32_Conv_I2I(const ir_node *node)
1581 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1582 int signed_mode = mode_is_signed(smaller_mode);
1583 const char *sign_suffix;
1585 assert(!mode_is_float(smaller_mode));
1587 sign_suffix = signed_mode ? "s" : "z";
1588 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1594 static void emit_ia32_Call(const ir_node *node)
1596 /* Special case: Call must not have its immediates prefixed by $, instead
1597 * address mode is prefixed by *. */
1598 ia32_emitf(node, "\tcall %*AS3\n");
1603 * Emits code to increase stack pointer.
1605 static void emit_be_IncSP(const ir_node *node)
1607 int offs = be_get_IncSP_offset(node);
1613 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1615 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1620 * Emits code for Copy/CopyKeep.
1622 static void Copy_emitter(const ir_node *node, const ir_node *op)
1624 const arch_register_t *in = arch_get_irn_register(op);
1625 const arch_register_t *out = arch_get_irn_register(node);
1630 /* copies of vf nodes aren't real... */
1631 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1634 if (get_irn_mode(node) == mode_E) {
1635 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1637 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1641 static void emit_be_Copy(const ir_node *node)
1643 Copy_emitter(node, be_get_Copy_op(node));
1646 static void emit_be_CopyKeep(const ir_node *node)
1648 Copy_emitter(node, be_get_CopyKeep_op(node));
1652 * Emits code for exchange.
1654 static void emit_be_Perm(const ir_node *node)
1656 const arch_register_t *in0, *in1;
1657 const arch_register_class_t *cls0, *cls1;
1659 in0 = arch_get_irn_register(get_irn_n(node, 0));
1660 in1 = arch_get_irn_register(get_irn_n(node, 1));
1662 cls0 = arch_register_get_class(in0);
1663 cls1 = arch_register_get_class(in1);
1665 assert(cls0 == cls1 && "Register class mismatch at Perm");
1667 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1668 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1669 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1670 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1671 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1672 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1673 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1675 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1678 panic("unexpected register class in be_Perm (%+F)", node);
1683 * Emits code for Constant loading.
1685 static void emit_ia32_Const(const ir_node *node)
1687 ia32_emitf(node, "\tmovl %I, %D0\n");
1691 * Emits code to load the TLS base
1693 static void emit_ia32_LdTls(const ir_node *node)
1695 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1698 /* helper function for emit_ia32_Minus64Bit */
1699 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1701 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1704 /* helper function for emit_ia32_Minus64Bit */
1705 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1707 ia32_emitf(node, "\tnegl %R\n", reg);
1710 /* helper function for emit_ia32_Minus64Bit */
1711 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1713 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1716 /* helper function for emit_ia32_Minus64Bit */
1717 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1719 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1722 /* helper function for emit_ia32_Minus64Bit */
1723 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1725 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1728 /* helper function for emit_ia32_Minus64Bit */
1729 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1731 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1734 static void emit_ia32_Minus64Bit(const ir_node *node)
1736 const arch_register_t *in_lo = get_in_reg(node, 0);
1737 const arch_register_t *in_hi = get_in_reg(node, 1);
1738 const arch_register_t *out_lo = get_out_reg(node, 0);
1739 const arch_register_t *out_hi = get_out_reg(node, 1);
1741 if (out_lo == in_lo) {
1742 if (out_hi != in_hi) {
1743 /* a -> a, b -> d */
1746 /* a -> a, b -> b */
1749 } else if (out_lo == in_hi) {
1750 if (out_hi == in_lo) {
1751 /* a -> b, b -> a */
1752 emit_xchg(node, in_lo, in_hi);
1755 /* a -> b, b -> d */
1756 emit_mov(node, in_hi, out_hi);
1757 emit_mov(node, in_lo, out_lo);
1761 if (out_hi == in_lo) {
1762 /* a -> c, b -> a */
1763 emit_mov(node, in_lo, out_lo);
1765 } else if (out_hi == in_hi) {
1766 /* a -> c, b -> b */
1767 emit_mov(node, in_lo, out_lo);
1770 /* a -> c, b -> d */
1771 emit_mov(node, in_lo, out_lo);
1777 emit_neg( node, out_hi);
1778 emit_neg( node, out_lo);
1779 emit_sbb0(node, out_hi);
1783 emit_zero(node, out_hi);
1784 emit_neg( node, out_lo);
1785 emit_sbb( node, in_hi, out_hi);
1788 static void emit_ia32_GetEIP(const ir_node *node)
1790 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1791 ia32_emitf(NULL, "%s:\n", pic_base_label);
1792 ia32_emitf(node, "\tpopl %D0\n");
1795 static void emit_ia32_ClimbFrame(const ir_node *node)
1797 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1799 ia32_emitf(node, "\tmovl %S0, %D0\n");
1800 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1801 be_gas_emit_block_name(node);
1802 be_emit_cstring(":\n");
1803 be_emit_write_line();
1804 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1805 ia32_emitf(node, "\tdec %S1\n");
1806 be_emit_cstring("\tjnz ");
1807 be_gas_emit_block_name(node);
1808 be_emit_finish_line_gas(node);
1811 static void emit_be_Return(const ir_node *node)
1813 unsigned pop = be_Return_get_pop(node);
1815 if (pop > 0 || be_Return_get_emit_pop(node)) {
1816 ia32_emitf(node, "\tret $%u\n", pop);
1818 ia32_emitf(node, "\tret\n");
1822 static void emit_Nothing(const ir_node *node)
1829 * Enters the emitter functions for handled nodes into the generic
1830 * pointer of an opcode.
1832 static void ia32_register_emitters(void)
1834 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1835 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1836 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1837 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1838 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1839 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1841 /* first clear the generic function pointer for all ops */
1842 clear_irp_opcodes_generic_func();
1844 /* register all emitter functions defined in spec */
1845 ia32_register_spec_emitters();
1847 /* other ia32 emitter functions */
1848 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1853 IA32_EMIT(Conv_FP2FP);
1854 IA32_EMIT(Conv_FP2I);
1855 IA32_EMIT(Conv_I2FP);
1856 IA32_EMIT(Conv_I2I);
1864 IA32_EMIT(Minus64Bit);
1865 IA32_EMIT(SwitchJmp);
1866 IA32_EMIT(ClimbFrame);
1869 /* benode emitter */
1890 typedef void (*emit_func_ptr) (const ir_node *);
1893 * Assign and emit an exception label if the current instruction can fail.
1895 static void ia32_assign_exc_label(ir_node *node)
1897 /* assign a new ID to the instruction */
1898 set_ia32_exc_label_id(node, ++exc_label_id);
1900 ia32_emit_exc_label(node);
1902 be_emit_pad_comment();
1903 be_emit_cstring("/* exception to Block ");
1904 ia32_emit_cfop_target(node);
1905 be_emit_cstring(" */\n");
1906 be_emit_write_line();
1910 * Emits code for a node.
1912 static void ia32_emit_node(ir_node *node)
1914 ir_op *op = get_irn_op(node);
1916 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1918 if (is_ia32_irn(node)) {
1919 if (get_ia32_exc_label(node)) {
1920 /* emit the exception label of this instruction */
1921 ia32_assign_exc_label(node);
1923 if (mark_spill_reload) {
1924 if (is_ia32_is_spill(node)) {
1925 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1927 if (is_ia32_is_reload(node)) {
1928 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1930 if (is_ia32_is_remat(node)) {
1931 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1935 if (op->ops.generic) {
1936 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1938 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1943 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1949 * Emits gas alignment directives
1951 static void ia32_emit_alignment(unsigned align, unsigned skip)
1953 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1957 * Emits gas alignment directives for Labels depended on cpu architecture.
1959 static void ia32_emit_align_label(void)
1961 unsigned align = ia32_cg_config.label_alignment;
1962 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1963 ia32_emit_alignment(align, maximum_skip);
1967 * Test whether a block should be aligned.
1968 * For cpus in the P4/Athlon class it is useful to align jump labels to
1969 * 16 bytes. However we should only do that if the alignment nops before the
1970 * label aren't executed more often than we have jumps to the label.
1972 static int should_align_block(const ir_node *block)
1974 static const double DELTA = .0001;
1975 ir_exec_freq *exec_freq = be_get_irg_exec_freq(cg->irg);
1976 ir_node *prev = get_prev_block_sched(block);
1978 double prev_freq = 0; /**< execfreq of the fallthrough block */
1979 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1982 if (exec_freq == NULL)
1984 if (ia32_cg_config.label_alignment_factor <= 0)
1987 block_freq = get_block_execfreq(exec_freq, block);
1988 if (block_freq < DELTA)
1991 n_cfgpreds = get_Block_n_cfgpreds(block);
1992 for (i = 0; i < n_cfgpreds; ++i) {
1993 const ir_node *pred = get_Block_cfgpred_block(block, i);
1994 double pred_freq = get_block_execfreq(exec_freq, pred);
1997 prev_freq += pred_freq;
1999 jmp_freq += pred_freq;
2003 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2006 jmp_freq /= prev_freq;
2008 return jmp_freq > ia32_cg_config.label_alignment_factor;
2012 * Emit the block header for a block.
2014 * @param block the block
2015 * @param prev_block the previous block
2017 static void ia32_emit_block_header(ir_node *block)
2019 ir_graph *irg = current_ir_graph;
2020 int need_label = block_needs_label(block);
2022 ir_exec_freq *exec_freq = be_get_irg_exec_freq(cg->irg);
2024 if (block == get_irg_end_block(irg))
2027 if (ia32_cg_config.label_alignment > 0) {
2028 /* align the current block if:
2029 * a) if should be aligned due to its execution frequency
2030 * b) there is no fall-through here
2032 if (should_align_block(block)) {
2033 ia32_emit_align_label();
2035 /* if the predecessor block has no fall-through,
2036 we can always align the label. */
2038 int has_fallthrough = 0;
2040 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2041 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2042 if (can_be_fallthrough(cfg_pred)) {
2043 has_fallthrough = 1;
2048 if (!has_fallthrough)
2049 ia32_emit_align_label();
2054 be_gas_emit_block_name(block);
2057 be_emit_pad_comment();
2058 be_emit_cstring(" /* ");
2060 be_emit_cstring("\t/* ");
2061 be_gas_emit_block_name(block);
2062 be_emit_cstring(": ");
2065 be_emit_cstring("preds:");
2067 /* emit list of pred blocks in comment */
2068 arity = get_irn_arity(block);
2070 be_emit_cstring(" none");
2072 for (i = 0; i < arity; ++i) {
2073 ir_node *predblock = get_Block_cfgpred_block(block, i);
2074 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2077 if (exec_freq != NULL) {
2078 be_emit_irprintf(", freq: %f",
2079 get_block_execfreq(exec_freq, block));
2081 be_emit_cstring(" */\n");
2082 be_emit_write_line();
2086 * Walks over the nodes in a block connected by scheduling edges
2087 * and emits code for each node.
2089 static void ia32_gen_block(ir_node *block)
2093 ia32_emit_block_header(block);
2095 /* emit the contents of the block */
2096 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2097 sched_foreach(block, node) {
2098 ia32_emit_node(node);
2102 typedef struct exc_entry {
2103 ir_node *exc_instr; /** The instruction that can issue an exception. */
2104 ir_node *block; /** The block to call then. */
2109 * Sets labels for control flow nodes (jump target).
2110 * Links control predecessors to there destination blocks.
2112 static void ia32_gen_labels(ir_node *block, void *data)
2114 exc_entry **exc_list = data;
2118 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2119 pred = get_Block_cfgpred(block, n);
2120 set_irn_link(pred, block);
2122 pred = skip_Proj(pred);
2123 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2128 ARR_APP1(exc_entry, *exc_list, e);
2129 set_irn_link(pred, block);
2135 * Compare two exception_entries.
2137 static int cmp_exc_entry(const void *a, const void *b)
2139 const exc_entry *ea = a;
2140 const exc_entry *eb = b;
2142 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2148 * Main driver. Emits the code for one routine.
2150 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2152 ir_entity *entity = get_irg_entity(irg);
2153 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2158 do_pic = be_get_irg_options(cg->irg)->pic;
2160 be_gas_elf_type_char = '@';
2162 ia32_register_emitters();
2164 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2166 be_dbg_method_begin(entity);
2167 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2169 /* we use links to point to target blocks */
2170 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2171 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2173 /* initialize next block links */
2174 n = ARR_LEN(cg->blk_sched);
2175 for (i = 0; i < n; ++i) {
2176 ir_node *block = cg->blk_sched[i];
2177 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2179 set_irn_link(block, prev);
2182 for (i = 0; i < n; ++i) {
2183 ir_node *block = cg->blk_sched[i];
2185 ia32_gen_block(block);
2188 be_gas_emit_function_epilog(entity);
2189 be_dbg_method_end();
2191 be_emit_write_line();
2193 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2195 /* Sort the exception table using the exception label id's.
2196 Those are ascending with ascending addresses. */
2197 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2201 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2202 be_emit_cstring("\t.long ");
2203 ia32_emit_exc_label(exc_list[i].exc_instr);
2205 be_emit_cstring("\t.long ");
2206 be_gas_emit_block_name(exc_list[i].block);
2210 DEL_ARR_F(exc_list);
2213 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2214 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2218 /* ==== Experimental binary emitter ==== */
2220 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2221 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2222 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2223 static unsigned char pnc_map_signed[8];
2224 static unsigned char pnc_map_unsigned[8];
2226 static void build_reg_map(void)
2228 reg_gp_map[REG_EAX] = 0x0;
2229 reg_gp_map[REG_ECX] = 0x1;
2230 reg_gp_map[REG_EDX] = 0x2;
2231 reg_gp_map[REG_EBX] = 0x3;
2232 reg_gp_map[REG_ESP] = 0x4;
2233 reg_gp_map[REG_EBP] = 0x5;
2234 reg_gp_map[REG_ESI] = 0x6;
2235 reg_gp_map[REG_EDI] = 0x7;
2237 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2238 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2239 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2240 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2241 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2242 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2244 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2245 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2246 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2247 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2248 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2249 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2252 /** Returns the encoding for a pnc field. */
2253 static unsigned char pnc2cc(int pnc)
2256 if (pnc == ia32_pn_Cmp_parity) {
2258 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2259 cc = pnc_map_unsigned[pnc & 0x07];
2261 cc = pnc_map_signed[pnc & 0x07];
2267 /** Sign extension bit values for binops */
2269 UNSIGNED_IMM = 0, /**< unsigned immediate */
2270 SIGNEXT_IMM = 2, /**< sign extended immediate */
2273 /** The mod encoding of the ModR/M */
2275 MOD_IND = 0x00, /**< [reg1] */
2276 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2277 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2278 MOD_REG = 0xC0 /**< reg1 */
2281 /** create R/M encoding for ModR/M */
2282 #define ENC_RM(x) (x)
2283 /** create REG encoding for ModR/M */
2284 #define ENC_REG(x) ((x) << 3)
2286 /** create encoding for a SIB byte */
2287 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2289 /* Node: The following routines are supposed to append bytes, words, dwords
2290 to the output stream.
2291 Currently the implementation is stupid in that it still creates output
2292 for an "assembler" in the form of .byte, .long
2293 We will change this when enough infrastructure is there to create complete
2294 machine code in memory/object files */
2296 static void bemit8(const unsigned char byte)
2298 be_emit_irprintf("\t.byte 0x%x\n", byte);
2299 be_emit_write_line();
2302 static void bemit16(const unsigned short u16)
2304 be_emit_irprintf("\t.word 0x%x\n", u16);
2305 be_emit_write_line();
2308 static void bemit32(const unsigned u32)
2310 be_emit_irprintf("\t.long 0x%x\n", u32);
2311 be_emit_write_line();
2315 * Emit address of an entity. If @p is_relative is true then a relative
2316 * offset from behind the address to the entity is created.
2318 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2321 if (entity == NULL) {
2326 /* the final version should remember the position in the bytestream
2327 and patch it with the correct address at linktime... */
2328 be_emit_cstring("\t.long ");
2331 be_gas_emit_entity(entity);
2333 if (get_entity_owner(entity) == get_tls_type()) {
2334 if (get_entity_visibility(entity) == ir_visibility_external) {
2335 be_emit_cstring("@INDNTPOFF");
2337 be_emit_cstring("@NTPOFF");
2342 be_emit_cstring("-.");
2347 be_emit_irprintf("%+d", offset);
2350 be_emit_write_line();
2353 static void bemit_jmp_destination(const ir_node *dest_block)
2355 be_emit_cstring("\t.long ");
2356 be_gas_emit_block_name(dest_block);
2357 be_emit_cstring(" - . - 4\n");
2358 be_emit_write_line();
2361 /* end emit routines, all emitters following here should only use the functions
2364 typedef enum reg_modifier {
2369 /** Create a ModR/M byte for src1,src2 registers */
2370 static void bemit_modrr(const arch_register_t *src1,
2371 const arch_register_t *src2)
2373 unsigned char modrm = MOD_REG;
2374 modrm |= ENC_RM(reg_gp_map[src1->index]);
2375 modrm |= ENC_REG(reg_gp_map[src2->index]);
2379 /** Create a ModR/M8 byte for src1,src2 registers */
2380 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2381 reg_modifier_t high_part2, const arch_register_t *src2)
2383 unsigned char modrm = MOD_REG;
2384 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2385 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2389 /** Create a ModR/M byte for one register and extension */
2390 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2392 unsigned char modrm = MOD_REG;
2394 modrm |= ENC_RM(reg_gp_map[reg->index]);
2395 modrm |= ENC_REG(ext);
2399 /** Create a ModR/M8 byte for one register */
2400 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2402 unsigned char modrm = MOD_REG;
2403 assert(reg_gp_map[reg->index] < 4);
2404 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2410 * Calculate the size of an signed immediate in bytes.
2412 * @param offset an offset
2414 static unsigned get_signed_imm_size(int offset)
2416 if (-128 <= offset && offset < 128) {
2418 } else if (-32768 <= offset && offset < 32768) {
2426 * Emit an address mode.
2428 * @param reg content of the reg field: either a register index or an opcode extension
2429 * @param node the node
2431 static void bemit_mod_am(unsigned reg, const ir_node *node)
2433 ir_entity *ent = get_ia32_am_sc(node);
2434 int offs = get_ia32_am_offs_int(node);
2435 ir_node *base = get_irn_n(node, n_ia32_base);
2436 int has_base = !is_ia32_NoReg_GP(base);
2437 ir_node *index = get_irn_n(node, n_ia32_index);
2438 int has_index = !is_ia32_NoReg_GP(index);
2441 unsigned emitoffs = 0;
2442 bool emitsib = false;
2445 /* set the mod part depending on displacement */
2447 modrm |= MOD_IND_WORD_OFS;
2449 } else if (offs == 0) {
2452 } else if (-128 <= offs && offs < 128) {
2453 modrm |= MOD_IND_BYTE_OFS;
2456 modrm |= MOD_IND_WORD_OFS;
2461 const arch_register_t *base_reg = arch_get_irn_register(base);
2462 base_enc = reg_gp_map[base_reg->index];
2464 /* Use the EBP encoding + MOD_IND if NO base register. There is
2465 * always a 32bit offset present in this case. */
2471 /* Determine if we need a SIB byte. */
2473 const arch_register_t *reg_index = arch_get_irn_register(index);
2474 int scale = get_ia32_am_scale(node);
2476 /* R/M set to ESP means SIB in 32bit mode. */
2477 modrm |= ENC_RM(0x04);
2478 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2480 } else if (base_enc == 0x04) {
2481 /* for the above reason we are forced to emit a SIB when base is ESP.
2482 * Only the base is used, index must be ESP too, which means no index.
2484 modrm |= ENC_RM(0x04);
2485 sib = ENC_SIB(0, 0x04, 0x04);
2488 modrm |= ENC_RM(base_enc);
2491 /* We are forced to emit an 8bit offset as EBP base without offset is a
2492 * special case for SIB without base register. */
2493 if (base_enc == 0x05 && emitoffs == 0) {
2494 modrm |= MOD_IND_BYTE_OFS;
2498 modrm |= ENC_REG(reg);
2504 /* emit displacement */
2505 if (emitoffs == 8) {
2506 bemit8((unsigned) offs);
2507 } else if (emitoffs == 32) {
2508 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2513 * Emit a binop with a immediate operand.
2515 * @param node the node to emit
2516 * @param opcode_eax the opcode for the op eax, imm variant
2517 * @param opcode the opcode for the reg, imm variant
2518 * @param ruval the opcode extension for opcode
2520 static void bemit_binop_with_imm(
2521 const ir_node *node,
2522 unsigned char opcode_ax,
2523 unsigned char opcode, unsigned char ruval)
2525 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2526 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2527 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2530 /* Some instructions (test) have no short form with 32bit value + 8bit
2532 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2535 /* check for sign extension */
2536 size = get_signed_imm_size(attr->offset);
2541 bemit8(opcode | SIGNEXT_IMM);
2542 /* cmp has this special mode */
2543 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2544 bemit_mod_am(ruval, node);
2546 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2547 bemit_modru(reg, ruval);
2549 bemit8((unsigned char)attr->offset);
2553 /* check for eax variant: this variant is shorter for 32bit immediates only */
2554 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2556 bemit_mod_am(ruval, node);
2558 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2559 if (reg->index == REG_EAX) {
2563 bemit_modru(reg, ruval);
2566 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2569 panic("invalid imm size?!?");
2575 static void bemit_binop_2(const ir_node *node, unsigned code)
2577 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2579 if (get_ia32_op_type(node) == ia32_Normal) {
2580 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2581 bemit_modrr(op2, out);
2583 bemit_mod_am(reg_gp_map[out->index], node);
2590 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2592 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2593 if (is_ia32_Immediate(right)) {
2594 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2596 bemit_binop_2(node, opcodes[0]);
2603 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2606 if (get_ia32_op_type(node) == ia32_Normal) {
2607 const arch_register_t *in = get_in_reg(node, input);
2608 bemit_modru(in, ext);
2610 bemit_mod_am(ext, node);
2614 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2616 const arch_register_t *out = get_out_reg(node, 0);
2617 bemit_unop(node, code, reg_gp_map[out->index], input);
2620 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2622 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2625 bemit8(size == 8 ? code : code + 1);
2626 bemit_mod_am(ext, node);
2629 static void bemit_immediate(const ir_node *node, bool relative)
2631 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2632 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2635 static void bemit_copy(const ir_node *copy)
2637 const arch_register_t *in = get_in_reg(copy, 0);
2638 const arch_register_t *out = get_out_reg(copy, 0);
2642 /* copies of vf nodes aren't real... */
2643 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2646 if (get_irn_mode(copy) == mode_E) {
2649 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2651 bemit_modrr(in, out);
2655 static void bemit_perm(const ir_node *node)
2657 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2658 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2659 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2661 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2663 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2664 if (in0->index == REG_EAX) {
2665 bemit8(0x90 + reg_gp_map[in1->index]);
2666 } else if (in1->index == REG_EAX) {
2667 bemit8(0x90 + reg_gp_map[in0->index]);
2670 bemit_modrr(in0, in1);
2672 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2673 panic("unimplemented"); // TODO implement
2674 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2675 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2676 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2677 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2679 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2682 panic("unexpected register class in be_Perm (%+F)", node);
2686 static void bemit_xor0(const ir_node *node)
2688 const arch_register_t *out = get_out_reg(node, 0);
2690 bemit_modrr(out, out);
2693 static void bemit_mov_const(const ir_node *node)
2695 const arch_register_t *out = get_out_reg(node, 0);
2696 bemit8(0xB8 + reg_gp_map[out->index]);
2697 bemit_immediate(node, false);
2701 * Creates a function for a Binop with 3 possible encodings.
2703 #define BINOP(op, op0, op1, op2, op2_ext) \
2704 static void bemit_ ## op(const ir_node *node) { \
2705 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2706 bemit_binop(node, op ## _codes); \
2709 /* insn def eax,imm imm */
2710 BINOP(add, 0x03, 0x05, 0x81, 0)
2711 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2712 BINOP(adc, 0x13, 0x15, 0x81, 2)
2713 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2714 BINOP(and, 0x23, 0x25, 0x81, 4)
2715 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2716 BINOP(xor, 0x33, 0x35, 0x81, 6)
2717 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2719 #define BINOPMEM(op, ext) \
2720 static void bemit_##op(const ir_node *node) \
2723 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2726 val = get_irn_n(node, n_ia32_unary_op); \
2727 if (is_ia32_Immediate(val)) { \
2728 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2729 int offset = attr->offset; \
2730 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2732 bemit_mod_am(ext, node); \
2736 bemit_mod_am(ext, node); \
2740 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2744 bemit8(ext << 3 | 1); \
2745 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2749 static void bemit_##op##8bit(const ir_node *node) \
2751 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2752 if (is_ia32_Immediate(val)) { \
2754 bemit_mod_am(ext, node); \
2755 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2758 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2770 * Creates a function for an Unop with code /ext encoding.
2772 #define UNOP(op, code, ext, input) \
2773 static void bemit_ ## op(const ir_node *node) { \
2774 bemit_unop(node, code, ext, input); \
2777 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2778 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2779 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2780 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2781 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2782 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2784 /* TODO: am support for IJmp */
2785 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2787 #define SHIFT(op, ext) \
2788 static void bemit_##op(const ir_node *node) \
2790 const arch_register_t *out = get_out_reg(node, 0); \
2791 ir_node *count = get_irn_n(node, 1); \
2792 if (is_ia32_Immediate(count)) { \
2793 int offset = get_ia32_immediate_attr_const(count)->offset; \
2794 if (offset == 1) { \
2796 bemit_modru(out, ext); \
2799 bemit_modru(out, ext); \
2804 bemit_modru(out, ext); \
2808 static void bemit_##op##mem(const ir_node *node) \
2811 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2814 count = get_irn_n(node, 1); \
2815 if (is_ia32_Immediate(count)) { \
2816 int offset = get_ia32_immediate_attr_const(count)->offset; \
2817 if (offset == 1) { \
2818 bemit8(size == 8 ? 0xD0 : 0xD1); \
2819 bemit_mod_am(ext, node); \
2821 bemit8(size == 8 ? 0xC0 : 0xC1); \
2822 bemit_mod_am(ext, node); \
2826 bemit8(size == 8 ? 0xD2 : 0xD3); \
2827 bemit_mod_am(ext, node); \
2837 static void bemit_shld(const ir_node *node)
2839 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2840 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2841 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2843 if (is_ia32_Immediate(count)) {
2845 bemit_modrr(out, in);
2846 bemit8(get_ia32_immediate_attr_const(count)->offset);
2849 bemit_modrr(out, in);
2853 static void bemit_shrd(const ir_node *node)
2855 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2856 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2857 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2859 if (is_ia32_Immediate(count)) {
2861 bemit_modrr(out, in);
2862 bemit8(get_ia32_immediate_attr_const(count)->offset);
2865 bemit_modrr(out, in);
2870 * binary emitter for setcc.
2872 static void bemit_setcc(const ir_node *node)
2874 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2876 pn_Cmp pnc = get_ia32_condcode(node);
2877 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
2878 if (pnc & ia32_pn_Cmp_float) {
2879 switch (pnc & 0x0f) {
2884 bemit_modrm8(REG_LOW, dreg);
2891 bemit_modrm8(REG_LOW, dreg);
2899 bemit8(0x90 | pnc2cc(pnc));
2900 bemit_modrm8(REG_LOW, dreg);
2905 bemit_modrm8(REG_HIGH, dreg);
2907 /* andb %>dreg, %<dreg */
2909 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2917 bemit8(0x90 | pnc2cc(pnc));
2918 bemit_modrm8(REG_LOW, dreg);
2923 bemit_modrm8(REG_HIGH, dreg);
2925 /* orb %>dreg, %<dreg */
2927 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2936 bemit8(0x90 | pnc2cc(pnc));
2937 bemit_modrm8(REG_LOW, dreg);
2940 static void bemit_cmovcc(const ir_node *node)
2942 const ia32_attr_t *attr = get_ia32_attr_const(node);
2943 int ins_permuted = attr->data.ins_permuted;
2944 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2945 pn_Cmp pnc = get_ia32_condcode(node);
2946 const arch_register_t *in_true;
2947 const arch_register_t *in_false;
2949 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
2951 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2952 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2954 /* should be same constraint fullfilled? */
2955 if (out == in_false) {
2956 /* yes -> nothing to do */
2957 } else if (out == in_true) {
2958 assert(get_ia32_op_type(node) == ia32_Normal);
2959 ins_permuted = !ins_permuted;
2963 bemit8(0x8B); // mov %in_false, %out
2964 bemit_modrr(in_false, out);
2968 pnc = ia32_get_negated_pnc(pnc);
2970 /* TODO: handling of Nans isn't correct yet */
2973 bemit8(0x40 | pnc2cc(pnc));
2974 if (get_ia32_op_type(node) == ia32_Normal) {
2975 bemit_modrr(in_true, out);
2977 bemit_mod_am(reg_gp_map[out->index], node);
2981 static void bemit_cmp(const ir_node *node)
2983 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2989 right = get_irn_n(node, n_ia32_binary_right);
2990 if (is_ia32_Immediate(right)) {
2991 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2992 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2993 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2996 if (attr->symconst != NULL) {
2999 /* check for sign extension */
3000 size = get_signed_imm_size(attr->offset);
3005 bemit8(0x81 | SIGNEXT_IMM);
3006 /* cmp has this special mode */
3007 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3008 bemit_mod_am(7, node);
3010 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3011 bemit_modru(reg, 7);
3013 bemit8((unsigned char)attr->offset);
3017 /* check for eax variant: this variant is shorter for 32bit immediates only */
3018 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3020 bemit_mod_am(7, node);
3022 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3023 if (reg->index == REG_EAX) {
3027 bemit_modru(reg, 7);
3030 if (ls_size == 16) {
3031 bemit16(attr->offset);
3033 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3037 panic("invalid imm size?!?");
3039 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3041 if (get_ia32_op_type(node) == ia32_Normal) {
3042 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3043 bemit_modrr(op2, out);
3045 bemit_mod_am(reg_gp_map[out->index], node);
3050 static void bemit_cmp8bit(const ir_node *node)
3052 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3053 if (is_ia32_Immediate(right)) {
3054 if (get_ia32_op_type(node) == ia32_Normal) {
3055 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3056 if (out->index == REG_EAX) {
3060 bemit_modru(out, 7);
3064 bemit_mod_am(7, node);
3066 bemit8(get_ia32_immediate_attr_const(right)->offset);
3068 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3070 if (get_ia32_op_type(node) == ia32_Normal) {
3071 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3072 bemit_modrr(out, in);
3074 bemit_mod_am(reg_gp_map[out->index], node);
3079 static void bemit_test8bit(const ir_node *node)
3081 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3082 if (is_ia32_Immediate(right)) {
3083 if (get_ia32_op_type(node) == ia32_Normal) {
3084 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3085 if (out->index == REG_EAX) {
3089 bemit_modru(out, 0);
3093 bemit_mod_am(0, node);
3095 bemit8(get_ia32_immediate_attr_const(right)->offset);
3097 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3099 if (get_ia32_op_type(node) == ia32_Normal) {
3100 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3101 bemit_modrr(out, in);
3103 bemit_mod_am(reg_gp_map[out->index], node);
3108 static void bemit_imul(const ir_node *node)
3110 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3111 /* Do we need the immediate form? */
3112 if (is_ia32_Immediate(right)) {
3113 int imm = get_ia32_immediate_attr_const(right)->offset;
3114 if (get_signed_imm_size(imm) == 1) {
3115 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3118 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3123 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3127 static void bemit_dec(const ir_node *node)
3129 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3130 bemit8(0x48 + reg_gp_map[out->index]);
3133 static void bemit_inc(const ir_node *node)
3135 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3136 bemit8(0x40 + reg_gp_map[out->index]);
3139 #define UNOPMEM(op, code, ext) \
3140 static void bemit_##op(const ir_node *node) \
3142 bemit_unop_mem(node, code, ext); \
3145 UNOPMEM(notmem, 0xF6, 2)
3146 UNOPMEM(negmem, 0xF6, 3)
3147 UNOPMEM(incmem, 0xFE, 0)
3148 UNOPMEM(decmem, 0xFE, 1)
3150 static void bemit_ldtls(const ir_node *node)
3152 const arch_register_t *out = get_out_reg(node, 0);
3154 bemit8(0x65); // gs:
3155 if (out->index == REG_EAX) {
3156 bemit8(0xA1); // movl 0, %eax
3158 bemit8(0x8B); // movl 0, %reg
3159 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3167 static void bemit_lea(const ir_node *node)
3169 const arch_register_t *out = get_out_reg(node, 0);
3171 bemit_mod_am(reg_gp_map[out->index], node);
3174 /* helper function for bemit_minus64bit */
3175 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3177 bemit8(0x8B); // movl %src, %dst
3178 bemit_modrr(src, dst);
3181 /* helper function for bemit_minus64bit */
3182 static void bemit_helper_neg(const arch_register_t *reg)
3184 bemit8(0xF7); // negl %reg
3185 bemit_modru(reg, 3);
3188 /* helper function for bemit_minus64bit */
3189 static void bemit_helper_sbb0(const arch_register_t *reg)
3191 bemit8(0x83); // sbbl $0, %reg
3192 bemit_modru(reg, 3);
3196 /* helper function for bemit_minus64bit */
3197 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3199 bemit8(0x1B); // sbbl %src, %dst
3200 bemit_modrr(src, dst);
3203 /* helper function for bemit_minus64bit */
3204 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3206 if (src->index == REG_EAX) {
3207 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3208 } else if (dst->index == REG_EAX) {
3209 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3211 bemit8(0x87); // xchgl %src, %dst
3212 bemit_modrr(src, dst);
3216 /* helper function for bemit_minus64bit */
3217 static void bemit_helper_zero(const arch_register_t *reg)
3219 bemit8(0x33); // xorl %reg, %reg
3220 bemit_modrr(reg, reg);
3223 static void bemit_minus64bit(const ir_node *node)
3225 const arch_register_t *in_lo = get_in_reg(node, 0);
3226 const arch_register_t *in_hi = get_in_reg(node, 1);
3227 const arch_register_t *out_lo = get_out_reg(node, 0);
3228 const arch_register_t *out_hi = get_out_reg(node, 1);
3230 if (out_lo == in_lo) {
3231 if (out_hi != in_hi) {
3232 /* a -> a, b -> d */
3235 /* a -> a, b -> b */
3238 } else if (out_lo == in_hi) {
3239 if (out_hi == in_lo) {
3240 /* a -> b, b -> a */
3241 bemit_helper_xchg(in_lo, in_hi);
3244 /* a -> b, b -> d */
3245 bemit_helper_mov(in_hi, out_hi);
3246 bemit_helper_mov(in_lo, out_lo);
3250 if (out_hi == in_lo) {
3251 /* a -> c, b -> a */
3252 bemit_helper_mov(in_lo, out_lo);
3254 } else if (out_hi == in_hi) {
3255 /* a -> c, b -> b */
3256 bemit_helper_mov(in_lo, out_lo);
3259 /* a -> c, b -> d */
3260 bemit_helper_mov(in_lo, out_lo);
3266 bemit_helper_neg( out_hi);
3267 bemit_helper_neg( out_lo);
3268 bemit_helper_sbb0(out_hi);
3272 bemit_helper_zero(out_hi);
3273 bemit_helper_neg( out_lo);
3274 bemit_helper_sbb( in_hi, out_hi);
3278 * Emit a single opcode.
3280 #define EMIT_SINGLEOP(op, code) \
3281 static void bemit_ ## op(const ir_node *node) { \
3286 //EMIT_SINGLEOP(daa, 0x27)
3287 //EMIT_SINGLEOP(das, 0x2F)
3288 //EMIT_SINGLEOP(aaa, 0x37)
3289 //EMIT_SINGLEOP(aas, 0x3F)
3290 //EMIT_SINGLEOP(nop, 0x90)
3291 EMIT_SINGLEOP(cwtl, 0x98)
3292 EMIT_SINGLEOP(cltd, 0x99)
3293 //EMIT_SINGLEOP(fwait, 0x9B)
3294 EMIT_SINGLEOP(sahf, 0x9E)
3295 //EMIT_SINGLEOP(popf, 0x9D)
3296 EMIT_SINGLEOP(leave, 0xC9)
3297 EMIT_SINGLEOP(int3, 0xCC)
3298 //EMIT_SINGLEOP(iret, 0xCF)
3299 //EMIT_SINGLEOP(xlat, 0xD7)
3300 //EMIT_SINGLEOP(lock, 0xF0)
3301 EMIT_SINGLEOP(rep, 0xF3)
3302 //EMIT_SINGLEOP(halt, 0xF4)
3303 EMIT_SINGLEOP(cmc, 0xF5)
3304 EMIT_SINGLEOP(stc, 0xF9)
3305 //EMIT_SINGLEOP(cli, 0xFA)
3306 //EMIT_SINGLEOP(sti, 0xFB)
3307 //EMIT_SINGLEOP(std, 0xFD)
3310 * Emits a MOV out, [MEM].
3312 static void bemit_load(const ir_node *node)
3314 const arch_register_t *out = get_out_reg(node, 0);
3316 if (out->index == REG_EAX) {
3317 ir_node *base = get_irn_n(node, n_ia32_base);
3318 int has_base = !is_ia32_NoReg_GP(base);
3319 ir_node *index = get_irn_n(node, n_ia32_index);
3320 int has_index = !is_ia32_NoReg_GP(index);
3321 if (!has_base && !has_index) {
3322 ir_entity *ent = get_ia32_am_sc(node);
3323 int offs = get_ia32_am_offs_int(node);
3324 /* load from constant address to EAX can be encoded
3327 bemit_entity(ent, 0, offs, false);
3332 bemit_mod_am(reg_gp_map[out->index], node);
3336 * Emits a MOV [mem], in.
3338 static void bemit_store(const ir_node *node)
3340 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3341 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3343 if (is_ia32_Immediate(value)) {
3346 bemit_mod_am(0, node);
3347 bemit8(get_ia32_immediate_attr_const(value)->offset);
3348 } else if (size == 16) {
3351 bemit_mod_am(0, node);
3352 bemit16(get_ia32_immediate_attr_const(value)->offset);
3355 bemit_mod_am(0, node);
3356 bemit_immediate(value, false);
3359 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3361 if (in->index == REG_EAX) {
3362 ir_node *base = get_irn_n(node, n_ia32_base);
3363 int has_base = !is_ia32_NoReg_GP(base);
3364 ir_node *index = get_irn_n(node, n_ia32_index);
3365 int has_index = !is_ia32_NoReg_GP(index);
3366 if (!has_base && !has_index) {
3367 ir_entity *ent = get_ia32_am_sc(node);
3368 int offs = get_ia32_am_offs_int(node);
3369 /* store to constant address from EAX can be encoded as
3370 * 0xA2/0xA3 [offset]*/
3378 bemit_entity(ent, 0, offs, false);
3390 bemit_mod_am(reg_gp_map[in->index], node);
3394 static void bemit_conv_i2i(const ir_node *node)
3396 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3405 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3406 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3407 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3413 static void bemit_push(const ir_node *node)
3415 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3417 if (is_ia32_Immediate(value)) {
3418 const ia32_immediate_attr_t *attr
3419 = get_ia32_immediate_attr_const(value);
3420 unsigned size = get_signed_imm_size(attr->offset);
3426 bemit8((unsigned char)attr->offset);
3431 bemit_immediate(value, false);
3434 } else if (is_ia32_NoReg_GP(value)) {
3436 bemit_mod_am(6, node);
3438 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3439 bemit8(0x50 + reg_gp_map[reg->index]);
3446 static void bemit_pop(const ir_node *node)
3448 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3449 bemit8(0x58 + reg_gp_map[reg->index]);
3452 static void bemit_popmem(const ir_node *node)
3455 bemit_mod_am(0, node);
3458 static void bemit_call(const ir_node *node)
3460 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3462 if (is_ia32_Immediate(proc)) {
3464 bemit_immediate(proc, true);
3466 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3470 static void bemit_jmp(const ir_node *dest_block)
3473 bemit_jmp_destination(dest_block);
3476 static void bemit_jump(const ir_node *node)
3478 if (can_be_fallthrough(node))
3481 bemit_jmp(get_cfop_target_block(node));
3484 static void bemit_jcc(int pnc, const ir_node *dest_block)
3486 unsigned char cc = pnc2cc(pnc);
3489 bemit_jmp_destination(dest_block);
3492 static void bemit_jp(bool odd, const ir_node *dest_block)
3496 bemit_jmp_destination(dest_block);
3499 static void bemit_ia32_jcc(const ir_node *node)
3501 int pnc = get_ia32_condcode(node);
3502 const ir_node *proj_true;
3503 const ir_node *proj_false;
3504 const ir_node *dest_true;
3505 const ir_node *dest_false;
3506 const ir_node *block;
3508 pnc = determine_final_pnc(node, 0, pnc);
3510 /* get both Projs */
3511 proj_true = get_proj(node, pn_ia32_Jcc_true);
3512 assert(proj_true && "Jcc without true Proj");
3514 proj_false = get_proj(node, pn_ia32_Jcc_false);
3515 assert(proj_false && "Jcc without false Proj");
3517 block = get_nodes_block(node);
3519 if (can_be_fallthrough(proj_true)) {
3520 /* exchange both proj's so the second one can be omitted */
3521 const ir_node *t = proj_true;
3523 proj_true = proj_false;
3525 pnc = ia32_get_negated_pnc(pnc);
3528 dest_true = get_cfop_target_block(proj_true);
3529 dest_false = get_cfop_target_block(proj_false);
3531 if (pnc & ia32_pn_Cmp_float) {
3532 /* Some floating point comparisons require a test of the parity flag,
3533 * which indicates that the result is unordered */
3536 bemit_jp(false, dest_true);
3541 bemit_jp(true, dest_true);
3547 /* we need a local label if the false proj is a fallthrough
3548 * as the falseblock might have no label emitted then */
3549 if (can_be_fallthrough(proj_false)) {
3551 bemit8(0x06); // jp + 6
3553 bemit_jp(false, dest_false);
3560 bemit_jp(false, dest_true);
3568 bemit_jcc(pnc, dest_true);
3571 /* the second Proj might be a fallthrough */
3572 if (can_be_fallthrough(proj_false)) {
3573 /* it's a fallthrough */
3575 bemit_jmp(dest_false);
3579 static void bemit_switchjmp(const ir_node *node)
3581 unsigned long interval;
3585 const arch_register_t *in;
3587 /* fill the table structure */
3588 generate_jump_table(&tbl, node);
3590 /* two-complement's magic make this work without overflow */
3591 interval = tbl.max_value - tbl.min_value;
3593 in = get_in_reg(node, 0);
3594 /* emit the table */
3595 if (get_signed_imm_size(interval) == 1) {
3596 bemit8(0x83); // cmpl $imm8, %in
3600 bemit8(0x81); // cmpl $imm32, %in
3604 bemit8(0x0F); // ja tbl.defProj
3606 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3608 if (tbl.num_branches > 1) {
3610 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3611 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3612 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3613 be_emit_irprintf("\t.long %s\n", tbl.label);
3615 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3616 be_emit_cstring(".align 4\n");
3617 be_emit_irprintf("%s:\n", tbl.label);
3619 last_value = tbl.branches[0].value;
3620 for (i = 0; i != tbl.num_branches; ++i) {
3621 while (last_value != tbl.branches[i].value) {
3622 ia32_emitf(tbl.defProj, ".long %L\n");
3625 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3628 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3630 /* one jump is enough */
3631 panic("switch only has one case");
3632 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3635 be_emit_write_line();
3643 static void bemit_return(const ir_node *node)
3645 unsigned pop = be_Return_get_pop(node);
3646 if (pop > 0 || be_Return_get_emit_pop(node)) {
3648 assert(pop <= 0xffff);
3655 static void bemit_subsp(const ir_node *node)
3657 const arch_register_t *out;
3660 /* mov %esp, %out */
3662 out = get_out_reg(node, 1);
3663 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3666 static void bemit_incsp(const ir_node *node)
3669 const arch_register_t *reg;
3673 offs = be_get_IncSP_offset(node);
3684 size = get_signed_imm_size(offs);
3685 bemit8(size == 1 ? 0x83 : 0x81);
3687 reg = get_out_reg(node, 0);
3688 bemit_modru(reg, ext);
3697 static void bemit_copybi(const ir_node *node)
3699 unsigned size = get_ia32_copyb_size(node);
3701 bemit8(0xA4); // movsb
3704 bemit8(0xA5); // movsw
3708 bemit8(0xA5); // movsl
3712 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3714 if (get_ia32_op_type(node) == ia32_Normal) {
3715 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3716 const arch_register_t *in1 = x87_attr->x87[0];
3717 const arch_register_t *in = x87_attr->x87[1];
3718 const arch_register_t *out = x87_attr->x87[2];
3722 } else if (out == in) {
3726 if (out->index == 0) {
3728 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3731 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3734 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3739 bemit_mod_am(code, node);
3743 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3745 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3746 const arch_register_t *out = x87_attr->x87[2];
3748 bemit8(code + out->index);
3751 static void bemit_fabs(const ir_node *node)
3759 static void bemit_fadd(const ir_node *node)
3761 bemit_fbinop(node, 0, 0);
3764 static void bemit_faddp(const ir_node *node)
3766 bemit_fbinopp(node, 0xC0);
3769 static void bemit_fchs(const ir_node *node)
3777 static void bemit_fdiv(const ir_node *node)
3779 bemit_fbinop(node, 6, 7);
3782 static void bemit_fdivp(const ir_node *node)
3784 bemit_fbinopp(node, 0xF8);
3787 static void bemit_fdivr(const ir_node *node)
3789 bemit_fbinop(node, 7, 6);
3792 static void bemit_fdivrp(const ir_node *node)
3794 bemit_fbinopp(node, 0xF0);
3797 static void bemit_fild(const ir_node *node)
3799 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3801 bemit8(0xDF); // filds
3802 bemit_mod_am(0, node);
3806 bemit8(0xDB); // fildl
3807 bemit_mod_am(0, node);
3811 bemit8(0xDF); // fildll
3812 bemit_mod_am(5, node);
3816 panic("invalid mode size");
3820 static void bemit_fist(const ir_node *node)
3822 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3824 bemit8(0xDF); // fists
3828 bemit8(0xDB); // fistl
3832 panic("invalid mode size");
3834 bemit_mod_am(2, node);
3837 static void bemit_fistp(const ir_node *node)
3839 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3841 bemit8(0xDF); // fistps
3842 bemit_mod_am(3, node);
3846 bemit8(0xDB); // fistpl
3847 bemit_mod_am(3, node);
3851 bemit8(0xDF); // fistpll
3852 bemit_mod_am(7, node);
3856 panic("invalid mode size");
3860 static void bemit_fld(const ir_node *node)
3862 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3864 bemit8(0xD9); // flds
3865 bemit_mod_am(0, node);
3869 bemit8(0xDD); // fldl
3870 bemit_mod_am(0, node);
3875 bemit8(0xDB); // fldt
3876 bemit_mod_am(5, node);
3880 panic("invalid mode size");
3884 static void bemit_fld1(const ir_node *node)
3888 bemit8(0xE8); // fld1
3891 static void bemit_fldcw(const ir_node *node)
3893 bemit8(0xD9); // fldcw
3894 bemit_mod_am(5, node);
3897 static void bemit_fldz(const ir_node *node)
3901 bemit8(0xEE); // fldz
3904 static void bemit_fmul(const ir_node *node)
3906 bemit_fbinop(node, 1, 1);
3909 static void bemit_fmulp(const ir_node *node)
3911 bemit_fbinopp(node, 0xC8);
3914 static void bemit_fpop(const ir_node *node)
3916 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3918 bemit8(0xD8 + attr->x87[0]->index);
3921 static void bemit_fpush(const ir_node *node)
3923 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3925 bemit8(0xC0 + attr->x87[0]->index);
3928 static void bemit_fpushcopy(const ir_node *node)
3930 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3932 bemit8(0xC0 + attr->x87[0]->index);
3935 static void bemit_fst(const ir_node *node)
3937 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3939 bemit8(0xD9); // fsts
3943 bemit8(0xDD); // fstl
3947 panic("invalid mode size");
3949 bemit_mod_am(2, node);
3952 static void bemit_fstp(const ir_node *node)
3954 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3956 bemit8(0xD9); // fstps
3957 bemit_mod_am(3, node);
3961 bemit8(0xDD); // fstpl
3962 bemit_mod_am(3, node);
3967 bemit8(0xDB); // fstpt
3968 bemit_mod_am(7, node);
3972 panic("invalid mode size");
3976 static void bemit_fsub(const ir_node *node)
3978 bemit_fbinop(node, 4, 5);
3981 static void bemit_fsubp(const ir_node *node)
3983 bemit_fbinopp(node, 0xE8);
3986 static void bemit_fsubr(const ir_node *node)
3988 bemit_fbinop(node, 5, 4);
3991 static void bemit_fsubrp(const ir_node *node)
3993 bemit_fbinopp(node, 0xE0);
3996 static void bemit_fnstcw(const ir_node *node)
3998 bemit8(0xD9); // fnstcw
3999 bemit_mod_am(7, node);
4002 static void bemit_fnstsw(void)
4004 bemit8(0xDF); // fnstsw %ax
4008 static void bemit_ftstfnstsw(const ir_node *node)
4012 bemit8(0xD9); // ftst
4017 static void bemit_fucomi(const ir_node *node)
4019 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4020 bemit8(0xDB); // fucomi
4021 bemit8(0xE8 + attr->x87[1]->index);
4024 static void bemit_fucomip(const ir_node *node)
4026 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4027 bemit8(0xDF); // fucomip
4028 bemit8(0xE8 + attr->x87[1]->index);
4031 static void bemit_fucomfnstsw(const ir_node *node)
4033 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4034 bemit8(0xDD); // fucom
4035 bemit8(0xE0 + attr->x87[1]->index);
4039 static void bemit_fucompfnstsw(const ir_node *node)
4041 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4042 bemit8(0xDD); // fucomp
4043 bemit8(0xE8 + attr->x87[1]->index);
4047 static void bemit_fucomppfnstsw(const ir_node *node)
4051 bemit8(0xDA); // fucompp
4056 static void bemit_fxch(const ir_node *node)
4058 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4060 bemit8(0xC8 + attr->x87[0]->index);
4064 * The type of a emitter function.
4066 typedef void (*emit_func) (const ir_node *);
4069 * Set a node emitter. Make it a bit more type safe.
4071 static void register_emitter(ir_op *op, emit_func func)
4073 op->ops.generic = (op_func) func;
4076 static void ia32_register_binary_emitters(void)
4078 /* first clear the generic function pointer for all ops */
4079 clear_irp_opcodes_generic_func();
4081 /* benode emitter */
4082 register_emitter(op_be_Copy, bemit_copy);
4083 register_emitter(op_be_CopyKeep, bemit_copy);
4084 register_emitter(op_be_IncSP, bemit_incsp);
4085 register_emitter(op_be_Perm, bemit_perm);
4086 register_emitter(op_be_Return, bemit_return);
4087 register_emitter(op_ia32_Adc, bemit_adc);
4088 register_emitter(op_ia32_Add, bemit_add);
4089 register_emitter(op_ia32_AddMem, bemit_addmem);
4090 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4091 register_emitter(op_ia32_And, bemit_and);
4092 register_emitter(op_ia32_AndMem, bemit_andmem);
4093 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4094 register_emitter(op_ia32_Breakpoint, bemit_int3);
4095 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4096 register_emitter(op_ia32_Call, bemit_call);
4097 register_emitter(op_ia32_Cltd, bemit_cltd);
4098 register_emitter(op_ia32_Cmc, bemit_cmc);
4099 register_emitter(op_ia32_Cmp, bemit_cmp);
4100 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4101 register_emitter(op_ia32_Const, bemit_mov_const);
4102 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4103 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4104 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4105 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4106 register_emitter(op_ia32_Dec, bemit_dec);
4107 register_emitter(op_ia32_DecMem, bemit_decmem);
4108 register_emitter(op_ia32_Div, bemit_div);
4109 register_emitter(op_ia32_FldCW, bemit_fldcw);
4110 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4111 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4112 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4113 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4114 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4115 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4116 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4117 register_emitter(op_ia32_IDiv, bemit_idiv);
4118 register_emitter(op_ia32_IJmp, bemit_ijmp);
4119 register_emitter(op_ia32_IMul, bemit_imul);
4120 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4121 register_emitter(op_ia32_Inc, bemit_inc);
4122 register_emitter(op_ia32_IncMem, bemit_incmem);
4123 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4124 register_emitter(op_ia32_Jmp, bemit_jump);
4125 register_emitter(op_ia32_LdTls, bemit_ldtls);
4126 register_emitter(op_ia32_Lea, bemit_lea);
4127 register_emitter(op_ia32_Leave, bemit_leave);
4128 register_emitter(op_ia32_Load, bemit_load);
4129 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4130 register_emitter(op_ia32_Mul, bemit_mul);
4131 register_emitter(op_ia32_Neg, bemit_neg);
4132 register_emitter(op_ia32_NegMem, bemit_negmem);
4133 register_emitter(op_ia32_Not, bemit_not);
4134 register_emitter(op_ia32_NotMem, bemit_notmem);
4135 register_emitter(op_ia32_Or, bemit_or);
4136 register_emitter(op_ia32_OrMem, bemit_ormem);
4137 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4138 register_emitter(op_ia32_Pop, bemit_pop);
4139 register_emitter(op_ia32_PopEbp, bemit_pop);
4140 register_emitter(op_ia32_PopMem, bemit_popmem);
4141 register_emitter(op_ia32_Push, bemit_push);
4142 register_emitter(op_ia32_RepPrefix, bemit_rep);
4143 register_emitter(op_ia32_Rol, bemit_rol);
4144 register_emitter(op_ia32_RolMem, bemit_rolmem);
4145 register_emitter(op_ia32_Ror, bemit_ror);
4146 register_emitter(op_ia32_RorMem, bemit_rormem);
4147 register_emitter(op_ia32_Sahf, bemit_sahf);
4148 register_emitter(op_ia32_Sar, bemit_sar);
4149 register_emitter(op_ia32_SarMem, bemit_sarmem);
4150 register_emitter(op_ia32_Sbb, bemit_sbb);
4151 register_emitter(op_ia32_Setcc, bemit_setcc);
4152 register_emitter(op_ia32_Shl, bemit_shl);
4153 register_emitter(op_ia32_ShlD, bemit_shld);
4154 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4155 register_emitter(op_ia32_Shr, bemit_shr);
4156 register_emitter(op_ia32_ShrD, bemit_shrd);
4157 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4158 register_emitter(op_ia32_Stc, bemit_stc);
4159 register_emitter(op_ia32_Store, bemit_store);
4160 register_emitter(op_ia32_Store8Bit, bemit_store);
4161 register_emitter(op_ia32_Sub, bemit_sub);
4162 register_emitter(op_ia32_SubMem, bemit_submem);
4163 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4164 register_emitter(op_ia32_SubSP, bemit_subsp);
4165 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4166 register_emitter(op_ia32_Test, bemit_test);
4167 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4168 register_emitter(op_ia32_Xor, bemit_xor);
4169 register_emitter(op_ia32_Xor0, bemit_xor0);
4170 register_emitter(op_ia32_XorMem, bemit_xormem);
4171 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4172 register_emitter(op_ia32_fabs, bemit_fabs);
4173 register_emitter(op_ia32_fadd, bemit_fadd);
4174 register_emitter(op_ia32_faddp, bemit_faddp);
4175 register_emitter(op_ia32_fchs, bemit_fchs);
4176 register_emitter(op_ia32_fdiv, bemit_fdiv);
4177 register_emitter(op_ia32_fdivp, bemit_fdivp);
4178 register_emitter(op_ia32_fdivr, bemit_fdivr);
4179 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4180 register_emitter(op_ia32_fild, bemit_fild);
4181 register_emitter(op_ia32_fist, bemit_fist);
4182 register_emitter(op_ia32_fistp, bemit_fistp);
4183 register_emitter(op_ia32_fld, bemit_fld);
4184 register_emitter(op_ia32_fld1, bemit_fld1);
4185 register_emitter(op_ia32_fldz, bemit_fldz);
4186 register_emitter(op_ia32_fmul, bemit_fmul);
4187 register_emitter(op_ia32_fmulp, bemit_fmulp);
4188 register_emitter(op_ia32_fpop, bemit_fpop);
4189 register_emitter(op_ia32_fpush, bemit_fpush);
4190 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4191 register_emitter(op_ia32_fst, bemit_fst);
4192 register_emitter(op_ia32_fstp, bemit_fstp);
4193 register_emitter(op_ia32_fsub, bemit_fsub);
4194 register_emitter(op_ia32_fsubp, bemit_fsubp);
4195 register_emitter(op_ia32_fsubr, bemit_fsubr);
4196 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4197 register_emitter(op_ia32_fxch, bemit_fxch);
4199 /* ignore the following nodes */
4200 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4201 register_emitter(op_be_Barrier, emit_Nothing);
4202 register_emitter(op_be_Keep, emit_Nothing);
4203 register_emitter(op_be_Start, emit_Nothing);
4204 register_emitter(op_Phi, emit_Nothing);
4205 register_emitter(op_Start, emit_Nothing);
4208 static void gen_binary_block(ir_node *block)
4212 ia32_emit_block_header(block);
4214 /* emit the contents of the block */
4215 sched_foreach(block, node) {
4216 ia32_emit_node(node);
4220 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
4222 ir_entity *entity = get_irg_entity(irg);
4228 ia32_register_binary_emitters();
4230 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4232 /* we use links to point to target blocks */
4233 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4234 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4236 /* initialize next block links */
4237 n = ARR_LEN(cg->blk_sched);
4238 for (i = 0; i < n; ++i) {
4239 ir_node *block = cg->blk_sched[i];
4240 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4242 set_irn_link(block, prev);
4245 for (i = 0; i < n; ++i) {
4246 ir_node *block = cg->blk_sched[i];
4247 gen_binary_block(block);
4250 be_gas_emit_function_epilog(entity);
4251 be_dbg_method_end();
4253 be_emit_write_line();
4255 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4261 void ia32_init_emitter(void)
4263 lc_opt_entry_t *be_grp;
4264 lc_opt_entry_t *ia32_grp;
4266 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4267 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4269 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4273 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");