2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
33 * pnc_Leg => NP (ordered)
55 #include "iredges_t.h"
59 #include "raw_bitset.h"
63 #include "../besched.h"
64 #include "../benode.h"
66 #include "../be_dbgout.h"
67 #include "../beemitter.h"
68 #include "../begnuas.h"
70 #include "../be_dbgout.h"
72 #include "ia32_emitter.h"
73 #include "ia32_common_transform.h"
74 #include "gen_ia32_emitter.h"
75 #include "gen_ia32_regalloc_if.h"
76 #include "ia32_nodes_attr.h"
77 #include "ia32_new_nodes.h"
78 #include "ia32_map_regs.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 #define SNPRINTF_BUF_LEN 128
86 static const ia32_isa_t *isa;
87 static char pic_base_label[128];
88 static ir_label_t exc_label_id;
89 static int mark_spill_reload = 0;
92 /** Return the next block in Block schedule */
93 static ir_node *get_prev_block_sched(const ir_node *block)
95 return (ir_node*)get_irn_link(block);
98 /** Checks if the current block is a fall-through target. */
99 static int is_fallthrough(const ir_node *cfgpred)
103 if (!is_Proj(cfgpred))
105 pred = get_Proj_pred(cfgpred);
106 if (is_ia32_SwitchJmp(pred))
113 * returns non-zero if the given block needs a label
114 * because of being a jump-target (and not a fall-through)
116 static int block_needs_label(const ir_node *block)
119 int n_cfgpreds = get_Block_n_cfgpreds(block);
121 if (has_Block_entity(block))
124 if (n_cfgpreds == 0) {
126 } else if (n_cfgpreds == 1) {
127 ir_node *cfgpred = get_Block_cfgpred(block, 0);
128 ir_node *cfgpred_block = get_nodes_block(cfgpred);
130 if (get_prev_block_sched(block) == cfgpred_block
131 && is_fallthrough(cfgpred)) {
140 * Returns the register at in position pos.
142 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
145 const arch_register_t *reg = NULL;
147 assert(get_irn_arity(irn) > pos && "Invalid IN position");
149 /* The out register of the operator at position pos is the
150 in register we need. */
151 op = get_irn_n(irn, pos);
153 reg = arch_get_irn_register(op);
155 assert(reg && "no in register found");
157 if (reg == &ia32_registers[REG_GP_NOREG])
158 panic("trying to emit noreg for %+F input %d", irn, pos);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
178 reg = arch_get_irn_register(irn);
179 } else if (is_ia32_irn(irn)) {
180 reg = arch_irn_get_register(irn, pos);
182 const ir_edge_t *edge;
184 foreach_out_edge(irn, edge) {
185 proj = get_edge_src_irn(edge);
186 assert(is_Proj(proj) && "non-Proj from mode_T node");
187 if (get_Proj_proj(proj) == pos) {
188 reg = arch_get_irn_register(proj);
194 assert(reg && "no out register found");
199 * Add a number to a prefix. This number will not be used a second time.
201 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
203 static unsigned long id = 0;
204 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
210 * Emit the name of the 8bit low register
212 static void emit_8bit_register(const arch_register_t *reg)
214 const char *reg_name = arch_register_get_name(reg);
217 be_emit_char(reg_name[1]);
222 * Emit the name of the 8bit high register
224 static void emit_8bit_register_high(const arch_register_t *reg)
226 const char *reg_name = arch_register_get_name(reg);
229 be_emit_char(reg_name[1]);
233 static void emit_16bit_register(const arch_register_t *reg)
235 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
238 be_emit_string(reg_name);
242 * emit a register, possible shortened by a mode
244 * @param reg the register
245 * @param mode the mode of the register or NULL for full register
247 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
249 const char *reg_name;
252 int size = get_mode_size_bits(mode);
254 case 8: emit_8bit_register(reg); return;
255 case 16: emit_16bit_register(reg); return;
257 assert(mode_is_float(mode) || size == 32);
260 reg_name = arch_register_get_name(reg);
263 be_emit_string(reg_name);
266 void ia32_emit_source_register(const ir_node *node, int pos)
268 const arch_register_t *reg = get_in_reg(node, pos);
270 emit_register(reg, NULL);
273 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
275 be_gas_emit_entity(entity);
277 if (get_entity_owner(entity) == get_tls_type()) {
278 if (get_entity_visibility(entity) == ir_visibility_external) {
279 be_emit_cstring("@INDNTPOFF");
281 be_emit_cstring("@NTPOFF");
285 if (do_pic && !no_pic_adjust) {
287 be_emit_string(pic_base_label);
291 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
293 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
295 if (attr->symconst != NULL) {
298 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
300 if (attr->symconst == NULL || attr->offset != 0) {
301 if (attr->symconst != NULL) {
302 be_emit_irprintf("%+d", attr->offset);
304 be_emit_irprintf("0x%X", attr->offset);
309 static void emit_ia32_Immediate(const ir_node *node)
312 emit_ia32_Immediate_no_prefix(node);
315 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
317 const arch_register_t *reg;
318 const ir_node *in = get_irn_n(node, pos);
319 if (is_ia32_Immediate(in)) {
320 emit_ia32_Immediate(in);
324 reg = get_in_reg(node, pos);
325 emit_8bit_register(reg);
328 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
330 const arch_register_t *reg = get_in_reg(node, pos);
331 emit_8bit_register_high(reg);
334 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
336 const arch_register_t *reg;
337 const ir_node *in = get_irn_n(node, pos);
338 if (is_ia32_Immediate(in)) {
339 emit_ia32_Immediate(in);
343 reg = get_in_reg(node, pos);
344 emit_16bit_register(reg);
347 void ia32_emit_dest_register(const ir_node *node, int pos)
349 const arch_register_t *reg = get_out_reg(node, pos);
351 emit_register(reg, NULL);
354 void ia32_emit_dest_register_size(const ir_node *node, int pos)
356 const arch_register_t *reg = get_out_reg(node, pos);
358 emit_register(reg, get_ia32_ls_mode(node));
361 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
363 const arch_register_t *reg = get_out_reg(node, pos);
365 emit_register(reg, mode_Bu);
368 void ia32_emit_x87_register(const ir_node *node, int pos)
370 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
374 be_emit_string(attr->x87[pos]->name);
377 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
379 assert(mode_is_int(mode) || mode_is_reference(mode));
380 switch (get_mode_size_bits(mode)) {
381 case 8: be_emit_char('b'); return;
382 case 16: be_emit_char('w'); return;
383 case 32: be_emit_char('l'); return;
384 /* gas docu says q is the suffix but gcc, objdump and icc use ll
386 case 64: be_emit_cstring("ll"); return;
388 panic("Can't output mode_suffix for %+F", mode);
391 void ia32_emit_mode_suffix(const ir_node *node)
393 ir_mode *mode = get_ia32_ls_mode(node);
397 ia32_emit_mode_suffix_mode(mode);
400 void ia32_emit_x87_mode_suffix(const ir_node *node)
404 /* we only need to emit the mode on address mode */
405 if (get_ia32_op_type(node) == ia32_Normal)
408 mode = get_ia32_ls_mode(node);
409 assert(mode != NULL);
411 if (mode_is_float(mode)) {
412 switch (get_mode_size_bits(mode)) {
413 case 32: be_emit_char('s'); return;
414 case 64: be_emit_char('l'); return;
415 /* long doubles have different sizes due to alignment on different
419 case 128: be_emit_char('t'); return;
422 assert(mode_is_int(mode) || mode_is_reference(mode));
423 switch (get_mode_size_bits(mode)) {
424 case 16: be_emit_char('s'); return;
425 case 32: be_emit_char('l'); return;
426 /* gas docu says q is the suffix but gcc, objdump and icc use ll
428 case 64: be_emit_cstring("ll"); return;
431 panic("Can't output mode_suffix for %+F", mode);
434 static char get_xmm_mode_suffix(ir_mode *mode)
436 assert(mode_is_float(mode));
437 switch (get_mode_size_bits(mode)) {
440 default: panic("Invalid XMM mode");
444 void ia32_emit_xmm_mode_suffix(const ir_node *node)
446 ir_mode *mode = get_ia32_ls_mode(node);
447 assert(mode != NULL);
449 be_emit_char(get_xmm_mode_suffix(mode));
452 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
454 ir_mode *mode = get_ia32_ls_mode(node);
455 assert(mode != NULL);
456 be_emit_char(get_xmm_mode_suffix(mode));
459 void ia32_emit_extend_suffix(const ir_node *node)
461 ir_mode *mode = get_ia32_ls_mode(node);
462 if (get_mode_size_bits(mode) == 32)
464 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
465 ia32_emit_mode_suffix_mode(mode);
468 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
470 ir_node *in = get_irn_n(node, pos);
471 if (is_ia32_Immediate(in)) {
472 emit_ia32_Immediate(in);
474 const ir_mode *mode = get_ia32_ls_mode(node);
475 const arch_register_t *reg = get_in_reg(node, pos);
476 emit_register(reg, mode);
481 * Returns the target block for a control flow node.
483 static ir_node *get_cfop_target_block(const ir_node *irn)
485 assert(get_irn_mode(irn) == mode_X);
486 return (ir_node*)get_irn_link(irn);
490 * Emits the target label for a control flow node.
492 static void ia32_emit_cfop_target(const ir_node *node)
494 ir_node *block = get_cfop_target_block(node);
495 be_gas_emit_block_name(block);
499 * positive conditions for signed compares
501 static const char *const cmp2condition_s[] = {
502 NULL, /* always false */
509 NULL /* always true */
513 * positive conditions for unsigned compares
515 static const char *const cmp2condition_u[] = {
516 NULL, /* always false */
523 NULL /* always true */
527 * Emit the suffix for a compare instruction.
529 static void ia32_emit_cmp_suffix(int pnc)
533 if (pnc == ia32_pn_Cmp_parity) {
538 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
539 str = cmp2condition_u[pnc & 7];
541 str = cmp2condition_s[pnc & 7];
547 typedef enum ia32_emit_mod_t {
549 EMIT_RESPECT_LS = 1U << 0,
550 EMIT_ALTERNATE_AM = 1U << 1,
552 EMIT_HIGH_REG = 1U << 3,
553 EMIT_LOW_REG = 1U << 4
555 ENUM_BITSET(ia32_emit_mod_t)
558 * Emits address mode.
560 void ia32_emit_am(const ir_node *node)
562 ir_entity *ent = get_ia32_am_sc(node);
563 int offs = get_ia32_am_offs_int(node);
564 ir_node *base = get_irn_n(node, n_ia32_base);
565 int has_base = !is_ia32_NoReg_GP(base);
566 ir_node *index = get_irn_n(node, n_ia32_index);
567 int has_index = !is_ia32_NoReg_GP(index);
569 /* just to be sure... */
570 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
574 const ia32_attr_t *attr = get_ia32_attr_const(node);
575 if (is_ia32_am_sc_sign(node))
577 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
580 /* also handle special case if nothing is set */
581 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
583 be_emit_irprintf("%+d", offs);
585 be_emit_irprintf("%d", offs);
589 if (has_base || has_index) {
594 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
595 emit_register(reg, NULL);
598 /* emit index + scale */
600 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
603 emit_register(reg, NULL);
605 scale = get_ia32_am_scale(node);
607 be_emit_irprintf(",%d", 1 << scale);
615 * fmt parameter output
616 * ---- ---------------------- ---------------------------------------------
618 * %AM <node> address mode of the node
619 * %AR const arch_register_t* address mode of the node or register
620 * %ASx <node> address mode of the node or source register x
621 * %Dx <node> destination register x
622 * %I <node> immediate of the node
623 * %L <node> control flow target of the node
624 * %M <node> mode suffix of the node
625 * %P int condition code
626 * %R const arch_register_t* register
627 * %Sx <node> source register x
628 * %s const char* string
629 * %u unsigned int unsigned int
630 * %d signed int signed int
633 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
634 * * modifier does not prefix immediates with $, but AM with *
635 * l modifier for %lu and %ld
636 * > modifier to output high 8bit register (ah, bh)
637 * < modifier to output low 8bit register (al, bl)
639 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
645 const char *start = fmt;
646 ia32_emit_mod_t mod = EMIT_NONE;
648 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
651 be_emit_string_len(start, fmt - start);
655 be_emit_finish_line_gas(node);
668 case '*': mod |= EMIT_ALTERNATE_AM; break;
669 case '#': mod |= EMIT_RESPECT_LS; break;
670 case 'l': mod |= EMIT_LONG; break;
671 case '>': mod |= EMIT_HIGH_REG; break;
672 case '<': mod |= EMIT_LOW_REG; break;
689 if (mod & EMIT_ALTERNATE_AM)
695 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
696 if (get_ia32_op_type(node) == ia32_AddrModeS) {
699 if (mod & EMIT_ALTERNATE_AM)
701 emit_register(reg, NULL);
707 if (get_ia32_op_type(node) == ia32_AddrModeS) {
711 assert(get_ia32_op_type(node) == ia32_Normal);
716 default: goto unknown;
723 const arch_register_t *reg;
725 if (*fmt < '0' || '9' <= *fmt)
729 reg = get_out_reg(node, pos);
730 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
735 if (!(mod & EMIT_ALTERNATE_AM))
737 emit_ia32_Immediate_no_prefix(node);
741 ia32_emit_cfop_target(node);
745 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
750 int pnc = va_arg(ap, int);
751 ia32_emit_cmp_suffix(pnc);
756 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
757 if (mod & EMIT_HIGH_REG) {
758 emit_8bit_register_high(reg);
759 } else if (mod & EMIT_LOW_REG) {
760 emit_8bit_register(reg);
762 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
772 if (*fmt < '0' || '9' <= *fmt)
776 in = get_irn_n(node, pos);
777 if (is_ia32_Immediate(in)) {
778 if (!(mod & EMIT_ALTERNATE_AM))
780 emit_ia32_Immediate_no_prefix(in);
782 const arch_register_t *reg;
784 if (mod & EMIT_ALTERNATE_AM)
786 reg = get_in_reg(node, pos);
787 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
793 const char *str = va_arg(ap, const char*);
799 if (mod & EMIT_LONG) {
800 unsigned long num = va_arg(ap, unsigned long);
801 be_emit_irprintf("%lu", num);
803 unsigned num = va_arg(ap, unsigned);
804 be_emit_irprintf("%u", num);
809 if (mod & EMIT_LONG) {
810 long num = va_arg(ap, long);
811 be_emit_irprintf("%ld", num);
813 int num = va_arg(ap, int);
814 be_emit_irprintf("%d", num);
820 panic("unknown format conversion in ia32_emitf()");
828 * Emits registers and/or address mode of a binary operation.
830 void ia32_emit_binop(const ir_node *node)
832 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
833 ia32_emitf(node, "%#S4, %#AS3");
835 ia32_emitf(node, "%#AS4, %#S3");
840 * Emits registers and/or address mode of a binary operation.
842 void ia32_emit_x87_binop(const ir_node *node)
844 switch (get_ia32_op_type(node)) {
847 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
848 const arch_register_t *in1 = x87_attr->x87[0];
849 const arch_register_t *in = x87_attr->x87[1];
850 const arch_register_t *out = x87_attr->x87[2];
854 } else if (out == in) {
859 be_emit_string(arch_register_get_name(in));
860 be_emit_cstring(", %");
861 be_emit_string(arch_register_get_name(out));
869 assert(0 && "unsupported op type");
874 * Emits registers and/or address mode of a unary operation.
876 void ia32_emit_unop(const ir_node *node, int pos)
880 ia32_emitf(node, fmt);
883 static void emit_ia32_IMul(const ir_node *node)
885 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
886 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
888 /* do we need the 3-address form? */
889 if (is_ia32_NoReg_GP(left) ||
890 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
891 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
893 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
898 * walks up a tree of copies/perms/spills/reloads to find the original value
899 * that is moved around
901 static ir_node *find_original_value(ir_node *node)
903 if (irn_visited(node))
906 mark_irn_visited(node);
907 if (be_is_Copy(node)) {
908 return find_original_value(be_get_Copy_op(node));
909 } else if (be_is_CopyKeep(node)) {
910 return find_original_value(be_get_CopyKeep_op(node));
911 } else if (is_Proj(node)) {
912 ir_node *pred = get_Proj_pred(node);
913 if (be_is_Perm(pred)) {
914 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
915 } else if (be_is_MemPerm(pred)) {
916 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
917 } else if (is_ia32_Load(pred)) {
918 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
922 } else if (is_ia32_Store(node)) {
923 return find_original_value(get_irn_n(node, n_ia32_Store_val));
924 } else if (is_Phi(node)) {
926 arity = get_irn_arity(node);
927 for (i = 0; i < arity; ++i) {
928 ir_node *in = get_irn_n(node, i);
929 ir_node *res = find_original_value(in);
940 static int determine_final_pnc(const ir_node *node, int flags_pos, int pnc)
942 ir_node *flags = get_irn_n(node, flags_pos);
943 const ia32_attr_t *flags_attr;
944 flags = skip_Proj(flags);
946 if (is_ia32_Sahf(flags)) {
947 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
948 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
949 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
950 inc_irg_visited(current_ir_graph);
951 cmp = find_original_value(cmp);
953 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
954 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
957 flags_attr = get_ia32_attr_const(cmp);
958 if (flags_attr->data.ins_permuted)
959 pnc = get_mirrored_pnc(pnc);
960 pnc |= ia32_pn_Cmp_float;
961 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
962 || is_ia32_Fucompi(flags)) {
963 flags_attr = get_ia32_attr_const(flags);
965 if (flags_attr->data.ins_permuted)
966 pnc = get_mirrored_pnc(pnc);
967 pnc |= ia32_pn_Cmp_float;
969 flags_attr = get_ia32_attr_const(flags);
971 if (flags_attr->data.ins_permuted)
972 pnc = get_mirrored_pnc(pnc);
973 if (flags_attr->data.cmp_unsigned)
974 pnc |= ia32_pn_Cmp_unsigned;
980 static int ia32_get_negated_pnc(int pnc)
982 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
983 return get_negated_pnc(pnc, mode);
986 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
988 int pnc = get_ia32_condcode(node);
989 pnc = determine_final_pnc(node, flags_pos, pnc);
991 ia32_emit_cmp_suffix(pnc);
995 * Emits an exception label for a given node.
997 static void ia32_emit_exc_label(const ir_node *node)
999 be_emit_string(be_gas_insn_label_prefix());
1000 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1004 * Returns the Proj with projection number proj and NOT mode_M
1006 static ir_node *get_proj(const ir_node *node, long proj)
1008 const ir_edge_t *edge;
1011 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1013 foreach_out_edge(node, edge) {
1014 src = get_edge_src_irn(edge);
1016 assert(is_Proj(src) && "Proj expected");
1017 if (get_irn_mode(src) == mode_M)
1020 if (get_Proj_proj(src) == proj)
1026 static int can_be_fallthrough(const ir_node *node)
1028 ir_node *target_block = get_cfop_target_block(node);
1029 ir_node *block = get_nodes_block(node);
1030 return get_prev_block_sched(target_block) == block;
1034 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1036 static void emit_ia32_Jcc(const ir_node *node)
1038 int need_parity_label = 0;
1039 const ir_node *proj_true;
1040 const ir_node *proj_false;
1041 int pnc = get_ia32_condcode(node);
1043 pnc = determine_final_pnc(node, 0, pnc);
1045 /* get both Projs */
1046 proj_true = get_proj(node, pn_ia32_Jcc_true);
1047 assert(proj_true && "Jcc without true Proj");
1049 proj_false = get_proj(node, pn_ia32_Jcc_false);
1050 assert(proj_false && "Jcc without false Proj");
1052 if (can_be_fallthrough(proj_true)) {
1053 /* exchange both proj's so the second one can be omitted */
1054 const ir_node *t = proj_true;
1056 proj_true = proj_false;
1058 pnc = ia32_get_negated_pnc(pnc);
1061 if (pnc & ia32_pn_Cmp_float) {
1062 /* Some floating point comparisons require a test of the parity flag,
1063 * which indicates that the result is unordered */
1064 switch (pnc & 0x0f) {
1066 ia32_emitf(proj_true, "\tjp %L\n");
1071 ia32_emitf(proj_true, "\tjnp %L\n");
1077 /* we need a local label if the false proj is a fallthrough
1078 * as the falseblock might have no label emitted then */
1079 if (can_be_fallthrough(proj_false)) {
1080 need_parity_label = 1;
1081 ia32_emitf(proj_false, "\tjp 1f\n");
1083 ia32_emitf(proj_false, "\tjp %L\n");
1090 ia32_emitf(proj_true, "\tjp %L\n");
1098 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1101 if (need_parity_label) {
1102 ia32_emitf(NULL, "1:\n");
1105 /* the second Proj might be a fallthrough */
1106 if (can_be_fallthrough(proj_false)) {
1107 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1109 ia32_emitf(proj_false, "\tjmp %L\n");
1114 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1117 static void emit_ia32_Setcc(const ir_node *node)
1119 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1121 int pnc = get_ia32_condcode(node);
1122 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1123 if (pnc & ia32_pn_Cmp_float) {
1124 switch (pnc & 0x0f) {
1126 ia32_emitf(node, "\tsetp %#R\n", dreg);
1130 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1136 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1137 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1138 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1144 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1145 ia32_emitf(node, "\tsetp %>R\n", dreg);
1146 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1153 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1156 static void emit_ia32_CMovcc(const ir_node *node)
1158 const ia32_attr_t *attr = get_ia32_attr_const(node);
1159 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1160 int pnc = get_ia32_condcode(node);
1161 const arch_register_t *in_true;
1162 const arch_register_t *in_false;
1164 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1165 /* although you can't set ins_permuted in the constructor it might still
1166 * be set by memory operand folding
1167 * Permuting inputs of a cmov means the condition is negated!
1169 if (attr->data.ins_permuted)
1170 pnc = ia32_get_negated_pnc(pnc);
1172 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1173 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1175 /* should be same constraint fullfilled? */
1176 if (out == in_false) {
1177 /* yes -> nothing to do */
1178 } else if (out == in_true) {
1179 const arch_register_t *tmp;
1181 assert(get_ia32_op_type(node) == ia32_Normal);
1183 pnc = ia32_get_negated_pnc(pnc);
1190 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1193 /* TODO: handling of Nans isn't correct yet */
1194 if (pnc & ia32_pn_Cmp_float) {
1195 switch (pnc & 0x0f) {
1204 panic("CMov with floatingpoint compare/parity not supported yet");
1208 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1212 /* jump table entry (target and corresponding number) */
1213 typedef struct branch_t {
1218 /* jump table for switch generation */
1219 typedef struct jmp_tbl_t {
1220 ir_node *defProj; /**< default target */
1221 long min_value; /**< smallest switch case */
1222 long max_value; /**< largest switch case */
1223 long num_branches; /**< number of jumps */
1224 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1225 branch_t *branches; /**< jump array */
1229 * Compare two variables of type branch_t. Used to sort all switch cases
1231 static int ia32_cmp_branch_t(const void *a, const void *b)
1233 branch_t *b1 = (branch_t *)a;
1234 branch_t *b2 = (branch_t *)b;
1236 if (b1->value <= b2->value)
1242 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1248 const ir_edge_t *edge;
1250 /* fill the table structure */
1251 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1252 tbl->defProj = NULL;
1253 tbl->num_branches = get_irn_n_edges(node) - 1;
1254 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1255 tbl->min_value = LONG_MAX;
1256 tbl->max_value = LONG_MIN;
1258 default_pn = get_ia32_condcode(node);
1260 /* go over all proj's and collect them */
1261 foreach_out_edge(node, edge) {
1262 proj = get_edge_src_irn(edge);
1263 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1265 pnc = get_Proj_proj(proj);
1267 /* check for default proj */
1268 if (pnc == default_pn) {
1269 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1270 tbl->defProj = proj;
1272 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1273 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1275 /* create branch entry */
1276 tbl->branches[i].target = proj;
1277 tbl->branches[i].value = pnc;
1282 assert(i == tbl->num_branches);
1284 /* sort the branches by their number */
1285 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1289 * Emits code for a SwitchJmp (creates a jump table if
1290 * possible otherwise a cmp-jmp cascade). Port from
1293 static void emit_ia32_SwitchJmp(const ir_node *node)
1295 unsigned long interval;
1299 /* fill the table structure */
1300 generate_jump_table(&tbl, node);
1302 /* two-complement's magic make this work without overflow */
1303 interval = tbl.max_value - tbl.min_value;
1305 /* emit the table */
1306 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1307 ia32_emitf(tbl.defProj, "\tja %L\n");
1309 if (tbl.num_branches > 1) {
1311 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1313 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1314 ia32_emitf(NULL, "\t.align 4\n");
1315 ia32_emitf(NULL, "%s:\n", tbl.label);
1317 last_value = tbl.branches[0].value;
1318 for (i = 0; i != tbl.num_branches; ++i) {
1319 while (last_value != tbl.branches[i].value) {
1320 ia32_emitf(tbl.defProj, ".long %L\n");
1323 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1326 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1328 /* one jump is enough */
1329 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1336 * Emits code for a unconditional jump.
1338 static void emit_ia32_Jmp(const ir_node *node)
1342 /* for now, the code works for scheduled and non-schedules blocks */
1343 block = get_nodes_block(node);
1345 /* we have a block schedule */
1346 if (can_be_fallthrough(node)) {
1347 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1349 ia32_emitf(node, "\tjmp %L\n");
1354 * Emit an inline assembler operand.
1356 * @param node the ia32_ASM node
1357 * @param s points to the operand (a %c)
1359 * @return pointer to the first char in s NOT in the current operand
1361 static const char* emit_asm_operand(const ir_node *node, const char *s)
1363 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1364 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1366 const arch_register_t *reg;
1367 const ia32_asm_reg_t *asm_regs = attr->register_map;
1368 const ia32_asm_reg_t *asm_reg;
1369 const char *reg_name;
1378 /* parse modifiers */
1381 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1406 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1413 sscanf(s, "%d%n", &num, &p);
1415 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1422 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1424 "Error: Custom assembler references invalid input/output (%+F)\n",
1428 asm_reg = & asm_regs[num];
1429 assert(asm_reg->valid);
1432 if (asm_reg->use_input == 0) {
1433 reg = get_out_reg(node, asm_reg->inout_pos);
1435 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1437 /* might be an immediate value */
1438 if (is_ia32_Immediate(pred)) {
1439 emit_ia32_Immediate(pred);
1442 reg = get_in_reg(node, asm_reg->inout_pos);
1446 "Warning: no register assigned for %d asm op (%+F)\n",
1451 if (asm_reg->memory) {
1456 if (modifier != 0) {
1460 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1463 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1466 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1469 panic("Invalid asm op modifier");
1471 be_emit_string(reg_name);
1473 emit_register(reg, asm_reg->mode);
1476 if (asm_reg->memory) {
1484 * Emits code for an ASM pseudo op.
1486 static void emit_ia32_Asm(const ir_node *node)
1488 const void *gen_attr = get_irn_generic_attr_const(node);
1489 const ia32_asm_attr_t *attr
1490 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1491 ident *asm_text = attr->asm_text;
1492 const char *s = get_id_str(asm_text);
1494 ia32_emitf(node, "#APP\t\n");
1501 s = emit_asm_operand(node, s);
1507 ia32_emitf(NULL, "\n#NO_APP\n");
1512 * Emit movsb/w instructions to make mov count divideable by 4
1514 static void emit_CopyB_prolog(unsigned size)
1517 ia32_emitf(NULL, "\tmovsb\n");
1519 ia32_emitf(NULL, "\tmovsw\n");
1523 * Emit rep movsd instruction for memcopy.
1525 static void emit_ia32_CopyB(const ir_node *node)
1527 unsigned size = get_ia32_copyb_size(node);
1529 emit_CopyB_prolog(size);
1530 ia32_emitf(node, "\trep movsd\n");
1534 * Emits unrolled memcopy.
1536 static void emit_ia32_CopyB_i(const ir_node *node)
1538 unsigned size = get_ia32_copyb_size(node);
1540 emit_CopyB_prolog(size);
1544 ia32_emitf(NULL, "\tmovsd\n");
1550 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1552 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1555 ir_mode *ls_mode = get_ia32_ls_mode(node);
1556 int ls_bits = get_mode_size_bits(ls_mode);
1557 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1559 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1562 static void emit_ia32_Conv_I2FP(const ir_node *node)
1564 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1567 static void emit_ia32_Conv_FP2I(const ir_node *node)
1569 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1572 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1574 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1578 * Emits code for an Int conversion.
1580 static void emit_ia32_Conv_I2I(const ir_node *node)
1582 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1583 int signed_mode = mode_is_signed(smaller_mode);
1584 const char *sign_suffix;
1586 assert(!mode_is_float(smaller_mode));
1588 sign_suffix = signed_mode ? "s" : "z";
1589 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1595 static void emit_ia32_Call(const ir_node *node)
1597 /* Special case: Call must not have its immediates prefixed by $, instead
1598 * address mode is prefixed by *. */
1599 ia32_emitf(node, "\tcall %*AS3\n");
1604 * Emits code to increase stack pointer.
1606 static void emit_be_IncSP(const ir_node *node)
1608 int offs = be_get_IncSP_offset(node);
1614 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1616 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1621 * Emits code for Copy/CopyKeep.
1623 static void Copy_emitter(const ir_node *node, const ir_node *op)
1625 const arch_register_t *in = arch_get_irn_register(op);
1626 const arch_register_t *out = arch_get_irn_register(node);
1631 /* copies of vf nodes aren't real... */
1632 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1635 if (get_irn_mode(node) == mode_E) {
1636 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1638 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1642 static void emit_be_Copy(const ir_node *node)
1644 Copy_emitter(node, be_get_Copy_op(node));
1647 static void emit_be_CopyKeep(const ir_node *node)
1649 Copy_emitter(node, be_get_CopyKeep_op(node));
1653 * Emits code for exchange.
1655 static void emit_be_Perm(const ir_node *node)
1657 const arch_register_t *in0, *in1;
1658 const arch_register_class_t *cls0, *cls1;
1660 in0 = arch_get_irn_register(get_irn_n(node, 0));
1661 in1 = arch_get_irn_register(get_irn_n(node, 1));
1663 cls0 = arch_register_get_class(in0);
1664 cls1 = arch_register_get_class(in1);
1666 assert(cls0 == cls1 && "Register class mismatch at Perm");
1668 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1669 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1670 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1671 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1672 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1673 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1674 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1676 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1679 panic("unexpected register class in be_Perm (%+F)", node);
1684 * Emits code for Constant loading.
1686 static void emit_ia32_Const(const ir_node *node)
1688 ia32_emitf(node, "\tmovl %I, %D0\n");
1692 * Emits code to load the TLS base
1694 static void emit_ia32_LdTls(const ir_node *node)
1696 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1699 /* helper function for emit_ia32_Minus64Bit */
1700 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1702 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1705 /* helper function for emit_ia32_Minus64Bit */
1706 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1708 ia32_emitf(node, "\tnegl %R\n", reg);
1711 /* helper function for emit_ia32_Minus64Bit */
1712 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1714 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1717 /* helper function for emit_ia32_Minus64Bit */
1718 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1720 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1723 /* helper function for emit_ia32_Minus64Bit */
1724 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1726 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1729 /* helper function for emit_ia32_Minus64Bit */
1730 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1732 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1735 static void emit_ia32_Minus64Bit(const ir_node *node)
1737 const arch_register_t *in_lo = get_in_reg(node, 0);
1738 const arch_register_t *in_hi = get_in_reg(node, 1);
1739 const arch_register_t *out_lo = get_out_reg(node, 0);
1740 const arch_register_t *out_hi = get_out_reg(node, 1);
1742 if (out_lo == in_lo) {
1743 if (out_hi != in_hi) {
1744 /* a -> a, b -> d */
1747 /* a -> a, b -> b */
1750 } else if (out_lo == in_hi) {
1751 if (out_hi == in_lo) {
1752 /* a -> b, b -> a */
1753 emit_xchg(node, in_lo, in_hi);
1756 /* a -> b, b -> d */
1757 emit_mov(node, in_hi, out_hi);
1758 emit_mov(node, in_lo, out_lo);
1762 if (out_hi == in_lo) {
1763 /* a -> c, b -> a */
1764 emit_mov(node, in_lo, out_lo);
1766 } else if (out_hi == in_hi) {
1767 /* a -> c, b -> b */
1768 emit_mov(node, in_lo, out_lo);
1771 /* a -> c, b -> d */
1772 emit_mov(node, in_lo, out_lo);
1778 emit_neg( node, out_hi);
1779 emit_neg( node, out_lo);
1780 emit_sbb0(node, out_hi);
1784 emit_zero(node, out_hi);
1785 emit_neg( node, out_lo);
1786 emit_sbb( node, in_hi, out_hi);
1789 static void emit_ia32_GetEIP(const ir_node *node)
1791 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1792 ia32_emitf(NULL, "%s:\n", pic_base_label);
1793 ia32_emitf(node, "\tpopl %D0\n");
1796 static void emit_ia32_ClimbFrame(const ir_node *node)
1798 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1800 ia32_emitf(node, "\tmovl %S0, %D0\n");
1801 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1802 be_gas_emit_block_name(node);
1803 be_emit_cstring(":\n");
1804 be_emit_write_line();
1805 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1806 ia32_emitf(node, "\tdec %S1\n");
1807 be_emit_cstring("\tjnz ");
1808 be_gas_emit_block_name(node);
1809 be_emit_finish_line_gas(node);
1812 static void emit_be_Return(const ir_node *node)
1814 unsigned pop = be_Return_get_pop(node);
1816 if (pop > 0 || be_Return_get_emit_pop(node)) {
1817 ia32_emitf(node, "\tret $%u\n", pop);
1819 ia32_emitf(node, "\tret\n");
1823 static void emit_Nothing(const ir_node *node)
1830 * Enters the emitter functions for handled nodes into the generic
1831 * pointer of an opcode.
1833 static void ia32_register_emitters(void)
1835 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1836 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1837 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1838 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1839 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1840 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1842 /* first clear the generic function pointer for all ops */
1843 clear_irp_opcodes_generic_func();
1845 /* register all emitter functions defined in spec */
1846 ia32_register_spec_emitters();
1848 /* other ia32 emitter functions */
1849 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1854 IA32_EMIT(Conv_FP2FP);
1855 IA32_EMIT(Conv_FP2I);
1856 IA32_EMIT(Conv_I2FP);
1857 IA32_EMIT(Conv_I2I);
1865 IA32_EMIT(Minus64Bit);
1866 IA32_EMIT(SwitchJmp);
1867 IA32_EMIT(ClimbFrame);
1870 /* benode emitter */
1891 typedef void (*emit_func_ptr) (const ir_node *);
1894 * Assign and emit an exception label if the current instruction can fail.
1896 static void ia32_assign_exc_label(ir_node *node)
1898 /* assign a new ID to the instruction */
1899 set_ia32_exc_label_id(node, ++exc_label_id);
1901 ia32_emit_exc_label(node);
1903 be_emit_pad_comment();
1904 be_emit_cstring("/* exception to Block ");
1905 ia32_emit_cfop_target(node);
1906 be_emit_cstring(" */\n");
1907 be_emit_write_line();
1911 * Emits code for a node.
1913 static void ia32_emit_node(ir_node *node)
1915 ir_op *op = get_irn_op(node);
1917 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1919 if (is_ia32_irn(node)) {
1920 if (get_ia32_exc_label(node)) {
1921 /* emit the exception label of this instruction */
1922 ia32_assign_exc_label(node);
1924 if (mark_spill_reload) {
1925 if (is_ia32_is_spill(node)) {
1926 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1928 if (is_ia32_is_reload(node)) {
1929 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1931 if (is_ia32_is_remat(node)) {
1932 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1936 if (op->ops.generic) {
1937 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1939 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1944 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1950 * Emits gas alignment directives
1952 static void ia32_emit_alignment(unsigned align, unsigned skip)
1954 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1958 * Emits gas alignment directives for Labels depended on cpu architecture.
1960 static void ia32_emit_align_label(void)
1962 unsigned align = ia32_cg_config.label_alignment;
1963 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1964 ia32_emit_alignment(align, maximum_skip);
1968 * Test whether a block should be aligned.
1969 * For cpus in the P4/Athlon class it is useful to align jump labels to
1970 * 16 bytes. However we should only do that if the alignment nops before the
1971 * label aren't executed more often than we have jumps to the label.
1973 static int should_align_block(const ir_node *block)
1975 static const double DELTA = .0001;
1976 ir_graph *irg = get_irn_irg(block);
1977 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1978 ir_node *prev = get_prev_block_sched(block);
1980 double prev_freq = 0; /**< execfreq of the fallthrough block */
1981 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1984 if (exec_freq == NULL)
1986 if (ia32_cg_config.label_alignment_factor <= 0)
1989 block_freq = get_block_execfreq(exec_freq, block);
1990 if (block_freq < DELTA)
1993 n_cfgpreds = get_Block_n_cfgpreds(block);
1994 for (i = 0; i < n_cfgpreds; ++i) {
1995 const ir_node *pred = get_Block_cfgpred_block(block, i);
1996 double pred_freq = get_block_execfreq(exec_freq, pred);
1999 prev_freq += pred_freq;
2001 jmp_freq += pred_freq;
2005 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2008 jmp_freq /= prev_freq;
2010 return jmp_freq > ia32_cg_config.label_alignment_factor;
2014 * Emit the block header for a block.
2016 * @param block the block
2017 * @param prev_block the previous block
2019 static void ia32_emit_block_header(ir_node *block)
2021 ir_graph *irg = current_ir_graph;
2022 int need_label = block_needs_label(block);
2024 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
2026 if (block == get_irg_end_block(irg))
2029 if (ia32_cg_config.label_alignment > 0) {
2030 /* align the current block if:
2031 * a) if should be aligned due to its execution frequency
2032 * b) there is no fall-through here
2034 if (should_align_block(block)) {
2035 ia32_emit_align_label();
2037 /* if the predecessor block has no fall-through,
2038 we can always align the label. */
2040 int has_fallthrough = 0;
2042 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2043 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2044 if (can_be_fallthrough(cfg_pred)) {
2045 has_fallthrough = 1;
2050 if (!has_fallthrough)
2051 ia32_emit_align_label();
2056 be_gas_emit_block_name(block);
2059 be_emit_pad_comment();
2060 be_emit_cstring(" /* ");
2062 be_emit_cstring("\t/* ");
2063 be_gas_emit_block_name(block);
2064 be_emit_cstring(": ");
2067 be_emit_cstring("preds:");
2069 /* emit list of pred blocks in comment */
2070 arity = get_irn_arity(block);
2072 be_emit_cstring(" none");
2074 for (i = 0; i < arity; ++i) {
2075 ir_node *predblock = get_Block_cfgpred_block(block, i);
2076 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2079 if (exec_freq != NULL) {
2080 be_emit_irprintf(", freq: %f",
2081 get_block_execfreq(exec_freq, block));
2083 be_emit_cstring(" */\n");
2084 be_emit_write_line();
2088 * Walks over the nodes in a block connected by scheduling edges
2089 * and emits code for each node.
2091 static void ia32_gen_block(ir_node *block)
2095 ia32_emit_block_header(block);
2097 /* emit the contents of the block */
2098 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2099 sched_foreach(block, node) {
2100 ia32_emit_node(node);
2104 typedef struct exc_entry {
2105 ir_node *exc_instr; /** The instruction that can issue an exception. */
2106 ir_node *block; /** The block to call then. */
2111 * Sets labels for control flow nodes (jump target).
2112 * Links control predecessors to there destination blocks.
2114 static void ia32_gen_labels(ir_node *block, void *data)
2116 exc_entry **exc_list = (exc_entry**)data;
2120 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2121 pred = get_Block_cfgpred(block, n);
2122 set_irn_link(pred, block);
2124 pred = skip_Proj(pred);
2125 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2130 ARR_APP1(exc_entry, *exc_list, e);
2131 set_irn_link(pred, block);
2137 * Compare two exception_entries.
2139 static int cmp_exc_entry(const void *a, const void *b)
2141 const exc_entry *ea = (const exc_entry*)a;
2142 const exc_entry *eb = (const exc_entry*)b;
2144 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2150 * Main driver. Emits the code for one routine.
2152 void ia32_gen_routine(ir_graph *irg)
2154 ir_entity *entity = get_irg_entity(irg);
2155 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2156 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
2157 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
2158 ir_node **blk_sched = irg_data->blk_sched;
2161 isa = (ia32_isa_t*) arch_env;
2162 do_pic = be_get_irg_options(irg)->pic;
2164 be_gas_elf_type_char = '@';
2166 ia32_register_emitters();
2168 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2170 be_dbg_method_begin(entity);
2171 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2173 /* we use links to point to target blocks */
2174 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2175 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2177 /* initialize next block links */
2178 n = ARR_LEN(blk_sched);
2179 for (i = 0; i < n; ++i) {
2180 ir_node *block = blk_sched[i];
2181 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
2183 set_irn_link(block, prev);
2186 for (i = 0; i < n; ++i) {
2187 ir_node *block = blk_sched[i];
2189 ia32_gen_block(block);
2192 be_gas_emit_function_epilog(entity);
2193 be_dbg_method_end();
2195 be_emit_write_line();
2197 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2199 /* Sort the exception table using the exception label id's.
2200 Those are ascending with ascending addresses. */
2201 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2205 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2206 be_emit_cstring("\t.long ");
2207 ia32_emit_exc_label(exc_list[i].exc_instr);
2209 be_emit_cstring("\t.long ");
2210 be_gas_emit_block_name(exc_list[i].block);
2214 DEL_ARR_F(exc_list);
2217 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2218 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2222 /* ==== Experimental binary emitter ==== */
2224 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2225 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2226 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2227 static unsigned char pnc_map_signed[8];
2228 static unsigned char pnc_map_unsigned[8];
2230 static void build_reg_map(void)
2232 reg_gp_map[REG_GP_EAX] = 0x0;
2233 reg_gp_map[REG_GP_ECX] = 0x1;
2234 reg_gp_map[REG_GP_EDX] = 0x2;
2235 reg_gp_map[REG_GP_EBX] = 0x3;
2236 reg_gp_map[REG_GP_ESP] = 0x4;
2237 reg_gp_map[REG_GP_EBP] = 0x5;
2238 reg_gp_map[REG_GP_ESI] = 0x6;
2239 reg_gp_map[REG_GP_EDI] = 0x7;
2241 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2242 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2243 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2244 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2245 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2246 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2248 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2249 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2250 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2251 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2252 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2253 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2256 /** Returns the encoding for a pnc field. */
2257 static unsigned char pnc2cc(int pnc)
2260 if (pnc == ia32_pn_Cmp_parity) {
2262 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2263 cc = pnc_map_unsigned[pnc & 0x07];
2265 cc = pnc_map_signed[pnc & 0x07];
2271 /** Sign extension bit values for binops */
2273 UNSIGNED_IMM = 0, /**< unsigned immediate */
2274 SIGNEXT_IMM = 2, /**< sign extended immediate */
2277 /** The mod encoding of the ModR/M */
2279 MOD_IND = 0x00, /**< [reg1] */
2280 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2281 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2282 MOD_REG = 0xC0 /**< reg1 */
2285 /** create R/M encoding for ModR/M */
2286 #define ENC_RM(x) (x)
2287 /** create REG encoding for ModR/M */
2288 #define ENC_REG(x) ((x) << 3)
2290 /** create encoding for a SIB byte */
2291 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2293 /* Node: The following routines are supposed to append bytes, words, dwords
2294 to the output stream.
2295 Currently the implementation is stupid in that it still creates output
2296 for an "assembler" in the form of .byte, .long
2297 We will change this when enough infrastructure is there to create complete
2298 machine code in memory/object files */
2300 static void bemit8(const unsigned char byte)
2302 be_emit_irprintf("\t.byte 0x%x\n", byte);
2303 be_emit_write_line();
2306 static void bemit16(const unsigned short u16)
2308 be_emit_irprintf("\t.word 0x%x\n", u16);
2309 be_emit_write_line();
2312 static void bemit32(const unsigned u32)
2314 be_emit_irprintf("\t.long 0x%x\n", u32);
2315 be_emit_write_line();
2319 * Emit address of an entity. If @p is_relative is true then a relative
2320 * offset from behind the address to the entity is created.
2322 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2325 if (entity == NULL) {
2330 /* the final version should remember the position in the bytestream
2331 and patch it with the correct address at linktime... */
2332 be_emit_cstring("\t.long ");
2335 be_gas_emit_entity(entity);
2337 if (get_entity_owner(entity) == get_tls_type()) {
2338 if (get_entity_visibility(entity) == ir_visibility_external) {
2339 be_emit_cstring("@INDNTPOFF");
2341 be_emit_cstring("@NTPOFF");
2346 be_emit_cstring("-.");
2351 be_emit_irprintf("%+d", offset);
2354 be_emit_write_line();
2357 static void bemit_jmp_destination(const ir_node *dest_block)
2359 be_emit_cstring("\t.long ");
2360 be_gas_emit_block_name(dest_block);
2361 be_emit_cstring(" - . - 4\n");
2362 be_emit_write_line();
2365 /* end emit routines, all emitters following here should only use the functions
2368 typedef enum reg_modifier {
2373 /** Create a ModR/M byte for src1,src2 registers */
2374 static void bemit_modrr(const arch_register_t *src1,
2375 const arch_register_t *src2)
2377 unsigned char modrm = MOD_REG;
2378 modrm |= ENC_RM(reg_gp_map[src1->index]);
2379 modrm |= ENC_REG(reg_gp_map[src2->index]);
2383 /** Create a ModR/M8 byte for src1,src2 registers */
2384 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2385 reg_modifier_t high_part2, const arch_register_t *src2)
2387 unsigned char modrm = MOD_REG;
2388 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2389 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2393 /** Create a ModR/M byte for one register and extension */
2394 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2396 unsigned char modrm = MOD_REG;
2398 modrm |= ENC_RM(reg_gp_map[reg->index]);
2399 modrm |= ENC_REG(ext);
2403 /** Create a ModR/M8 byte for one register */
2404 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2406 unsigned char modrm = MOD_REG;
2407 assert(reg_gp_map[reg->index] < 4);
2408 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2414 * Calculate the size of an signed immediate in bytes.
2416 * @param offset an offset
2418 static unsigned get_signed_imm_size(int offset)
2420 if (-128 <= offset && offset < 128) {
2422 } else if (-32768 <= offset && offset < 32768) {
2430 * Emit an address mode.
2432 * @param reg content of the reg field: either a register index or an opcode extension
2433 * @param node the node
2435 static void bemit_mod_am(unsigned reg, const ir_node *node)
2437 ir_entity *ent = get_ia32_am_sc(node);
2438 int offs = get_ia32_am_offs_int(node);
2439 ir_node *base = get_irn_n(node, n_ia32_base);
2440 int has_base = !is_ia32_NoReg_GP(base);
2441 ir_node *index = get_irn_n(node, n_ia32_index);
2442 int has_index = !is_ia32_NoReg_GP(index);
2445 unsigned emitoffs = 0;
2446 bool emitsib = false;
2449 /* set the mod part depending on displacement */
2451 modrm |= MOD_IND_WORD_OFS;
2453 } else if (offs == 0) {
2456 } else if (-128 <= offs && offs < 128) {
2457 modrm |= MOD_IND_BYTE_OFS;
2460 modrm |= MOD_IND_WORD_OFS;
2465 const arch_register_t *base_reg = arch_get_irn_register(base);
2466 base_enc = reg_gp_map[base_reg->index];
2468 /* Use the EBP encoding + MOD_IND if NO base register. There is
2469 * always a 32bit offset present in this case. */
2475 /* Determine if we need a SIB byte. */
2477 const arch_register_t *reg_index = arch_get_irn_register(index);
2478 int scale = get_ia32_am_scale(node);
2480 /* R/M set to ESP means SIB in 32bit mode. */
2481 modrm |= ENC_RM(0x04);
2482 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2484 } else if (base_enc == 0x04) {
2485 /* for the above reason we are forced to emit a SIB when base is ESP.
2486 * Only the base is used, index must be ESP too, which means no index.
2488 modrm |= ENC_RM(0x04);
2489 sib = ENC_SIB(0, 0x04, 0x04);
2492 modrm |= ENC_RM(base_enc);
2495 /* We are forced to emit an 8bit offset as EBP base without offset is a
2496 * special case for SIB without base register. */
2497 if (base_enc == 0x05 && emitoffs == 0) {
2498 modrm |= MOD_IND_BYTE_OFS;
2502 modrm |= ENC_REG(reg);
2508 /* emit displacement */
2509 if (emitoffs == 8) {
2510 bemit8((unsigned) offs);
2511 } else if (emitoffs == 32) {
2512 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2517 * Emit a binop with a immediate operand.
2519 * @param node the node to emit
2520 * @param opcode_eax the opcode for the op eax, imm variant
2521 * @param opcode the opcode for the reg, imm variant
2522 * @param ruval the opcode extension for opcode
2524 static void bemit_binop_with_imm(
2525 const ir_node *node,
2526 unsigned char opcode_ax,
2527 unsigned char opcode, unsigned char ruval)
2529 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2530 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2531 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2534 /* Some instructions (test) have no short form with 32bit value + 8bit
2536 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2539 /* check for sign extension */
2540 size = get_signed_imm_size(attr->offset);
2545 bemit8(opcode | SIGNEXT_IMM);
2546 /* cmp has this special mode */
2547 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2548 bemit_mod_am(ruval, node);
2550 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2551 bemit_modru(reg, ruval);
2553 bemit8((unsigned char)attr->offset);
2557 /* check for eax variant: this variant is shorter for 32bit immediates only */
2558 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2560 bemit_mod_am(ruval, node);
2562 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2563 if (reg->index == REG_GP_EAX) {
2567 bemit_modru(reg, ruval);
2570 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2573 panic("invalid imm size?!?");
2579 static void bemit_binop_2(const ir_node *node, unsigned code)
2581 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2583 if (get_ia32_op_type(node) == ia32_Normal) {
2584 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2585 bemit_modrr(op2, out);
2587 bemit_mod_am(reg_gp_map[out->index], node);
2594 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2596 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2597 if (is_ia32_Immediate(right)) {
2598 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2600 bemit_binop_2(node, opcodes[0]);
2607 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2610 if (get_ia32_op_type(node) == ia32_Normal) {
2611 const arch_register_t *in = get_in_reg(node, input);
2612 bemit_modru(in, ext);
2614 bemit_mod_am(ext, node);
2618 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2620 const arch_register_t *out = get_out_reg(node, 0);
2621 bemit_unop(node, code, reg_gp_map[out->index], input);
2624 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2626 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2629 bemit8(size == 8 ? code : code + 1);
2630 bemit_mod_am(ext, node);
2633 static void bemit_immediate(const ir_node *node, bool relative)
2635 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2636 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2639 static void bemit_copy(const ir_node *copy)
2641 const arch_register_t *in = get_in_reg(copy, 0);
2642 const arch_register_t *out = get_out_reg(copy, 0);
2646 /* copies of vf nodes aren't real... */
2647 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2650 if (get_irn_mode(copy) == mode_E) {
2653 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2655 bemit_modrr(in, out);
2659 static void bemit_perm(const ir_node *node)
2661 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2662 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2663 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2665 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2667 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2668 if (in0->index == REG_GP_EAX) {
2669 bemit8(0x90 + reg_gp_map[in1->index]);
2670 } else if (in1->index == REG_GP_EAX) {
2671 bemit8(0x90 + reg_gp_map[in0->index]);
2674 bemit_modrr(in0, in1);
2676 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2677 panic("unimplemented"); // TODO implement
2678 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2679 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2680 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2681 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2683 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2686 panic("unexpected register class in be_Perm (%+F)", node);
2690 static void bemit_xor0(const ir_node *node)
2692 const arch_register_t *out = get_out_reg(node, 0);
2694 bemit_modrr(out, out);
2697 static void bemit_mov_const(const ir_node *node)
2699 const arch_register_t *out = get_out_reg(node, 0);
2700 bemit8(0xB8 + reg_gp_map[out->index]);
2701 bemit_immediate(node, false);
2705 * Creates a function for a Binop with 3 possible encodings.
2707 #define BINOP(op, op0, op1, op2, op2_ext) \
2708 static void bemit_ ## op(const ir_node *node) { \
2709 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2710 bemit_binop(node, op ## _codes); \
2713 /* insn def eax,imm imm */
2714 BINOP(add, 0x03, 0x05, 0x81, 0)
2715 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2716 BINOP(adc, 0x13, 0x15, 0x81, 2)
2717 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2718 BINOP(and, 0x23, 0x25, 0x81, 4)
2719 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2720 BINOP(xor, 0x33, 0x35, 0x81, 6)
2721 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2723 #define BINOPMEM(op, ext) \
2724 static void bemit_##op(const ir_node *node) \
2727 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2730 val = get_irn_n(node, n_ia32_unary_op); \
2731 if (is_ia32_Immediate(val)) { \
2732 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2733 int offset = attr->offset; \
2734 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2736 bemit_mod_am(ext, node); \
2740 bemit_mod_am(ext, node); \
2744 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2748 bemit8(ext << 3 | 1); \
2749 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2753 static void bemit_##op##8bit(const ir_node *node) \
2755 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2756 if (is_ia32_Immediate(val)) { \
2758 bemit_mod_am(ext, node); \
2759 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2762 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2774 * Creates a function for an Unop with code /ext encoding.
2776 #define UNOP(op, code, ext, input) \
2777 static void bemit_ ## op(const ir_node *node) { \
2778 bemit_unop(node, code, ext, input); \
2781 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2782 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2783 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2784 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2785 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2786 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2788 /* TODO: am support for IJmp */
2789 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2791 #define SHIFT(op, ext) \
2792 static void bemit_##op(const ir_node *node) \
2794 const arch_register_t *out = get_out_reg(node, 0); \
2795 ir_node *count = get_irn_n(node, 1); \
2796 if (is_ia32_Immediate(count)) { \
2797 int offset = get_ia32_immediate_attr_const(count)->offset; \
2798 if (offset == 1) { \
2800 bemit_modru(out, ext); \
2803 bemit_modru(out, ext); \
2808 bemit_modru(out, ext); \
2812 static void bemit_##op##mem(const ir_node *node) \
2815 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2818 count = get_irn_n(node, 1); \
2819 if (is_ia32_Immediate(count)) { \
2820 int offset = get_ia32_immediate_attr_const(count)->offset; \
2821 if (offset == 1) { \
2822 bemit8(size == 8 ? 0xD0 : 0xD1); \
2823 bemit_mod_am(ext, node); \
2825 bemit8(size == 8 ? 0xC0 : 0xC1); \
2826 bemit_mod_am(ext, node); \
2830 bemit8(size == 8 ? 0xD2 : 0xD3); \
2831 bemit_mod_am(ext, node); \
2841 static void bemit_shld(const ir_node *node)
2843 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2844 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2845 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2847 if (is_ia32_Immediate(count)) {
2849 bemit_modrr(out, in);
2850 bemit8(get_ia32_immediate_attr_const(count)->offset);
2853 bemit_modrr(out, in);
2857 static void bemit_shrd(const ir_node *node)
2859 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2860 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2861 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2863 if (is_ia32_Immediate(count)) {
2865 bemit_modrr(out, in);
2866 bemit8(get_ia32_immediate_attr_const(count)->offset);
2869 bemit_modrr(out, in);
2874 * binary emitter for setcc.
2876 static void bemit_setcc(const ir_node *node)
2878 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2880 int pnc = get_ia32_condcode(node);
2881 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
2882 if (pnc & ia32_pn_Cmp_float) {
2883 switch (pnc & 0x0f) {
2888 bemit_modrm8(REG_LOW, dreg);
2895 bemit_modrm8(REG_LOW, dreg);
2903 bemit8(0x90 | pnc2cc(pnc));
2904 bemit_modrm8(REG_LOW, dreg);
2909 bemit_modrm8(REG_HIGH, dreg);
2911 /* andb %>dreg, %<dreg */
2913 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2921 bemit8(0x90 | pnc2cc(pnc));
2922 bemit_modrm8(REG_LOW, dreg);
2927 bemit_modrm8(REG_HIGH, dreg);
2929 /* orb %>dreg, %<dreg */
2931 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2940 bemit8(0x90 | pnc2cc(pnc));
2941 bemit_modrm8(REG_LOW, dreg);
2944 static void bemit_cmovcc(const ir_node *node)
2946 const ia32_attr_t *attr = get_ia32_attr_const(node);
2947 int ins_permuted = attr->data.ins_permuted;
2948 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2949 int pnc = get_ia32_condcode(node);
2950 const arch_register_t *in_true;
2951 const arch_register_t *in_false;
2953 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
2955 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2956 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2958 /* should be same constraint fullfilled? */
2959 if (out == in_false) {
2960 /* yes -> nothing to do */
2961 } else if (out == in_true) {
2962 assert(get_ia32_op_type(node) == ia32_Normal);
2963 ins_permuted = !ins_permuted;
2967 bemit8(0x8B); // mov %in_false, %out
2968 bemit_modrr(in_false, out);
2972 pnc = ia32_get_negated_pnc(pnc);
2974 /* TODO: handling of Nans isn't correct yet */
2977 bemit8(0x40 | pnc2cc(pnc));
2978 if (get_ia32_op_type(node) == ia32_Normal) {
2979 bemit_modrr(in_true, out);
2981 bemit_mod_am(reg_gp_map[out->index], node);
2985 static void bemit_cmp(const ir_node *node)
2987 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2993 right = get_irn_n(node, n_ia32_binary_right);
2994 if (is_ia32_Immediate(right)) {
2995 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2996 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2997 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
3000 if (attr->symconst != NULL) {
3003 /* check for sign extension */
3004 size = get_signed_imm_size(attr->offset);
3009 bemit8(0x81 | SIGNEXT_IMM);
3010 /* cmp has this special mode */
3011 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3012 bemit_mod_am(7, node);
3014 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3015 bemit_modru(reg, 7);
3017 bemit8((unsigned char)attr->offset);
3021 /* check for eax variant: this variant is shorter for 32bit immediates only */
3022 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3024 bemit_mod_am(7, node);
3026 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3027 if (reg->index == REG_GP_EAX) {
3031 bemit_modru(reg, 7);
3034 if (ls_size == 16) {
3035 bemit16(attr->offset);
3037 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3041 panic("invalid imm size?!?");
3043 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3045 if (get_ia32_op_type(node) == ia32_Normal) {
3046 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3047 bemit_modrr(op2, out);
3049 bemit_mod_am(reg_gp_map[out->index], node);
3054 static void bemit_cmp8bit(const ir_node *node)
3056 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3057 if (is_ia32_Immediate(right)) {
3058 if (get_ia32_op_type(node) == ia32_Normal) {
3059 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3060 if (out->index == REG_GP_EAX) {
3064 bemit_modru(out, 7);
3068 bemit_mod_am(7, node);
3070 bemit8(get_ia32_immediate_attr_const(right)->offset);
3072 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3074 if (get_ia32_op_type(node) == ia32_Normal) {
3075 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3076 bemit_modrr(out, in);
3078 bemit_mod_am(reg_gp_map[out->index], node);
3083 static void bemit_test8bit(const ir_node *node)
3085 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3086 if (is_ia32_Immediate(right)) {
3087 if (get_ia32_op_type(node) == ia32_Normal) {
3088 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3089 if (out->index == REG_GP_EAX) {
3093 bemit_modru(out, 0);
3097 bemit_mod_am(0, node);
3099 bemit8(get_ia32_immediate_attr_const(right)->offset);
3101 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3103 if (get_ia32_op_type(node) == ia32_Normal) {
3104 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3105 bemit_modrr(out, in);
3107 bemit_mod_am(reg_gp_map[out->index], node);
3112 static void bemit_imul(const ir_node *node)
3114 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3115 /* Do we need the immediate form? */
3116 if (is_ia32_Immediate(right)) {
3117 int imm = get_ia32_immediate_attr_const(right)->offset;
3118 if (get_signed_imm_size(imm) == 1) {
3119 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3122 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3127 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3131 static void bemit_dec(const ir_node *node)
3133 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3134 bemit8(0x48 + reg_gp_map[out->index]);
3137 static void bemit_inc(const ir_node *node)
3139 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3140 bemit8(0x40 + reg_gp_map[out->index]);
3143 #define UNOPMEM(op, code, ext) \
3144 static void bemit_##op(const ir_node *node) \
3146 bemit_unop_mem(node, code, ext); \
3149 UNOPMEM(notmem, 0xF6, 2)
3150 UNOPMEM(negmem, 0xF6, 3)
3151 UNOPMEM(incmem, 0xFE, 0)
3152 UNOPMEM(decmem, 0xFE, 1)
3154 static void bemit_ldtls(const ir_node *node)
3156 const arch_register_t *out = get_out_reg(node, 0);
3158 bemit8(0x65); // gs:
3159 if (out->index == REG_GP_EAX) {
3160 bemit8(0xA1); // movl 0, %eax
3162 bemit8(0x8B); // movl 0, %reg
3163 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3171 static void bemit_lea(const ir_node *node)
3173 const arch_register_t *out = get_out_reg(node, 0);
3175 bemit_mod_am(reg_gp_map[out->index], node);
3178 /* helper function for bemit_minus64bit */
3179 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3181 bemit8(0x8B); // movl %src, %dst
3182 bemit_modrr(src, dst);
3185 /* helper function for bemit_minus64bit */
3186 static void bemit_helper_neg(const arch_register_t *reg)
3188 bemit8(0xF7); // negl %reg
3189 bemit_modru(reg, 3);
3192 /* helper function for bemit_minus64bit */
3193 static void bemit_helper_sbb0(const arch_register_t *reg)
3195 bemit8(0x83); // sbbl $0, %reg
3196 bemit_modru(reg, 3);
3200 /* helper function for bemit_minus64bit */
3201 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3203 bemit8(0x1B); // sbbl %src, %dst
3204 bemit_modrr(src, dst);
3207 /* helper function for bemit_minus64bit */
3208 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3210 if (src->index == REG_GP_EAX) {
3211 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3212 } else if (dst->index == REG_GP_EAX) {
3213 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3215 bemit8(0x87); // xchgl %src, %dst
3216 bemit_modrr(src, dst);
3220 /* helper function for bemit_minus64bit */
3221 static void bemit_helper_zero(const arch_register_t *reg)
3223 bemit8(0x33); // xorl %reg, %reg
3224 bemit_modrr(reg, reg);
3227 static void bemit_minus64bit(const ir_node *node)
3229 const arch_register_t *in_lo = get_in_reg(node, 0);
3230 const arch_register_t *in_hi = get_in_reg(node, 1);
3231 const arch_register_t *out_lo = get_out_reg(node, 0);
3232 const arch_register_t *out_hi = get_out_reg(node, 1);
3234 if (out_lo == in_lo) {
3235 if (out_hi != in_hi) {
3236 /* a -> a, b -> d */
3239 /* a -> a, b -> b */
3242 } else if (out_lo == in_hi) {
3243 if (out_hi == in_lo) {
3244 /* a -> b, b -> a */
3245 bemit_helper_xchg(in_lo, in_hi);
3248 /* a -> b, b -> d */
3249 bemit_helper_mov(in_hi, out_hi);
3250 bemit_helper_mov(in_lo, out_lo);
3254 if (out_hi == in_lo) {
3255 /* a -> c, b -> a */
3256 bemit_helper_mov(in_lo, out_lo);
3258 } else if (out_hi == in_hi) {
3259 /* a -> c, b -> b */
3260 bemit_helper_mov(in_lo, out_lo);
3263 /* a -> c, b -> d */
3264 bemit_helper_mov(in_lo, out_lo);
3270 bemit_helper_neg( out_hi);
3271 bemit_helper_neg( out_lo);
3272 bemit_helper_sbb0(out_hi);
3276 bemit_helper_zero(out_hi);
3277 bemit_helper_neg( out_lo);
3278 bemit_helper_sbb( in_hi, out_hi);
3282 * Emit a single opcode.
3284 #define EMIT_SINGLEOP(op, code) \
3285 static void bemit_ ## op(const ir_node *node) { \
3290 //EMIT_SINGLEOP(daa, 0x27)
3291 //EMIT_SINGLEOP(das, 0x2F)
3292 //EMIT_SINGLEOP(aaa, 0x37)
3293 //EMIT_SINGLEOP(aas, 0x3F)
3294 //EMIT_SINGLEOP(nop, 0x90)
3295 EMIT_SINGLEOP(cwtl, 0x98)
3296 EMIT_SINGLEOP(cltd, 0x99)
3297 //EMIT_SINGLEOP(fwait, 0x9B)
3298 EMIT_SINGLEOP(sahf, 0x9E)
3299 //EMIT_SINGLEOP(popf, 0x9D)
3300 EMIT_SINGLEOP(leave, 0xC9)
3301 EMIT_SINGLEOP(int3, 0xCC)
3302 //EMIT_SINGLEOP(iret, 0xCF)
3303 //EMIT_SINGLEOP(xlat, 0xD7)
3304 //EMIT_SINGLEOP(lock, 0xF0)
3305 EMIT_SINGLEOP(rep, 0xF3)
3306 //EMIT_SINGLEOP(halt, 0xF4)
3307 EMIT_SINGLEOP(cmc, 0xF5)
3308 EMIT_SINGLEOP(stc, 0xF9)
3309 //EMIT_SINGLEOP(cli, 0xFA)
3310 //EMIT_SINGLEOP(sti, 0xFB)
3311 //EMIT_SINGLEOP(std, 0xFD)
3314 * Emits a MOV out, [MEM].
3316 static void bemit_load(const ir_node *node)
3318 const arch_register_t *out = get_out_reg(node, 0);
3320 if (out->index == REG_GP_EAX) {
3321 ir_node *base = get_irn_n(node, n_ia32_base);
3322 int has_base = !is_ia32_NoReg_GP(base);
3323 ir_node *index = get_irn_n(node, n_ia32_index);
3324 int has_index = !is_ia32_NoReg_GP(index);
3325 if (!has_base && !has_index) {
3326 ir_entity *ent = get_ia32_am_sc(node);
3327 int offs = get_ia32_am_offs_int(node);
3328 /* load from constant address to EAX can be encoded
3331 bemit_entity(ent, 0, offs, false);
3336 bemit_mod_am(reg_gp_map[out->index], node);
3340 * Emits a MOV [mem], in.
3342 static void bemit_store(const ir_node *node)
3344 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3345 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3347 if (is_ia32_Immediate(value)) {
3350 bemit_mod_am(0, node);
3351 bemit8(get_ia32_immediate_attr_const(value)->offset);
3352 } else if (size == 16) {
3355 bemit_mod_am(0, node);
3356 bemit16(get_ia32_immediate_attr_const(value)->offset);
3359 bemit_mod_am(0, node);
3360 bemit_immediate(value, false);
3363 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3365 if (in->index == REG_GP_EAX) {
3366 ir_node *base = get_irn_n(node, n_ia32_base);
3367 int has_base = !is_ia32_NoReg_GP(base);
3368 ir_node *index = get_irn_n(node, n_ia32_index);
3369 int has_index = !is_ia32_NoReg_GP(index);
3370 if (!has_base && !has_index) {
3371 ir_entity *ent = get_ia32_am_sc(node);
3372 int offs = get_ia32_am_offs_int(node);
3373 /* store to constant address from EAX can be encoded as
3374 * 0xA2/0xA3 [offset]*/
3382 bemit_entity(ent, 0, offs, false);
3394 bemit_mod_am(reg_gp_map[in->index], node);
3398 static void bemit_conv_i2i(const ir_node *node)
3400 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3409 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3410 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3411 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3417 static void bemit_push(const ir_node *node)
3419 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3421 if (is_ia32_Immediate(value)) {
3422 const ia32_immediate_attr_t *attr
3423 = get_ia32_immediate_attr_const(value);
3424 unsigned size = get_signed_imm_size(attr->offset);
3430 bemit8((unsigned char)attr->offset);
3435 bemit_immediate(value, false);
3438 } else if (is_ia32_NoReg_GP(value)) {
3440 bemit_mod_am(6, node);
3442 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3443 bemit8(0x50 + reg_gp_map[reg->index]);
3450 static void bemit_pop(const ir_node *node)
3452 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3453 bemit8(0x58 + reg_gp_map[reg->index]);
3456 static void bemit_popmem(const ir_node *node)
3459 bemit_mod_am(0, node);
3462 static void bemit_call(const ir_node *node)
3464 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3466 if (is_ia32_Immediate(proc)) {
3468 bemit_immediate(proc, true);
3470 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3474 static void bemit_jmp(const ir_node *dest_block)
3477 bemit_jmp_destination(dest_block);
3480 static void bemit_jump(const ir_node *node)
3482 if (can_be_fallthrough(node))
3485 bemit_jmp(get_cfop_target_block(node));
3488 static void bemit_jcc(int pnc, const ir_node *dest_block)
3490 unsigned char cc = pnc2cc(pnc);
3493 bemit_jmp_destination(dest_block);
3496 static void bemit_jp(bool odd, const ir_node *dest_block)
3500 bemit_jmp_destination(dest_block);
3503 static void bemit_ia32_jcc(const ir_node *node)
3505 int pnc = get_ia32_condcode(node);
3506 const ir_node *proj_true;
3507 const ir_node *proj_false;
3508 const ir_node *dest_true;
3509 const ir_node *dest_false;
3510 const ir_node *block;
3512 pnc = determine_final_pnc(node, 0, pnc);
3514 /* get both Projs */
3515 proj_true = get_proj(node, pn_ia32_Jcc_true);
3516 assert(proj_true && "Jcc without true Proj");
3518 proj_false = get_proj(node, pn_ia32_Jcc_false);
3519 assert(proj_false && "Jcc without false Proj");
3521 block = get_nodes_block(node);
3523 if (can_be_fallthrough(proj_true)) {
3524 /* exchange both proj's so the second one can be omitted */
3525 const ir_node *t = proj_true;
3527 proj_true = proj_false;
3529 pnc = ia32_get_negated_pnc(pnc);
3532 dest_true = get_cfop_target_block(proj_true);
3533 dest_false = get_cfop_target_block(proj_false);
3535 if (pnc & ia32_pn_Cmp_float) {
3536 /* Some floating point comparisons require a test of the parity flag,
3537 * which indicates that the result is unordered */
3540 bemit_jp(false, dest_true);
3545 bemit_jp(true, dest_true);
3551 /* we need a local label if the false proj is a fallthrough
3552 * as the falseblock might have no label emitted then */
3553 if (can_be_fallthrough(proj_false)) {
3555 bemit8(0x06); // jp + 6
3557 bemit_jp(false, dest_false);
3564 bemit_jp(false, dest_true);
3572 bemit_jcc(pnc, dest_true);
3575 /* the second Proj might be a fallthrough */
3576 if (can_be_fallthrough(proj_false)) {
3577 /* it's a fallthrough */
3579 bemit_jmp(dest_false);
3583 static void bemit_switchjmp(const ir_node *node)
3585 unsigned long interval;
3589 const arch_register_t *in;
3591 /* fill the table structure */
3592 generate_jump_table(&tbl, node);
3594 /* two-complement's magic make this work without overflow */
3595 interval = tbl.max_value - tbl.min_value;
3597 in = get_in_reg(node, 0);
3598 /* emit the table */
3599 if (get_signed_imm_size(interval) == 1) {
3600 bemit8(0x83); // cmpl $imm8, %in
3604 bemit8(0x81); // cmpl $imm32, %in
3608 bemit8(0x0F); // ja tbl.defProj
3610 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3612 if (tbl.num_branches > 1) {
3614 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3615 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3616 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3617 be_emit_irprintf("\t.long %s\n", tbl.label);
3619 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3620 be_emit_cstring(".align 4\n");
3621 be_emit_irprintf("%s:\n", tbl.label);
3623 last_value = tbl.branches[0].value;
3624 for (i = 0; i != tbl.num_branches; ++i) {
3625 while (last_value != tbl.branches[i].value) {
3626 ia32_emitf(tbl.defProj, ".long %L\n");
3629 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3632 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3634 /* one jump is enough */
3635 panic("switch only has one case");
3636 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3639 be_emit_write_line();
3647 static void bemit_return(const ir_node *node)
3649 unsigned pop = be_Return_get_pop(node);
3650 if (pop > 0 || be_Return_get_emit_pop(node)) {
3652 assert(pop <= 0xffff);
3659 static void bemit_subsp(const ir_node *node)
3661 const arch_register_t *out;
3664 /* mov %esp, %out */
3666 out = get_out_reg(node, 1);
3667 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3670 static void bemit_incsp(const ir_node *node)
3673 const arch_register_t *reg;
3677 offs = be_get_IncSP_offset(node);
3688 size = get_signed_imm_size(offs);
3689 bemit8(size == 1 ? 0x83 : 0x81);
3691 reg = get_out_reg(node, 0);
3692 bemit_modru(reg, ext);
3701 static void bemit_copybi(const ir_node *node)
3703 unsigned size = get_ia32_copyb_size(node);
3705 bemit8(0xA4); // movsb
3708 bemit8(0xA5); // movsw
3712 bemit8(0xA5); // movsl
3716 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3718 if (get_ia32_op_type(node) == ia32_Normal) {
3719 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3720 const arch_register_t *in1 = x87_attr->x87[0];
3721 const arch_register_t *in = x87_attr->x87[1];
3722 const arch_register_t *out = x87_attr->x87[2];
3726 } else if (out == in) {
3730 if (out->index == 0) {
3732 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3735 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3738 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3743 bemit_mod_am(code, node);
3747 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3749 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3750 const arch_register_t *out = x87_attr->x87[2];
3752 bemit8(code + out->index);
3755 static void bemit_fabs(const ir_node *node)
3763 static void bemit_fadd(const ir_node *node)
3765 bemit_fbinop(node, 0, 0);
3768 static void bemit_faddp(const ir_node *node)
3770 bemit_fbinopp(node, 0xC0);
3773 static void bemit_fchs(const ir_node *node)
3781 static void bemit_fdiv(const ir_node *node)
3783 bemit_fbinop(node, 6, 7);
3786 static void bemit_fdivp(const ir_node *node)
3788 bemit_fbinopp(node, 0xF8);
3791 static void bemit_fdivr(const ir_node *node)
3793 bemit_fbinop(node, 7, 6);
3796 static void bemit_fdivrp(const ir_node *node)
3798 bemit_fbinopp(node, 0xF0);
3801 static void bemit_fild(const ir_node *node)
3803 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3805 bemit8(0xDF); // filds
3806 bemit_mod_am(0, node);
3810 bemit8(0xDB); // fildl
3811 bemit_mod_am(0, node);
3815 bemit8(0xDF); // fildll
3816 bemit_mod_am(5, node);
3820 panic("invalid mode size");
3824 static void bemit_fist(const ir_node *node)
3826 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3828 bemit8(0xDF); // fists
3832 bemit8(0xDB); // fistl
3836 panic("invalid mode size");
3838 bemit_mod_am(2, node);
3841 static void bemit_fistp(const ir_node *node)
3843 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3845 bemit8(0xDF); // fistps
3846 bemit_mod_am(3, node);
3850 bemit8(0xDB); // fistpl
3851 bemit_mod_am(3, node);
3855 bemit8(0xDF); // fistpll
3856 bemit_mod_am(7, node);
3860 panic("invalid mode size");
3864 static void bemit_fld(const ir_node *node)
3866 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3868 bemit8(0xD9); // flds
3869 bemit_mod_am(0, node);
3873 bemit8(0xDD); // fldl
3874 bemit_mod_am(0, node);
3879 bemit8(0xDB); // fldt
3880 bemit_mod_am(5, node);
3884 panic("invalid mode size");
3888 static void bemit_fld1(const ir_node *node)
3892 bemit8(0xE8); // fld1
3895 static void bemit_fldcw(const ir_node *node)
3897 bemit8(0xD9); // fldcw
3898 bemit_mod_am(5, node);
3901 static void bemit_fldz(const ir_node *node)
3905 bemit8(0xEE); // fldz
3908 static void bemit_fmul(const ir_node *node)
3910 bemit_fbinop(node, 1, 1);
3913 static void bemit_fmulp(const ir_node *node)
3915 bemit_fbinopp(node, 0xC8);
3918 static void bemit_fpop(const ir_node *node)
3920 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3922 bemit8(0xD8 + attr->x87[0]->index);
3925 static void bemit_fpush(const ir_node *node)
3927 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3929 bemit8(0xC0 + attr->x87[0]->index);
3932 static void bemit_fpushcopy(const ir_node *node)
3934 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3936 bemit8(0xC0 + attr->x87[0]->index);
3939 static void bemit_fst(const ir_node *node)
3941 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3943 bemit8(0xD9); // fsts
3947 bemit8(0xDD); // fstl
3951 panic("invalid mode size");
3953 bemit_mod_am(2, node);
3956 static void bemit_fstp(const ir_node *node)
3958 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3960 bemit8(0xD9); // fstps
3961 bemit_mod_am(3, node);
3965 bemit8(0xDD); // fstpl
3966 bemit_mod_am(3, node);
3971 bemit8(0xDB); // fstpt
3972 bemit_mod_am(7, node);
3976 panic("invalid mode size");
3980 static void bemit_fsub(const ir_node *node)
3982 bemit_fbinop(node, 4, 5);
3985 static void bemit_fsubp(const ir_node *node)
3987 bemit_fbinopp(node, 0xE8);
3990 static void bemit_fsubr(const ir_node *node)
3992 bemit_fbinop(node, 5, 4);
3995 static void bemit_fsubrp(const ir_node *node)
3997 bemit_fbinopp(node, 0xE0);
4000 static void bemit_fnstcw(const ir_node *node)
4002 bemit8(0xD9); // fnstcw
4003 bemit_mod_am(7, node);
4006 static void bemit_fnstsw(void)
4008 bemit8(0xDF); // fnstsw %ax
4012 static void bemit_ftstfnstsw(const ir_node *node)
4016 bemit8(0xD9); // ftst
4021 static void bemit_fucomi(const ir_node *node)
4023 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4024 bemit8(0xDB); // fucomi
4025 bemit8(0xE8 + attr->x87[1]->index);
4028 static void bemit_fucomip(const ir_node *node)
4030 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4031 bemit8(0xDF); // fucomip
4032 bemit8(0xE8 + attr->x87[1]->index);
4035 static void bemit_fucomfnstsw(const ir_node *node)
4037 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4038 bemit8(0xDD); // fucom
4039 bemit8(0xE0 + attr->x87[1]->index);
4043 static void bemit_fucompfnstsw(const ir_node *node)
4045 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4046 bemit8(0xDD); // fucomp
4047 bemit8(0xE8 + attr->x87[1]->index);
4051 static void bemit_fucomppfnstsw(const ir_node *node)
4055 bemit8(0xDA); // fucompp
4060 static void bemit_fxch(const ir_node *node)
4062 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4064 bemit8(0xC8 + attr->x87[0]->index);
4068 * The type of a emitter function.
4070 typedef void (*emit_func) (const ir_node *);
4073 * Set a node emitter. Make it a bit more type safe.
4075 static void register_emitter(ir_op *op, emit_func func)
4077 op->ops.generic = (op_func) func;
4080 static void ia32_register_binary_emitters(void)
4082 /* first clear the generic function pointer for all ops */
4083 clear_irp_opcodes_generic_func();
4085 /* benode emitter */
4086 register_emitter(op_be_Copy, bemit_copy);
4087 register_emitter(op_be_CopyKeep, bemit_copy);
4088 register_emitter(op_be_IncSP, bemit_incsp);
4089 register_emitter(op_be_Perm, bemit_perm);
4090 register_emitter(op_be_Return, bemit_return);
4091 register_emitter(op_ia32_Adc, bemit_adc);
4092 register_emitter(op_ia32_Add, bemit_add);
4093 register_emitter(op_ia32_AddMem, bemit_addmem);
4094 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4095 register_emitter(op_ia32_And, bemit_and);
4096 register_emitter(op_ia32_AndMem, bemit_andmem);
4097 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4098 register_emitter(op_ia32_Breakpoint, bemit_int3);
4099 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4100 register_emitter(op_ia32_Call, bemit_call);
4101 register_emitter(op_ia32_Cltd, bemit_cltd);
4102 register_emitter(op_ia32_Cmc, bemit_cmc);
4103 register_emitter(op_ia32_Cmp, bemit_cmp);
4104 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4105 register_emitter(op_ia32_Const, bemit_mov_const);
4106 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4107 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4108 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4109 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4110 register_emitter(op_ia32_Dec, bemit_dec);
4111 register_emitter(op_ia32_DecMem, bemit_decmem);
4112 register_emitter(op_ia32_Div, bemit_div);
4113 register_emitter(op_ia32_FldCW, bemit_fldcw);
4114 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4115 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4116 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4117 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4118 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4119 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4120 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4121 register_emitter(op_ia32_IDiv, bemit_idiv);
4122 register_emitter(op_ia32_IJmp, bemit_ijmp);
4123 register_emitter(op_ia32_IMul, bemit_imul);
4124 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4125 register_emitter(op_ia32_Inc, bemit_inc);
4126 register_emitter(op_ia32_IncMem, bemit_incmem);
4127 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4128 register_emitter(op_ia32_Jmp, bemit_jump);
4129 register_emitter(op_ia32_LdTls, bemit_ldtls);
4130 register_emitter(op_ia32_Lea, bemit_lea);
4131 register_emitter(op_ia32_Leave, bemit_leave);
4132 register_emitter(op_ia32_Load, bemit_load);
4133 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4134 register_emitter(op_ia32_Mul, bemit_mul);
4135 register_emitter(op_ia32_Neg, bemit_neg);
4136 register_emitter(op_ia32_NegMem, bemit_negmem);
4137 register_emitter(op_ia32_Not, bemit_not);
4138 register_emitter(op_ia32_NotMem, bemit_notmem);
4139 register_emitter(op_ia32_Or, bemit_or);
4140 register_emitter(op_ia32_OrMem, bemit_ormem);
4141 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4142 register_emitter(op_ia32_Pop, bemit_pop);
4143 register_emitter(op_ia32_PopEbp, bemit_pop);
4144 register_emitter(op_ia32_PopMem, bemit_popmem);
4145 register_emitter(op_ia32_Push, bemit_push);
4146 register_emitter(op_ia32_RepPrefix, bemit_rep);
4147 register_emitter(op_ia32_Rol, bemit_rol);
4148 register_emitter(op_ia32_RolMem, bemit_rolmem);
4149 register_emitter(op_ia32_Ror, bemit_ror);
4150 register_emitter(op_ia32_RorMem, bemit_rormem);
4151 register_emitter(op_ia32_Sahf, bemit_sahf);
4152 register_emitter(op_ia32_Sar, bemit_sar);
4153 register_emitter(op_ia32_SarMem, bemit_sarmem);
4154 register_emitter(op_ia32_Sbb, bemit_sbb);
4155 register_emitter(op_ia32_Setcc, bemit_setcc);
4156 register_emitter(op_ia32_Shl, bemit_shl);
4157 register_emitter(op_ia32_ShlD, bemit_shld);
4158 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4159 register_emitter(op_ia32_Shr, bemit_shr);
4160 register_emitter(op_ia32_ShrD, bemit_shrd);
4161 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4162 register_emitter(op_ia32_Stc, bemit_stc);
4163 register_emitter(op_ia32_Store, bemit_store);
4164 register_emitter(op_ia32_Store8Bit, bemit_store);
4165 register_emitter(op_ia32_Sub, bemit_sub);
4166 register_emitter(op_ia32_SubMem, bemit_submem);
4167 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4168 register_emitter(op_ia32_SubSP, bemit_subsp);
4169 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4170 register_emitter(op_ia32_Test, bemit_test);
4171 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4172 register_emitter(op_ia32_Xor, bemit_xor);
4173 register_emitter(op_ia32_Xor0, bemit_xor0);
4174 register_emitter(op_ia32_XorMem, bemit_xormem);
4175 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4176 register_emitter(op_ia32_fabs, bemit_fabs);
4177 register_emitter(op_ia32_fadd, bemit_fadd);
4178 register_emitter(op_ia32_faddp, bemit_faddp);
4179 register_emitter(op_ia32_fchs, bemit_fchs);
4180 register_emitter(op_ia32_fdiv, bemit_fdiv);
4181 register_emitter(op_ia32_fdivp, bemit_fdivp);
4182 register_emitter(op_ia32_fdivr, bemit_fdivr);
4183 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4184 register_emitter(op_ia32_fild, bemit_fild);
4185 register_emitter(op_ia32_fist, bemit_fist);
4186 register_emitter(op_ia32_fistp, bemit_fistp);
4187 register_emitter(op_ia32_fld, bemit_fld);
4188 register_emitter(op_ia32_fld1, bemit_fld1);
4189 register_emitter(op_ia32_fldz, bemit_fldz);
4190 register_emitter(op_ia32_fmul, bemit_fmul);
4191 register_emitter(op_ia32_fmulp, bemit_fmulp);
4192 register_emitter(op_ia32_fpop, bemit_fpop);
4193 register_emitter(op_ia32_fpush, bemit_fpush);
4194 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4195 register_emitter(op_ia32_fst, bemit_fst);
4196 register_emitter(op_ia32_fstp, bemit_fstp);
4197 register_emitter(op_ia32_fsub, bemit_fsub);
4198 register_emitter(op_ia32_fsubp, bemit_fsubp);
4199 register_emitter(op_ia32_fsubr, bemit_fsubr);
4200 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4201 register_emitter(op_ia32_fxch, bemit_fxch);
4203 /* ignore the following nodes */
4204 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4205 register_emitter(op_be_Barrier, emit_Nothing);
4206 register_emitter(op_be_Keep, emit_Nothing);
4207 register_emitter(op_be_Start, emit_Nothing);
4208 register_emitter(op_Phi, emit_Nothing);
4209 register_emitter(op_Start, emit_Nothing);
4212 static void gen_binary_block(ir_node *block)
4216 ia32_emit_block_header(block);
4218 /* emit the contents of the block */
4219 sched_foreach(block, node) {
4220 ia32_emit_node(node);
4224 void ia32_gen_binary_routine(ir_graph *irg)
4226 ir_entity *entity = get_irg_entity(irg);
4227 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
4228 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
4229 ir_node **blk_sched = irg_data->blk_sched;
4232 isa = (ia32_isa_t*) arch_env;
4234 ia32_register_binary_emitters();
4236 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4238 /* we use links to point to target blocks */
4239 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4240 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4242 /* initialize next block links */
4243 n = ARR_LEN(blk_sched);
4244 for (i = 0; i < n; ++i) {
4245 ir_node *block = blk_sched[i];
4246 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
4248 set_irn_link(block, prev);
4251 for (i = 0; i < n; ++i) {
4252 ir_node *block = blk_sched[i];
4253 gen_binary_block(block);
4256 be_gas_emit_function_epilog(entity);
4257 be_dbg_method_end();
4259 be_emit_write_line();
4261 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4265 void ia32_init_emitter(void)
4267 lc_opt_entry_t *be_grp;
4268 lc_opt_entry_t *ia32_grp;
4270 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4271 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4273 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4277 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");