2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "../be_dbgout.h"
29 #include "ia32_emitter.h"
30 #include "gen_ia32_emitter.h"
31 #include "gen_ia32_regalloc_if.h"
32 #include "ia32_nodes_attr.h"
33 #include "ia32_new_nodes.h"
34 #include "ia32_map_regs.h"
35 #include "bearch_ia32_t.h"
37 #define BLOCK_PREFIX(x) ".L" x
39 #define SNPRINTF_BUF_LEN 128
41 /* global arch_env for lc_printf functions */
42 static const arch_env_t *arch_env = NULL;
44 /** by default, we generate assembler code for the Linux gas */
45 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
48 * Switch to a new section
50 void ia32_switch_section(FILE *F, section_t sec) {
51 static section_t curr_sec = NO_SECTION;
52 static const char *text[ASM_MAX][SECTION_MAX] = {
58 ".section\t.tbss,\"awT\",@nobits",
59 ".section\t.ctors,\"aw\",@progbits"
64 ".section .rdata,\"dr\"",
66 ".section\t.tbss,\"awT\",@nobits",
67 ".section\t.ctors,\"aw\",@progbits"
86 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
94 static void ia32_dump_function_object(FILE *F, const char *name)
96 switch (asm_flavour) {
98 fprintf(F, "\t.type\t%s, @function\n", name);
101 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
108 static void ia32_dump_function_size(FILE *F, const char *name)
110 switch (asm_flavour) {
112 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
119 /*************************************************************
121 * (_) | | / _| | | | |
122 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
123 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
124 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
125 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
128 *************************************************************/
130 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
132 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
133 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
134 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
138 * returns true if a node has x87 registers
140 static INLINE int has_x87_register(const ir_node *n) {
141 return is_irn_machine_user(n, 0);
144 /* We always pass the ir_node which is a pointer. */
145 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
146 return lc_arg_type_ptr;
151 * Returns the register at in position pos.
153 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
155 const arch_register_t *reg = NULL;
157 assert(get_irn_arity(irn) > pos && "Invalid IN position");
159 /* The out register of the operator at position pos is the
160 in register we need. */
161 op = get_irn_n(irn, pos);
163 reg = arch_get_irn_register(arch_env, op);
165 assert(reg && "no in register found");
167 /* in case of unknown: just return a register */
168 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
169 reg = &ia32_gp_regs[REG_EAX];
170 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
171 reg = &ia32_xmm_regs[REG_XMM0];
172 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
173 reg = &ia32_vfp_regs[REG_VF0];
179 * Returns the register at out position pos.
181 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
183 const arch_register_t *reg = NULL;
185 /* 1st case: irn is not of mode_T, so it has only */
186 /* one OUT register -> good */
187 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
188 /* Proj with the corresponding projnum for the register */
190 if (get_irn_mode(irn) != mode_T) {
191 reg = arch_get_irn_register(arch_env, irn);
193 else if (is_ia32_irn(irn)) {
194 reg = get_ia32_out_reg(irn, pos);
197 const ir_edge_t *edge;
199 foreach_out_edge(irn, edge) {
200 proj = get_edge_src_irn(edge);
201 assert(is_Proj(proj) && "non-Proj from mode_T node");
202 if (get_Proj_proj(proj) == pos) {
203 reg = arch_get_irn_register(arch_env, proj);
209 assert(reg && "no out register found");
219 * Returns the name of the in register at position pos.
221 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
222 const arch_register_t *reg;
224 if (in_out == IN_REG) {
225 reg = get_in_reg(irn, pos);
227 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
228 /* FIXME: works for binop only */
229 assert(2 <= pos && pos <= 3);
230 reg = get_ia32_attr(irn)->x87[pos - 2];
234 /* destination address mode nodes don't have outputs */
235 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
239 reg = get_out_reg(irn, pos);
240 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
241 reg = get_ia32_attr(irn)->x87[pos + 2];
243 return arch_register_get_name(reg);
247 * Get the register name for a node.
249 static int ia32_get_reg_name(lc_appendable_t *app,
250 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
253 ir_node *irn = arg->v_ptr;
254 int nr = occ->width - 1;
257 return lc_appendable_snadd(app, "(null)", 6);
259 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
261 /* append the stupid % to register names */
262 lc_appendable_chadd(app, '%');
263 return lc_appendable_snadd(app, buf, strlen(buf));
267 * Get the x87 register name for a node.
269 static int ia32_get_x87_name(lc_appendable_t *app,
270 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
273 ir_node *irn = arg->v_ptr;
274 int nr = occ->width - 1;
278 return lc_appendable_snadd(app, "(null)", 6);
280 attr = get_ia32_attr(irn);
281 buf = attr->x87[nr]->name;
282 lc_appendable_chadd(app, '%');
283 return lc_appendable_snadd(app, buf, strlen(buf));
287 * Returns the tarval, offset or scale of an ia32 as a string.
289 static int ia32_const_to_str(lc_appendable_t *app,
290 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
293 ir_node *irn = arg->v_ptr;
296 return lc_arg_append(app, occ, "(null)", 6);
298 if (occ->conversion == 'C') {
299 buf = get_ia32_cnst(irn);
302 buf = get_ia32_am_offs(irn);
305 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
309 * Determines the SSE suffix depending on the mode.
311 static int ia32_get_mode_suffix(lc_appendable_t *app,
312 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
314 ir_node *irn = arg->v_ptr;
315 ir_mode *mode = get_irn_mode(irn);
317 if (mode == mode_T) {
318 mode = get_ia32_res_mode(irn);
320 mode = get_ia32_ls_mode(irn);
324 return lc_arg_append(app, occ, "(null)", 6);
326 if (mode_is_float(mode)) {
327 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
330 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
335 * Return the ia32 printf arg environment.
336 * We use the firm environment with some additional handlers.
338 const lc_arg_env_t *ia32_get_arg_env(void) {
339 static lc_arg_env_t *env = NULL;
341 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
342 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
343 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
344 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
347 /* extend the firm printer */
348 env = firm_get_arg_env();
350 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
351 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
352 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
353 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
354 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
355 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
361 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
362 switch(get_mode_size_bits(mode)) {
364 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
366 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
368 return (char *)arch_register_get_name(reg);
373 * Emits registers and/or address mode of a binary operation.
375 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
376 static char *buf = NULL;
378 /* verify that this function is never called on non-AM supporting operations */
379 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
381 #define PRODUCES_RESULT(n) \
382 (!(is_ia32_St(n) || \
383 is_ia32_Store8Bit(n) || \
384 is_ia32_CondJmp(n) || \
385 is_ia32_xCondJmp(n) || \
386 is_ia32_CmpSet(n) || \
387 is_ia32_xCmpSet(n) || \
388 is_ia32_SwitchJmp(n)))
391 buf = xcalloc(1, SNPRINTF_BUF_LEN);
394 memset(buf, 0, SNPRINTF_BUF_LEN);
397 switch(get_ia32_op_type(n)) {
399 if (is_ia32_ImmConst(n)) {
400 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
402 else if (is_ia32_ImmSymConst(n)) {
403 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
406 const arch_register_t *in1 = get_in_reg(n, 2);
407 const arch_register_t *in2 = get_in_reg(n, 3);
408 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
409 const arch_register_t *in;
412 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
413 out = out ? out : in1;
414 in_name = arch_register_get_name(in);
416 if (is_ia32_emit_cl(n)) {
417 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
421 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
425 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
426 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
427 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
430 if (PRODUCES_RESULT(n)) {
431 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
434 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
439 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
440 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
441 ia32_emit_am(n, env),
442 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
443 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
446 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
447 ir_mode *mode = get_ia32_res_mode(n);
450 mode = mode ? mode : get_ia32_ls_mode(n);
451 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
453 if (is_ia32_emit_cl(n)) {
454 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
458 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
462 assert(0 && "unsupported op type");
465 #undef PRODUCES_RESULT
471 * Returns the xxx PTR string for a given mode
473 * @param mode the mode
474 * @param x87_insn if non-zero returns the string for a x87 instruction
475 * else for a SSE instruction
477 static const char *pointer_size(ir_mode *mode, int x87_insn)
480 switch (get_mode_size_bits(mode)) {
481 case 8: return "BYTE PTR";
482 case 16: return "WORD PTR";
483 case 32: return "DWORD PTR";
489 case 96: return "XWORD PTR";
490 default: return NULL;
497 * Emits registers and/or address mode of a binary operation.
499 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
500 static char *buf = NULL;
502 /* verify that this function is never called on non-AM supporting operations */
503 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
506 buf = xcalloc(1, SNPRINTF_BUF_LEN);
509 memset(buf, 0, SNPRINTF_BUF_LEN);
512 switch(get_ia32_op_type(n)) {
514 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
515 ir_mode *mode = get_ia32_ls_mode(n);
516 const char *p = pointer_size(mode, 1);
517 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
520 ia32_attr_t *attr = get_ia32_attr(n);
521 const arch_register_t *in1 = attr->x87[0];
522 const arch_register_t *in2 = attr->x87[1];
523 const arch_register_t *out = attr->x87[2];
524 const arch_register_t *in;
527 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
528 out = out ? out : in1;
529 in_name = arch_register_get_name(in);
531 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
536 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
539 assert(0 && "unsupported op type");
546 * Emits registers and/or address mode of a unary operation.
548 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
549 static char *buf = NULL;
552 buf = xcalloc(1, SNPRINTF_BUF_LEN);
555 memset(buf, 0, SNPRINTF_BUF_LEN);
558 switch(get_ia32_op_type(n)) {
560 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
561 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
564 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
565 /* MulS and Mulh implicitly multiply by EAX */
566 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
569 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
573 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
577 Mulh is emitted via emit_unop
578 imul [MEM] means EDX:EAX <- EAX * [MEM]
580 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
581 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
584 assert(0 && "unsupported op type");
591 * Emits address mode.
593 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
594 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
598 static struct obstack *obst = NULL;
599 ir_mode *mode = get_ia32_ls_mode(n);
601 if (! is_ia32_Lea(n))
602 assert(mode && "AM node must have ls_mode attribute set.");
605 obst = xcalloc(1, sizeof(*obst));
608 obstack_free(obst, NULL);
611 /* obstack_free with NULL results in an uninitialized obstack */
614 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
616 obstack_printf(obst, "%s ", p);
618 /* emit address mode symconst */
619 if (get_ia32_am_sc(n)) {
620 if (is_ia32_am_sc_sign(n))
621 obstack_printf(obst, "-");
622 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
625 if (am_flav & ia32_B) {
626 obstack_printf(obst, "[");
627 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
631 if (am_flav & ia32_I) {
633 obstack_printf(obst, "+");
636 obstack_printf(obst, "[");
639 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
641 if (am_flav & ia32_S) {
642 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
648 if (am_flav & ia32_O) {
649 s = get_ia32_am_offs(n);
652 /* omit explicit + if there was no base or index */
654 obstack_printf(obst, "[");
659 obstack_printf(obst, s);
665 obstack_printf(obst, "] ");
667 obstack_1grow(obst, '\0');
668 s = obstack_finish(obst);
676 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
678 static char buf[SNPRINTF_BUF_LEN];
679 ir_mode *mode = get_ia32_ls_mode(irn);
680 const char *adr = get_ia32_cnst(irn);
681 const char *pref = pointer_size(mode, has_x87_register(irn));
683 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
688 * Formated print of commands and comments.
690 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
692 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
695 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
697 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
703 * Add a number to a prefix. This number will not be used a second time.
705 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
706 static unsigned long id = 0;
707 snprintf(buf, buflen, "%s%lu", prefix, ++id);
713 /*************************************************
716 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
717 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
718 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
719 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
721 *************************************************/
724 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
727 * coding of conditions
729 struct cmp2conditon_t {
735 * positive conditions for signed compares
737 static const struct cmp2conditon_t cmp2condition_s[] = {
738 { NULL, pn_Cmp_False }, /* always false */
739 { "e", pn_Cmp_Eq }, /* == */
740 { "l", pn_Cmp_Lt }, /* < */
741 { "le", pn_Cmp_Le }, /* <= */
742 { "g", pn_Cmp_Gt }, /* > */
743 { "ge", pn_Cmp_Ge }, /* >= */
744 { "ne", pn_Cmp_Lg }, /* != */
745 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
746 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
747 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
748 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
749 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
750 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
751 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
752 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
753 { NULL, pn_Cmp_True }, /* always true */
757 * positive conditions for unsigned compares
759 static const struct cmp2conditon_t cmp2condition_u[] = {
760 { NULL, pn_Cmp_False }, /* always false */
761 { "e", pn_Cmp_Eq }, /* == */
762 { "b", pn_Cmp_Lt }, /* < */
763 { "be", pn_Cmp_Le }, /* <= */
764 { "a", pn_Cmp_Gt }, /* > */
765 { "ae", pn_Cmp_Ge }, /* >= */
766 { "ne", pn_Cmp_Lg }, /* != */
767 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
768 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
769 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
770 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
771 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
772 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
773 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
774 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
775 { NULL, pn_Cmp_True }, /* always true */
779 * returns the condition code
781 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
783 assert(cmp2condition_s[cmp_code].num == cmp_code);
784 assert(cmp2condition_u[cmp_code].num == cmp_code);
786 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
790 * Returns the target block for a control flow node.
792 static ir_node *get_cfop_target_block(const ir_node *irn) {
793 return get_irn_link(irn);
797 * Returns the target label for a control flow node.
799 static char *get_cfop_target(const ir_node *irn, char *buf) {
800 ir_node *bl = get_cfop_target_block(irn);
802 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
806 /** Return the next block in Block schedule */
807 static ir_node *next_blk_sched(const ir_node *block) {
808 return get_irn_link(block);
812 * Returns the Proj with projection number proj and NOT mode_M
814 static ir_node *get_proj(const ir_node *irn, long proj) {
815 const ir_edge_t *edge;
818 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
820 foreach_out_edge(irn, edge) {
821 src = get_edge_src_irn(edge);
823 assert(is_Proj(src) && "Proj expected");
824 if (get_irn_mode(src) == mode_M)
827 if (get_Proj_proj(src) == proj)
834 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
836 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
837 const ir_node *proj_true;
838 const ir_node *proj_false;
839 const ir_node *block;
840 const ir_node *next_block;
841 char buf[SNPRINTF_BUF_LEN];
842 char cmd_buf[SNPRINTF_BUF_LEN];
843 char cmnt_buf[SNPRINTF_BUF_LEN];
848 /* get both Proj's */
849 proj_true = get_proj(irn, pn_Cond_true);
850 assert(proj_true && "CondJmp without true Proj");
852 proj_false = get_proj(irn, pn_Cond_false);
853 assert(proj_false && "CondJmp without false Proj");
855 pnc = get_ia32_pncode(irn);
857 /* for now, the code works for scheduled and non-schedules blocks */
858 block = get_nodes_block(irn);
860 /* we have a block schedule */
861 next_block = next_blk_sched(block);
863 if (get_cfop_target_block(proj_true) == next_block) {
864 /* exchange both proj's so the second one can be omitted */
865 const ir_node *t = proj_true;
866 proj_true = proj_false;
870 pnc = get_negated_pnc(pnc, mode);
873 /* the first Proj must always be created */
874 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
875 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
876 get_cmp_suffix(pnc, is_unsigned),
877 get_cfop_target(proj_true, buf));
878 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* %s(a, b) %s*/",
879 get_pnc_string(pnc), flipped ? "(was flipped)" : "");
882 /* the second Proj might be a fallthrough */
883 if (get_cfop_target_block(proj_false) != next_block) {
884 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj_false, buf));
885 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
889 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj_false, buf));
895 * Emits code for conditional jump.
897 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
899 char cmd_buf[SNPRINTF_BUF_LEN];
900 char cmnt_buf[SNPRINTF_BUF_LEN];
902 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
903 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
905 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
909 * Emits code for conditional jump with two variables.
911 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
912 CondJmp_emitter(irn, env);
916 * Emits code for conditional test and jump.
918 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
920 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
923 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
924 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
925 char cmd_buf[SNPRINTF_BUF_LEN];
926 char cmnt_buf[SNPRINTF_BUF_LEN];
929 op2 = arch_register_get_name(get_in_reg(irn, 1));
931 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
932 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
935 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
941 * Emits code for conditional test and jump with two variables.
943 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
944 TestJmp_emitter(irn, env);
947 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
949 char cmd_buf[SNPRINTF_BUF_LEN];
950 char cmnt_buf[SNPRINTF_BUF_LEN];
952 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
953 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
955 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
958 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
960 char cmd_buf[SNPRINTF_BUF_LEN];
961 char cmnt_buf[SNPRINTF_BUF_LEN];
963 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
964 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
966 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
970 * Emits code for conditional SSE floating point jump with two variables.
972 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
974 char cmd_buf[SNPRINTF_BUF_LEN];
975 char cmnt_buf[SNPRINTF_BUF_LEN];
977 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
978 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
980 finish_CondJmp(F, irn, mode_F);
985 * Emits code for conditional x87 floating point jump with two variables.
987 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
989 char cmd_buf[SNPRINTF_BUF_LEN];
990 char cmnt_buf[SNPRINTF_BUF_LEN];
991 ia32_attr_t *attr = get_ia32_attr(irn);
992 const char *reg = attr->x87[1]->name;
993 const char *instr = "fcom";
996 switch (get_ia32_irn_opcode(irn)) {
997 case iro_ia32_fcomrJmp:
999 case iro_ia32_fcomJmp:
1003 case iro_ia32_fcomrpJmp:
1005 case iro_ia32_fcompJmp:
1008 case iro_ia32_fcomrppJmp:
1010 case iro_ia32_fcomppJmp:
1017 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1019 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %s%s", instr, reg[0] == '\0' ? "" : "%", reg);
1020 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1022 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1023 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1025 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1026 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1029 /* the compare flags must be evaluated using carry , ie unsigned */
1030 finish_CondJmp(F, irn, mode_Iu);
1033 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1035 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1036 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1037 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1038 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1039 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1040 int idx_left = 2 - is_PsiCondCMov;
1041 int idx_right = 3 - is_PsiCondCMov;
1043 char cmd_buf[SNPRINTF_BUF_LEN];
1044 char cmnt_buf[SNPRINTF_BUF_LEN];
1045 const arch_register_t *in1, *in2, *out;
1047 out = arch_get_irn_register(env->arch_env, irn);
1048 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_left));
1049 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, idx_right));
1051 /* we have to emit the cmp first, because the destination register */
1052 /* could be one of the compare registers */
1053 if (is_ia32_CmpCMov(irn)) {
1054 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1056 else if (is_ia32_xCmpCMov(irn)) {
1057 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1059 else if (is_PsiCondCMov) {
1060 /* omit compare because flags are already set by And/Or */
1061 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "test %1S, %1S", irn, irn);
1064 assert(0 && "unsupported CMov");
1066 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1069 if (REGS_ARE_EQUAL(out, in2)) {
1070 /* best case: default in == out -> do nothing */
1072 else if (REGS_ARE_EQUAL(out, in1)) {
1073 /* true in == out -> need complement compare and exchange true and default in */
1074 ir_node *t = get_irn_n(irn, idx_left);
1075 set_irn_n(irn, idx_left, get_irn_n(irn, idx_right));
1076 set_irn_n(irn, idx_right, t);
1078 cmp_suffix = get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), get_irn_mode(irn)), is_unsigned);
1082 /* out is different from in: need copy default -> out */
1084 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1086 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1088 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1093 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %2S", cmp_suffix, irn, irn);
1095 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1097 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1101 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1102 CMov_emitter(irn, env);
1105 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1106 CMov_emitter(irn, env);
1109 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1110 CMov_emitter(irn, env);
1113 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1115 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1116 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1117 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1118 const char *reg8bit;
1120 char cmd_buf[SNPRINTF_BUF_LEN];
1121 char cmnt_buf[SNPRINTF_BUF_LEN];
1122 const arch_register_t *out;
1124 out = arch_get_irn_register(env->arch_env, irn);
1125 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1127 if (is_ia32_CmpSet(irn)) {
1128 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1130 else if (is_ia32_xCmpSet(irn)) {
1131 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1133 else if (is_ia32_PsiCondSet(irn)) {
1134 /* omit compare because flags are already set by And/Or */
1135 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1138 assert(0 && "unsupported Set");
1140 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1143 /* use mov to clear target because it doesn't affect the eflags */
1144 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1145 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1148 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1149 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1153 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1154 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1157 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1158 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1161 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1162 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1165 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1167 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1169 long pnc = get_ia32_pncode(irn);
1170 long unord = pnc & pn_Cmp_Uo;
1171 char cmd_buf[SNPRINTF_BUF_LEN];
1172 char cmnt_buf[SNPRINTF_BUF_LEN];
1175 case pn_Cmp_Leg: /* odered */
1178 case pn_Cmp_Uo: /* unordered */
1182 case pn_Cmp_Eq: /* == */
1186 case pn_Cmp_Lt: /* < */
1190 case pn_Cmp_Le: /* <= */
1194 case pn_Cmp_Gt: /* > */
1198 case pn_Cmp_Ge: /* >= */
1202 case pn_Cmp_Lg: /* != */
1207 assert(sse_pnc >= 0 && "unsupported compare");
1209 if (unord && sse_pnc != 3) {
1211 We need a separate compare against unordered.
1212 Quick and Dirty solution:
1213 - get some memory on stack
1217 - and result and stored result
1220 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1221 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1223 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1224 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1226 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1227 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1231 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1232 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1235 if (unord && sse_pnc != 3) {
1236 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1237 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1239 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1240 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1245 /*********************************************************
1248 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1249 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1250 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1251 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1254 *********************************************************/
1256 /* jump table entry (target and corresponding number) */
1257 typedef struct _branch_t {
1262 /* jump table for switch generation */
1263 typedef struct _jmp_tbl_t {
1264 ir_node *defProj; /**< default target */
1265 int min_value; /**< smallest switch case */
1266 int max_value; /**< largest switch case */
1267 int num_branches; /**< number of jumps */
1268 char *label; /**< label of the jump table */
1269 branch_t *branches; /**< jump array */
1273 * Compare two variables of type branch_t. Used to sort all switch cases
1275 static int ia32_cmp_branch_t(const void *a, const void *b) {
1276 branch_t *b1 = (branch_t *)a;
1277 branch_t *b2 = (branch_t *)b;
1279 if (b1->value <= b2->value)
1286 * Emits code for a SwitchJmp (creates a jump table if
1287 * possible otherwise a cmp-jmp cascade). Port from
1290 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1291 unsigned long interval;
1292 char buf[SNPRINTF_BUF_LEN];
1293 int last_value, i, pn;
1296 const ir_edge_t *edge;
1297 const lc_arg_env_t *env = ia32_get_arg_env();
1298 FILE *F = emit_env->out;
1299 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1301 /* fill the table structure */
1302 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1303 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1305 tbl.num_branches = get_irn_n_edges(irn);
1306 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1307 tbl.min_value = INT_MAX;
1308 tbl.max_value = INT_MIN;
1311 /* go over all proj's and collect them */
1312 foreach_out_edge(irn, edge) {
1313 proj = get_edge_src_irn(edge);
1314 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1316 pn = get_Proj_proj(proj);
1318 /* create branch entry */
1319 tbl.branches[i].target = proj;
1320 tbl.branches[i].value = pn;
1322 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1323 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1325 /* check for default proj */
1326 if (pn == get_ia32_pncode(irn)) {
1327 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1334 /* sort the branches by their number */
1335 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1337 /* two-complement's magic make this work without overflow */
1338 interval = tbl.max_value - tbl.min_value;
1340 /* emit the table */
1341 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1342 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1345 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1346 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1349 if (tbl.num_branches > 1) {
1352 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1353 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1356 ia32_switch_section(F, SECTION_RODATA);
1357 fprintf(F, "\t.align 4\n");
1359 fprintf(F, "%s:\n", tbl.label);
1361 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1362 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1365 last_value = tbl.branches[0].value;
1366 for (i = 1; i < tbl.num_branches; ++i) {
1367 while (++last_value < tbl.branches[i].value) {
1368 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1369 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1372 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1373 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1376 ia32_switch_section(F, SECTION_TEXT);
1379 /* one jump is enough */
1380 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1381 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1392 * Emits code for a unconditional jump.
1394 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1395 ir_node *block, *next_bl;
1397 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1399 /* for now, the code works for scheduled and non-schedules blocks */
1400 block = get_nodes_block(irn);
1402 /* we have a block schedule */
1403 next_bl = next_blk_sched(block);
1404 if (get_cfop_target_block(irn) != next_bl) {
1405 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1406 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1410 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1415 /****************************
1418 * _ __ _ __ ___ _ ___
1419 * | '_ \| '__/ _ \| |/ __|
1420 * | |_) | | | (_) | |\__ \
1421 * | .__/|_| \___/| ||___/
1424 ****************************/
1427 * Emits code for a proj -> node
1429 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1430 ir_node *pred = get_Proj_pred(irn);
1432 if (get_irn_op(pred) == op_Start) {
1433 switch(get_Proj_proj(irn)) {
1434 case pn_Start_X_initial_exec:
1443 /**********************************
1446 * | | ___ _ __ _ _| |_) |
1447 * | | / _ \| '_ \| | | | _ <
1448 * | |___| (_) | |_) | |_| | |_) |
1449 * \_____\___/| .__/ \__, |____/
1452 **********************************/
1455 * Emit movsb/w instructions to make mov count divideable by 4
1457 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1458 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1460 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1462 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1463 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1468 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1469 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1473 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1474 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1478 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1479 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1481 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1482 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1490 * Emit rep movsd instruction for memcopy.
1492 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1493 FILE *F = emit_env->out;
1494 tarval *tv = get_ia32_Immop_tarval(irn);
1495 int rem = get_tarval_long(tv);
1496 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1498 emit_CopyB_prolog(F, irn, rem);
1500 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1501 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1506 * Emits unrolled memcopy.
1508 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1509 tarval *tv = get_ia32_Immop_tarval(irn);
1510 int size = get_tarval_long(tv);
1511 FILE *F = emit_env->out;
1512 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1514 emit_CopyB_prolog(F, irn, size & 0x3);
1518 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1519 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1526 /***************************
1530 * | | / _ \| '_ \ \ / /
1531 * | |___| (_) | | | \ V /
1532 * \_____\___/|_| |_|\_/
1534 ***************************/
1537 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1539 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1540 FILE *F = emit_env->out;
1541 const lc_arg_env_t *env = ia32_get_arg_env();
1542 ir_mode *src_mode = get_ia32_src_mode(irn);
1543 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1544 char *from, *to, buf[64];
1545 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1547 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1548 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1550 switch(get_ia32_op_type(irn)) {
1552 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1554 case ia32_AddrModeS:
1555 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1558 assert(0 && "unsupported op type for Conv");
1561 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1562 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1566 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1567 emit_ia32_Conv_with_FP(irn, emit_env);
1570 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1571 emit_ia32_Conv_with_FP(irn, emit_env);
1574 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1575 emit_ia32_Conv_with_FP(irn, emit_env);
1579 * Emits code for an Int conversion.
1581 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1582 FILE *F = emit_env->out;
1583 const lc_arg_env_t *env = ia32_get_arg_env();
1584 char *move_cmd = "movzx";
1585 char *conv_cmd = NULL;
1586 ir_mode *src_mode = get_ia32_src_mode(irn);
1587 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1589 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1590 const arch_register_t *in_reg, *out_reg;
1592 n = get_mode_size_bits(src_mode);
1593 m = get_mode_size_bits(tgt_mode);
1595 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1597 if (n == 8 || m == 8)
1599 else if (n == 16 || m == 16)
1602 printf("%d -> %d unsupported\n", n, m);
1603 assert(0 && "unsupported Conv_I2I");
1607 switch(get_ia32_op_type(irn)) {
1609 in_reg = get_in_reg(irn, 2);
1610 out_reg = get_out_reg(irn, 0);
1612 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1613 REGS_ARE_EQUAL(out_reg, in_reg) &&
1614 mode_is_signed(n < m ? src_mode : tgt_mode))
1616 /* argument and result are both in EAX and */
1617 /* signedness is ok: -> use converts */
1618 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1620 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1621 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1623 /* argument and result are in the same register */
1624 /* and signedness is ok: -> use and with mask */
1625 int mask = (1 << (n < m ? n : m)) - 1;
1626 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1629 /* use move w/o sign extension */
1630 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1631 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1635 case ia32_AddrModeS:
1636 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1637 move_cmd, irn, ia32_emit_am(irn, emit_env));
1640 assert(0 && "unsupported op type for Conv");
1643 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1644 irn, n, src_mode, m, tgt_mode);
1650 * Emits code for an 8Bit Int conversion.
1652 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1653 emit_ia32_Conv_I2I(irn, emit_env);
1657 /*******************************************
1660 * | |__ ___ _ __ ___ __| | ___ ___
1661 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1662 * | |_) | __/ | | | (_) | (_| | __/\__ \
1663 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1665 *******************************************/
1668 * Emits a backend call
1670 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1671 FILE *F = emit_env->out;
1672 entity *ent = be_Call_get_entity(irn);
1673 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1676 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1679 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1682 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1688 * Emits code to increase stack pointer.
1690 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1691 FILE *F = emit_env->out;
1692 int offs = be_get_IncSP_offset(irn);
1693 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1697 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1699 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1700 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1703 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1704 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1711 * Emits code to set stack pointer.
1713 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1714 FILE *F = emit_env->out;
1715 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1717 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1718 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1723 * Emits code for Copy/CopyKeep.
1725 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1726 FILE *F = emit_env->out;
1727 const arch_env_t *aenv = emit_env->arch_env;
1728 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1730 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1731 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1734 if (mode_is_float(get_irn_mode(irn)))
1735 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1737 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1738 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1742 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1743 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1746 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1747 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1751 * Emits code for exchange.
1753 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1754 FILE *F = emit_env->out;
1755 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1756 const arch_register_t *in1, *in2;
1757 const arch_register_class_t *cls1, *cls2;
1759 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1760 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1762 cls1 = arch_register_get_class(in1);
1763 cls2 = arch_register_get_class(in2);
1765 assert(cls1 == cls2 && "Register class mismatch at Perm");
1767 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1768 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1770 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1771 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1772 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1774 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1778 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1783 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1788 * Emits code for Constant loading.
1790 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1792 char cmd_buf[256], cmnt_buf[256];
1793 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1794 ir_mode *mode = get_irn_mode(n);
1795 tarval *tv = get_ia32_Immop_tarval(n);
1797 if (get_ia32_op_type(n) == ia32_SymConst) {
1798 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1799 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1801 assert(mode == get_tarval_mode(tv));
1802 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1803 if (tv == get_tarval_b_false() || tv == get_tarval_null(mode)) {
1804 const char *instr = "xor";
1805 if (env->isa->opt_arch == arch_pentium_4) {
1806 /* P4 prefers sub r, r, others xor r, r */
1809 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1810 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1812 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1813 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1816 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1820 * Emits code to increase stack pointer.
1822 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1823 FILE *F = emit_env->out;
1824 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1826 if (is_ia32_ImmConst(irn)) {
1827 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1829 else if (is_ia32_ImmSymConst(irn)) {
1830 if (get_ia32_op_type(irn) == ia32_Normal)
1831 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1832 else /* source address mode */
1833 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1836 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1838 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1844 * Emits code to increase stack pointer.
1846 static void emit_ia32_SubSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1847 FILE *F = emit_env->out;
1848 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1850 if (is_ia32_ImmConst(irn)) {
1851 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %C", irn, irn);
1853 else if (is_ia32_ImmSymConst(irn)) {
1854 if (get_ia32_op_type(irn) == ia32_Normal)
1855 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, OFFSET_FLAT:%C", irn, irn);
1856 else /* source address mode */
1857 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1860 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1D, %2S", irn, irn);
1862 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free space on stack */");
1868 * Emits code to load the TLS base
1870 static void emit_ia32_LdTls(const ir_node *irn, ia32_emit_env_t *emit_env) {
1871 FILE *F = emit_env->out;
1872 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1874 switch (asm_flavour) {
1876 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1879 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, DWORD PTR %%gs:0", irn);
1882 assert(0 && "unsupported TLS");
1885 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get thread local storage base */");
1890 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1892 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1894 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1897 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1900 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1904 /***********************************************************************************
1907 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1908 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1909 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1910 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1912 ***********************************************************************************/
1915 * Enters the emitter functions for handled nodes into the generic
1916 * pointer of an opcode.
1918 static void ia32_register_emitters(void) {
1920 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1921 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1922 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1923 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1924 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1925 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1927 /* first clear the generic function pointer for all ops */
1928 clear_irp_opcodes_generic_func();
1930 /* register all emitter functions defined in spec */
1931 ia32_register_spec_emitters();
1933 /* other ia32 emitter functions */
1939 IA32_EMIT(PsiCondCMov);
1941 IA32_EMIT(PsiCondSet);
1942 IA32_EMIT(SwitchJmp);
1945 IA32_EMIT(Conv_I2FP);
1946 IA32_EMIT(Conv_FP2I);
1947 IA32_EMIT(Conv_FP2FP);
1948 IA32_EMIT(Conv_I2I);
1949 IA32_EMIT(Conv_I2I8Bit);
1956 IA32_EMIT(xCmpCMov);
1957 IA32_EMIT(xCondJmp);
1958 IA32_EMIT2(fcomJmp, x87CondJmp);
1959 IA32_EMIT2(fcompJmp, x87CondJmp);
1960 IA32_EMIT2(fcomppJmp, x87CondJmp);
1961 IA32_EMIT2(fcomrJmp, x87CondJmp);
1962 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1963 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1965 /* benode emitter */
1991 static unsigned last_line = -1;
1992 static unsigned num = -1;
1995 * Emit the debug support for node irn.
1997 static void ia32_emit_dbg(const ir_node *irn, ia32_emit_env_t *env) {
1998 dbg_info *db = get_irn_dbg_info(irn);
2000 const char *fname = be_retrieve_dbg_info(db, &lineno);
2002 if (fname && last_line != lineno) {
2006 snprintf(name, sizeof(name), ".LM%u", ++num);
2008 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2009 fprintf(F, "%s:\n", name);
2014 * Emits code for a node.
2016 static void ia32_emit_node(const ir_node *irn, void *env) {
2017 ia32_emit_env_t *emit_env = env;
2018 ir_op *op = get_irn_op(irn);
2019 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
2021 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
2023 if (op->ops.generic) {
2024 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
2025 ia32_emit_dbg(irn, emit_env);
2029 emit_Nothing(irn, env);
2030 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
2035 * Emits gas alignment directives
2037 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
2038 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
2042 * Emits gas alignment directives for Functions depended on cpu architecture.
2044 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
2045 unsigned align; unsigned maximum_skip;
2060 maximum_skip = (1 << align) - 1;
2061 ia32_emit_alignment(F, align, maximum_skip);
2065 * Emits gas alignment directives for Labels depended on cpu architecture.
2067 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
2068 unsigned align; unsigned maximum_skip;
2083 maximum_skip = (1 << align) - 1;
2084 ia32_emit_alignment(F, align, maximum_skip);
2088 * Walks over the nodes in a block connected by scheduling edges
2089 * and emits code for each node.
2091 static void ia32_gen_block(ir_node *block, void *env) {
2092 ia32_emit_env_t *emit_env = env;
2094 int need_label = block != get_irg_start_block(get_irn_irg(block));
2095 FILE *F = emit_env->out;
2097 if (! is_Block(block))
2100 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2101 /* if the extended block scheduler is used, only leader blocks need
2103 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2107 char cmd_buf[SNPRINTF_BUF_LEN];
2110 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2112 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2113 get_irn_node_nr(block));
2114 fprintf(F, "%-43s ", cmd_buf);
2116 /* emit list of pred blocks in comment */
2117 fprintf(F, "/* preds:");
2119 arity = get_irn_arity(block);
2120 for(i = 0; i < arity; ++i) {
2121 ir_node *predblock = get_Block_cfgpred_block(block, i);
2122 fprintf(F, " %ld", get_irn_node_nr(predblock));
2124 fprintf(F, " */\n");
2127 /* emit the contents of the block */
2128 ia32_emit_dbg(block, env);
2129 sched_foreach(block, irn) {
2130 ia32_emit_node(irn, env);
2135 * Emits code for function start.
2137 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2138 entity *irg_ent = get_irg_entity(irg);
2139 const char *irg_name = get_entity_ld_name(irg_ent);
2140 cpu_support cpu = emit_env->isa->opt_arch;
2141 const be_irg_t *birg = emit_env->cg->birg;
2144 ia32_switch_section(F, SECTION_TEXT);
2145 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2146 ia32_emit_align_func(F, cpu);
2147 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2148 fprintf(F, ".globl %s\n", irg_name);
2150 ia32_dump_function_object(F, irg_name);
2151 fprintf(F, "%s:\n", irg_name);
2155 * Emits code for function end
2157 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg, ia32_emit_env_t *emit_env) {
2158 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2159 const be_irg_t *birg = emit_env->cg->birg;
2161 ia32_dump_function_size(F, irg_name);
2162 be_dbg_method_end(birg->main_env->db_handle);
2168 * Sets labels for control flow nodes (jump target)
2169 * TODO: Jump optimization
2171 static void ia32_gen_labels(ir_node *block, void *env) {
2173 int n = get_Block_n_cfgpreds(block);
2175 for (n--; n >= 0; n--) {
2176 pred = get_Block_cfgpred(block, n);
2177 set_irn_link(pred, block);
2182 * Main driver. Emits the code for one routine.
2184 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2185 ia32_emit_env_t emit_env;
2189 emit_env.arch_env = cg->arch_env;
2191 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2192 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2194 /* set the global arch_env (needed by print hooks) */
2195 arch_env = cg->arch_env;
2197 ia32_register_emitters();
2199 ia32_emit_func_prolog(F, irg, &emit_env);
2200 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2202 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2203 int i, n = ARR_LEN(cg->blk_sched);
2205 for (i = 0; i < n;) {
2208 block = cg->blk_sched[i];
2210 next_bl = i < n ? cg->blk_sched[i] : NULL;
2212 /* set here the link. the emitter expects to find the next block here */
2213 set_irn_link(block, next_bl);
2214 ia32_gen_block(block, &emit_env);
2218 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2219 in the block schedule. As this number should NEVER be equal the next block,
2220 we does not need a clear block link here. */
2221 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2224 ia32_emit_func_epilog(F, irg, &emit_env);