2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
42 #include "raw_bitset.h"
45 #include "../besched_t.h"
46 #include "../benode_t.h"
48 #include "../be_dbgout.h"
49 #include "../beemitter.h"
50 #include "../begnuas.h"
51 #include "../beirg_t.h"
52 #include "../be_dbgout.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
72 static char pic_base_label[128];
73 static ir_label_t exc_label_id;
74 static int mark_spill_reload = 0;
76 /** Return the next block in Block schedule */
77 static ir_node *get_prev_block_sched(const ir_node *block)
79 return get_irn_link(block);
82 static int is_fallthrough(const ir_node *cfgpred)
86 if (!is_Proj(cfgpred))
88 pred = get_Proj_pred(cfgpred);
89 if (is_ia32_SwitchJmp(pred))
95 static int block_needs_label(const ir_node *block)
98 int n_cfgpreds = get_Block_n_cfgpreds(block);
100 if (n_cfgpreds == 0) {
102 } else if (n_cfgpreds == 1) {
103 ir_node *cfgpred = get_Block_cfgpred(block, 0);
104 ir_node *cfgpred_block = get_nodes_block(cfgpred);
106 if (get_prev_block_sched(block) == cfgpred_block
107 && is_fallthrough(cfgpred)) {
116 * Returns the register at in position pos.
118 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
121 const arch_register_t *reg = NULL;
123 assert(get_irn_arity(irn) > pos && "Invalid IN position");
125 /* The out register of the operator at position pos is the
126 in register we need. */
127 op = get_irn_n(irn, pos);
129 reg = arch_get_irn_register(op);
131 assert(reg && "no in register found");
133 if (reg == &ia32_gp_regs[REG_GP_NOREG])
134 panic("trying to emit noreg for %+F input %d", irn, pos);
136 /* in case of unknown register: just return a valid register */
137 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
138 const arch_register_req_t *req = arch_get_register_req(irn, pos);
140 if (arch_register_req_is(req, limited)) {
141 /* in case of limited requirements: get the first allowed register */
142 unsigned idx = rbitset_next(req->limited, 0, 1);
143 reg = arch_register_for_index(req->cls, idx);
145 /* otherwise get first register in class */
146 reg = arch_register_for_index(req->cls, 0);
154 * Returns the register at out position pos.
156 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
159 const arch_register_t *reg = NULL;
161 /* 1st case: irn is not of mode_T, so it has only */
162 /* one OUT register -> good */
163 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
164 /* Proj with the corresponding projnum for the register */
166 if (get_irn_mode(irn) != mode_T) {
168 reg = arch_get_irn_register(irn);
169 } else if (is_ia32_irn(irn)) {
170 reg = get_ia32_out_reg(irn, pos);
172 const ir_edge_t *edge;
174 foreach_out_edge(irn, edge) {
175 proj = get_edge_src_irn(edge);
176 assert(is_Proj(proj) && "non-Proj from mode_T node");
177 if (get_Proj_proj(proj) == pos) {
178 reg = arch_get_irn_register(proj);
184 assert(reg && "no out register found");
189 * Add a number to a prefix. This number will not be used a second time.
191 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
193 static unsigned long id = 0;
194 snprintf(buf, buflen, "%s%lu", prefix, ++id);
198 /*************************************************************
200 * (_) | | / _| | | | |
201 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
202 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
203 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
204 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
207 *************************************************************/
209 static void emit_8bit_register(const arch_register_t *reg)
211 const char *reg_name = arch_register_get_name(reg);
214 be_emit_char(reg_name[1]);
218 static void emit_16bit_register(const arch_register_t *reg)
220 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
223 be_emit_string(reg_name);
226 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
228 const char *reg_name;
231 int size = get_mode_size_bits(mode);
233 case 8: emit_8bit_register(reg); return;
234 case 16: emit_16bit_register(reg); return;
236 assert(mode_is_float(mode) || size == 32);
239 reg_name = arch_register_get_name(reg);
242 be_emit_string(reg_name);
245 void ia32_emit_source_register(const ir_node *node, int pos)
247 const arch_register_t *reg = get_in_reg(node, pos);
249 emit_register(reg, NULL);
252 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
256 set_entity_backend_marked(entity, 1);
257 id = get_entity_ld_ident(entity);
260 if (get_entity_owner(entity) == get_tls_type()) {
261 if (get_entity_visibility(entity) == visibility_external_allocated) {
262 be_emit_cstring("@INDNTPOFF");
264 be_emit_cstring("@NTPOFF");
268 if (!no_pic_adjust && do_pic) {
269 /* TODO: only do this when necessary */
271 be_emit_string(pic_base_label);
275 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
277 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
279 if (attr->symconst != NULL) {
282 ia32_emit_entity(attr->symconst, 0);
284 if (attr->symconst == NULL || attr->offset != 0) {
285 if (attr->symconst != NULL) {
286 be_emit_irprintf("%+d", attr->offset);
288 be_emit_irprintf("0x%X", attr->offset);
293 static void emit_ia32_Immediate(const ir_node *node)
296 emit_ia32_Immediate_no_prefix(node);
299 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
301 const arch_register_t *reg;
302 ir_node *in = get_irn_n(node, pos);
303 if (is_ia32_Immediate(in)) {
304 emit_ia32_Immediate(in);
308 reg = get_in_reg(node, pos);
309 emit_8bit_register(reg);
312 void ia32_emit_dest_register(const ir_node *node, int pos)
314 const arch_register_t *reg = get_out_reg(node, pos);
316 emit_register(reg, NULL);
319 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
321 const arch_register_t *reg = get_out_reg(node, pos);
323 emit_register(reg, mode_Bu);
326 void ia32_emit_x87_register(const ir_node *node, int pos)
328 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
332 be_emit_string(attr->x87[pos]->name);
335 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
337 assert(mode_is_int(mode) || mode_is_reference(mode));
338 switch (get_mode_size_bits(mode)) {
339 case 8: be_emit_char('b'); return;
340 case 16: be_emit_char('w'); return;
341 case 32: be_emit_char('l'); return;
342 /* gas docu says q is the suffix but gcc, objdump and icc use ll
344 case 64: be_emit_cstring("ll"); return;
346 panic("Can't output mode_suffix for %+F", mode);
349 void ia32_emit_mode_suffix(const ir_node *node)
351 ir_mode *mode = get_ia32_ls_mode(node);
355 ia32_emit_mode_suffix_mode(mode);
358 void ia32_emit_x87_mode_suffix(const ir_node *node)
362 /* we only need to emit the mode on address mode */
363 if (get_ia32_op_type(node) == ia32_Normal)
366 mode = get_ia32_ls_mode(node);
367 assert(mode != NULL);
369 if (mode_is_float(mode)) {
370 switch (get_mode_size_bits(mode)) {
371 case 32: be_emit_char('s'); return;
372 case 64: be_emit_char('l'); return;
374 case 96: be_emit_char('t'); return;
377 assert(mode_is_int(mode));
378 switch (get_mode_size_bits(mode)) {
379 case 16: be_emit_char('s'); return;
380 case 32: be_emit_char('l'); return;
381 /* gas docu says q is the suffix but gcc, objdump and icc use ll
383 case 64: be_emit_cstring("ll"); return;
386 panic("Can't output mode_suffix for %+F", mode);
389 static char get_xmm_mode_suffix(ir_mode *mode)
391 assert(mode_is_float(mode));
392 switch(get_mode_size_bits(mode)) {
395 default: panic("Invalid XMM mode");
399 void ia32_emit_xmm_mode_suffix(const ir_node *node)
401 ir_mode *mode = get_ia32_ls_mode(node);
402 assert(mode != NULL);
404 be_emit_char(get_xmm_mode_suffix(mode));
407 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
409 ir_mode *mode = get_ia32_ls_mode(node);
410 assert(mode != NULL);
411 be_emit_char(get_xmm_mode_suffix(mode));
414 void ia32_emit_extend_suffix(const ir_mode *mode)
416 if (get_mode_size_bits(mode) == 32)
418 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
421 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
423 ir_node *in = get_irn_n(node, pos);
424 if (is_ia32_Immediate(in)) {
425 emit_ia32_Immediate(in);
427 const ir_mode *mode = get_ia32_ls_mode(node);
428 const arch_register_t *reg = get_in_reg(node, pos);
429 emit_register(reg, mode);
434 * Returns the target block for a control flow node.
436 static ir_node *get_cfop_target_block(const ir_node *irn)
438 assert(get_irn_mode(irn) == mode_X);
439 return get_irn_link(irn);
443 * Emits a block label for the given block.
445 static void ia32_emit_block_name(const ir_node *block)
447 if (has_Block_label(block)) {
448 be_emit_string(be_gas_block_label_prefix());
449 be_emit_irprintf("%lu", get_Block_label(block));
451 be_emit_cstring(BLOCK_PREFIX);
452 be_emit_irprintf("%ld", get_irn_node_nr(block));
457 * Emits the target label for a control flow node.
459 static void ia32_emit_cfop_target(const ir_node *node)
461 ir_node *block = get_cfop_target_block(node);
462 ia32_emit_block_name(block);
466 * coding of conditions
468 struct cmp2conditon_t {
474 * positive conditions for signed compares
476 static const struct cmp2conditon_t cmp2condition_s[] = {
477 { NULL, pn_Cmp_False }, /* always false */
478 { "e", pn_Cmp_Eq }, /* == */
479 { "l", pn_Cmp_Lt }, /* < */
480 { "le", pn_Cmp_Le }, /* <= */
481 { "g", pn_Cmp_Gt }, /* > */
482 { "ge", pn_Cmp_Ge }, /* >= */
483 { "ne", pn_Cmp_Lg }, /* != */
484 { NULL, pn_Cmp_Leg}, /* always true */
488 * positive conditions for unsigned compares
490 static const struct cmp2conditon_t cmp2condition_u[] = {
491 { NULL, pn_Cmp_False }, /* always false */
492 { "e", pn_Cmp_Eq }, /* == */
493 { "b", pn_Cmp_Lt }, /* < */
494 { "be", pn_Cmp_Le }, /* <= */
495 { "a", pn_Cmp_Gt }, /* > */
496 { "ae", pn_Cmp_Ge }, /* >= */
497 { "ne", pn_Cmp_Lg }, /* != */
498 { NULL, pn_Cmp_Leg }, /* always true */
501 static void ia32_emit_cmp_suffix(int pnc)
505 if ((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
507 assert(cmp2condition_u[pnc].num == pnc);
508 str = cmp2condition_u[pnc].name;
511 assert(cmp2condition_s[pnc].num == pnc);
512 str = cmp2condition_s[pnc].name;
518 typedef enum ia32_emit_mod_t {
519 EMIT_RESPECT_LS = 1U << 0,
520 EMIT_ALTERNATE_AM = 1U << 1
524 * fmt parameter output
525 * ---- ---------------------- ---------------------------------------------
527 * %AM <node> address mode of the node
528 * %AR const arch_register_t* address mode of the node or register
529 * %ASx <node> address mode of the node or source register x
530 * %Dx <node> destination register x
531 * %I <node> immediate of the node
532 * %L <node> control flow target of the node
533 * %M <node> mode suffix of the node
534 * %P int condition code
535 * %R const arch_register_t* register
536 * %Sx <node> source register x
537 * %s const char* string
538 * %u unsigned int unsigned int
541 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
542 * * modifier does not prefix immediates with $, but AM with *
544 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
550 const char *start = fmt;
551 ia32_emit_mod_t mod = 0;
553 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
556 be_emit_string_len(start, fmt - start);
560 be_emit_finish_line_gas(node);
572 mod |= EMIT_ALTERNATE_AM;
577 mod |= EMIT_RESPECT_LS;
589 if (mod & EMIT_ALTERNATE_AM)
595 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
596 if (mod & EMIT_ALTERNATE_AM)
598 if (get_ia32_op_type(node) == ia32_AddrModeS) {
601 emit_register(reg, NULL);
607 if (get_ia32_op_type(node) == ia32_AddrModeS) {
608 if (mod & EMIT_ALTERNATE_AM)
613 assert(get_ia32_op_type(node) == ia32_Normal);
618 default: goto unknown;
625 const arch_register_t *reg;
627 if (*fmt < '0' || '9' <= *fmt)
631 reg = get_out_reg(node, pos);
632 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
637 if (!(mod & EMIT_ALTERNATE_AM))
639 emit_ia32_Immediate_no_prefix(node);
643 ia32_emit_cfop_target(node);
647 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
652 int pnc = va_arg(ap, int);
653 ia32_emit_cmp_suffix(pnc);
658 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
659 emit_register(reg, NULL);
668 if (*fmt < '0' || '9' <= *fmt)
672 in = get_irn_n(node, pos);
673 if (is_ia32_Immediate(in)) {
674 if (!(mod & EMIT_ALTERNATE_AM))
676 emit_ia32_Immediate_no_prefix(in);
678 const arch_register_t *reg;
680 if (mod & EMIT_ALTERNATE_AM)
682 reg = get_in_reg(node, pos);
683 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
689 const char *str = va_arg(ap, const char*);
695 unsigned num = va_arg(ap, unsigned);
696 be_emit_irprintf("%u", num);
702 panic("unknown conversion");
710 * Emits registers and/or address mode of a binary operation.
712 void ia32_emit_binop(const ir_node *node)
714 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
715 ia32_emitf(node, "%#S4, %#AS3");
717 ia32_emitf(node, "%#AS4, %#S3");
722 * Emits registers and/or address mode of a binary operation.
724 void ia32_emit_x87_binop(const ir_node *node)
726 switch(get_ia32_op_type(node)) {
729 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
730 const arch_register_t *in1 = x87_attr->x87[0];
731 const arch_register_t *in = x87_attr->x87[1];
732 const arch_register_t *out = x87_attr->x87[2];
736 } else if (out == in) {
741 be_emit_string(arch_register_get_name(in));
742 be_emit_cstring(", %");
743 be_emit_string(arch_register_get_name(out));
751 assert(0 && "unsupported op type");
756 * Emits registers and/or address mode of a unary operation.
758 void ia32_emit_unop(const ir_node *node, int pos)
762 ia32_emitf(node, fmt);
766 * Emits address mode.
768 void ia32_emit_am(const ir_node *node)
770 ir_entity *ent = get_ia32_am_sc(node);
771 int offs = get_ia32_am_offs_int(node);
772 ir_node *base = get_irn_n(node, n_ia32_base);
773 int has_base = !is_ia32_NoReg_GP(base);
774 ir_node *index = get_irn_n(node, n_ia32_index);
775 int has_index = !is_ia32_NoReg_GP(index);
777 /* just to be sure... */
778 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
782 if (is_ia32_am_sc_sign(node))
784 ia32_emit_entity(ent, 0);
787 /* also handle special case if nothing is set */
788 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
790 be_emit_irprintf("%+d", offs);
792 be_emit_irprintf("%d", offs);
796 if (has_base || has_index) {
801 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
802 emit_register(reg, NULL);
805 /* emit index + scale */
807 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
810 emit_register(reg, NULL);
812 scale = get_ia32_am_scale(node);
814 be_emit_irprintf(",%d", 1 << scale);
821 static void emit_ia32_IMul(const ir_node *node)
823 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
824 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
826 /* do we need the 3-address form? */
827 if (is_ia32_NoReg_GP(left) ||
828 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
829 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
831 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
836 * walks up a tree of copies/perms/spills/reloads to find the original value
837 * that is moved around
839 static ir_node *find_original_value(ir_node *node)
841 if (irn_visited(node))
844 mark_irn_visited(node);
845 if (be_is_Copy(node)) {
846 return find_original_value(be_get_Copy_op(node));
847 } else if (be_is_CopyKeep(node)) {
848 return find_original_value(be_get_CopyKeep_op(node));
849 } else if (is_Proj(node)) {
850 ir_node *pred = get_Proj_pred(node);
851 if (be_is_Perm(pred)) {
852 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
853 } else if (be_is_MemPerm(pred)) {
854 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
855 } else if (is_ia32_Load(pred)) {
856 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
860 } else if (is_ia32_Store(node)) {
861 return find_original_value(get_irn_n(node, n_ia32_Store_val));
862 } else if (is_Phi(node)) {
864 arity = get_irn_arity(node);
865 for (i = 0; i < arity; ++i) {
866 ir_node *in = get_irn_n(node, i);
867 ir_node *res = find_original_value(in);
878 static int determine_final_pnc(const ir_node *node, int flags_pos,
881 ir_node *flags = get_irn_n(node, flags_pos);
882 const ia32_attr_t *flags_attr;
883 flags = skip_Proj(flags);
885 if (is_ia32_Sahf(flags)) {
886 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
887 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
888 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
889 inc_irg_visited(current_ir_graph);
890 cmp = find_original_value(cmp);
892 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
893 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
896 flags_attr = get_ia32_attr_const(cmp);
897 if (flags_attr->data.ins_permuted)
898 pnc = get_mirrored_pnc(pnc);
899 pnc |= ia32_pn_Cmp_float;
900 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
901 || is_ia32_Fucompi(flags)) {
902 flags_attr = get_ia32_attr_const(flags);
904 if (flags_attr->data.ins_permuted)
905 pnc = get_mirrored_pnc(pnc);
906 pnc |= ia32_pn_Cmp_float;
908 flags_attr = get_ia32_attr_const(flags);
910 if (flags_attr->data.ins_permuted)
911 pnc = get_mirrored_pnc(pnc);
912 if (flags_attr->data.cmp_unsigned)
913 pnc |= ia32_pn_Cmp_unsigned;
919 void ia32_emit_cmp_suffix_node(const ir_node *node,
922 const ia32_attr_t *attr = get_ia32_attr_const(node);
924 pn_Cmp pnc = get_ia32_condcode(node);
926 pnc = determine_final_pnc(node, flags_pos, pnc);
927 if (attr->data.ins_permuted) {
928 if (pnc & ia32_pn_Cmp_float) {
929 pnc = get_negated_pnc(pnc, mode_F);
931 pnc = get_negated_pnc(pnc, mode_Iu);
935 ia32_emit_cmp_suffix(pnc);
939 * Emits an exception label for a given node.
941 static void ia32_emit_exc_label(const ir_node *node)
943 be_emit_string(be_gas_insn_label_prefix());
944 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
948 * Returns the Proj with projection number proj and NOT mode_M
950 static ir_node *get_proj(const ir_node *node, long proj)
952 const ir_edge_t *edge;
955 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
957 foreach_out_edge(node, edge) {
958 src = get_edge_src_irn(edge);
960 assert(is_Proj(src) && "Proj expected");
961 if (get_irn_mode(src) == mode_M)
964 if (get_Proj_proj(src) == proj)
970 static int can_be_fallthrough(const ir_node *node)
972 ir_node *target_block = get_cfop_target_block(node);
973 ir_node *block = get_nodes_block(node);
974 return get_prev_block_sched(target_block) == block;
978 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
980 static void emit_ia32_Jcc(const ir_node *node)
982 int need_parity_label = 0;
983 const ir_node *proj_true;
984 const ir_node *proj_false;
985 const ir_node *block;
986 pn_Cmp pnc = get_ia32_condcode(node);
988 pnc = determine_final_pnc(node, 0, pnc);
991 proj_true = get_proj(node, pn_ia32_Jcc_true);
992 assert(proj_true && "Jcc without true Proj");
994 proj_false = get_proj(node, pn_ia32_Jcc_false);
995 assert(proj_false && "Jcc without false Proj");
997 block = get_nodes_block(node);
999 if (can_be_fallthrough(proj_true)) {
1000 /* exchange both proj's so the second one can be omitted */
1001 const ir_node *t = proj_true;
1003 proj_true = proj_false;
1005 if (pnc & ia32_pn_Cmp_float) {
1006 pnc = get_negated_pnc(pnc, mode_F);
1008 pnc = get_negated_pnc(pnc, mode_Iu);
1012 if (pnc & ia32_pn_Cmp_float) {
1013 /* Some floating point comparisons require a test of the parity flag,
1014 * which indicates that the result is unordered */
1017 ia32_emitf(proj_true, "\tjp %L\n");
1022 ia32_emitf(proj_true, "\tjnp %L\n");
1028 /* we need a local label if the false proj is a fallthrough
1029 * as the falseblock might have no label emitted then */
1030 if (can_be_fallthrough(proj_false)) {
1031 need_parity_label = 1;
1032 ia32_emitf(proj_false, "\tjp 1f\n");
1034 ia32_emitf(proj_false, "\tjp %L\n");
1041 ia32_emitf(proj_true, "\tjp %L\n");
1049 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1052 if (need_parity_label) {
1053 ia32_emitf(NULL, "1:\n");
1056 /* the second Proj might be a fallthrough */
1057 if (can_be_fallthrough(proj_false)) {
1058 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1060 ia32_emitf(proj_false, "\tjmp %L\n");
1064 static void emit_ia32_CMov(const ir_node *node)
1066 const ia32_attr_t *attr = get_ia32_attr_const(node);
1067 int ins_permuted = attr->data.ins_permuted;
1068 const arch_register_t *out = arch_get_irn_register(node);
1069 pn_Cmp pnc = get_ia32_condcode(node);
1070 const arch_register_t *in_true;
1071 const arch_register_t *in_false;
1073 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1075 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1076 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1078 /* should be same constraint fullfilled? */
1079 if (out == in_false) {
1080 /* yes -> nothing to do */
1081 } else if (out == in_true) {
1082 const arch_register_t *tmp;
1084 assert(get_ia32_op_type(node) == ia32_Normal);
1086 ins_permuted = !ins_permuted;
1093 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1097 if (pnc & ia32_pn_Cmp_float) {
1098 pnc = get_negated_pnc(pnc, mode_F);
1100 pnc = get_negated_pnc(pnc, mode_Iu);
1104 /* TODO: handling of Nans isn't correct yet */
1106 ia32_emitf(node, "\tcmov%P %AR, %#R\n", pnc, in_true, out);
1109 /*********************************************************
1112 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1113 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1114 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1115 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1118 *********************************************************/
1120 /* jump table entry (target and corresponding number) */
1121 typedef struct _branch_t {
1126 /* jump table for switch generation */
1127 typedef struct _jmp_tbl_t {
1128 ir_node *defProj; /**< default target */
1129 long min_value; /**< smallest switch case */
1130 long max_value; /**< largest switch case */
1131 long num_branches; /**< number of jumps */
1132 char *label; /**< label of the jump table */
1133 branch_t *branches; /**< jump array */
1137 * Compare two variables of type branch_t. Used to sort all switch cases
1139 static int ia32_cmp_branch_t(const void *a, const void *b)
1141 branch_t *b1 = (branch_t *)a;
1142 branch_t *b2 = (branch_t *)b;
1144 if (b1->value <= b2->value)
1151 * Emits code for a SwitchJmp (creates a jump table if
1152 * possible otherwise a cmp-jmp cascade). Port from
1155 static void emit_ia32_SwitchJmp(const ir_node *node)
1157 unsigned long interval;
1163 const ir_edge_t *edge;
1165 /* fill the table structure */
1166 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1167 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1169 tbl.num_branches = get_irn_n_edges(node) - 1;
1170 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1171 tbl.min_value = INT_MAX;
1172 tbl.max_value = INT_MIN;
1174 default_pn = get_ia32_condcode(node);
1176 /* go over all proj's and collect them */
1177 foreach_out_edge(node, edge) {
1178 proj = get_edge_src_irn(edge);
1179 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1181 pnc = get_Proj_proj(proj);
1183 /* check for default proj */
1184 if (pnc == default_pn) {
1185 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1188 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1189 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1191 /* create branch entry */
1192 tbl.branches[i].target = proj;
1193 tbl.branches[i].value = pnc;
1198 assert(i == tbl.num_branches);
1200 /* sort the branches by their number */
1201 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1203 /* two-complement's magic make this work without overflow */
1204 interval = tbl.max_value - tbl.min_value;
1206 /* emit the table */
1207 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1208 ia32_emitf(tbl.defProj, "\tja %L\n");
1210 if (tbl.num_branches > 1) {
1212 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1214 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1215 ia32_emitf(NULL, "\t.align 4\n");
1216 ia32_emitf(NULL, "%s:\n", tbl.label);
1218 last_value = tbl.branches[0].value;
1219 for (i = 0; i != tbl.num_branches; ++i) {
1220 while (last_value != tbl.branches[i].value) {
1221 ia32_emitf(tbl.defProj, ".long %L\n");
1224 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1227 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1229 /* one jump is enough */
1230 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1240 * Emits code for a unconditional jump.
1242 static void emit_Jmp(const ir_node *node)
1246 /* for now, the code works for scheduled and non-schedules blocks */
1247 block = get_nodes_block(node);
1249 /* we have a block schedule */
1250 if (can_be_fallthrough(node)) {
1251 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1253 ia32_emitf(node, "\tjmp %L\n");
1258 * Emit an inline assembler operand.
1260 * @param node the ia32_ASM node
1261 * @param s points to the operand (a %c)
1263 * @return pointer to the first char in s NOT in the current operand
1265 static const char* emit_asm_operand(const ir_node *node, const char *s)
1267 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1268 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1270 const arch_register_t *reg;
1271 const ia32_asm_reg_t *asm_regs = attr->register_map;
1272 const ia32_asm_reg_t *asm_reg;
1273 const char *reg_name;
1282 /* parse modifiers */
1285 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1309 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1310 "'%c' for asm op\n", node, c);
1316 sscanf(s, "%d%n", &num, &p);
1318 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1325 if (num < 0 || num >= ARR_LEN(asm_regs)) {
1326 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1327 "input/output (%+F)\n", node);
1330 asm_reg = & asm_regs[num];
1331 assert(asm_reg->valid);
1334 if (asm_reg->use_input == 0) {
1335 reg = get_out_reg(node, asm_reg->inout_pos);
1337 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1339 /* might be an immediate value */
1340 if (is_ia32_Immediate(pred)) {
1341 emit_ia32_Immediate(pred);
1344 reg = get_in_reg(node, asm_reg->inout_pos);
1347 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1348 "(%+F)\n", num, node);
1352 if (asm_reg->memory) {
1357 if (modifier != 0) {
1361 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1364 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1367 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1370 panic("Invalid asm op modifier");
1372 be_emit_string(reg_name);
1374 emit_register(reg, asm_reg->mode);
1377 if (asm_reg->memory) {
1385 * Emits code for an ASM pseudo op.
1387 static void emit_ia32_Asm(const ir_node *node)
1389 const void *gen_attr = get_irn_generic_attr_const(node);
1390 const ia32_asm_attr_t *attr
1391 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1392 ident *asm_text = attr->asm_text;
1393 const char *s = get_id_str(asm_text);
1395 ia32_emitf(node, "#APP\t\n");
1402 s = emit_asm_operand(node, s);
1408 ia32_emitf(NULL, "\n#NO_APP\n");
1411 /**********************************
1414 * | | ___ _ __ _ _| |_) |
1415 * | | / _ \| '_ \| | | | _ <
1416 * | |___| (_) | |_) | |_| | |_) |
1417 * \_____\___/| .__/ \__, |____/
1420 **********************************/
1423 * Emit movsb/w instructions to make mov count divideable by 4
1425 static void emit_CopyB_prolog(unsigned size)
1428 ia32_emitf(NULL, "\tmovsb\n");
1430 ia32_emitf(NULL, "\tmovsw\n");
1434 * Emit rep movsd instruction for memcopy.
1436 static void emit_ia32_CopyB(const ir_node *node)
1438 unsigned size = get_ia32_copyb_size(node);
1440 emit_CopyB_prolog(size);
1441 ia32_emitf(node, "\trep movsd\n");
1445 * Emits unrolled memcopy.
1447 static void emit_ia32_CopyB_i(const ir_node *node)
1449 unsigned size = get_ia32_copyb_size(node);
1451 emit_CopyB_prolog(size);
1455 ia32_emitf(NULL, "\tmovsd\n");
1461 /***************************
1465 * | | / _ \| '_ \ \ / /
1466 * | |___| (_) | | | \ V /
1467 * \_____\___/|_| |_|\_/
1469 ***************************/
1472 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1474 static void emit_ia32_Conv_with_FP(const ir_node *node)
1476 ir_mode *ls_mode = get_ia32_ls_mode(node);
1477 int ls_bits = get_mode_size_bits(ls_mode);
1480 if (is_ia32_Conv_I2FP(node)) {
1481 if (ls_bits == 32) {
1486 } else if (is_ia32_Conv_FP2I(node)) {
1487 if (ls_bits == 32) {
1493 assert(is_ia32_Conv_FP2FP(node));
1494 if (ls_bits == 32) {
1501 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1504 static void emit_ia32_Conv_I2FP(const ir_node *node)
1506 emit_ia32_Conv_with_FP(node);
1509 static void emit_ia32_Conv_FP2I(const ir_node *node)
1511 emit_ia32_Conv_with_FP(node);
1514 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1516 emit_ia32_Conv_with_FP(node);
1520 * Emits code for an Int conversion.
1522 static void emit_ia32_Conv_I2I(const ir_node *node)
1524 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1525 int smaller_bits = get_mode_size_bits(smaller_mode);
1526 int signed_mode = mode_is_signed(smaller_mode);
1528 assert(!mode_is_float(smaller_mode));
1529 assert(smaller_bits == 8 || smaller_bits == 16);
1532 smaller_bits == 16 &&
1533 &ia32_gp_regs[REG_EAX] == get_out_reg(node, 0) &&
1534 &ia32_gp_regs[REG_EAX] == arch_get_irn_register(get_irn_n(node, n_ia32_unary_op))) {
1535 /* argument and result are both in EAX and signedness is ok: use the
1536 * smaller cwtl opcode */
1537 ia32_emitf(node, "\tcwtl\n");
1539 const char *sign_suffix = signed_mode ? "s" : "z";
1540 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1547 static void emit_ia32_Call(const ir_node *node)
1549 /* Special case: Call must not have its immediates prefixed by $, instead
1550 * address mode is prefixed by *. */
1551 ia32_emitf(node, "\tcall %*AS3\n");
1555 /*******************************************
1558 * | |__ ___ _ __ ___ __| | ___ ___
1559 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1560 * | |_) | __/ | | | (_) | (_| | __/\__ \
1561 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1563 *******************************************/
1566 * Emits code to increase stack pointer.
1568 static void emit_be_IncSP(const ir_node *node)
1570 int offs = be_get_IncSP_offset(node);
1576 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1578 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1583 * Emits code for Copy/CopyKeep.
1585 static void Copy_emitter(const ir_node *node, const ir_node *op)
1587 const arch_register_t *in = arch_get_irn_register(op);
1588 const arch_register_t *out = arch_get_irn_register(node);
1593 if (is_unknown_reg(in))
1595 /* copies of vf nodes aren't real... */
1596 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1599 if (get_irn_mode(node) == mode_E) {
1600 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1602 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1606 static void emit_be_Copy(const ir_node *node)
1608 Copy_emitter(node, be_get_Copy_op(node));
1611 static void emit_be_CopyKeep(const ir_node *node)
1613 Copy_emitter(node, be_get_CopyKeep_op(node));
1617 * Emits code for exchange.
1619 static void emit_be_Perm(const ir_node *node)
1621 const arch_register_t *in0, *in1;
1622 const arch_register_class_t *cls0, *cls1;
1624 in0 = arch_get_irn_register(get_irn_n(node, 0));
1625 in1 = arch_get_irn_register(get_irn_n(node, 1));
1627 cls0 = arch_register_get_class(in0);
1628 cls1 = arch_register_get_class(in1);
1630 assert(cls0 == cls1 && "Register class mismatch at Perm");
1632 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1633 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1634 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1635 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1636 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1637 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1638 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1640 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1643 panic("unexpected register class in be_Perm (%+F)", node);
1648 * Emits code for Constant loading.
1650 static void emit_ia32_Const(const ir_node *node)
1652 ia32_emitf(node, "\tmovl %I, %D0\n");
1656 * Emits code to load the TLS base
1658 static void emit_ia32_LdTls(const ir_node *node)
1660 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1663 /* helper function for emit_ia32_Minus64Bit */
1664 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1666 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1669 /* helper function for emit_ia32_Minus64Bit */
1670 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1672 ia32_emitf(node, "\tnegl %R\n", reg);
1675 /* helper function for emit_ia32_Minus64Bit */
1676 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1678 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1681 /* helper function for emit_ia32_Minus64Bit */
1682 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1684 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1687 /* helper function for emit_ia32_Minus64Bit */
1688 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1690 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1693 /* helper function for emit_ia32_Minus64Bit */
1694 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1696 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1699 static void emit_ia32_Minus64Bit(const ir_node *node)
1701 const arch_register_t *in_lo = get_in_reg(node, 0);
1702 const arch_register_t *in_hi = get_in_reg(node, 1);
1703 const arch_register_t *out_lo = get_out_reg(node, 0);
1704 const arch_register_t *out_hi = get_out_reg(node, 1);
1706 if (out_lo == in_lo) {
1707 if (out_hi != in_hi) {
1708 /* a -> a, b -> d */
1711 /* a -> a, b -> b */
1714 } else if (out_lo == in_hi) {
1715 if (out_hi == in_lo) {
1716 /* a -> b, b -> a */
1717 emit_xchg(node, in_lo, in_hi);
1720 /* a -> b, b -> d */
1721 emit_mov(node, in_hi, out_hi);
1722 emit_mov(node, in_lo, out_lo);
1726 if (out_hi == in_lo) {
1727 /* a -> c, b -> a */
1728 emit_mov(node, in_lo, out_lo);
1730 } else if (out_hi == in_hi) {
1731 /* a -> c, b -> b */
1732 emit_mov(node, in_lo, out_lo);
1735 /* a -> c, b -> d */
1736 emit_mov(node, in_lo, out_lo);
1742 emit_neg( node, out_hi);
1743 emit_neg( node, out_lo);
1744 emit_sbb0(node, out_hi);
1748 emit_zero(node, out_hi);
1749 emit_neg( node, out_lo);
1750 emit_sbb( node, in_hi, out_hi);
1753 static void emit_ia32_GetEIP(const ir_node *node)
1755 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1756 ia32_emitf(NULL, "%s:\n", pic_base_label);
1757 ia32_emitf(node, "\tpopl %D0\n");
1760 static void emit_be_Return(const ir_node *node)
1762 unsigned pop = be_Return_get_pop(node);
1764 if (pop > 0 || be_Return_get_emit_pop(node)) {
1765 ia32_emitf(node, "\tret $%u\n", pop);
1767 ia32_emitf(node, "\tret\n");
1771 static void emit_Nothing(const ir_node *node)
1777 /***********************************************************************************
1780 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1781 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1782 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1783 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1785 ***********************************************************************************/
1788 * Enters the emitter functions for handled nodes into the generic
1789 * pointer of an opcode.
1791 static void ia32_register_emitters(void)
1793 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1794 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1795 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1796 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1797 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1798 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1800 /* first clear the generic function pointer for all ops */
1801 clear_irp_opcodes_generic_func();
1803 /* register all emitter functions defined in spec */
1804 ia32_register_spec_emitters();
1806 /* other ia32 emitter functions */
1807 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1812 IA32_EMIT(Conv_FP2FP);
1813 IA32_EMIT(Conv_FP2I);
1814 IA32_EMIT(Conv_I2FP);
1815 IA32_EMIT(Conv_I2I);
1822 IA32_EMIT(Minus64Bit);
1823 IA32_EMIT(SwitchJmp);
1825 /* benode emitter */
1848 typedef void (*emit_func_ptr) (const ir_node *);
1851 * Assign and emit an exception label if the current instruction can fail.
1853 static void ia32_assign_exc_label(ir_node *node)
1855 /* assign a new ID to the instruction */
1856 set_ia32_exc_label_id(node, ++exc_label_id);
1858 ia32_emit_exc_label(node);
1860 be_emit_pad_comment();
1861 be_emit_cstring("/* exception to Block ");
1862 ia32_emit_cfop_target(node);
1863 be_emit_cstring(" */\n");
1864 be_emit_write_line();
1868 * Emits code for a node.
1870 static void ia32_emit_node(ir_node *node)
1872 ir_op *op = get_irn_op(node);
1874 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1876 if (is_ia32_irn(node)) {
1877 if (get_ia32_exc_label(node)) {
1878 /* emit the exception label of this instruction */
1879 ia32_assign_exc_label(node);
1881 if (mark_spill_reload) {
1882 if (is_ia32_is_spill(node)) {
1883 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1885 if (is_ia32_is_reload(node)) {
1886 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1888 if (is_ia32_is_remat(node)) {
1889 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1893 if (op->ops.generic) {
1894 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1896 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1901 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1907 * Emits gas alignment directives
1909 static void ia32_emit_alignment(unsigned align, unsigned skip)
1911 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1915 * Emits gas alignment directives for Labels depended on cpu architecture.
1917 static void ia32_emit_align_label(void)
1919 unsigned align = ia32_cg_config.label_alignment;
1920 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1921 ia32_emit_alignment(align, maximum_skip);
1925 * Test whether a block should be aligned.
1926 * For cpus in the P4/Athlon class it is useful to align jump labels to
1927 * 16 bytes. However we should only do that if the alignment nops before the
1928 * label aren't executed more often than we have jumps to the label.
1930 static int should_align_block(const ir_node *block)
1932 static const double DELTA = .0001;
1933 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1934 ir_node *prev = get_prev_block_sched(block);
1936 double prev_freq = 0; /**< execfreq of the fallthrough block */
1937 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1940 if (exec_freq == NULL)
1942 if (ia32_cg_config.label_alignment_factor <= 0)
1945 block_freq = get_block_execfreq(exec_freq, block);
1946 if (block_freq < DELTA)
1949 n_cfgpreds = get_Block_n_cfgpreds(block);
1950 for(i = 0; i < n_cfgpreds; ++i) {
1951 const ir_node *pred = get_Block_cfgpred_block(block, i);
1952 double pred_freq = get_block_execfreq(exec_freq, pred);
1955 prev_freq += pred_freq;
1957 jmp_freq += pred_freq;
1961 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1964 jmp_freq /= prev_freq;
1966 return jmp_freq > ia32_cg_config.label_alignment_factor;
1970 * Emit the block header for a block.
1972 * @param block the block
1973 * @param prev_block the previous block
1975 static void ia32_emit_block_header(ir_node *block)
1977 ir_graph *irg = current_ir_graph;
1978 int need_label = block_needs_label(block);
1980 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1982 if (block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
1985 if (ia32_cg_config.label_alignment > 0) {
1986 /* align the current block if:
1987 * a) if should be aligned due to its execution frequency
1988 * b) there is no fall-through here
1990 if (should_align_block(block)) {
1991 ia32_emit_align_label();
1993 /* if the predecessor block has no fall-through,
1994 we can always align the label. */
1996 int has_fallthrough = 0;
1998 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1999 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2000 if (can_be_fallthrough(cfg_pred)) {
2001 has_fallthrough = 1;
2006 if (!has_fallthrough)
2007 ia32_emit_align_label();
2011 if (need_label || has_Block_label(block)) {
2012 ia32_emit_block_name(block);
2015 be_emit_pad_comment();
2016 be_emit_cstring(" /* ");
2018 be_emit_cstring("\t/* ");
2019 ia32_emit_block_name(block);
2020 be_emit_cstring(": ");
2023 be_emit_cstring("preds:");
2025 /* emit list of pred blocks in comment */
2026 arity = get_irn_arity(block);
2027 for (i = 0; i < arity; ++i) {
2028 ir_node *predblock = get_Block_cfgpred_block(block, i);
2029 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2031 if (exec_freq != NULL) {
2032 be_emit_irprintf(" freq: %f",
2033 get_block_execfreq(exec_freq, block));
2035 be_emit_cstring(" */\n");
2036 be_emit_write_line();
2040 * Walks over the nodes in a block connected by scheduling edges
2041 * and emits code for each node.
2043 static void ia32_gen_block(ir_node *block)
2047 ia32_emit_block_header(block);
2049 /* emit the contents of the block */
2050 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2051 sched_foreach(block, node) {
2052 ia32_emit_node(node);
2056 typedef struct exc_entry {
2057 ir_node *exc_instr; /** The instruction that can issue an exception. */
2058 ir_node *block; /** The block to call then. */
2063 * Sets labels for control flow nodes (jump target).
2064 * Links control predecessors to there destination blocks.
2066 static void ia32_gen_labels(ir_node *block, void *data)
2068 exc_entry **exc_list = data;
2072 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2073 pred = get_Block_cfgpred(block, n);
2074 set_irn_link(pred, block);
2076 pred = skip_Proj(pred);
2077 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2082 ARR_APP1(exc_entry, *exc_list, e);
2083 set_irn_link(pred, block);
2089 * Compare two exception_entries.
2091 static int cmp_exc_entry(const void *a, const void *b)
2093 const exc_entry *ea = a;
2094 const exc_entry *eb = b;
2096 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2102 * Main driver. Emits the code for one routine.
2104 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2106 ir_entity *entity = get_irg_entity(irg);
2107 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2112 do_pic = cg->birg->main_env->options->pic;
2114 ia32_register_emitters();
2116 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2118 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2119 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2121 /* we use links to point to target blocks */
2122 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2123 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2125 /* initialize next block links */
2126 n = ARR_LEN(cg->blk_sched);
2127 for (i = 0; i < n; ++i) {
2128 ir_node *block = cg->blk_sched[i];
2129 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2131 set_irn_link(block, prev);
2134 for (i = 0; i < n; ++i) {
2135 ir_node *block = cg->blk_sched[i];
2137 ia32_gen_block(block);
2140 be_gas_emit_function_epilog(entity);
2141 be_dbg_method_end();
2143 be_emit_write_line();
2145 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2147 /* Sort the exception table using the exception label id's.
2148 Those are ascending with ascending addresses. */
2149 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2153 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2154 be_emit_cstring("\t.long ");
2155 ia32_emit_exc_label(exc_list[i].exc_instr);
2157 be_emit_cstring("\t.long ");
2158 ia32_emit_block_name(exc_list[i].block);
2162 DEL_ARR_F(exc_list);
2165 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2166 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2170 void ia32_init_emitter(void)
2172 lc_opt_entry_t *be_grp;
2173 lc_opt_entry_t *ia32_grp;
2175 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2176 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2178 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2180 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");