2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
69 * Returns the register at in position pos.
72 const arch_register_t *get_in_reg(ia32_emit_env_t *env, const ir_node *irn,
75 const arch_env_t *arch_env = env->arch_env;
77 const arch_register_t *reg = NULL;
79 assert(get_irn_arity(irn) > pos && "Invalid IN position");
81 /* The out register of the operator at position pos is the
82 in register we need. */
83 op = get_irn_n(irn, pos);
85 reg = arch_get_irn_register(arch_env, op);
87 assert(reg && "no in register found");
89 if(reg == &ia32_gp_regs[REG_GP_NOREG])
90 panic("trying to emit noreg");
92 /* in case of unknown register: just return a valid register */
93 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
94 const arch_register_req_t *req;
96 /* ask for the requirements */
97 req = arch_get_register_req(arch_env, irn, pos);
99 if (arch_register_req_is(req, limited)) {
100 /* in case of limited requirements: get the first allowed register */
101 unsigned idx = rbitset_next(req->limited, 0, 1);
102 reg = arch_register_for_index(req->cls, idx);
104 /* otherwise get first register in class */
105 reg = arch_register_for_index(req->cls, 0);
113 * Returns the register at out position pos.
116 const arch_register_t *get_out_reg(ia32_emit_env_t *env, const ir_node *irn,
119 const arch_env_t *arch_env = env->arch_env;
121 const arch_register_t *reg = NULL;
123 /* 1st case: irn is not of mode_T, so it has only */
124 /* one OUT register -> good */
125 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
126 /* Proj with the corresponding projnum for the register */
128 if (get_irn_mode(irn) != mode_T) {
129 reg = arch_get_irn_register(arch_env, irn);
130 } else if (is_ia32_irn(irn)) {
131 reg = get_ia32_out_reg(irn, pos);
133 const ir_edge_t *edge;
135 foreach_out_edge(irn, edge) {
136 proj = get_edge_src_irn(edge);
137 assert(is_Proj(proj) && "non-Proj from mode_T node");
138 if (get_Proj_proj(proj) == pos) {
139 reg = arch_get_irn_register(arch_env, proj);
145 assert(reg && "no out register found");
150 * Determine the gnu assembler suffix that indicates a mode
153 char get_mode_suffix(const ir_mode *mode) {
154 if(mode_is_float(mode)) {
155 switch(get_mode_size_bits(mode)) {
165 assert(mode_is_int(mode) || mode_is_reference(mode) || mode_is_character(mode));
166 switch(get_mode_size_bits(mode)) {
177 panic("Can't output mode_suffix for %+F\n", mode);
181 int produces_result(const ir_node *node) {
183 !is_ia32_CmpSet(node) &&
184 !is_ia32_CondJmp(node) &&
186 !is_ia32_SwitchJmp(node) &&
187 !is_ia32_TestJmp(node) &&
188 !is_ia32_xCmpSet(node) &&
189 !is_ia32_xCondJmp(node);
193 const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode,
194 const arch_register_t *reg) {
195 switch(get_mode_size_bits(mode)) {
197 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
199 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
201 return (char *)arch_register_get_name(reg);
206 * Add a number to a prefix. This number will not be used a second time.
209 char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
210 static unsigned long id = 0;
211 snprintf(buf, buflen, "%s%lu", prefix, ++id);
215 /*************************************************************
217 * (_) | | / _| | | | |
218 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
219 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
220 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
221 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
224 *************************************************************/
226 // we have no C++ and can't define an implicit ia32_emit_env_t* cast to
227 // be_emit_env_t* so we cheat a bit...
228 #define be_emit_char(env,c) be_emit_char(env->emit,c)
229 #define be_emit_string(env,s) be_emit_string(env->emit,s)
230 #undef be_emit_cstring
231 #define be_emit_cstring(env,x) { be_emit_string_len(env->emit, x, sizeof(x)-1); }
232 #define be_emit_ident(env,i) be_emit_ident(env->emit,i)
233 #define be_emit_tarval(env,tv) be_emit_tarval(env->emit,tv)
234 #define be_emit_write_line(env) be_emit_write_line(env->emit)
235 #define be_emit_finish_line_gas(env,n) be_emit_finish_line_gas(env->emit,n)
236 #define be_emit_pad_comment(env) be_emit_pad_comment(env->emit)
238 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
240 const arch_register_t *reg = get_in_reg(env, node, pos);
241 const char *reg_name = arch_register_get_name(reg);
243 assert(pos < get_irn_arity(node));
245 be_emit_char(env, '%');
246 be_emit_string(env, reg_name);
249 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
250 const arch_register_t *reg = get_out_reg(env, node, pos);
251 const char *reg_name = arch_register_get_name(reg);
253 be_emit_char(env, '%');
254 be_emit_string(env, reg_name);
257 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
259 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
262 be_emit_char(env, '%');
263 be_emit_string(env, attr->x87[pos]->name);
266 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
272 be_emit_char(env, '$');
274 switch(get_ia32_immop_type(node)) {
276 tv = get_ia32_Immop_tarval(node);
277 be_emit_tarval(env, tv);
279 case ia32_ImmSymConst:
280 ent = get_ia32_Immop_symconst(node);
281 set_entity_backend_marked(ent, 1);
282 id = get_entity_ld_ident(ent);
283 be_emit_ident(env, id);
290 be_emit_string(env, "BAD");
295 void ia32_emit_mode_suffix_mode(ia32_emit_env_t *env, const ir_mode *mode)
297 be_emit_char(env, get_mode_suffix(mode));
300 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
302 ir_mode *mode = get_ia32_ls_mode(node);
306 ia32_emit_mode_suffix_mode(env, mode);
309 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
311 ir_mode *mode = get_ia32_ls_mode(node);
313 ia32_emit_mode_suffix_mode(env, mode);
317 char get_xmm_mode_suffix(ir_mode *mode)
319 assert(mode_is_float(mode));
320 switch(get_mode_size_bits(mode)) {
331 void ia32_emit_xmm_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
333 ir_mode *mode = get_ia32_ls_mode(node);
334 assert(mode != NULL);
335 be_emit_char(env, 's');
336 be_emit_char(env, get_xmm_mode_suffix(mode));
339 void ia32_emit_xmm_mode_suffix_s(ia32_emit_env_t *env, const ir_node *node)
341 ir_mode *mode = get_ia32_ls_mode(node);
342 assert(mode != NULL);
343 be_emit_char(env, get_xmm_mode_suffix(mode));
346 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
348 if(get_mode_size_bits(mode) == 32)
350 if(mode_is_signed(mode)) {
351 be_emit_char(env, 's');
353 be_emit_char(env, 'z');
358 void ia32_emit_function_object(ia32_emit_env_t *env, const char *name)
360 switch (be_gas_flavour) {
361 case GAS_FLAVOUR_NORMAL:
362 be_emit_cstring(env, "\t.type\t");
363 be_emit_string(env, name);
364 be_emit_cstring(env, ", @function\n");
365 be_emit_write_line(env);
367 case GAS_FLAVOUR_MINGW:
368 be_emit_cstring(env, "\t.def\t");
369 be_emit_string(env, name);
370 be_emit_cstring(env, ";\t.scl\t2;\t.type\t32;\t.endef\n");
371 be_emit_write_line(env);
379 void ia32_emit_function_size(ia32_emit_env_t *env, const char *name)
381 switch (be_gas_flavour) {
382 case GAS_FLAVOUR_NORMAL:
383 be_emit_cstring(env, "\t.size\t");
384 be_emit_string(env, name);
385 be_emit_cstring(env, ", .-");
386 be_emit_string(env, name);
387 be_emit_char(env, '\n');
388 be_emit_write_line(env);
397 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node);
400 * Emits registers and/or address mode of a binary operation.
402 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
404 const ir_node *right_op = get_irn_n(node, 3);
406 switch(get_ia32_op_type(node)) {
408 if(is_ia32_Immediate(right_op)) {
409 emit_ia32_Immediate(env, right_op);
410 be_emit_cstring(env, ", ");
411 ia32_emit_source_register(env, node, 2);
413 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
414 ia32_emit_immediate(env, node);
415 be_emit_cstring(env, ", ");
416 ia32_emit_source_register(env, node, 2);
418 const arch_register_t *in1 = get_in_reg(env, node, 2);
419 const arch_register_t *in2 = get_in_reg(env, node, 3);
420 const arch_register_t *out = produces_result(node) ? get_out_reg(env, node, 0) : NULL;
421 const arch_register_t *in;
424 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
425 out = out ? out : in1;
426 in_name = arch_register_get_name(in);
428 if (is_ia32_emit_cl(node)) {
429 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
433 be_emit_char(env, '%');
434 be_emit_string(env, in_name);
435 be_emit_cstring(env, ", %");
436 be_emit_string(env, arch_register_get_name(out));
440 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
441 assert(!produces_result(node) &&
442 "Source AM with Const must not produce result");
443 ia32_emit_immediate(env, node);
444 be_emit_cstring(env, ", ");
445 ia32_emit_am(env, node);
446 } else if(is_ia32_Immediate(right_op)) {
447 assert(!produces_result(node) &&
448 "Source AM with Const must not produce result");
450 emit_ia32_Immediate(env, right_op);
451 be_emit_cstring(env, ", ");
452 ia32_emit_am(env, node);
453 } else if (produces_result(node)) {
454 ia32_emit_am(env, node);
455 be_emit_cstring(env, ", ");
456 ia32_emit_dest_register(env, node, 0);
458 ia32_emit_am(env, node);
459 be_emit_cstring(env, ", ");
460 ia32_emit_source_register(env, node, 2);
464 right_pos = get_irn_arity(node) >= 5 ? 3 : 2;
465 right_op = get_irn_n(node, right_pos);
466 if(is_ia32_Immediate(right_op)) {
467 emit_ia32_Immediate(env, right_op);
468 be_emit_cstring(env, ", ");
469 ia32_emit_am(env, node);
471 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
472 ia32_emit_immediate(env, node);
473 be_emit_cstring(env, ", ");
474 ia32_emit_am(env, node);
476 const arch_register_t *in1 = get_in_reg(env, node, right_pos);
477 ir_mode *mode = get_ia32_ls_mode(node);
480 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
482 if (is_ia32_emit_cl(node)) {
483 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
487 be_emit_char(env, '%');
488 be_emit_string(env, in_name);
489 be_emit_cstring(env, ", ");
490 ia32_emit_am(env, node);
494 assert(0 && "unsupported op type");
499 * Emits registers and/or address mode of a binary operation.
501 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
502 switch(get_ia32_op_type(node)) {
504 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
505 // should not happen...
508 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
509 const arch_register_t *in1 = x87_attr->x87[0];
510 const arch_register_t *in2 = x87_attr->x87[1];
511 const arch_register_t *out = x87_attr->x87[2];
512 const arch_register_t *in;
514 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
515 out = out ? out : in1;
517 be_emit_char(env, '%');
518 be_emit_string(env, arch_register_get_name(in));
519 be_emit_cstring(env, ", %");
520 be_emit_string(env, arch_register_get_name(out));
525 ia32_emit_am(env, node);
528 assert(0 && "unsupported op type");
532 void ia32_emit_am_or_dest_register(ia32_emit_env_t *env, const ir_node *node,
534 if(get_ia32_op_type(node) == ia32_Normal) {
535 ia32_emit_dest_register(env, node, pos);
537 assert(get_ia32_op_type(node) == ia32_AddrModeD);
538 ia32_emit_am(env, node);
543 * Emits registers and/or address mode of a unary operation.
545 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node, int pos) {
548 switch(get_ia32_op_type(node)) {
550 op = get_irn_n(node, pos);
551 if (is_ia32_Immediate(op)) {
552 emit_ia32_Immediate(env, op);
553 } else if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
554 ia32_emit_immediate(env, node);
556 ia32_emit_source_register(env, node, pos);
561 ia32_emit_am(env, node);
564 assert(0 && "unsupported op type");
569 * Emits address mode.
571 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
572 ir_entity *ent = get_ia32_am_sc(node);
573 int offs = get_ia32_am_offs_int(node);
574 ir_node *base = get_irn_n(node, 0);
575 int has_base = !is_ia32_NoReg_GP(base);
576 ir_node *index = get_irn_n(node, 1);
577 int has_index = !is_ia32_NoReg_GP(index);
579 /* just to be sure... */
580 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
586 set_entity_backend_marked(ent, 1);
587 id = get_entity_ld_ident(ent);
588 if (is_ia32_am_sc_sign(node))
589 be_emit_char(env, '-');
590 be_emit_ident(env, id);
592 if(get_entity_owner(ent) == get_tls_type()) {
593 if (get_entity_visibility(ent) == visibility_external_allocated) {
594 be_emit_cstring(env, "@INDNTPOFF");
596 be_emit_cstring(env, "@NTPOFF");
603 be_emit_irprintf(env->emit, "%+d", offs);
605 be_emit_irprintf(env->emit, "%d", offs);
609 if (has_base || has_index) {
610 be_emit_char(env, '(');
614 ia32_emit_source_register(env, node, 0);
617 /* emit index + scale */
620 be_emit_char(env, ',');
621 ia32_emit_source_register(env, node, 1);
623 scale = get_ia32_am_scale(node);
625 be_emit_irprintf(env->emit, ",%d", 1 << get_ia32_am_scale(node));
628 be_emit_char(env, ')');
632 /*************************************************
635 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
636 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
637 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
638 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
640 *************************************************/
643 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
646 * coding of conditions
648 struct cmp2conditon_t {
654 * positive conditions for signed compares
657 const struct cmp2conditon_t cmp2condition_s[] = {
658 { NULL, pn_Cmp_False }, /* always false */
659 { "e", pn_Cmp_Eq }, /* == */
660 { "l", pn_Cmp_Lt }, /* < */
661 { "le", pn_Cmp_Le }, /* <= */
662 { "g", pn_Cmp_Gt }, /* > */
663 { "ge", pn_Cmp_Ge }, /* >= */
664 { "ne", pn_Cmp_Lg }, /* != */
665 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
666 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
667 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
668 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
669 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
670 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
671 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
672 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
673 { NULL, pn_Cmp_True }, /* always true */
677 * positive conditions for unsigned compares
680 const struct cmp2conditon_t cmp2condition_u[] = {
681 { NULL, pn_Cmp_False }, /* always false */
682 { "e", pn_Cmp_Eq }, /* == */
683 { "b", pn_Cmp_Lt }, /* < */
684 { "be", pn_Cmp_Le }, /* <= */
685 { "a", pn_Cmp_Gt }, /* > */
686 { "ae", pn_Cmp_Ge }, /* >= */
687 { "ne", pn_Cmp_Lg }, /* != */
688 { NULL, pn_Cmp_True }, /* always true */
692 * returns the condition code
695 const char *get_cmp_suffix(pn_Cmp cmp_code)
697 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
698 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
700 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
701 return cmp2condition_u[cmp_code & 7].name;
703 return cmp2condition_s[cmp_code & 15].name;
707 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
709 be_emit_string(env, get_cmp_suffix(pnc));
714 * Returns the target block for a control flow node.
717 ir_node *get_cfop_target_block(const ir_node *irn) {
718 return get_irn_link(irn);
722 * Emits a block label for the given block.
725 void ia32_emit_block_name(ia32_emit_env_t *env, const ir_node *block)
727 be_emit_cstring(env, BLOCK_PREFIX);
728 be_emit_irprintf(env->emit, "%d", get_irn_node_nr(block));
732 * Emits the target label for a control flow node.
735 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
736 ir_node *block = get_cfop_target_block(node);
738 ia32_emit_block_name(env, block);
741 /** Return the next block in Block schedule */
742 static ir_node *next_blk_sched(const ir_node *block) {
743 return get_irn_link(block);
747 * Returns the Proj with projection number proj and NOT mode_M
750 ir_node *get_proj(const ir_node *node, long proj) {
751 const ir_edge_t *edge;
754 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
756 foreach_out_edge(node, edge) {
757 src = get_edge_src_irn(edge);
759 assert(is_Proj(src) && "Proj expected");
760 if (get_irn_mode(src) == mode_M)
763 if (get_Proj_proj(src) == proj)
770 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
773 void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode,
775 const ir_node *proj_true;
776 const ir_node *proj_false;
777 const ir_node *block;
778 const ir_node *next_block;
781 /* get both Proj's */
782 proj_true = get_proj(node, pn_Cond_true);
783 assert(proj_true && "CondJmp without true Proj");
785 proj_false = get_proj(node, pn_Cond_false);
786 assert(proj_false && "CondJmp without false Proj");
788 /* for now, the code works for scheduled and non-schedules blocks */
789 block = get_nodes_block(node);
791 /* we have a block schedule */
792 next_block = next_blk_sched(block);
794 if (get_cfop_target_block(proj_true) == next_block) {
795 /* exchange both proj's so the second one can be omitted */
796 const ir_node *t = proj_true;
798 proj_true = proj_false;
801 pnc = get_negated_pnc(pnc, mode);
804 /* in case of unordered compare, check for parity */
805 if (pnc & pn_Cmp_Uo) {
806 be_emit_cstring(env, "\tjp ");
807 ia32_emit_cfop_target(env, proj_true);
808 be_emit_finish_line_gas(env, proj_true);
811 be_emit_cstring(env, "\tj");
812 ia32_emit_cmp_suffix(env, pnc);
813 be_emit_char(env, ' ');
814 ia32_emit_cfop_target(env, proj_true);
815 be_emit_finish_line_gas(env, proj_true);
817 /* the second Proj might be a fallthrough */
818 if (get_cfop_target_block(proj_false) != next_block) {
819 be_emit_cstring(env, "\tjmp ");
820 ia32_emit_cfop_target(env, proj_false);
821 be_emit_finish_line_gas(env, proj_false);
823 be_emit_cstring(env, "\t/* fallthrough to ");
824 ia32_emit_cfop_target(env, proj_false);
825 be_emit_cstring(env, " */");
826 be_emit_finish_line_gas(env, proj_false);
831 * Emits code for conditional jump.
834 void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
835 be_emit_cstring(env, "\tcmp");
836 ia32_emit_mode_suffix(env, node);
837 be_emit_char(env, ' ');
838 ia32_emit_binop(env, node);
839 be_emit_finish_line_gas(env, node);
841 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
845 * Emits code for conditional jump with two variables.
848 void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
849 CondJmp_emitter(env, node);
853 * Emits code for conditional test and jump.
856 void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
857 be_emit_cstring(env, "\ttest");
858 ia32_emit_mode_suffix(env, node);
859 be_emit_char(env, ' ');
861 ia32_emit_binop(env, node);
862 be_emit_finish_line_gas(env, node);
864 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
868 * Emits code for conditional test and jump with two variables.
871 void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
872 TestJmp_emitter(env, node);
876 * Emits code for conditional SSE floating point jump with two variables.
879 void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
880 be_emit_cstring(env, "\tucomi");
881 ia32_emit_xmm_mode_suffix(env, node);
882 be_emit_char(env, ' ');
883 ia32_emit_binop(env, node);
884 be_emit_finish_line_gas(env, node);
886 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
890 * Emits code for conditional x87 floating point jump with two variables.
893 void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
894 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
895 const char *reg = x87_attr->x87[1]->name;
896 long pnc = get_ia32_pncode(node);
898 switch (get_ia32_irn_opcode(node)) {
899 case iro_ia32_fcomrJmp:
900 pnc = get_inversed_pnc(pnc);
901 reg = x87_attr->x87[0]->name;
902 case iro_ia32_fcomJmp:
904 be_emit_cstring(env, "\tfucom ");
906 case iro_ia32_fcomrpJmp:
907 pnc = get_inversed_pnc(pnc);
908 reg = x87_attr->x87[0]->name;
909 case iro_ia32_fcompJmp:
910 be_emit_cstring(env, "\tfucomp ");
912 case iro_ia32_fcomrppJmp:
913 pnc = get_inversed_pnc(pnc);
914 case iro_ia32_fcomppJmp:
915 be_emit_cstring(env, "\tfucompp ");
921 be_emit_char(env, '%');
922 be_emit_string(env, reg);
924 be_emit_finish_line_gas(env, node);
926 be_emit_cstring(env, "\tfnstsw %ax");
927 be_emit_finish_line_gas(env, node);
928 be_emit_cstring(env, "\tsahf");
929 be_emit_finish_line_gas(env, node);
931 finish_CondJmp(env, node, mode_E, pnc);
935 void emit_register_or_immediate(ia32_emit_env_t *env, const ir_node *node,
938 ir_node *op = get_irn_n(node, pos);
939 if(is_ia32_Immediate(op)) {
940 emit_ia32_Immediate(env, op);
942 ia32_emit_source_register(env, node, pos);
947 int is_ia32_Immediate_0(const ir_node *node)
949 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
951 return attr->offset == 0 && attr->symconst == NULL;
955 void CMov_emitter(ia32_emit_env_t *env, const ir_node *node)
957 long pnc = get_ia32_pncode(node);
958 const arch_register_t *in1, *in2, *out;
960 out = arch_get_irn_register(env->arch_env, node);
961 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 2));
962 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 3));
964 /* we have to emit the cmp first, because the destination register */
965 /* could be one of the compare registers */
966 if (is_ia32_CmpCMov(node)) {
967 long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
968 ir_node *cmp_right = get_irn_n(node, 1);
970 if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
971 && is_ia32_Immediate(cmp_right)
972 && is_ia32_Immediate_0(cmp_right)) {
973 be_emit_cstring(env, "\ttest ");
974 ia32_emit_source_register(env, node, 0);
975 be_emit_cstring(env, ", ");
976 ia32_emit_source_register(env, node, 0);
978 be_emit_cstring(env, "\tcmp ");
979 emit_register_or_immediate(env, node, 1);
980 be_emit_cstring(env, ", ");
981 ia32_emit_source_register(env, node, 0);
983 } else if (is_ia32_xCmpCMov(node)) {
984 be_emit_cstring(env, "\tucomis");
985 ia32_emit_mode_suffix_mode(env, get_irn_mode(node));
986 be_emit_char(env, ' ');
987 ia32_emit_source_register(env, node, 1);
988 be_emit_cstring(env, ", ");
989 ia32_emit_source_register(env, node, 0);
991 assert(0 && "unsupported CMov");
993 be_emit_finish_line_gas(env, node);
995 if (REGS_ARE_EQUAL(out, in2)) {
996 /* best case: default in == out -> do nothing */
997 } else if (REGS_ARE_EQUAL(out, in1)) {
998 ir_node *n = (ir_node*) node;
999 /* true in == out -> need complement compare and exchange true and default in */
1000 ir_node *t = get_irn_n(n, 2);
1001 set_irn_n(n, 2, get_irn_n(n, 3));
1004 pnc = get_negated_pnc(pnc, get_irn_mode(node));
1006 /* out is different from in: need copy default -> out */
1007 be_emit_cstring(env, "\tmovl ");
1008 ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_false);
1009 be_emit_cstring(env, ", ");
1010 ia32_emit_dest_register(env, node, 0);
1011 be_emit_finish_line_gas(env, node);
1014 be_emit_cstring(env, "\tcmov");
1015 ia32_emit_cmp_suffix(env, pnc);
1016 be_emit_cstring(env, "l ");
1017 ia32_emit_source_register(env, node, n_ia32_CmpCMov_val_true);
1018 be_emit_cstring(env, ", ");
1019 ia32_emit_dest_register(env, node, 0);
1020 be_emit_finish_line_gas(env, node);
1024 void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node)
1026 CMov_emitter(env, node);
1030 void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node)
1032 CMov_emitter(env, node);
1036 void Set_emitter(ia32_emit_env_t *env, const ir_node *node)
1038 long pnc = get_ia32_pncode(node);
1039 const char *reg8bit;
1040 const arch_register_t *out;
1042 out = arch_get_irn_register(env->arch_env, node);
1043 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1045 if (is_ia32_CmpSet(node)) {
1046 long pncr = pnc & ~ia32_pn_Cmp_Unsigned;
1047 ir_node *cmp_right = get_irn_n(node, n_ia32_CmpSet_cmp_right);
1049 if( (pncr == pn_Cmp_Eq || pncr == pn_Cmp_Lg)
1050 && is_ia32_Immediate(cmp_right)
1051 && is_ia32_Immediate_0(cmp_right)) {
1052 be_emit_cstring(env, "\ttest ");
1053 ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
1054 be_emit_cstring(env, ", ");
1055 ia32_emit_source_register(env, node, n_ia32_CmpSet_cmp_left);
1057 be_emit_cstring(env, "\tcmp ");
1058 ia32_emit_binop(env, node);
1060 } else if (is_ia32_xCmpSet(node)) {
1061 be_emit_cstring(env, "\tucomis");
1062 ia32_emit_mode_suffix_mode(env, get_irn_mode(get_irn_n(node, 2)));
1063 be_emit_char(env, ' ');
1064 ia32_emit_binop(env, node);
1066 assert(0 && "unsupported Set");
1068 be_emit_finish_line_gas(env, node);
1070 /* use mov to clear target because it doesn't affect the eflags */
1071 be_emit_cstring(env, "\tmovl $0, %");
1072 be_emit_string(env, arch_register_get_name(out));
1073 be_emit_finish_line_gas(env, node);
1075 be_emit_cstring(env, "\tset");
1076 ia32_emit_cmp_suffix(env, pnc);
1077 be_emit_cstring(env, " %");
1078 be_emit_string(env, reg8bit);
1079 be_emit_finish_line_gas(env, node);
1083 void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1084 Set_emitter(env, node);
1088 void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1089 Set_emitter(env, node);
1093 void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1095 long pnc = get_ia32_pncode(node);
1096 long unord = pnc & pn_Cmp_Uo;
1098 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1101 case pn_Cmp_Leg: /* odered */
1104 case pn_Cmp_Uo: /* unordered */
1108 case pn_Cmp_Eq: /* == */
1112 case pn_Cmp_Lt: /* < */
1116 case pn_Cmp_Le: /* <= */
1120 case pn_Cmp_Gt: /* > */
1124 case pn_Cmp_Ge: /* >= */
1128 case pn_Cmp_Lg: /* != */
1133 assert(sse_pnc >= 0 && "unsupported compare");
1135 if (unord && sse_pnc != 3) {
1137 We need a separate compare against unordered.
1138 Quick and Dirty solution:
1139 - get some memory on stack
1143 - and result and stored result
1146 be_emit_cstring(env, "\tsubl $8, %esp");
1147 be_emit_finish_line_gas(env, node);
1149 be_emit_cstring(env, "\tcmpsd $3, ");
1150 ia32_emit_binop(env, node);
1151 be_emit_finish_line_gas(env, node);
1153 be_emit_cstring(env, "\tmovsd ");
1154 ia32_emit_dest_register(env, node, 0);
1155 be_emit_cstring(env, ", (%esp)");
1156 be_emit_finish_line_gas(env, node);
1159 be_emit_cstring(env, "\tcmpsd ");
1160 be_emit_irprintf(env->emit, "%d, ", sse_pnc);
1161 ia32_emit_binop(env, node);
1162 be_emit_finish_line_gas(env, node);
1164 if (unord && sse_pnc != 3) {
1165 be_emit_cstring(env, "\tandpd (%esp), ");
1166 ia32_emit_dest_register(env, node, 0);
1167 be_emit_finish_line_gas(env, node);
1169 be_emit_cstring(env, "\taddl $8, %esp");
1170 be_emit_finish_line_gas(env, node);
1174 /*********************************************************
1177 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1178 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1179 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1180 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1183 *********************************************************/
1185 /* jump table entry (target and corresponding number) */
1186 typedef struct _branch_t {
1191 /* jump table for switch generation */
1192 typedef struct _jmp_tbl_t {
1193 ir_node *defProj; /**< default target */
1194 long min_value; /**< smallest switch case */
1195 long max_value; /**< largest switch case */
1196 long num_branches; /**< number of jumps */
1197 char *label; /**< label of the jump table */
1198 branch_t *branches; /**< jump array */
1202 * Compare two variables of type branch_t. Used to sort all switch cases
1205 int ia32_cmp_branch_t(const void *a, const void *b) {
1206 branch_t *b1 = (branch_t *)a;
1207 branch_t *b2 = (branch_t *)b;
1209 if (b1->value <= b2->value)
1216 * Emits code for a SwitchJmp (creates a jump table if
1217 * possible otherwise a cmp-jmp cascade). Port from
1221 void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1222 unsigned long interval;
1227 const ir_edge_t *edge;
1229 /* fill the table structure */
1230 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1231 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1233 tbl.num_branches = get_irn_n_edges(node);
1234 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1235 tbl.min_value = INT_MAX;
1236 tbl.max_value = INT_MIN;
1239 /* go over all proj's and collect them */
1240 foreach_out_edge(node, edge) {
1241 proj = get_edge_src_irn(edge);
1242 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1244 pnc = get_Proj_proj(proj);
1246 /* create branch entry */
1247 tbl.branches[i].target = proj;
1248 tbl.branches[i].value = pnc;
1250 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1251 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1253 /* check for default proj */
1254 if (pnc == get_ia32_pncode(node)) {
1255 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1262 /* sort the branches by their number */
1263 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1265 /* two-complement's magic make this work without overflow */
1266 interval = tbl.max_value - tbl.min_value;
1268 /* emit the table */
1269 be_emit_cstring(env, "\tcmpl $");
1270 be_emit_irprintf(env->emit, "%u, ", interval);
1271 ia32_emit_source_register(env, node, 0);
1272 be_emit_finish_line_gas(env, node);
1274 be_emit_cstring(env, "\tja ");
1275 ia32_emit_cfop_target(env, tbl.defProj);
1276 be_emit_finish_line_gas(env, node);
1278 if (tbl.num_branches > 1) {
1280 be_emit_cstring(env, "\tjmp *");
1281 be_emit_string(env, tbl.label);
1282 be_emit_cstring(env, "(,");
1283 ia32_emit_source_register(env, node, 0);
1284 be_emit_cstring(env, ",4)");
1285 be_emit_finish_line_gas(env, node);
1287 be_gas_emit_switch_section(env->emit, GAS_SECTION_RODATA);
1288 be_emit_cstring(env, "\t.align 4\n");
1289 be_emit_write_line(env);
1291 be_emit_string(env, tbl.label);
1292 be_emit_cstring(env, ":\n");
1293 be_emit_write_line(env);
1295 be_emit_cstring(env, ".long ");
1296 ia32_emit_cfop_target(env, tbl.branches[0].target);
1297 be_emit_finish_line_gas(env, NULL);
1299 last_value = tbl.branches[0].value;
1300 for (i = 1; i < tbl.num_branches; ++i) {
1301 while (++last_value < tbl.branches[i].value) {
1302 be_emit_cstring(env, ".long ");
1303 ia32_emit_cfop_target(env, tbl.defProj);
1304 be_emit_finish_line_gas(env, NULL);
1306 be_emit_cstring(env, ".long ");
1307 ia32_emit_cfop_target(env, tbl.branches[i].target);
1308 be_emit_finish_line_gas(env, NULL);
1310 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
1312 /* one jump is enough */
1313 be_emit_cstring(env, "\tjmp ");
1314 ia32_emit_cfop_target(env, tbl.branches[0].target);
1315 be_emit_finish_line_gas(env, node);
1325 * Emits code for a unconditional jump.
1328 void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1329 ir_node *block, *next_block;
1331 /* for now, the code works for scheduled and non-schedules blocks */
1332 block = get_nodes_block(node);
1334 /* we have a block schedule */
1335 next_block = next_blk_sched(block);
1336 if (get_cfop_target_block(node) != next_block) {
1337 be_emit_cstring(env, "\tjmp ");
1338 ia32_emit_cfop_target(env, node);
1340 be_emit_cstring(env, "\t/* fallthrough to ");
1341 ia32_emit_cfop_target(env, node);
1342 be_emit_cstring(env, " */");
1344 be_emit_finish_line_gas(env, node);
1348 void emit_ia32_Immediate(ia32_emit_env_t *env, const ir_node *node)
1350 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1352 be_emit_char(env, '$');
1353 if(attr->symconst != NULL) {
1354 ident *id = get_entity_ld_ident(attr->symconst);
1356 if(attr->attr.data.am_sc_sign)
1357 be_emit_char(env, '-');
1358 be_emit_ident(env, id);
1360 if(attr->symconst == NULL || attr->offset != 0) {
1361 if(attr->symconst != NULL)
1362 be_emit_char(env, '+');
1363 be_emit_irprintf(env->emit, "%d", attr->offset);
1368 const char* emit_asm_operand(ia32_emit_env_t *env, const ir_node *node,
1371 const arch_register_t *reg;
1372 const char *reg_name;
1376 const ia32_attr_t *attr;
1383 /* parse modifiers */
1386 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1387 be_emit_char(env, '%');
1390 be_emit_char(env, '%');
1410 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1411 "'%c' for asm op\n", node, c);
1417 sscanf(s, "%d%n", &num, &p);
1419 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1427 attr = get_ia32_attr_const(node);
1428 n_outs = ARR_LEN(attr->slots);
1430 reg = get_out_reg(env, node, num);
1433 int in = num - n_outs;
1434 if(in >= get_irn_arity(node)) {
1435 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1436 "op (%+F)\n", num, node);
1439 pred = get_irn_n(node, in);
1440 /* might be an immediate value */
1441 if(is_ia32_Immediate(pred)) {
1442 emit_ia32_Immediate(env, pred);
1445 reg = get_in_reg(env, node, in);
1448 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1449 "(%+F)\n", num, node);
1454 be_emit_char(env, '%');
1457 reg_name = arch_register_get_name(reg);
1460 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
1463 reg_name = ia32_get_mapped_reg_name(env->isa->regs_8bit_high, reg);
1466 reg_name = ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
1469 panic("Invalid asm op modifier");
1471 be_emit_string(env, reg_name);
1477 * Emits code for an ASM pseudo op.
1480 void emit_ia32_Asm(ia32_emit_env_t *env, const ir_node *node)
1482 const void *gen_attr = get_irn_generic_attr_const(node);
1483 const ia32_asm_attr_t *attr
1484 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1485 ident *asm_text = attr->asm_text;
1486 const char *s = get_id_str(asm_text);
1488 be_emit_cstring(env, "# Begin ASM \t");
1489 be_emit_finish_line_gas(env, node);
1492 be_emit_char(env, '\t');
1496 s = emit_asm_operand(env, node, s);
1499 be_emit_char(env, *s);
1504 be_emit_char(env, '\n');
1505 be_emit_write_line(env);
1507 be_emit_cstring(env, "# End ASM\n");
1508 be_emit_write_line(env);
1511 /**********************************
1514 * | | ___ _ __ _ _| |_) |
1515 * | | / _ \| '_ \| | | | _ <
1516 * | |___| (_) | |_) | |_| | |_) |
1517 * \_____\___/| .__/ \__, |____/
1520 **********************************/
1523 * Emit movsb/w instructions to make mov count divideable by 4
1526 void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1527 be_emit_cstring(env, "\tcld");
1528 be_emit_finish_line_gas(env, NULL);
1532 be_emit_cstring(env, "\tmovsb");
1533 be_emit_finish_line_gas(env, NULL);
1536 be_emit_cstring(env, "\tmovsw");
1537 be_emit_finish_line_gas(env, NULL);
1540 be_emit_cstring(env, "\tmovsb");
1541 be_emit_finish_line_gas(env, NULL);
1542 be_emit_cstring(env, "\tmovsw");
1543 be_emit_finish_line_gas(env, NULL);
1549 * Emit rep movsd instruction for memcopy.
1552 void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1553 tarval *tv = get_ia32_Immop_tarval(node);
1554 int rem = get_tarval_long(tv);
1556 emit_CopyB_prolog(env, rem);
1558 be_emit_cstring(env, "\trep movsd");
1559 be_emit_finish_line_gas(env, node);
1563 * Emits unrolled memcopy.
1566 void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1567 tarval *tv = get_ia32_Immop_tarval(node);
1568 int size = get_tarval_long(tv);
1570 emit_CopyB_prolog(env, size & 0x3);
1574 be_emit_cstring(env, "\tmovsd");
1575 be_emit_finish_line_gas(env, NULL);
1581 /***************************
1585 * | | / _ \| '_ \ \ / /
1586 * | |___| (_) | | | \ V /
1587 * \_____\___/|_| |_|\_/
1589 ***************************/
1592 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1595 void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1596 ir_mode *ls_mode = get_ia32_ls_mode(node);
1597 int ls_bits = get_mode_size_bits(ls_mode);
1599 be_emit_cstring(env, "\tcvt");
1601 if(is_ia32_Conv_I2FP(node)) {
1603 be_emit_cstring(env, "si2ss");
1605 be_emit_cstring(env, "si2sd");
1607 } else if(is_ia32_Conv_FP2I(node)) {
1609 be_emit_cstring(env, "ss2si");
1611 be_emit_cstring(env, "sd2si");
1614 assert(is_ia32_Conv_FP2FP(node));
1616 be_emit_cstring(env, "sd2ss");
1618 be_emit_cstring(env, "ss2sd");
1621 be_emit_char(env, ' ');
1623 switch(get_ia32_op_type(node)) {
1625 ia32_emit_source_register(env, node, 2);
1626 be_emit_cstring(env, ", ");
1627 ia32_emit_dest_register(env, node, 0);
1629 case ia32_AddrModeS:
1630 ia32_emit_dest_register(env, node, 0);
1631 be_emit_cstring(env, ", ");
1632 ia32_emit_am(env, node);
1635 assert(0 && "unsupported op type for Conv");
1637 be_emit_finish_line_gas(env, node);
1641 void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1642 emit_ia32_Conv_with_FP(env, node);
1646 void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1647 emit_ia32_Conv_with_FP(env, node);
1651 void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1652 emit_ia32_Conv_with_FP(env, node);
1656 * Emits code for an Int conversion.
1659 void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1660 const char *sign_suffix;
1661 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1662 int smaller_bits = get_mode_size_bits(smaller_mode);
1664 const arch_register_t *in_reg, *out_reg;
1666 assert(!mode_is_float(smaller_mode));
1667 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1669 signed_mode = mode_is_signed(smaller_mode);
1670 if(smaller_bits == 32) {
1671 // this should not happen as it's no convert
1675 sign_suffix = signed_mode ? "s" : "z";
1678 switch(get_ia32_op_type(node)) {
1680 in_reg = get_in_reg(env, node, 2);
1681 out_reg = get_out_reg(env, node, 0);
1683 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1684 REGS_ARE_EQUAL(out_reg, in_reg) &&
1688 /* argument and result are both in EAX and */
1689 /* signedness is ok: -> use the smaller cwtl opcode */
1690 be_emit_cstring(env, "\tcwtl");
1692 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1694 be_emit_cstring(env, "\tmov");
1695 be_emit_string(env, sign_suffix);
1696 ia32_emit_mode_suffix_mode(env, smaller_mode);
1697 be_emit_cstring(env, "l %");
1698 be_emit_string(env, sreg);
1699 be_emit_cstring(env, ", ");
1700 ia32_emit_dest_register(env, node, 0);
1703 case ia32_AddrModeS: {
1704 be_emit_cstring(env, "\tmov");
1705 be_emit_string(env, sign_suffix);
1706 ia32_emit_mode_suffix_mode(env, smaller_mode);
1707 be_emit_cstring(env, "l %");
1708 ia32_emit_am(env, node);
1709 be_emit_cstring(env, ", ");
1710 ia32_emit_dest_register(env, node, 0);
1714 assert(0 && "unsupported op type for Conv");
1716 be_emit_finish_line_gas(env, node);
1720 * Emits code for an 8Bit Int conversion.
1722 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1723 emit_ia32_Conv_I2I(env, node);
1727 /*******************************************
1730 * | |__ ___ _ __ ___ __| | ___ ___
1731 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1732 * | |_) | __/ | | | (_) | (_| | __/\__ \
1733 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1735 *******************************************/
1738 * Emits a backend call
1741 void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1742 ir_entity *ent = be_Call_get_entity(node);
1744 be_emit_cstring(env, "\tcall ");
1746 set_entity_backend_marked(ent, 1);
1747 be_emit_string(env, get_entity_ld_name(ent));
1749 be_emit_char(env, '*');
1750 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1752 be_emit_finish_line_gas(env, node);
1756 * Emits code to increase stack pointer.
1759 void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1760 int offs = be_get_IncSP_offset(node);
1766 be_emit_cstring(env, "\tsubl $");
1767 be_emit_irprintf(env->emit, "%u, ", offs);
1768 ia32_emit_source_register(env, node, 0);
1770 be_emit_cstring(env, "\taddl $");
1771 be_emit_irprintf(env->emit, "%u, ", -offs);
1772 ia32_emit_source_register(env, node, 0);
1774 be_emit_finish_line_gas(env, node);
1778 * Emits code to set stack pointer.
1781 void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1782 be_emit_cstring(env, "\tmovl ");
1783 ia32_emit_source_register(env, node, 2);
1784 be_emit_cstring(env, ", ");
1785 ia32_emit_dest_register(env, node, 0);
1786 be_emit_finish_line_gas(env, node);
1790 * Emits code for Copy/CopyKeep.
1793 void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op)
1795 const arch_env_t *aenv = env->arch_env;
1798 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1799 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1802 mode = get_irn_mode(node);
1803 if (mode == mode_E) {
1804 be_emit_cstring(env, "\tmovsd ");
1805 ia32_emit_source_register(env, node, 0);
1806 be_emit_cstring(env, ", ");
1807 ia32_emit_dest_register(env, node, 0);
1809 be_emit_cstring(env, "\tmovl ");
1810 ia32_emit_source_register(env, node, 0);
1811 be_emit_cstring(env, ", ");
1812 ia32_emit_dest_register(env, node, 0);
1814 be_emit_finish_line_gas(env, node);
1818 void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1819 Copy_emitter(env, node, be_get_Copy_op(node));
1823 void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1824 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1828 * Emits code for exchange.
1831 void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1832 const arch_register_t *in1, *in2;
1833 const arch_register_class_t *cls1, *cls2;
1835 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1836 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1838 cls1 = arch_register_get_class(in1);
1839 cls2 = arch_register_get_class(in2);
1841 assert(cls1 == cls2 && "Register class mismatch at Perm");
1843 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1844 be_emit_cstring(env, "\txchg ");
1845 ia32_emit_source_register(env, node, 1);
1846 be_emit_cstring(env, ", ");
1847 ia32_emit_source_register(env, node, 0);
1848 be_emit_finish_line_gas(env, node);
1849 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1850 be_emit_cstring(env, "\txorpd ");
1851 ia32_emit_source_register(env, node, 1);
1852 be_emit_cstring(env, ", ");
1853 ia32_emit_source_register(env, node, 0);
1854 be_emit_finish_line_gas(env, NULL);
1856 be_emit_cstring(env, "\txorpd ");
1857 ia32_emit_source_register(env, node, 0);
1858 be_emit_cstring(env, ", ");
1859 ia32_emit_source_register(env, node, 1);
1860 be_emit_finish_line_gas(env, NULL);
1862 be_emit_cstring(env, "\txorpd ");
1863 ia32_emit_source_register(env, node, 1);
1864 be_emit_cstring(env, ", ");
1865 ia32_emit_source_register(env, node, 0);
1866 be_emit_finish_line_gas(env, node);
1867 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1869 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1875 * Emits code for Constant loading.
1878 void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1879 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1881 if (imm_tp == ia32_ImmSymConst) {
1882 be_emit_cstring(env, "\tmovl ");
1883 ia32_emit_immediate(env, node);
1884 be_emit_cstring(env, ", ");
1885 ia32_emit_dest_register(env, node, 0);
1887 tarval *tv = get_ia32_Immop_tarval(node);
1888 assert(get_irn_mode(node) == mode_Iu);
1889 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1890 if (tarval_is_null(tv)) {
1891 if (env->isa->opt_arch == arch_pentium_4) {
1892 /* P4 prefers sub r, r, others xor r, r */
1893 be_emit_cstring(env, "\tsubl ");
1895 be_emit_cstring(env, "\txorl ");
1897 ia32_emit_dest_register(env, node, 0);
1898 be_emit_cstring(env, ", ");
1899 ia32_emit_dest_register(env, node, 0);
1901 be_emit_cstring(env, "\tmovl ");
1902 ia32_emit_immediate(env, node);
1903 be_emit_cstring(env, ", ");
1904 ia32_emit_dest_register(env, node, 0);
1907 be_emit_finish_line_gas(env, node);
1911 * Emits code to load the TLS base
1914 void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1915 be_emit_cstring(env, "\tmovl %gs:0, ");
1916 ia32_emit_dest_register(env, node, 0);
1917 be_emit_finish_line_gas(env, node);
1921 void emit_be_Return(ia32_emit_env_t *env, const ir_node *node)
1923 be_emit_cstring(env, "\tret");
1924 be_emit_finish_line_gas(env, node);
1928 void emit_Nothing(ia32_emit_env_t *env, const ir_node *node)
1935 /***********************************************************************************
1938 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1939 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1940 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1941 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1943 ***********************************************************************************/
1946 * Enters the emitter functions for handled nodes into the generic
1947 * pointer of an opcode.
1950 void ia32_register_emitters(void) {
1952 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1953 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1954 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1955 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1956 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1957 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1959 /* first clear the generic function pointer for all ops */
1960 clear_irp_opcodes_generic_func();
1962 /* register all emitter functions defined in spec */
1963 ia32_register_spec_emitters();
1965 /* other ia32 emitter functions */
1971 IA32_EMIT(SwitchJmp);
1974 IA32_EMIT(Conv_I2FP);
1975 IA32_EMIT(Conv_FP2I);
1976 IA32_EMIT(Conv_FP2FP);
1977 IA32_EMIT(Conv_I2I);
1978 IA32_EMIT(Conv_I2I8Bit);
1983 IA32_EMIT(xCmpCMov);
1984 IA32_EMIT(xCondJmp);
1985 IA32_EMIT2(fcomJmp, x87CondJmp);
1986 IA32_EMIT2(fcompJmp, x87CondJmp);
1987 IA32_EMIT2(fcomppJmp, x87CondJmp);
1988 IA32_EMIT2(fcomrJmp, x87CondJmp);
1989 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1990 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1992 /* benode emitter */
2018 static const char *last_name = NULL;
2019 static unsigned last_line = -1;
2020 static unsigned num = -1;
2023 * Emit the debug support for node node.
2026 void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
2027 dbg_info *db = get_irn_dbg_info(node);
2029 const char *fname = be_retrieve_dbg_info(db, &lineno);
2031 if (! env->cg->birg->main_env->options->stabs_debug_support)
2035 if (last_name != fname) {
2037 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
2040 if (last_line != lineno) {
2043 snprintf(name, sizeof(name), ".LM%u", ++num);
2045 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
2046 be_emit_string(env, name);
2047 be_emit_cstring(env, ":\n");
2048 be_emit_write_line(env);
2053 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
2056 * Emits code for a node.
2059 void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
2060 ir_op *op = get_irn_op(node);
2062 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2064 if (op->ops.generic) {
2065 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2066 ia32_emit_dbg(env, node);
2067 (*func) (env, node);
2069 emit_Nothing(env, node);
2070 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
2075 * Emits gas alignment directives
2078 void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
2079 be_emit_cstring(env, "\t.p2align ");
2080 be_emit_irprintf(env->emit, "%u,,%u\n", align, skip);
2081 be_emit_write_line(env);
2085 * Emits gas alignment directives for Functions depended on cpu architecture.
2088 void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
2090 unsigned maximum_skip;
2105 maximum_skip = (1 << align) - 1;
2106 ia32_emit_alignment(env, align, maximum_skip);
2110 * Emits gas alignment directives for Labels depended on cpu architecture.
2113 void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
2114 unsigned align; unsigned maximum_skip;
2129 maximum_skip = (1 << align) - 1;
2130 ia32_emit_alignment(env, align, maximum_skip);
2134 * Test wether a block should be aligned.
2135 * For cpus in the P4/Athlon class it is usefull to align jump labels to
2136 * 16 bytes. However we should only do that if the alignment nops before the
2137 * label aren't executed more often than we have jumps to the label.
2140 int should_align_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev) {
2141 static const double DELTA = .0001;
2142 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2144 double prev_freq = 0; /**< execfreq of the fallthrough block */
2145 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2146 cpu_support cpu = env->isa->opt_arch;
2149 if(exec_freq == NULL)
2151 if(cpu == arch_i386 || cpu == arch_i486)
2154 block_freq = get_block_execfreq(exec_freq, block);
2155 if(block_freq < DELTA)
2158 n_cfgpreds = get_Block_n_cfgpreds(block);
2159 for(i = 0; i < n_cfgpreds; ++i) {
2160 ir_node *pred = get_Block_cfgpred_block(block, i);
2161 double pred_freq = get_block_execfreq(exec_freq, pred);
2164 prev_freq += pred_freq;
2166 jmp_freq += pred_freq;
2170 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2173 jmp_freq /= prev_freq;
2177 case arch_athlon_64:
2179 return jmp_freq > 3;
2181 return jmp_freq > 2;
2186 void ia32_emit_block_header(ia32_emit_env_t *env, ir_node *block, ir_node *prev)
2191 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2194 n_cfgpreds = get_Block_n_cfgpreds(block);
2195 if (n_cfgpreds == 0) {
2197 } else if (n_cfgpreds == 1) {
2198 ir_node *pred = get_Block_cfgpred(block, 0);
2199 ir_node *pred_block = get_nodes_block(pred);
2201 /* we don't need labels for fallthrough blocks, however switch-jmps
2202 * are no fallthroughs */
2203 if(pred_block == prev &&
2204 !(is_Proj(pred) && is_ia32_SwitchJmp(get_Proj_pred(pred)))) {
2213 if (should_align_block(env, block, prev)) {
2215 ia32_emit_align_label(env, env->isa->opt_arch);
2219 ia32_emit_block_name(env, block);
2220 be_emit_char(env, ':');
2222 be_emit_pad_comment(env);
2223 be_emit_cstring(env, " /* preds:");
2225 /* emit list of pred blocks in comment */
2226 arity = get_irn_arity(block);
2227 for (i = 0; i < arity; ++i) {
2228 ir_node *predblock = get_Block_cfgpred_block(block, i);
2229 be_emit_irprintf(env->emit, " %d", get_irn_node_nr(predblock));
2232 be_emit_cstring(env, "\t/* ");
2233 ia32_emit_block_name(env, block);
2234 be_emit_cstring(env, ": ");
2236 if (exec_freq != NULL) {
2237 be_emit_irprintf(env->emit, " freq: %f",
2238 get_block_execfreq(exec_freq, block));
2240 be_emit_cstring(env, " */\n");
2241 be_emit_write_line(env);
2245 * Walks over the nodes in a block connected by scheduling edges
2246 * and emits code for each node.
2249 void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block)
2251 const ir_node *node;
2253 ia32_emit_block_header(env, block, last_block);
2255 /* emit the contents of the block */
2256 ia32_emit_dbg(env, block);
2257 sched_foreach(block, node) {
2258 ia32_emit_node(env, node);
2263 * Emits code for function start.
2266 void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2267 ir_entity *irg_ent = get_irg_entity(irg);
2268 const char *irg_name = get_entity_ld_name(irg_ent);
2269 cpu_support cpu = env->isa->opt_arch;
2270 const be_irg_t *birg = env->cg->birg;
2272 be_emit_write_line(env);
2273 be_gas_emit_switch_section(env->emit, GAS_SECTION_TEXT);
2274 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2275 ia32_emit_align_func(env, cpu);
2276 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2277 be_emit_cstring(env, ".global ");
2278 be_emit_string(env, irg_name);
2279 be_emit_char(env, '\n');
2280 be_emit_write_line(env);
2282 ia32_emit_function_object(env, irg_name);
2283 be_emit_string(env, irg_name);
2284 be_emit_cstring(env, ":\n");
2285 be_emit_write_line(env);
2289 * Emits code for function end
2292 void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2293 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2294 const be_irg_t *birg = env->cg->birg;
2296 ia32_emit_function_size(env, irg_name);
2297 be_dbg_method_end(birg->main_env->db_handle);
2298 be_emit_char(env, '\n');
2299 be_emit_write_line(env);
2304 * Sets labels for control flow nodes (jump target)
2307 void ia32_gen_labels(ir_node *block, void *data)
2310 int n = get_Block_n_cfgpreds(block);
2313 for (n--; n >= 0; n--) {
2314 pred = get_Block_cfgpred(block, n);
2315 set_irn_link(pred, block);
2320 * Emit an exception label if the current instruction can fail.
2322 void ia32_emit_exc_label(ia32_emit_env_t *env, const ir_node *node) {
2323 if (get_ia32_exc_label(node)) {
2324 be_emit_irprintf(env->emit, ".EXL%u\n", 0);
2325 be_emit_write_line(env);
2330 * Main driver. Emits the code for one routine.
2332 void ia32_gen_routine(ia32_code_gen_t *cg, ir_graph *irg) {
2333 ia32_emit_env_t env;
2335 ir_node *last_block = NULL;
2338 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2339 env.emit = &env.isa->emit;
2340 env.arch_env = cg->arch_env;
2343 ia32_register_emitters();
2345 ia32_emit_func_prolog(&env, irg);
2346 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2348 n = ARR_LEN(cg->blk_sched);
2349 for (i = 0; i < n;) {
2352 block = cg->blk_sched[i];
2354 next_bl = i < n ? cg->blk_sched[i] : NULL;
2356 /* set here the link. the emitter expects to find the next block here */
2357 set_irn_link(block, next_bl);
2358 ia32_gen_block(&env, block, last_block);
2362 ia32_emit_func_epilog(&env, irg);
2365 void ia32_init_emitter(void)
2367 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");