2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const arch_env_t *arch_env;
70 static const ia32_isa_t *isa;
71 static ia32_code_gen_t *cg;
74 * Returns the register at in position pos.
76 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
79 const arch_register_t *reg = NULL;
81 assert(get_irn_arity(irn) > pos && "Invalid IN position");
83 /* The out register of the operator at position pos is the
84 in register we need. */
85 op = get_irn_n(irn, pos);
87 reg = arch_get_irn_register(arch_env, op);
89 assert(reg && "no in register found");
91 if(reg == &ia32_gp_regs[REG_GP_NOREG])
92 panic("trying to emit noreg for %+F input %d", irn, pos);
94 /* in case of unknown register: just return a valid register */
95 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
96 const arch_register_req_t *req;
98 /* ask for the requirements */
99 req = arch_get_register_req(arch_env, irn, pos);
101 if (arch_register_req_is(req, limited)) {
102 /* in case of limited requirements: get the first allowed register */
103 unsigned idx = rbitset_next(req->limited, 0, 1);
104 reg = arch_register_for_index(req->cls, idx);
106 /* otherwise get first register in class */
107 reg = arch_register_for_index(req->cls, 0);
115 * Returns the register at out position pos.
117 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
120 const arch_register_t *reg = NULL;
122 /* 1st case: irn is not of mode_T, so it has only */
123 /* one OUT register -> good */
124 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
125 /* Proj with the corresponding projnum for the register */
127 if (get_irn_mode(irn) != mode_T) {
129 reg = arch_get_irn_register(arch_env, irn);
130 } else if (is_ia32_irn(irn)) {
131 reg = get_ia32_out_reg(irn, pos);
133 const ir_edge_t *edge;
135 foreach_out_edge(irn, edge) {
136 proj = get_edge_src_irn(edge);
137 assert(is_Proj(proj) && "non-Proj from mode_T node");
138 if (get_Proj_proj(proj) == pos) {
139 reg = arch_get_irn_register(arch_env, proj);
145 assert(reg && "no out register found");
150 * Add a number to a prefix. This number will not be used a second time.
152 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
154 static unsigned long id = 0;
155 snprintf(buf, buflen, "%s%lu", prefix, ++id);
159 /*************************************************************
161 * (_) | | / _| | | | |
162 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
163 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
164 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
165 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
168 *************************************************************/
170 static void emit_8bit_register(const arch_register_t *reg)
172 const char *reg_name = arch_register_get_name(reg);
175 be_emit_char(reg_name[1]);
179 static void emit_16bit_register(const arch_register_t *reg)
181 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
184 be_emit_string(reg_name);
187 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
189 const char *reg_name;
192 int size = get_mode_size_bits(mode);
194 emit_8bit_register(reg);
196 } else if(size == 16) {
197 emit_16bit_register(reg);
200 assert(mode_is_float(mode) || size == 32);
204 reg_name = arch_register_get_name(reg);
207 be_emit_string(reg_name);
210 void ia32_emit_source_register(const ir_node *node, int pos)
212 const arch_register_t *reg = get_in_reg(node, pos);
214 emit_register(reg, NULL);
217 static void emit_ia32_Immediate(const ir_node *node);
219 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
221 const arch_register_t *reg;
222 ir_node *in = get_irn_n(node, pos);
223 if(is_ia32_Immediate(in)) {
224 emit_ia32_Immediate(in);
228 reg = get_in_reg(node, pos);
229 emit_8bit_register(reg);
232 void ia32_emit_dest_register(const ir_node *node, int pos)
234 const arch_register_t *reg = get_out_reg(node, pos);
236 emit_register(reg, NULL);
239 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
241 const arch_register_t *reg = get_out_reg(node, pos);
243 emit_register(reg, mode_Bu);
246 void ia32_emit_x87_register(const ir_node *node, int pos)
248 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
252 be_emit_string(attr->x87[pos]->name);
255 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
257 if(mode_is_float(mode)) {
258 switch(get_mode_size_bits(mode)) {
259 case 32: be_emit_char('s'); return;
260 case 64: be_emit_char('l'); return;
262 case 96: be_emit_char('t'); return;
265 assert(mode_is_int(mode) || mode_is_reference(mode));
266 switch(get_mode_size_bits(mode)) {
267 case 64: be_emit_cstring("ll"); return;
268 /* gas docu says q is the suffix but gcc, objdump and icc use
270 case 32: be_emit_char('l'); return;
271 case 16: be_emit_char('w'); return;
272 case 8: be_emit_char('b'); return;
275 panic("Can't output mode_suffix for %+F\n", mode);
278 void ia32_emit_mode_suffix(const ir_node *node)
280 ir_mode *mode = get_ia32_ls_mode(node);
284 ia32_emit_mode_suffix_mode(mode);
287 void ia32_emit_x87_mode_suffix(const ir_node *node)
289 ir_mode *mode = get_ia32_ls_mode(node);
290 assert(mode != NULL);
291 /* we only need to emit the mode on address mode */
292 if(get_ia32_op_type(node) != ia32_Normal)
293 ia32_emit_mode_suffix_mode(mode);
297 char get_xmm_mode_suffix(ir_mode *mode)
299 assert(mode_is_float(mode));
300 switch(get_mode_size_bits(mode)) {
311 void ia32_emit_xmm_mode_suffix(const ir_node *node)
313 ir_mode *mode = get_ia32_ls_mode(node);
314 assert(mode != NULL);
316 be_emit_char(get_xmm_mode_suffix(mode));
319 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
321 ir_mode *mode = get_ia32_ls_mode(node);
322 assert(mode != NULL);
323 be_emit_char(get_xmm_mode_suffix(mode));
326 void ia32_emit_extend_suffix(const ir_mode *mode)
328 if(get_mode_size_bits(mode) == 32)
330 if(mode_is_signed(mode)) {
338 void ia32_emit_function_object(const char *name)
340 switch (be_gas_flavour) {
341 case GAS_FLAVOUR_NORMAL:
342 be_emit_cstring("\t.type\t");
343 be_emit_string(name);
344 be_emit_cstring(", @function\n");
345 be_emit_write_line();
347 case GAS_FLAVOUR_MINGW:
348 be_emit_cstring("\t.def\t");
349 be_emit_string(name);
350 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
351 be_emit_write_line();
359 void ia32_emit_function_size(const char *name)
361 switch (be_gas_flavour) {
362 case GAS_FLAVOUR_NORMAL:
363 be_emit_cstring("\t.size\t");
364 be_emit_string(name);
365 be_emit_cstring(", .-");
366 be_emit_string(name);
368 be_emit_write_line();
376 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
378 ir_node *in = get_irn_n(node, pos);
379 if(is_ia32_Immediate(in)) {
380 emit_ia32_Immediate(in);
382 const ir_mode *mode = get_ia32_ls_mode(node);
383 const arch_register_t *reg = get_in_reg(node, pos);
384 emit_register(reg, mode);
389 * Emits registers and/or address mode of a binary operation.
391 void ia32_emit_binop(const ir_node *node) {
392 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
393 const ir_mode *mode = get_ia32_ls_mode(node);
394 const arch_register_t *reg_left;
396 switch(get_ia32_op_type(node)) {
398 reg_left = get_in_reg(node, n_ia32_binary_left);
399 if(is_ia32_Immediate(right_op)) {
400 emit_ia32_Immediate(right_op);
401 be_emit_cstring(", ");
402 emit_register(reg_left, mode);
405 const arch_register_t *reg_right
406 = get_in_reg(node, n_ia32_binary_right);
407 emit_register(reg_right, mode);
408 be_emit_cstring(", ");
409 emit_register(reg_left, mode);
413 if(is_ia32_Immediate(right_op)) {
414 emit_ia32_Immediate(right_op);
415 be_emit_cstring(", ");
418 reg_left = get_in_reg(node, n_ia32_binary_left);
420 be_emit_cstring(", ");
421 emit_register(reg_left, mode);
425 panic("DestMode can't be output by %%binop anymore");
428 assert(0 && "unsupported op type");
433 * Emits registers and/or address mode of a binary operation.
435 void ia32_emit_x87_binop(const ir_node *node) {
436 switch(get_ia32_op_type(node)) {
439 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
440 const arch_register_t *in1 = x87_attr->x87[0];
441 const arch_register_t *in2 = x87_attr->x87[1];
442 const arch_register_t *out = x87_attr->x87[2];
443 const arch_register_t *in;
445 in = out ? ((out == in2) ? in1 : in2) : in2;
446 out = out ? out : in1;
449 be_emit_string(arch_register_get_name(in));
450 be_emit_cstring(", %");
451 be_emit_string(arch_register_get_name(out));
459 assert(0 && "unsupported op type");
463 void ia32_emit_am_or_dest_register(const ir_node *node,
465 if(get_ia32_op_type(node) == ia32_Normal) {
466 ia32_emit_dest_register(node, pos);
468 assert(get_ia32_op_type(node) == ia32_AddrModeD);
474 * Emits registers and/or address mode of a unary operation.
476 void ia32_emit_unop(const ir_node *node, int pos) {
479 switch(get_ia32_op_type(node)) {
481 op = get_irn_n(node, pos);
482 if (is_ia32_Immediate(op)) {
483 emit_ia32_Immediate(op);
485 ia32_emit_source_register(node, pos);
493 assert(0 && "unsupported op type");
498 * Emits address mode.
500 void ia32_emit_am(const ir_node *node) {
501 ir_entity *ent = get_ia32_am_sc(node);
502 int offs = get_ia32_am_offs_int(node);
503 ir_node *base = get_irn_n(node, 0);
504 int has_base = !is_ia32_NoReg_GP(base);
505 ir_node *index = get_irn_n(node, 1);
506 int has_index = !is_ia32_NoReg_GP(index);
508 /* just to be sure... */
509 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
515 set_entity_backend_marked(ent, 1);
516 id = get_entity_ld_ident(ent);
517 if (is_ia32_am_sc_sign(node))
521 if(get_entity_owner(ent) == get_tls_type()) {
522 if (get_entity_visibility(ent) == visibility_external_allocated) {
523 be_emit_cstring("@INDNTPOFF");
525 be_emit_cstring("@NTPOFF");
532 be_emit_irprintf("%+d", offs);
534 be_emit_irprintf("%d", offs);
538 if (has_base || has_index) {
543 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
544 emit_register(reg, NULL);
547 /* emit index + scale */
549 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
552 emit_register(reg, NULL);
554 scale = get_ia32_am_scale(node);
556 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
562 /* special case if nothing is set */
563 if(ent == NULL && offs == 0 && !has_base && !has_index) {
568 static void emit_ia32_IMul(const ir_node *node)
570 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
571 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
573 be_emit_cstring("\timul");
574 ia32_emit_mode_suffix(node);
577 ia32_emit_binop(node);
579 /* do we need the 3-address form? */
580 if(is_ia32_NoReg_GP(left) ||
581 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
582 be_emit_cstring(", ");
583 emit_register(out_reg, get_ia32_ls_mode(node));
585 be_emit_finish_line_gas(node);
588 /*************************************************
591 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
592 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
593 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
594 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
596 *************************************************/
599 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
602 * coding of conditions
604 struct cmp2conditon_t {
610 * positive conditions for signed compares
612 static const struct cmp2conditon_t cmp2condition_s[] = {
613 { NULL, pn_Cmp_False }, /* always false */
614 { "e", pn_Cmp_Eq }, /* == */
615 { "l", pn_Cmp_Lt }, /* < */
616 { "le", pn_Cmp_Le }, /* <= */
617 { "g", pn_Cmp_Gt }, /* > */
618 { "ge", pn_Cmp_Ge }, /* >= */
619 { "ne", pn_Cmp_Lg }, /* != */
620 { NULL, pn_Cmp_Leg}, /* always true */
624 * positive conditions for unsigned compares
626 static const struct cmp2conditon_t cmp2condition_u[] = {
627 { NULL, pn_Cmp_False }, /* always false */
628 { "e", pn_Cmp_Eq }, /* == */
629 { "b", pn_Cmp_Lt }, /* < */
630 { "be", pn_Cmp_Le }, /* <= */
631 { "a", pn_Cmp_Gt }, /* > */
632 { "ae", pn_Cmp_Ge }, /* >= */
633 { "ne", pn_Cmp_Lg }, /* != */
634 { NULL, pn_Cmp_Leg }, /* always true */
638 ia32_pn_Cmp_unsigned = 0x1000,
639 ia32_pn_Cmp_float = 0x2000,
643 * walks up a tree of copies/perms/spills/reloads to find the original value
644 * that is moved around
646 static ir_node *find_original_value(ir_node *node)
648 inc_irg_visited(current_ir_graph);
650 mark_irn_visited(node);
651 if(be_is_Copy(node)) {
652 node = be_get_Copy_op(node);
653 } else if(be_is_CopyKeep(node)) {
654 node = be_get_CopyKeep_op(node);
655 } else if(is_Proj(node)) {
656 ir_node *pred = get_Proj_pred(node);
657 if(be_is_Perm(pred)) {
658 node = get_irn_n(pred, get_Proj_proj(node));
659 } else if(be_is_MemPerm(pred)) {
660 node = get_irn_n(pred, get_Proj_proj(node) + 1);
661 } else if(is_ia32_Load(pred)) {
662 node = get_irn_n(pred, n_ia32_Load_mem);
666 } else if(is_ia32_Store(node)) {
667 node = get_irn_n(node, n_ia32_Store_val);
668 } else if(is_Phi(node)) {
670 arity = get_irn_arity(node);
671 for(i = 0; i < arity; ++i) {
672 ir_node *in = get_irn_n(node, i);
685 static int determine_final_pnc(const ir_node *node, int flags_pos,
688 ir_node *flags = get_irn_n(node, flags_pos);
689 const ia32_attr_t *flags_attr;
690 flags = skip_Proj(flags);
692 if(is_ia32_Sahf(flags)) {
693 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
694 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
695 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
696 cmp = find_original_value(cmp);
697 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
698 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
701 flags_attr = get_ia32_attr_const(cmp);
702 if(flags_attr->data.ins_permuted)
703 pnc = get_mirrored_pnc(pnc);
704 pnc |= ia32_pn_Cmp_float;
705 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
706 || is_ia32_Fucompi(flags)) {
707 flags_attr = get_ia32_attr_const(flags);
709 if(flags_attr->data.ins_permuted)
710 pnc = get_mirrored_pnc(pnc);
711 pnc |= ia32_pn_Cmp_float;
714 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
715 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
717 flags_attr = get_ia32_attr_const(flags);
719 if(flags_attr->data.ins_permuted)
720 pnc = get_mirrored_pnc(pnc);
721 if(flags_attr->data.cmp_unsigned)
722 pnc |= ia32_pn_Cmp_unsigned;
728 static void ia32_emit_cmp_suffix(int pnc)
732 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
734 assert(cmp2condition_u[pnc].num == pnc);
735 str = cmp2condition_u[pnc].name;
738 assert(cmp2condition_s[pnc].num == pnc);
739 str = cmp2condition_s[pnc].name;
745 void ia32_emit_cmp_suffix_node(const ir_node *node,
748 const ia32_attr_t *attr = get_ia32_attr_const(node);
750 pn_Cmp pnc = get_ia32_condcode(node);
752 pnc = determine_final_pnc(node, flags_pos, pnc);
753 if(attr->data.ins_permuted) {
754 if(pnc & ia32_pn_Cmp_float) {
755 pnc = get_negated_pnc(pnc, mode_F);
757 pnc = get_negated_pnc(pnc, mode_Iu);
761 ia32_emit_cmp_suffix(pnc);
765 * Returns the target block for a control flow node.
768 ir_node *get_cfop_target_block(const ir_node *irn) {
769 return get_irn_link(irn);
773 * Emits a block label for the given block.
776 void ia32_emit_block_name(const ir_node *block)
778 if (has_Block_label(block)) {
779 be_emit_string(be_gas_label_prefix());
780 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
782 be_emit_cstring(BLOCK_PREFIX);
783 be_emit_irprintf("%d", get_irn_node_nr(block));
788 * Emits the target label for a control flow node.
790 static void ia32_emit_cfop_target(const ir_node *node)
792 ir_node *block = get_cfop_target_block(node);
794 ia32_emit_block_name(block);
797 /** Return the next block in Block schedule */
798 static ir_node *next_blk_sched(const ir_node *block)
800 return get_irn_link(block);
804 * Returns the Proj with projection number proj and NOT mode_M
806 static ir_node *get_proj(const ir_node *node, long proj) {
807 const ir_edge_t *edge;
810 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
812 foreach_out_edge(node, edge) {
813 src = get_edge_src_irn(edge);
815 assert(is_Proj(src) && "Proj expected");
816 if (get_irn_mode(src) == mode_M)
819 if (get_Proj_proj(src) == proj)
826 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
828 static void emit_ia32_Jcc(const ir_node *node)
830 const ir_node *proj_true;
831 const ir_node *proj_false;
832 const ir_node *block;
833 const ir_node *next_block;
834 pn_Cmp pnc = get_ia32_condcode(node);
836 pnc = determine_final_pnc(node, 0, pnc);
839 proj_true = get_proj(node, pn_ia32_Jcc_true);
840 assert(proj_true && "Jcc without true Proj");
842 proj_false = get_proj(node, pn_ia32_Jcc_false);
843 assert(proj_false && "Jcc without false Proj");
845 block = get_nodes_block(node);
846 next_block = next_blk_sched(block);
848 if (get_cfop_target_block(proj_true) == next_block) {
849 /* exchange both proj's so the second one can be omitted */
850 const ir_node *t = proj_true;
852 proj_true = proj_false;
854 if(pnc & ia32_pn_Cmp_float) {
855 pnc = get_negated_pnc(pnc, mode_F);
857 pnc = get_negated_pnc(pnc, mode_Iu);
861 if (pnc & ia32_pn_Cmp_float) {
862 /* Some floating point comparisons require a test of the parity flag,
863 * which indicates that the result is unordered */
866 be_emit_cstring("\tjp ");
867 ia32_emit_cfop_target(proj_true);
868 be_emit_finish_line_gas(proj_true);
872 be_emit_cstring("\tjnp ");
873 ia32_emit_cfop_target(proj_true);
874 be_emit_finish_line_gas(proj_true);
880 be_emit_cstring("\tjp ");
881 ia32_emit_cfop_target(proj_false);
882 be_emit_finish_line_gas(proj_false);
888 be_emit_cstring("\tjp ");
889 ia32_emit_cfop_target(proj_true);
890 be_emit_finish_line_gas(proj_true);
898 be_emit_cstring("\tj");
899 ia32_emit_cmp_suffix(pnc);
901 ia32_emit_cfop_target(proj_true);
902 be_emit_finish_line_gas(proj_true);
905 /* the second Proj might be a fallthrough */
906 if (get_cfop_target_block(proj_false) != next_block) {
907 be_emit_cstring("\tjmp ");
908 ia32_emit_cfop_target(proj_false);
909 be_emit_finish_line_gas(proj_false);
911 be_emit_cstring("\t/* fallthrough to ");
912 ia32_emit_cfop_target(proj_false);
913 be_emit_cstring(" */");
914 be_emit_finish_line_gas(proj_false);
918 static void emit_ia32_CMov(const ir_node *node)
920 const ia32_attr_t *attr = get_ia32_attr_const(node);
921 int ins_permuted = attr->data.ins_permuted;
922 const arch_register_t *out = arch_get_irn_register(arch_env, node);
923 pn_Cmp pnc = get_ia32_condcode(node);
924 const arch_register_t *in_true;
925 const arch_register_t *in_false;
927 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
929 in_true = arch_get_irn_register(arch_env,
930 get_irn_n(node, n_ia32_CMov_val_true));
931 in_false = arch_get_irn_register(arch_env,
932 get_irn_n(node, n_ia32_CMov_val_false));
934 /* should be same constraint fullfilled? */
935 if(out == in_false) {
936 /* yes -> nothing to do */
937 } else if(out == in_true) {
938 const arch_register_t *tmp;
940 assert(get_ia32_op_type(node) == ia32_Normal);
942 ins_permuted = !ins_permuted;
949 be_emit_cstring("\tmovl ");
950 emit_register(in_false, NULL);
951 be_emit_cstring(", ");
952 emit_register(out, NULL);
953 be_emit_finish_line_gas(node);
957 if(pnc & ia32_pn_Cmp_float) {
958 pnc = get_negated_pnc(pnc, mode_F);
960 pnc = get_negated_pnc(pnc, mode_Iu);
964 /* TODO: handling of Nans isn't correct yet */
966 be_emit_cstring("\tcmov");
967 ia32_emit_cmp_suffix(pnc);
969 if(get_ia32_op_type(node) == ia32_AddrModeS) {
972 emit_register(in_true, get_ia32_ls_mode(node));
974 be_emit_cstring(", ");
975 emit_register(out, get_ia32_ls_mode(node));
976 be_emit_finish_line_gas(node);
979 /*********************************************************
982 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
983 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
984 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
985 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
988 *********************************************************/
990 /* jump table entry (target and corresponding number) */
991 typedef struct _branch_t {
996 /* jump table for switch generation */
997 typedef struct _jmp_tbl_t {
998 ir_node *defProj; /**< default target */
999 long min_value; /**< smallest switch case */
1000 long max_value; /**< largest switch case */
1001 long num_branches; /**< number of jumps */
1002 char *label; /**< label of the jump table */
1003 branch_t *branches; /**< jump array */
1007 * Compare two variables of type branch_t. Used to sort all switch cases
1010 int ia32_cmp_branch_t(const void *a, const void *b) {
1011 branch_t *b1 = (branch_t *)a;
1012 branch_t *b2 = (branch_t *)b;
1014 if (b1->value <= b2->value)
1021 * Emits code for a SwitchJmp (creates a jump table if
1022 * possible otherwise a cmp-jmp cascade). Port from
1026 void emit_ia32_SwitchJmp(const ir_node *node) {
1027 unsigned long interval;
1032 const ir_edge_t *edge;
1034 /* fill the table structure */
1035 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1036 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1038 tbl.num_branches = get_irn_n_edges(node);
1039 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1040 tbl.min_value = INT_MAX;
1041 tbl.max_value = INT_MIN;
1044 /* go over all proj's and collect them */
1045 foreach_out_edge(node, edge) {
1046 proj = get_edge_src_irn(edge);
1047 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1049 pnc = get_Proj_proj(proj);
1051 /* create branch entry */
1052 tbl.branches[i].target = proj;
1053 tbl.branches[i].value = pnc;
1055 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1056 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1058 /* check for default proj */
1059 if (pnc == get_ia32_condcode(node)) {
1060 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1067 /* sort the branches by their number */
1068 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1070 /* two-complement's magic make this work without overflow */
1071 interval = tbl.max_value - tbl.min_value;
1073 /* emit the table */
1074 be_emit_cstring("\tcmpl $");
1075 be_emit_irprintf("%u, ", interval);
1076 ia32_emit_source_register(node, 0);
1077 be_emit_finish_line_gas(node);
1079 be_emit_cstring("\tja ");
1080 ia32_emit_cfop_target(tbl.defProj);
1081 be_emit_finish_line_gas(node);
1083 if (tbl.num_branches > 1) {
1085 be_emit_cstring("\tjmp *");
1086 be_emit_string(tbl.label);
1087 be_emit_cstring("(,");
1088 ia32_emit_source_register(node, 0);
1089 be_emit_cstring(",4)");
1090 be_emit_finish_line_gas(node);
1092 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1093 be_emit_cstring("\t.align 4\n");
1094 be_emit_write_line();
1096 be_emit_string(tbl.label);
1097 be_emit_cstring(":\n");
1098 be_emit_write_line();
1100 be_emit_cstring(".long ");
1101 ia32_emit_cfop_target(tbl.branches[0].target);
1102 be_emit_finish_line_gas(NULL);
1104 last_value = tbl.branches[0].value;
1105 for (i = 1; i < tbl.num_branches; ++i) {
1106 while (++last_value < tbl.branches[i].value) {
1107 be_emit_cstring(".long ");
1108 ia32_emit_cfop_target(tbl.defProj);
1109 be_emit_finish_line_gas(NULL);
1111 be_emit_cstring(".long ");
1112 ia32_emit_cfop_target(tbl.branches[i].target);
1113 be_emit_finish_line_gas(NULL);
1115 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1117 /* one jump is enough */
1118 be_emit_cstring("\tjmp ");
1119 ia32_emit_cfop_target(tbl.branches[0].target);
1120 be_emit_finish_line_gas(node);
1130 * Emits code for a unconditional jump.
1132 static void emit_Jmp(const ir_node *node)
1134 ir_node *block, *next_block;
1136 /* for now, the code works for scheduled and non-schedules blocks */
1137 block = get_nodes_block(node);
1139 /* we have a block schedule */
1140 next_block = next_blk_sched(block);
1141 if (get_cfop_target_block(node) != next_block) {
1142 be_emit_cstring("\tjmp ");
1143 ia32_emit_cfop_target(node);
1145 be_emit_cstring("\t/* fallthrough to ");
1146 ia32_emit_cfop_target(node);
1147 be_emit_cstring(" */");
1149 be_emit_finish_line_gas(node);
1152 static void emit_ia32_Immediate(const ir_node *node)
1154 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1157 if(attr->symconst != NULL) {
1158 ident *id = get_entity_ld_ident(attr->symconst);
1164 if(attr->symconst == NULL || attr->offset != 0) {
1165 if(attr->symconst != NULL) {
1166 be_emit_irprintf("%+d", attr->offset);
1168 be_emit_irprintf("0x%X", attr->offset);
1174 * Emit an inline assembler operand.
1176 * @param node the ia32_ASM node
1177 * @param s points to the operand (a %c)
1179 * @return pointer to the first char in s NOT in the current operand
1181 static const char* emit_asm_operand(const ir_node *node, const char *s)
1183 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1184 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1186 const arch_register_t *reg;
1187 const ia32_asm_reg_t *asm_regs = attr->register_map;
1188 const ia32_asm_reg_t *asm_reg;
1189 const char *reg_name;
1198 /* parse modifiers */
1201 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1225 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1226 "'%c' for asm op\n", node, c);
1232 sscanf(s, "%d%n", &num, &p);
1234 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1241 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1242 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1243 "input/output (%+F)\n", node);
1246 asm_reg = & asm_regs[num];
1247 assert(asm_reg->valid);
1250 if(asm_reg->use_input == 0) {
1251 reg = get_out_reg(node, asm_reg->inout_pos);
1253 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1255 /* might be an immediate value */
1256 if(is_ia32_Immediate(pred)) {
1257 emit_ia32_Immediate(pred);
1260 reg = get_in_reg(node, asm_reg->inout_pos);
1263 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1264 "(%+F)\n", num, node);
1268 if(asm_reg->memory) {
1277 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1280 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1283 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1286 panic("Invalid asm op modifier");
1288 be_emit_string(reg_name);
1290 emit_register(reg, asm_reg->mode);
1293 if(asm_reg->memory) {
1301 * Emits code for an ASM pseudo op.
1303 static void emit_ia32_Asm(const ir_node *node)
1305 const void *gen_attr = get_irn_generic_attr_const(node);
1306 const ia32_asm_attr_t *attr
1307 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1308 ident *asm_text = attr->asm_text;
1309 const char *s = get_id_str(asm_text);
1311 be_emit_cstring("# Begin ASM \t");
1312 be_emit_finish_line_gas(node);
1319 s = emit_asm_operand(node, s);
1328 be_emit_write_line();
1330 be_emit_cstring("# End ASM\n");
1331 be_emit_write_line();
1334 /**********************************
1337 * | | ___ _ __ _ _| |_) |
1338 * | | / _ \| '_ \| | | | _ <
1339 * | |___| (_) | |_) | |_| | |_) |
1340 * \_____\___/| .__/ \__, |____/
1343 **********************************/
1346 * Emit movsb/w instructions to make mov count divideable by 4
1348 static void emit_CopyB_prolog(unsigned size) {
1349 be_emit_cstring("\tcld");
1350 be_emit_finish_line_gas(NULL);
1354 be_emit_cstring("\tmovsb");
1355 be_emit_finish_line_gas(NULL);
1358 be_emit_cstring("\tmovsw");
1359 be_emit_finish_line_gas(NULL);
1362 be_emit_cstring("\tmovsb");
1363 be_emit_finish_line_gas(NULL);
1364 be_emit_cstring("\tmovsw");
1365 be_emit_finish_line_gas(NULL);
1371 * Emit rep movsd instruction for memcopy.
1373 static void emit_ia32_CopyB(const ir_node *node)
1375 unsigned size = get_ia32_copyb_size(node);
1377 emit_CopyB_prolog(size);
1379 be_emit_cstring("\trep movsd");
1380 be_emit_finish_line_gas(node);
1384 * Emits unrolled memcopy.
1386 static void emit_ia32_CopyB_i(const ir_node *node)
1388 unsigned size = get_ia32_copyb_size(node);
1390 emit_CopyB_prolog(size & 0x3);
1394 be_emit_cstring("\tmovsd");
1395 be_emit_finish_line_gas(NULL);
1401 /***************************
1405 * | | / _ \| '_ \ \ / /
1406 * | |___| (_) | | | \ V /
1407 * \_____\___/|_| |_|\_/
1409 ***************************/
1412 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1414 static void emit_ia32_Conv_with_FP(const ir_node *node)
1416 ir_mode *ls_mode = get_ia32_ls_mode(node);
1417 int ls_bits = get_mode_size_bits(ls_mode);
1419 be_emit_cstring("\tcvt");
1421 if(is_ia32_Conv_I2FP(node)) {
1423 be_emit_cstring("si2ss");
1425 be_emit_cstring("si2sd");
1427 } else if(is_ia32_Conv_FP2I(node)) {
1429 be_emit_cstring("ss2si");
1431 be_emit_cstring("sd2si");
1434 assert(is_ia32_Conv_FP2FP(node));
1436 be_emit_cstring("sd2ss");
1438 be_emit_cstring("ss2sd");
1443 switch(get_ia32_op_type(node)) {
1445 ia32_emit_source_register(node, n_ia32_unary_op);
1447 case ia32_AddrModeS:
1451 assert(0 && "unsupported op type for Conv");
1453 be_emit_cstring(", ");
1454 ia32_emit_dest_register(node, 0);
1455 be_emit_finish_line_gas(node);
1458 static void emit_ia32_Conv_I2FP(const ir_node *node)
1460 emit_ia32_Conv_with_FP(node);
1463 static void emit_ia32_Conv_FP2I(const ir_node *node)
1465 emit_ia32_Conv_with_FP(node);
1468 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1470 emit_ia32_Conv_with_FP(node);
1474 * Emits code for an Int conversion.
1476 static void emit_ia32_Conv_I2I(const ir_node *node)
1478 const char *sign_suffix;
1479 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1480 int smaller_bits = get_mode_size_bits(smaller_mode);
1482 const arch_register_t *in_reg, *out_reg;
1484 assert(!mode_is_float(smaller_mode));
1485 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1487 signed_mode = mode_is_signed(smaller_mode);
1488 if(smaller_bits == 32) {
1489 // this should not happen as it's no convert
1493 sign_suffix = signed_mode ? "s" : "z";
1496 out_reg = get_out_reg(node, 0);
1498 switch(get_ia32_op_type(node)) {
1500 in_reg = get_in_reg(node, n_ia32_unary_op);
1502 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1503 out_reg == &ia32_gp_regs[REG_EAX] &&
1507 /* argument and result are both in EAX and */
1508 /* signedness is ok: -> use the smaller cwtl opcode */
1509 be_emit_cstring("\tcwtl");
1511 be_emit_cstring("\tmov");
1512 be_emit_string(sign_suffix);
1513 ia32_emit_mode_suffix_mode(smaller_mode);
1514 be_emit_cstring("l ");
1515 emit_register(in_reg, smaller_mode);
1516 be_emit_cstring(", ");
1517 emit_register(out_reg, NULL);
1520 case ia32_AddrModeS: {
1521 be_emit_cstring("\tmov");
1522 be_emit_string(sign_suffix);
1523 ia32_emit_mode_suffix_mode(smaller_mode);
1524 be_emit_cstring("l ");
1526 be_emit_cstring(", ");
1527 emit_register(out_reg, NULL);
1531 assert(0 && "unsupported op type for Conv");
1533 be_emit_finish_line_gas(node);
1537 /*******************************************
1540 * | |__ ___ _ __ ___ __| | ___ ___
1541 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1542 * | |_) | __/ | | | (_) | (_| | __/\__ \
1543 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1545 *******************************************/
1548 * Emits a backend call
1550 static void emit_be_Call(const ir_node *node)
1552 ir_entity *ent = be_Call_get_entity(node);
1554 be_emit_cstring("\tcall ");
1556 set_entity_backend_marked(ent, 1);
1557 be_emit_string(get_entity_ld_name(ent));
1559 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1561 emit_register(reg, NULL);
1563 be_emit_finish_line_gas(node);
1567 * Emits code to increase stack pointer.
1569 static void emit_be_IncSP(const ir_node *node)
1571 int offs = be_get_IncSP_offset(node);
1572 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1578 be_emit_cstring("\tsubl $");
1579 be_emit_irprintf("%u, ", offs);
1580 emit_register(reg, NULL);
1582 be_emit_cstring("\taddl $");
1583 be_emit_irprintf("%u, ", -offs);
1584 emit_register(reg, NULL);
1586 be_emit_finish_line_gas(node);
1590 * Emits code for Copy/CopyKeep.
1592 static void Copy_emitter(const ir_node *node, const ir_node *op)
1594 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1595 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1601 if(is_unknown_reg(in))
1603 /* copies of vf nodes aren't real... */
1604 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1607 mode = get_irn_mode(node);
1608 if (mode == mode_E) {
1609 be_emit_cstring("\tmovsd ");
1610 emit_register(in, NULL);
1611 be_emit_cstring(", ");
1612 emit_register(out, NULL);
1614 be_emit_cstring("\tmovl ");
1615 emit_register(in, NULL);
1616 be_emit_cstring(", ");
1617 emit_register(out, NULL);
1619 be_emit_finish_line_gas(node);
1622 static void emit_be_Copy(const ir_node *node)
1624 Copy_emitter(node, be_get_Copy_op(node));
1627 static void emit_be_CopyKeep(const ir_node *node)
1629 Copy_emitter(node, be_get_CopyKeep_op(node));
1633 * Emits code for exchange.
1635 static void emit_be_Perm(const ir_node *node)
1637 const arch_register_t *in0, *in1;
1638 const arch_register_class_t *cls0, *cls1;
1640 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1641 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1643 cls0 = arch_register_get_class(in0);
1644 cls1 = arch_register_get_class(in1);
1646 assert(cls0 == cls1 && "Register class mismatch at Perm");
1648 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1649 be_emit_cstring("\txchg ");
1650 emit_register(in1, NULL);
1651 be_emit_cstring(", ");
1652 emit_register(in0, NULL);
1653 be_emit_finish_line_gas(node);
1654 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1655 be_emit_cstring("\txorpd ");
1656 emit_register(in1, NULL);
1657 be_emit_cstring(", ");
1658 emit_register(in0, NULL);
1659 be_emit_finish_line_gas(NULL);
1661 be_emit_cstring("\txorpd ");
1662 emit_register(in0, NULL);
1663 be_emit_cstring(", ");
1664 emit_register(in1, NULL);
1665 be_emit_finish_line_gas(NULL);
1667 be_emit_cstring("\txorpd ");
1668 emit_register(in1, NULL);
1669 be_emit_cstring(", ");
1670 emit_register(in0, NULL);
1671 be_emit_finish_line_gas(node);
1672 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1674 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1677 panic("unexpected register class in be_Perm (%+F)\n", node);
1682 * Emits code for Constant loading.
1684 static void emit_ia32_Const(const ir_node *node)
1686 be_emit_cstring("\tmovl ");
1687 emit_ia32_Immediate(node);
1688 be_emit_cstring(", ");
1689 ia32_emit_dest_register(node, 0);
1691 be_emit_finish_line_gas(node);
1695 * Emits code to load the TLS base
1697 static void emit_ia32_LdTls(const ir_node *node)
1699 be_emit_cstring("\tmovl %gs:0, ");
1700 ia32_emit_dest_register(node, 0);
1701 be_emit_finish_line_gas(node);
1704 /* helper function for emit_ia32_Minus64Bit */
1705 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1707 be_emit_cstring("\tmovl ");
1708 emit_register(src, NULL);
1709 be_emit_cstring(", ");
1710 emit_register(dst, NULL);
1711 be_emit_finish_line_gas(node);
1714 /* helper function for emit_ia32_Minus64Bit */
1715 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1717 be_emit_cstring("\tnegl ");
1718 emit_register(reg, NULL);
1719 be_emit_finish_line_gas(node);
1722 /* helper function for emit_ia32_Minus64Bit */
1723 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1725 be_emit_cstring("\tsbbl $0, ");
1726 emit_register(reg, NULL);
1727 be_emit_finish_line_gas(node);
1730 /* helper function for emit_ia32_Minus64Bit */
1731 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1733 be_emit_cstring("\tsbbl ");
1734 emit_register(src, NULL);
1735 be_emit_cstring(", ");
1736 emit_register(dst, NULL);
1737 be_emit_finish_line_gas(node);
1740 /* helper function for emit_ia32_Minus64Bit */
1741 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1743 be_emit_cstring("\txchgl ");
1744 emit_register(src, NULL);
1745 be_emit_cstring(", ");
1746 emit_register(dst, NULL);
1747 be_emit_finish_line_gas(node);
1750 /* helper function for emit_ia32_Minus64Bit */
1751 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1753 be_emit_cstring("\txorl ");
1754 emit_register(reg, NULL);
1755 be_emit_cstring(", ");
1756 emit_register(reg, NULL);
1757 be_emit_finish_line_gas(node);
1760 static void emit_ia32_Minus64Bit(const ir_node *node)
1762 const arch_register_t *in_lo = get_in_reg(node, 0);
1763 const arch_register_t *in_hi = get_in_reg(node, 1);
1764 const arch_register_t *out_lo = get_out_reg(node, 0);
1765 const arch_register_t *out_hi = get_out_reg(node, 1);
1767 if (out_lo == in_lo) {
1768 if (out_hi != in_hi) {
1769 /* a -> a, b -> d */
1772 /* a -> a, b -> b */
1775 } else if (out_lo == in_hi) {
1776 if (out_hi == in_lo) {
1777 /* a -> b, b -> a */
1778 emit_xchg(node, in_lo, in_hi);
1781 /* a -> b, b -> d */
1782 emit_mov(node, in_hi, out_hi);
1783 emit_mov(node, in_lo, out_lo);
1787 if (out_hi == in_lo) {
1788 /* a -> c, b -> a */
1789 emit_mov(node, in_lo, out_lo);
1791 } else if (out_hi == in_hi) {
1792 /* a -> c, b -> b */
1793 emit_mov(node, in_lo, out_lo);
1796 /* a -> c, b -> d */
1797 emit_mov(node, in_lo, out_lo);
1803 emit_neg( node, out_hi);
1804 emit_neg( node, out_lo);
1805 emit_sbb0(node, out_hi);
1809 emit_zero(node, out_hi);
1810 emit_neg( node, out_lo);
1811 emit_sbb( node, in_hi, out_hi);
1814 static void emit_be_Return(const ir_node *node)
1817 be_emit_cstring("\tret");
1819 pop = be_Return_get_pop(node);
1821 be_emit_irprintf(" $%d", pop);
1823 be_emit_finish_line_gas(node);
1826 static void emit_Nothing(const ir_node *node)
1832 /***********************************************************************************
1835 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1836 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1837 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1838 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1840 ***********************************************************************************/
1843 * Enters the emitter functions for handled nodes into the generic
1844 * pointer of an opcode.
1847 void ia32_register_emitters(void) {
1849 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1850 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1851 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1852 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1853 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1854 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1856 /* first clear the generic function pointer for all ops */
1857 clear_irp_opcodes_generic_func();
1859 /* register all emitter functions defined in spec */
1860 ia32_register_spec_emitters();
1862 /* other ia32 emitter functions */
1866 IA32_EMIT(SwitchJmp);
1869 IA32_EMIT(Conv_I2FP);
1870 IA32_EMIT(Conv_FP2I);
1871 IA32_EMIT(Conv_FP2FP);
1872 IA32_EMIT(Conv_I2I);
1873 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1876 IA32_EMIT(Minus64Bit);
1879 /* benode emitter */
1904 static const char *last_name = NULL;
1905 static unsigned last_line = -1;
1906 static unsigned num = -1;
1909 * Emit the debug support for node node.
1911 static void ia32_emit_dbg(const ir_node *node)
1913 dbg_info *db = get_irn_dbg_info(node);
1915 const char *fname = be_retrieve_dbg_info(db, &lineno);
1917 if (! cg->birg->main_env->options->stabs_debug_support)
1921 if (last_name != fname) {
1923 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1926 if (last_line != lineno) {
1929 snprintf(name, sizeof(name), ".LM%u", ++num);
1931 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1932 be_emit_string(name);
1933 be_emit_cstring(":\n");
1934 be_emit_write_line();
1939 typedef void (*emit_func_ptr) (const ir_node *);
1942 * Emits code for a node.
1944 static void ia32_emit_node(const ir_node *node)
1946 ir_op *op = get_irn_op(node);
1948 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1950 if (op->ops.generic) {
1951 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1952 ia32_emit_dbg(node);
1956 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1962 * Emits gas alignment directives
1964 static void ia32_emit_alignment(unsigned align, unsigned skip)
1966 be_emit_cstring("\t.p2align ");
1967 be_emit_irprintf("%u,,%u\n", align, skip);
1968 be_emit_write_line();
1972 * Emits gas alignment directives for Functions depended on cpu architecture.
1974 static void ia32_emit_align_func(void)
1976 unsigned align = ia32_cg_config.function_alignment;
1977 unsigned maximum_skip = (1 << align) - 1;
1979 ia32_emit_alignment(align, maximum_skip);
1983 * Emits gas alignment directives for Labels depended on cpu architecture.
1985 static void ia32_emit_align_label(void)
1987 unsigned align = ia32_cg_config.label_alignment;
1988 unsigned maximum_skip = (1 << align) - 1;
1989 ia32_emit_alignment(align, maximum_skip);
1993 * Test wether a block should be aligned.
1994 * For cpus in the P4/Athlon class it is useful to align jump labels to
1995 * 16 bytes. However we should only do that if the alignment nops before the
1996 * label aren't executed more often than we have jumps to the label.
1998 static int should_align_block(ir_node *block, ir_node *prev)
2000 static const double DELTA = .0001;
2001 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2003 double prev_freq = 0; /**< execfreq of the fallthrough block */
2004 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2007 if(exec_freq == NULL)
2009 if(ia32_cg_config.label_alignment_factor <= 0)
2012 block_freq = get_block_execfreq(exec_freq, block);
2013 if(block_freq < DELTA)
2016 n_cfgpreds = get_Block_n_cfgpreds(block);
2017 for(i = 0; i < n_cfgpreds; ++i) {
2018 ir_node *pred = get_Block_cfgpred_block(block, i);
2019 double pred_freq = get_block_execfreq(exec_freq, pred);
2022 prev_freq += pred_freq;
2024 jmp_freq += pred_freq;
2028 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2031 jmp_freq /= prev_freq;
2033 return jmp_freq > ia32_cg_config.label_alignment_factor;
2036 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2041 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2043 n_cfgpreds = get_Block_n_cfgpreds(block);
2044 need_label = (n_cfgpreds != 0);
2046 if (should_align_block(block, prev)) {
2048 ia32_emit_align_label();
2052 ia32_emit_block_name(block);
2055 be_emit_pad_comment();
2056 be_emit_cstring(" /* preds:");
2058 /* emit list of pred blocks in comment */
2059 arity = get_irn_arity(block);
2060 for (i = 0; i < arity; ++i) {
2061 ir_node *predblock = get_Block_cfgpred_block(block, i);
2062 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2065 be_emit_cstring("\t/* ");
2066 ia32_emit_block_name(block);
2067 be_emit_cstring(": ");
2069 if (exec_freq != NULL) {
2070 be_emit_irprintf(" freq: %f",
2071 get_block_execfreq(exec_freq, block));
2073 be_emit_cstring(" */\n");
2074 be_emit_write_line();
2078 * Walks over the nodes in a block connected by scheduling edges
2079 * and emits code for each node.
2081 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2083 const ir_node *node;
2085 ia32_emit_block_header(block, last_block);
2087 /* emit the contents of the block */
2088 ia32_emit_dbg(block);
2089 sched_foreach(block, node) {
2090 ia32_emit_node(node);
2095 * Emits code for function start.
2097 static void ia32_emit_func_prolog(ir_graph *irg)
2099 ir_entity *irg_ent = get_irg_entity(irg);
2100 const char *irg_name = get_entity_ld_name(irg_ent);
2101 const be_irg_t *birg = cg->birg;
2103 /* write the begin line (used by scripts processing the assembler... */
2104 be_emit_write_line();
2105 be_emit_cstring("# -- Begin ");
2106 be_emit_string(irg_name);
2108 be_emit_write_line();
2110 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2111 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2112 ia32_emit_align_func();
2113 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2114 be_emit_cstring(".global ");
2115 be_emit_string(irg_name);
2117 be_emit_write_line();
2119 ia32_emit_function_object(irg_name);
2120 be_emit_string(irg_name);
2121 be_emit_cstring(":\n");
2122 be_emit_write_line();
2126 * Emits code for function end
2128 static void ia32_emit_func_epilog(ir_graph *irg)
2130 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2131 const be_irg_t *birg = cg->birg;
2133 ia32_emit_function_size(irg_name);
2134 be_dbg_method_end(birg->main_env->db_handle);
2136 be_emit_cstring("# -- End ");
2137 be_emit_string(irg_name);
2139 be_emit_write_line();
2142 be_emit_write_line();
2147 * Sets labels for control flow nodes (jump target)
2149 static void ia32_gen_labels(ir_node *block, void *data)
2152 int n = get_Block_n_cfgpreds(block);
2155 for (n--; n >= 0; n--) {
2156 pred = get_Block_cfgpred(block, n);
2157 set_irn_link(pred, block);
2162 * Emit an exception label if the current instruction can fail.
2164 void ia32_emit_exc_label(const ir_node *node)
2166 if (get_ia32_exc_label(node)) {
2167 be_emit_irprintf(".EXL%u\n", 0);
2168 be_emit_write_line();
2173 * Main driver. Emits the code for one routine.
2175 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2178 ir_node *last_block = NULL;
2182 isa = (const ia32_isa_t*) cg->arch_env->isa;
2183 arch_env = cg->arch_env;
2185 ia32_register_emitters();
2187 ia32_emit_func_prolog(irg);
2188 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2190 n = ARR_LEN(cg->blk_sched);
2191 for (i = 0; i < n;) {
2194 block = cg->blk_sched[i];
2196 next_bl = i < n ? cg->blk_sched[i] : NULL;
2198 /* set here the link. the emitter expects to find the next block here */
2199 set_irn_link(block, next_bl);
2200 ia32_gen_block(block, last_block);
2204 ia32_emit_func_epilog(irg);
2207 void ia32_init_emitter(void)
2209 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");