2 * This file implements the node emitter.
3 * @author Christian Wuerdig, Matthias Braun
21 #include "iredges_t.h"
25 #include "../besched_t.h"
26 #include "../benode_t.h"
28 #include "../be_dbgout.h"
30 #include "ia32_emitter.h"
31 #include "gen_ia32_emitter.h"
32 #include "gen_ia32_regalloc_if.h"
33 #include "ia32_nodes_attr.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_map_regs.h"
36 #include "bearch_ia32_t.h"
38 #define BLOCK_PREFIX ".L"
40 #define SNPRINTF_BUF_LEN 128
42 /* global arch_env for lc_printf functions */
43 static const arch_env_t *arch_env = NULL;
45 /** by default, we generate assembler code for the Linux gas */
46 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
49 * Switch to a new section
51 void ia32_switch_section(FILE *F, section_t sec) {
52 static section_t curr_sec = NO_SECTION;
53 static const char *text[ASM_MAX][SECTION_MAX] = {
59 ".section\t.tbss,\"awT\",@nobits",
60 ".section\t.ctors,\"aw\",@progbits"
65 ".section .rdata,\"dr\"",
67 ".section\t.tbss,\"awT\",@nobits",
68 ".section\t.ctors,\"aw\",@progbits"
87 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
95 static void ia32_dump_function_object(FILE *F, const char *name)
97 switch (asm_flavour) {
99 fprintf(F, "\t.type\t%s, @function\n", name);
102 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
109 static void ia32_dump_function_size(FILE *F, const char *name)
111 switch (asm_flavour) {
113 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
125 const arch_register_t *reg = NULL;
127 assert(get_irn_arity(irn) > pos && "Invalid IN position");
129 /* The out register of the operator at position pos is the
130 in register we need. */
131 op = get_irn_n(irn, pos);
133 reg = arch_get_irn_register(arch_env, op);
135 assert(reg && "no in register found");
137 /* in case of a joker register: just return a valid register */
138 if (arch_register_type_is(reg, joker)) {
139 arch_register_req_t req;
140 const arch_register_req_t *p_req;
142 /* ask for the requirements */
143 p_req = arch_get_register_req(arch_env, &req, irn, pos);
145 if (arch_register_req_is(p_req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
148 bitset_t *bs = bitset_alloca(arch_register_class_n_regs(p_req->cls));
151 p_req->limited(p_req->limited_env, bs);
152 idx = bitset_next_set(bs, 0);
153 reg = arch_register_for_index(p_req->cls, idx);
155 /* otherwise get first register in class */
156 reg = arch_register_for_index(p_req->cls, 0);
164 * Returns the register at out position pos.
166 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
168 const arch_register_t *reg = NULL;
170 /* 1st case: irn is not of mode_T, so it has only */
171 /* one OUT register -> good */
172 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
173 /* Proj with the corresponding projnum for the register */
175 if (get_irn_mode(irn) != mode_T) {
176 reg = arch_get_irn_register(arch_env, irn);
177 } else if (is_ia32_irn(irn)) {
178 reg = get_ia32_out_reg(irn, pos);
180 const ir_edge_t *edge;
182 foreach_out_edge(irn, edge) {
183 proj = get_edge_src_irn(edge);
184 assert(is_Proj(proj) && "non-Proj from mode_T node");
185 if (get_Proj_proj(proj) == pos) {
186 reg = arch_get_irn_register(arch_env, proj);
192 assert(reg && "no out register found");
197 * Returns an ident for the given tarval tv.
199 static ident *get_ident_for_tv(tarval *tv) {
201 int len = tarval_snprintf(buf, sizeof(buf), tv);
203 return new_id_from_str(buf);
207 * Determine the gnu assembler suffix that indicates a mode
209 static char get_mode_suffix(const ir_mode *mode) {
210 if(mode_is_float(mode)) {
211 switch(get_mode_size_bits(mode)) {
220 assert(mode_is_int(mode) || mode_is_reference(mode));
221 switch(get_mode_size_bits(mode)) {
232 panic("Can't output mode_suffix for %+F\n", mode);
235 static int produces_result(const ir_node *node) {
236 return !(is_ia32_St(node) ||
237 is_ia32_Store8Bit(node) ||
238 is_ia32_CondJmp(node) ||
239 is_ia32_xCondJmp(node) ||
240 is_ia32_CmpSet(node) ||
241 is_ia32_xCmpSet(node) ||
242 is_ia32_SwitchJmp(node));
245 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
246 switch(get_mode_size_bits(mode)) {
248 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
250 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
252 return (char *)arch_register_get_name(reg);
258 * Determines the SSE suffix depending on the mode.
260 static int ia32_print_mode_suffix(lc_appendable_t *app,
261 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
263 ir_node *irn = arg->v_ptr;
264 ir_mode *mode = get_ia32_ls_mode(irn);
266 if (mode_is_float(mode)) {
267 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
269 if(get_mode_size_bits(mode) == 32)
272 if(mode_is_signed(mode))
273 lc_appendable_chadd(app, 's');
275 lc_appendable_chadd(app, 'z');
277 lc_appendable_chadd(app, get_mode_suffix(mode));
284 * Add a number to a prefix. This number will not be used a second time.
286 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
287 static unsigned long id = 0;
288 snprintf(buf, buflen, "%s%lu", prefix, ++id);
292 /*************************************************************
294 * (_) | | / _| | | | |
295 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
296 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
297 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
298 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
301 *************************************************************/
303 void ia32_emit_ident(ia32_emit_env_t *env, ident *id)
305 size_t len = get_id_strlen(id);
306 const char* str = get_id_str(id);
308 ia32_emit_string_len(env, str, len);
311 void ia32_emit_irprintf(ia32_emit_env_t *env, const char *fmt, ...)
317 ir_vsnprintf(buf, sizeof(buf), fmt, ap);
320 ia32_emit_string(env, buf);
323 void ia32_emit_source_register(ia32_emit_env_t *env, const ir_node *node, int pos)
325 const arch_register_t *reg = get_in_reg(node, pos);
326 const char *reg_name = arch_register_get_name(reg);
328 assert(pos < get_irn_arity(node));
330 ia32_emit_char(env, '%');
331 ia32_emit_string(env, reg_name);
334 void ia32_emit_dest_register(ia32_emit_env_t *env, const ir_node *node, int pos) {
335 const arch_register_t *reg = get_out_reg(node, pos);
336 const char *reg_name = arch_register_get_name(reg);
338 ia32_emit_char(env, '%');
339 ia32_emit_string(env, reg_name);
342 void ia32_emit_x87_name(ia32_emit_env_t *env, const ir_node *node, int pos)
344 ia32_attr_t *attr = get_ia32_attr(node);
347 ia32_emit_char(env, '%');
348 ia32_emit_string(env, attr->x87[pos]->name);
351 void ia32_emit_immediate(ia32_emit_env_t *env, const ir_node *node)
356 switch(get_ia32_immop_type(node)) {
358 tv = get_ia32_Immop_tarval(node);
359 id = get_ident_for_tv(tv);
361 case ia32_ImmSymConst:
362 id = get_ia32_Immop_symconst(node);
366 ia32_emit_string(env, "BAD");
370 ia32_emit_ident(env, id);
373 void ia32_emit_mode_suffix(ia32_emit_env_t *env, const ir_mode *mode)
375 ia32_emit_char(env, get_mode_suffix(mode));
378 void ia32_emit_x87_mode_suffix(ia32_emit_env_t *env, const ir_node *node)
380 ir_mode *mode = get_ia32_ls_mode(node);
382 ia32_emit_mode_suffix(env, mode);
385 void ia32_emit_extend_suffix(ia32_emit_env_t *env, const ir_mode *mode)
387 if(get_mode_size_bits(mode) == 32)
389 if(mode_is_signed(mode)) {
390 ia32_emit_char(env, 's');
392 ia32_emit_char(env, 'z');
397 * Emits registers and/or address mode of a binary operation.
399 void ia32_emit_binop(ia32_emit_env_t *env, const ir_node *node) {
400 switch(get_ia32_op_type(node)) {
402 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
403 ia32_emit_char(env, '$');
404 ia32_emit_immediate(env, node);
405 ia32_emit_cstring(env, ", ");
406 ia32_emit_source_register(env, node, 2);
408 const arch_register_t *in1 = get_in_reg(node, 2);
409 const arch_register_t *in2 = get_in_reg(node, 3);
410 const arch_register_t *out = produces_result(node) ? get_out_reg(node, 0) : NULL;
411 const arch_register_t *in;
414 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
415 out = out ? out : in1;
416 in_name = arch_register_get_name(in);
418 if (is_ia32_emit_cl(node)) {
419 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
423 ia32_emit_char(env, '%');
424 ia32_emit_string(env, in_name);
425 ia32_emit_cstring(env, ", %");
426 ia32_emit_string(env, arch_register_get_name(out));
430 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
431 assert(!produces_result(node) && "Source AM with Const must not produce result");
432 ia32_emit_am(env, node);
433 ia32_emit_cstring(env, ", $");
434 ia32_emit_immediate(env, node);
435 } else if (produces_result(node)) {
436 ia32_emit_am(env, node);
437 ia32_emit_cstring(env, ", ");
438 ia32_emit_dest_register(env, node, 0);
440 ia32_emit_am(env, node);
441 ia32_emit_cstring(env, ", ");
442 ia32_emit_source_register(env, node, 2);
446 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
447 ia32_emit_char(env, '$');
448 ia32_emit_immediate(env, node);
449 ia32_emit_cstring(env, ", ");
450 ia32_emit_am(env, node);
452 const arch_register_t *in1 = get_in_reg(node, get_irn_arity(node) == 5 ? 3 : 2);
453 ir_mode *mode = get_ia32_ls_mode(node);
456 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
458 if (is_ia32_emit_cl(node)) {
459 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
463 ia32_emit_char(env, '%');
464 ia32_emit_string(env, in_name);
465 ia32_emit_cstring(env, ", ");
466 ia32_emit_am(env, node);
470 assert(0 && "unsupported op type");
475 * Emits registers and/or address mode of a binary operation.
477 void ia32_emit_x87_binop(ia32_emit_env_t *env, const ir_node *node) {
478 switch(get_ia32_op_type(node)) {
480 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
481 // should not happen...
484 ia32_attr_t *attr = get_ia32_attr(node);
485 const arch_register_t *in1 = attr->x87[0];
486 const arch_register_t *in2 = attr->x87[1];
487 const arch_register_t *out = attr->x87[2];
488 const arch_register_t *in;
490 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
491 out = out ? out : in1;
493 ia32_emit_char(env, '%');
494 ia32_emit_string(env, arch_register_get_name(in));
495 ia32_emit_cstring(env, ", %");
496 ia32_emit_string(env, arch_register_get_name(out));
501 ia32_emit_am(env, node);
504 assert(0 && "unsupported op type");
509 * Emits registers and/or address mode of a unary operation.
511 void ia32_emit_unop(ia32_emit_env_t *env, const ir_node *node) {
512 switch(get_ia32_op_type(node)) {
514 if (is_ia32_ImmConst(node) || is_ia32_ImmSymConst(node)) {
515 ia32_emit_char(env, '$');
516 ia32_emit_immediate(env, node);
518 if (is_ia32_IMul(node) || is_ia32_Mulh(node)) {
519 /* MulS and Mulh implicitly multiply by EAX */
520 ia32_emit_source_register(env, node, 3);
521 } else if(is_ia32_IDiv(node)) {
522 ia32_emit_source_register(env, node, 1);
523 } else if(is_ia32_Push(node)) {
524 ia32_emit_source_register(env, node, 2);
525 } else if(is_ia32_Pop(node)) {
526 ia32_emit_dest_register(env, node, 1);
528 ia32_emit_dest_register(env, node, 0);
534 ia32_emit_am(env, node);
537 assert(0 && "unsupported op type");
542 * Emits address mode.
544 void ia32_emit_am(ia32_emit_env_t *env, const ir_node *node) {
545 ia32_am_flavour_t am_flav = get_ia32_am_flavour(node);
546 ident *id = get_ia32_am_sc(node);
547 int offs = get_ia32_am_offs_int(node);
549 /* just to be sure... */
550 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
554 if (is_ia32_am_sc_sign(node))
555 ia32_emit_char(env, '-');
556 ia32_emit_ident(env, id);
561 ia32_emit_irprintf(env, "%+d", offs);
563 ia32_emit_irprintf(env, "%d", offs);
567 if (am_flav & (ia32_B | ia32_I)) {
568 ia32_emit_char(env, '(');
571 if (am_flav & ia32_B) {
572 ia32_emit_source_register(env, node, 0);
575 /* emit index + scale */
576 if (am_flav & ia32_I) {
577 ia32_emit_char(env, ',');
578 ia32_emit_source_register(env, node, 1);
580 if (am_flav & ia32_S) {
581 ia32_emit_irprintf(env, ",%d", 1 << get_ia32_am_scale(node));
584 ia32_emit_char(env, ')');
590 * Formated print of commands and comments.
592 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
594 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
597 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
599 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
603 void ia32_write_line(ia32_emit_env_t *env)
605 char *finished_line = obstack_finish(env->obst);
607 fwrite(finished_line, env->linelength, 1, env->out);
609 obstack_free(env->obst, finished_line);
612 void ia32_pad_comment(ia32_emit_env_t *env)
614 while(env->linelength <= 30) {
615 ia32_emit_char(env, ' ');
617 ia32_emit_cstring(env, " ");
620 void ia32_emit_finish_line(ia32_emit_env_t *env, const ir_node *node)
623 const char *sourcefile;
627 ia32_emit_char(env, '\n');
628 ia32_write_line(env);
632 ia32_pad_comment(env);
633 ia32_emit_cstring(env, "/* ");
634 ia32_emit_irprintf(env, "%+F ", node);
636 dbg = get_irn_dbg_info(node);
637 sourcefile = be_retrieve_dbg_info(dbg, &lineno);
638 if(sourcefile != NULL) {
639 ia32_emit_string(env, sourcefile);
640 ia32_emit_irprintf(env, ":%u", lineno);
642 ia32_emit_cstring(env, " */\n");
643 ia32_write_line(env);
647 /*************************************************
650 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
651 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
652 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
653 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
655 *************************************************/
658 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
661 * coding of conditions
663 struct cmp2conditon_t {
669 * positive conditions for signed compares
671 static const struct cmp2conditon_t cmp2condition_s[] = {
672 { NULL, pn_Cmp_False }, /* always false */
673 { "e", pn_Cmp_Eq }, /* == */
674 { "l", pn_Cmp_Lt }, /* < */
675 { "le", pn_Cmp_Le }, /* <= */
676 { "g", pn_Cmp_Gt }, /* > */
677 { "ge", pn_Cmp_Ge }, /* >= */
678 { "ne", pn_Cmp_Lg }, /* != */
679 { NULL, pn_Cmp_Leg}, /* Floating point: ordered */
680 { NULL, pn_Cmp_Uo }, /* Floating point: unordered */
681 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
682 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
683 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
684 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
685 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
686 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
687 { NULL, pn_Cmp_True }, /* always true */
691 * positive conditions for unsigned compares
693 static const struct cmp2conditon_t cmp2condition_u[] = {
694 { NULL, pn_Cmp_False }, /* always false */
695 { "e", pn_Cmp_Eq }, /* == */
696 { "b", pn_Cmp_Lt }, /* < */
697 { "be", pn_Cmp_Le }, /* <= */
698 { "a", pn_Cmp_Gt }, /* > */
699 { "ae", pn_Cmp_Ge }, /* >= */
700 { "ne", pn_Cmp_Lg }, /* != */
701 { NULL, pn_Cmp_True }, /* always true */
705 * returns the condition code
707 static const char *get_cmp_suffix(int cmp_code)
709 assert( (cmp2condition_s[cmp_code & 15].num) == (cmp_code & 15));
710 assert( (cmp2condition_u[cmp_code & 7].num) == (cmp_code & 7));
712 if((cmp_code & ia32_pn_Cmp_Unsigned)) {
713 return cmp2condition_u[cmp_code & 7].name;
715 return cmp2condition_s[cmp_code & 15].name;
719 void ia32_emit_cmp_suffix(ia32_emit_env_t *env, long pnc)
721 ia32_emit_string(env, get_cmp_suffix(pnc));
726 * Returns the target block for a control flow node.
728 static ir_node *get_cfop_target_block(const ir_node *irn) {
729 return get_irn_link(irn);
733 * Returns the target label for a control flow node.
735 void ia32_emit_cfop_target(ia32_emit_env_t * env, const ir_node *node) {
736 ir_node *block = get_cfop_target_block(node);
738 ia32_emit_cstring(env, BLOCK_PREFIX);
739 ia32_emit_irprintf(env, "%d", get_irn_node_nr(block));
742 /** Return the next block in Block schedule */
743 static ir_node *next_blk_sched(const ir_node *block) {
744 return get_irn_link(block);
748 * Returns the Proj with projection number proj and NOT mode_M
750 static ir_node *get_proj(const ir_node *node, long proj) {
751 const ir_edge_t *edge;
754 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
756 foreach_out_edge(node, edge) {
757 src = get_edge_src_irn(edge);
759 assert(is_Proj(src) && "Proj expected");
760 if (get_irn_mode(src) == mode_M)
763 if (get_Proj_proj(src) == proj)
770 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
772 static void finish_CondJmp(ia32_emit_env_t *env, const ir_node *node,
773 ir_mode *mode, long pnc) {
774 const ir_node *proj_true;
775 const ir_node *proj_false;
776 const ir_node *block;
777 const ir_node *next_block;
780 /* get both Proj's */
781 proj_true = get_proj(node, pn_Cond_true);
782 assert(proj_true && "CondJmp without true Proj");
784 proj_false = get_proj(node, pn_Cond_false);
785 assert(proj_false && "CondJmp without false Proj");
787 /* for now, the code works for scheduled and non-schedules blocks */
788 block = get_nodes_block(node);
790 /* we have a block schedule */
791 next_block = next_blk_sched(block);
793 if (get_cfop_target_block(proj_true) == next_block) {
794 /* exchange both proj's so the second one can be omitted */
795 const ir_node *t = proj_true;
797 proj_true = proj_false;
800 pnc = get_negated_pnc(pnc, mode);
803 /* in case of unordered compare, check for parity */
804 if (pnc & pn_Cmp_Uo) {
805 ia32_emit_cstring(env, "\tjp ");
806 ia32_emit_cfop_target(env, proj_true);
807 ia32_emit_finish_line(env, proj_true);
810 ia32_emit_cstring(env, "\tj");
811 ia32_emit_cmp_suffix(env, pnc);
812 ia32_emit_char(env, ' ');
813 ia32_emit_cfop_target(env, proj_true);
814 ia32_emit_finish_line(env, proj_true);
816 /* the second Proj might be a fallthrough */
817 if (get_cfop_target_block(proj_false) != next_block) {
818 ia32_emit_cstring(env, "\tjmp ");
819 ia32_emit_cfop_target(env, proj_false);
820 ia32_emit_finish_line(env, proj_false);
822 ia32_emit_cstring(env, "\t/* fallthrough to");
823 ia32_emit_cfop_target(env, proj_false);
824 ia32_emit_cstring(env, " */");
825 ia32_emit_finish_line(env, proj_false);
830 * Emits code for conditional jump.
832 static void CondJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
833 ia32_emit_cstring(env, "\tcmp ");
834 ia32_emit_binop(env, node);
835 ia32_emit_finish_line(env, node);
837 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
841 * Emits code for conditional jump with two variables.
843 static void emit_ia32_CondJmp(ia32_emit_env_t *env, const ir_node *node) {
844 CondJmp_emitter(env, node);
848 * Emits code for conditional test and jump.
850 static void TestJmp_emitter(ia32_emit_env_t *env, const ir_node *node) {
851 if(is_ia32_ImmSymConst(node) || is_ia32_ImmConst(node)) {
852 ia32_emit_cstring(env, "\ttest $");
853 ia32_emit_immediate(env, node);
854 ia32_emit_cstring(env, ", ");
855 ia32_emit_source_register(env, node, 0);
856 ia32_emit_finish_line(env, node);
858 ia32_emit_cstring(env, "\ttest ");
859 ia32_emit_source_register(env, node, 1);
860 ia32_emit_cstring(env, ", ");
861 ia32_emit_source_register(env, node, 0);
862 ia32_emit_finish_line(env, node);
864 finish_CondJmp(env, node, mode_Iu, get_ia32_pncode(node));
868 * Emits code for conditional test and jump with two variables.
870 static void emit_ia32_TestJmp(ia32_emit_env_t *env, const ir_node *node) {
871 TestJmp_emitter(env, node);
874 static void emit_ia32_CJmp(ia32_emit_env_t *env, const ir_node *node) {
875 ia32_emit_cstring(env, "/* omitted redundant test */");
876 ia32_emit_finish_line(env, node);
878 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
881 static void emit_ia32_CJmpAM(ia32_emit_env_t *env, const ir_node *node) {
882 ia32_emit_cstring(env, "/* omitted redundant test/cmp */");
883 ia32_emit_finish_line(env, node);
885 finish_CondJmp(env, node, mode_Is, get_ia32_pncode(node));
889 * Emits code for conditional SSE floating point jump with two variables.
891 static void emit_ia32_xCondJmp(ia32_emit_env_t *env, const ir_node *node) {
892 ia32_emit_cstring(env, "\tucomis");
893 ia32_emit_mode_suffix(env, get_irn_mode(node));
894 ia32_emit_char(env, ' ');
895 ia32_emit_binop(env, node);
896 ia32_emit_finish_line(env, node);
898 finish_CondJmp(env, node, mode_F, get_ia32_pncode(node));
902 * Emits code for conditional x87 floating point jump with two variables.
904 static void emit_ia32_x87CondJmp(ia32_emit_env_t *env, const ir_node *node) {
905 ia32_attr_t *attr = get_ia32_attr(node);
906 const char *reg = attr->x87[1]->name;
907 long pnc = get_ia32_pncode(node);
909 switch (get_ia32_irn_opcode(node)) {
910 case iro_ia32_fcomrJmp:
911 pnc = get_inversed_pnc(pnc);
912 case iro_ia32_fcomJmp:
914 ia32_emit_cstring(env, "\tfucom ");
916 case iro_ia32_fcomrpJmp:
917 pnc = get_inversed_pnc(pnc);
918 case iro_ia32_fcompJmp:
919 ia32_emit_cstring(env, "\tfucomp ");
921 case iro_ia32_fcomrppJmp:
922 pnc = get_inversed_pnc(pnc);
923 case iro_ia32_fcomppJmp:
924 ia32_emit_cstring(env, "\tfucompp ");
930 ia32_emit_char(env, '%');
931 ia32_emit_string(env, reg);
933 ia32_emit_finish_line(env, node);
935 ia32_emit_cstring(env, "\tfnstsw %ax");
936 ia32_emit_finish_line(env, node);
937 ia32_emit_cstring(env, "\tsahf");
938 ia32_emit_finish_line(env, node);
940 finish_CondJmp(env, node, mode_E, pnc);
943 static void CMov_emitter(ia32_emit_env_t *env, const ir_node *node) {
944 long pnc = get_ia32_pncode(node);
945 int is_PsiCondCMov = is_ia32_PsiCondCMov(node);
946 int idx_left = 2 - is_PsiCondCMov;
947 int idx_right = 3 - is_PsiCondCMov;
948 const arch_register_t *in1, *in2, *out;
950 out = arch_get_irn_register(env->arch_env, node);
951 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_left));
952 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, idx_right));
954 /* we have to emit the cmp first, because the destination register */
955 /* could be one of the compare registers */
956 if (is_ia32_CmpCMov(node)) {
957 ia32_emit_cstring(env, "\tcmp ");
958 ia32_emit_source_register(env, node, 1);
959 ia32_emit_cstring(env, ", ");
960 ia32_emit_source_register(env, node, 0);
961 } else if (is_ia32_xCmpCMov(node)) {
962 ia32_emit_cstring(env, "\tucomis");
963 ia32_emit_mode_suffix(env, get_irn_mode(node));
964 ia32_emit_char(env, ' ');
965 ia32_emit_source_register(env, node, 1);
966 ia32_emit_cstring(env, ", ");
967 ia32_emit_source_register(env, node, 0);
968 } else if (is_PsiCondCMov) {
969 /* omit compare because flags are already set by And/Or */
970 ia32_emit_cstring(env, "\ttest ");
971 ia32_emit_source_register(env, node, 0);
972 ia32_emit_cstring(env, ", ");
973 ia32_emit_source_register(env, node, 0);
975 assert(0 && "unsupported CMov");
977 ia32_emit_finish_line(env, node);
979 if (REGS_ARE_EQUAL(out, in2)) {
980 /* best case: default in == out -> do nothing */
981 } else if (REGS_ARE_EQUAL(out, in1)) {
982 ir_node *n = (ir_node*) node;
983 /* true in == out -> need complement compare and exchange true and default in */
984 ir_node *t = get_irn_n(n, idx_left);
985 set_irn_n(n, idx_left, get_irn_n(n, idx_right));
986 set_irn_n(n, idx_right, t);
988 pnc = get_negated_pnc(pnc, get_irn_mode(node));
990 /* out is different from in: need copy default -> out */
991 if (is_PsiCondCMov) {
992 ia32_emit_cstring(env, "\tmovl ");
993 ia32_emit_dest_register(env, node, 2);
994 ia32_emit_cstring(env, ", ");
995 ia32_emit_dest_register(env, node, 0);
997 ia32_emit_cstring(env, "\tmovl ");
998 ia32_emit_source_register(env, node, 3);
999 ia32_emit_cstring(env, ", ");
1000 ia32_emit_dest_register(env, node, 0);
1002 ia32_emit_finish_line(env, node);
1005 if (is_PsiCondCMov) {
1006 ia32_emit_cstring(env, "\tcmov");
1007 ia32_emit_cmp_suffix(env, pnc);
1008 ia32_emit_cstring(env, "l ");
1009 ia32_emit_source_register(env, node, 1);
1010 ia32_emit_cstring(env, ", ");
1011 ia32_emit_dest_register(env, node, 0);
1013 ia32_emit_cstring(env, "\tcmov");
1014 ia32_emit_cmp_suffix(env, pnc);
1015 ia32_emit_cstring(env, "l ");
1016 ia32_emit_source_register(env, node, 2);
1017 ia32_emit_cstring(env, ", ");
1018 ia32_emit_dest_register(env, node, 0);
1020 ia32_emit_finish_line(env, node);
1023 static void emit_ia32_CmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1024 CMov_emitter(env, node);
1027 static void emit_ia32_PsiCondCMov(ia32_emit_env_t *env, const ir_node *node) {
1028 CMov_emitter(env, node);
1031 static void emit_ia32_xCmpCMov(ia32_emit_env_t *env, const ir_node *node) {
1032 CMov_emitter(env, node);
1035 static void Set_emitter(ia32_emit_env_t *env, const ir_node *node, ir_mode *mode) {
1036 int pnc = get_ia32_pncode(node);
1037 const char *reg8bit;
1038 const arch_register_t *out;
1040 out = arch_get_irn_register(env->arch_env, node);
1041 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1043 if (is_ia32_CmpSet(node)) {
1044 ia32_emit_cstring(env, "\tcmp ");
1045 ia32_emit_binop(env, node);
1046 } else if (is_ia32_xCmpSet(node)) {
1047 ia32_emit_cstring(env, "\tucomis");
1048 ia32_emit_mode_suffix(env, get_irn_mode(get_irn_n(node, 2)));
1049 ia32_emit_char(env, ' ');
1050 ia32_emit_binop(env, node);
1051 } else if (is_ia32_PsiCondSet(node)) {
1052 ia32_emit_cstring(env, "\tcmp $0, ");
1053 ia32_emit_source_register(env, node, 0);
1055 assert(0 && "unsupported Set");
1057 ia32_emit_finish_line(env, node);
1059 /* use mov to clear target because it doesn't affect the eflags */
1060 ia32_emit_cstring(env, "\tmovl $0, %");
1061 ia32_emit_string(env, arch_register_get_name(out));
1062 ia32_emit_finish_line(env, node);
1064 ia32_emit_cstring(env, "\tset");
1065 ia32_emit_cmp_suffix(env, pnc);
1066 ia32_emit_cstring(env, " %");
1067 ia32_emit_string(env, reg8bit);
1068 ia32_emit_finish_line(env, node);
1071 static void emit_ia32_CmpSet(ia32_emit_env_t *env, const ir_node *node) {
1072 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1075 static void emit_ia32_PsiCondSet(ia32_emit_env_t *env, const ir_node *node) {
1076 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 0)));
1079 static void emit_ia32_xCmpSet(ia32_emit_env_t *env, const ir_node *node) {
1080 Set_emitter(env, node, get_irn_mode(get_irn_n(node, 2)));
1083 static void emit_ia32_xCmp(ia32_emit_env_t *env, const ir_node *node) {
1085 long pnc = get_ia32_pncode(node);
1086 long unord = pnc & pn_Cmp_Uo;
1088 assert( (pnc & ia32_pn_Cmp_Unsigned) == 0);
1091 case pn_Cmp_Leg: /* odered */
1094 case pn_Cmp_Uo: /* unordered */
1098 case pn_Cmp_Eq: /* == */
1102 case pn_Cmp_Lt: /* < */
1106 case pn_Cmp_Le: /* <= */
1110 case pn_Cmp_Gt: /* > */
1114 case pn_Cmp_Ge: /* >= */
1118 case pn_Cmp_Lg: /* != */
1123 assert(sse_pnc >= 0 && "unsupported compare");
1125 if (unord && sse_pnc != 3) {
1127 We need a separate compare against unordered.
1128 Quick and Dirty solution:
1129 - get some memory on stack
1133 - and result and stored result
1136 ia32_emit_cstring(env, "\tsubl $8, %esp");
1137 ia32_emit_finish_line(env, node);
1139 ia32_emit_cstring(env, "\tcmpsd $3, ");
1140 ia32_emit_binop(env, node);
1141 ia32_emit_finish_line(env, node);
1143 ia32_emit_cstring(env, "\tmovsd ");
1144 ia32_emit_dest_register(env, node, 0);
1145 ia32_emit_cstring(env, ", (%esp)");
1146 ia32_emit_finish_line(env, node);
1149 ia32_emit_cstring(env, "\tcmpsd ");
1150 ia32_emit_irprintf(env, "%d, ", sse_pnc);
1151 ia32_emit_binop(env, node);
1152 ia32_emit_finish_line(env, node);
1154 if (unord && sse_pnc != 3) {
1155 ia32_emit_cstring(env, "\tandpd (%esp), ");
1156 ia32_emit_dest_register(env, node, 0);
1157 ia32_emit_finish_line(env, node);
1159 ia32_emit_cstring(env, "\taddl $8, %esp");
1160 ia32_emit_finish_line(env, node);
1164 /*********************************************************
1167 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1168 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1169 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1170 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1173 *********************************************************/
1175 /* jump table entry (target and corresponding number) */
1176 typedef struct _branch_t {
1181 /* jump table for switch generation */
1182 typedef struct _jmp_tbl_t {
1183 ir_node *defProj; /**< default target */
1184 int min_value; /**< smallest switch case */
1185 int max_value; /**< largest switch case */
1186 int num_branches; /**< number of jumps */
1187 char *label; /**< label of the jump table */
1188 branch_t *branches; /**< jump array */
1192 * Compare two variables of type branch_t. Used to sort all switch cases
1194 static int ia32_cmp_branch_t(const void *a, const void *b) {
1195 branch_t *b1 = (branch_t *)a;
1196 branch_t *b2 = (branch_t *)b;
1198 if (b1->value <= b2->value)
1205 * Emits code for a SwitchJmp (creates a jump table if
1206 * possible otherwise a cmp-jmp cascade). Port from
1209 static void emit_ia32_SwitchJmp(ia32_emit_env_t *env, const ir_node *node) {
1210 unsigned long interval;
1215 const ir_edge_t *edge;
1217 /* fill the table structure */
1218 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1219 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1221 tbl.num_branches = get_irn_n_edges(node);
1222 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1223 tbl.min_value = INT_MAX;
1224 tbl.max_value = INT_MIN;
1227 /* go over all proj's and collect them */
1228 foreach_out_edge(node, edge) {
1229 proj = get_edge_src_irn(edge);
1230 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1232 pnc = get_Proj_proj(proj);
1234 /* create branch entry */
1235 tbl.branches[i].target = proj;
1236 tbl.branches[i].value = pnc;
1238 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1239 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1241 /* check for default proj */
1242 if (pnc == get_ia32_pncode(node)) {
1243 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1250 /* sort the branches by their number */
1251 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1253 /* two-complement's magic make this work without overflow */
1254 interval = tbl.max_value - tbl.min_value;
1256 /* emit the table */
1257 ia32_emit_cstring(env, "\tcmpl $");
1258 ia32_emit_irprintf(env, "%u, ", interval);
1259 ia32_emit_source_register(env, node, 0);
1260 ia32_emit_finish_line(env, node);
1262 ia32_emit_cstring(env, "\tja ");
1263 ia32_emit_cfop_target(env, tbl.defProj);
1264 ia32_emit_finish_line(env, node);
1266 if (tbl.num_branches > 1) {
1268 ia32_emit_cstring(env, "\tjmp *");
1269 ia32_emit_string(env, tbl.label);
1270 ia32_emit_cstring(env, "(,");
1271 ia32_emit_source_register(env, node, 0);
1272 ia32_emit_cstring(env, ",4)");
1273 ia32_emit_finish_line(env, node);
1275 ia32_switch_section(env->out, SECTION_RODATA);
1276 ia32_emit_cstring(env, "\t.align 4\n");
1277 ia32_write_line(env);
1279 ia32_emit_string(env, tbl.label);
1280 ia32_emit_cstring(env, ":\n");
1281 ia32_write_line(env);
1283 ia32_emit_cstring(env, ".long ");
1284 ia32_emit_cfop_target(env, tbl.branches[0].target);
1285 ia32_emit_finish_line(env, NULL);
1287 last_value = tbl.branches[0].value;
1288 for (i = 1; i < tbl.num_branches; ++i) {
1289 while (++last_value < tbl.branches[i].value) {
1290 ia32_emit_cstring(env, ".long ");
1291 ia32_emit_cfop_target(env, tbl.defProj);
1292 ia32_emit_finish_line(env, NULL);
1294 ia32_emit_cstring(env, ".long ");
1295 ia32_emit_cfop_target(env, tbl.branches[i].target);
1296 ia32_emit_finish_line(env, NULL);
1298 ia32_switch_section(env->out, SECTION_TEXT);
1300 /* one jump is enough */
1301 ia32_emit_cstring(env, "\tjmp ");
1302 ia32_emit_cfop_target(env, tbl.branches[0].target);
1303 ia32_emit_finish_line(env, node);
1313 * Emits code for a unconditional jump.
1315 static void emit_Jmp(ia32_emit_env_t *env, const ir_node *node) {
1316 ir_node *block, *next_block;
1318 /* for now, the code works for scheduled and non-schedules blocks */
1319 block = get_nodes_block(node);
1321 /* we have a block schedule */
1322 next_block = next_blk_sched(block);
1323 if (get_cfop_target_block(node) != next_block) {
1324 ia32_emit_cstring(env, "\tjmp ");
1325 ia32_emit_cfop_target(env, node);
1327 ia32_emit_cstring(env, "\t/* fallthrough to ");
1328 ia32_emit_cfop_target(env, node);
1329 ia32_emit_cstring(env, " */");
1331 ia32_emit_finish_line(env, node);
1334 /**********************************
1337 * | | ___ _ __ _ _| |_) |
1338 * | | / _ \| '_ \| | | | _ <
1339 * | |___| (_) | |_) | |_| | |_) |
1340 * \_____\___/| .__/ \__, |____/
1343 **********************************/
1346 * Emit movsb/w instructions to make mov count divideable by 4
1348 static void emit_CopyB_prolog(ia32_emit_env_t *env, int rem) {
1349 ia32_emit_cstring(env, "\tcld");
1350 ia32_emit_finish_line(env, NULL);
1354 ia32_emit_cstring(env, "\tmovsb");
1355 ia32_emit_finish_line(env, NULL);
1358 ia32_emit_cstring(env, "\tmovsw");
1359 ia32_emit_finish_line(env, NULL);
1362 ia32_emit_cstring(env, "\tmovsb");
1363 ia32_emit_finish_line(env, NULL);
1364 ia32_emit_cstring(env, "\tmovsw");
1365 ia32_emit_finish_line(env, NULL);
1371 * Emit rep movsd instruction for memcopy.
1373 static void emit_ia32_CopyB(ia32_emit_env_t *env, const ir_node *node) {
1374 tarval *tv = get_ia32_Immop_tarval(node);
1375 int rem = get_tarval_long(tv);
1377 emit_CopyB_prolog(env, rem);
1379 ia32_emit_cstring(env, "\trep movsd");
1380 ia32_emit_finish_line(env, node);
1384 * Emits unrolled memcopy.
1386 static void emit_ia32_CopyB_i(ia32_emit_env_t *env, const ir_node *node) {
1387 tarval *tv = get_ia32_Immop_tarval(node);
1388 int size = get_tarval_long(tv);
1390 emit_CopyB_prolog(env, size & 0x3);
1394 ia32_emit_cstring(env, "\tmovsd");
1395 ia32_emit_finish_line(env, NULL);
1401 /***************************
1405 * | | / _ \| '_ \ \ / /
1406 * | |___| (_) | | | \ V /
1407 * \_____\___/|_| |_|\_/
1409 ***************************/
1412 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1414 static void emit_ia32_Conv_with_FP(ia32_emit_env_t *env, const ir_node *node) {
1415 ir_mode *ls_mode = get_ia32_ls_mode(node);
1416 int ls_bits = get_mode_size_bits(ls_mode);
1418 ia32_emit_cstring(env, "\tcvt");
1420 if(is_ia32_Conv_I2FP(node)) {
1422 ia32_emit_cstring(env, "si2ss");
1424 ia32_emit_cstring(env, "si2sd");
1426 } else if(is_ia32_Conv_FP2I(node)) {
1428 ia32_emit_cstring(env, "ss2si");
1430 ia32_emit_cstring(env, "sd2si");
1433 assert(is_ia32_Conv_FP2FP(node));
1435 ia32_emit_cstring(env, "sd2ss");
1437 ia32_emit_cstring(env, "ss2sd");
1441 switch(get_ia32_op_type(node)) {
1443 ia32_emit_dest_register(env, node, 0);
1444 ia32_emit_cstring(env, ", ");
1445 ia32_emit_source_register(env, node, 2);
1447 case ia32_AddrModeS:
1448 ia32_emit_dest_register(env, node, 0);
1449 ia32_emit_cstring(env, ", ");
1450 ia32_emit_am(env, node);
1453 assert(0 && "unsupported op type for Conv");
1455 ia32_emit_finish_line(env, node);
1458 static void emit_ia32_Conv_I2FP(ia32_emit_env_t *env, const ir_node *node) {
1459 emit_ia32_Conv_with_FP(env, node);
1462 static void emit_ia32_Conv_FP2I(ia32_emit_env_t *env, const ir_node *node) {
1463 emit_ia32_Conv_with_FP(env, node);
1466 static void emit_ia32_Conv_FP2FP(ia32_emit_env_t *env, const ir_node *node) {
1467 emit_ia32_Conv_with_FP(env, node);
1471 * Emits code for an Int conversion.
1473 static void emit_ia32_Conv_I2I(ia32_emit_env_t *env, const ir_node *node) {
1474 const char *sign_suffix;
1475 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1476 int smaller_bits = get_mode_size_bits(smaller_mode);
1478 const arch_register_t *in_reg, *out_reg;
1480 assert(!mode_is_float(smaller_mode));
1481 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1483 signed_mode = mode_is_signed(smaller_mode);
1484 if(smaller_bits == 32) {
1485 // this should not happen as it's no convert
1489 sign_suffix = signed_mode ? "s" : "z";
1492 switch(get_ia32_op_type(node)) {
1494 in_reg = get_in_reg(node, 2);
1495 out_reg = get_out_reg(node, 0);
1497 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1498 REGS_ARE_EQUAL(out_reg, in_reg) &&
1501 /* argument and result are both in EAX and */
1502 /* signedness is ok: -> use converts */
1503 if (smaller_bits == 8) {
1504 ia32_emit_cstring(env, "\tcbtw");
1505 } else if (smaller_bits == 16) {
1506 ia32_emit_cstring(env, "\tcwtl");
1510 } else if (REGS_ARE_EQUAL(out_reg, in_reg) && !signed_mode) {
1511 /* argument and result are in the same register */
1512 /* and signedness is ok: -> use and with mask */
1513 int mask = (1 << smaller_bits) - 1;
1514 ia32_emit_cstring(env, "\tandl $0x");
1515 ia32_emit_irprintf(env, "%x, ", mask);
1516 ia32_emit_dest_register(env, node, 0);
1518 const char *sreg = ia32_get_reg_name_for_mode(env, smaller_mode, in_reg);
1520 ia32_emit_cstring(env, "\tmov");
1521 ia32_emit_string(env, sign_suffix);
1522 ia32_emit_mode_suffix(env, smaller_mode);
1523 ia32_emit_cstring(env, "l %");
1524 ia32_emit_string(env, sreg);
1525 ia32_emit_cstring(env, ", ");
1526 ia32_emit_dest_register(env, node, 0);
1529 case ia32_AddrModeS: {
1530 ia32_emit_cstring(env, "\tmov");
1531 ia32_emit_string(env, sign_suffix);
1532 ia32_emit_mode_suffix(env, smaller_mode);
1533 ia32_emit_cstring(env, "l %");
1534 ia32_emit_am(env, node);
1535 ia32_emit_cstring(env, ", ");
1536 ia32_emit_dest_register(env, node, 0);
1540 assert(0 && "unsupported op type for Conv");
1542 ia32_emit_finish_line(env, node);
1546 * Emits code for an 8Bit Int conversion.
1548 void emit_ia32_Conv_I2I8Bit(ia32_emit_env_t *env, const ir_node *node) {
1549 emit_ia32_Conv_I2I(env, node);
1553 /*******************************************
1556 * | |__ ___ _ __ ___ __| | ___ ___
1557 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1558 * | |_) | __/ | | | (_) | (_| | __/\__ \
1559 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1561 *******************************************/
1564 * Emits a backend call
1566 static void emit_be_Call(ia32_emit_env_t *env, const ir_node *node) {
1567 ir_entity *ent = be_Call_get_entity(node);
1569 ia32_emit_cstring(env, "\tcall ");
1571 ia32_emit_string(env, get_entity_ld_name(ent));
1573 ia32_emit_char(env, '*');
1574 ia32_emit_dest_register(env, get_irn_n(node, be_pos_Call_ptr), 0);
1576 ia32_emit_finish_line(env, node);
1580 * Emits code to increase stack pointer.
1582 static void emit_be_IncSP(ia32_emit_env_t *env, const ir_node *node) {
1583 int offs = be_get_IncSP_offset(node);
1589 ia32_emit_cstring(env, "\tsubl $");
1590 ia32_emit_irprintf(env, "%u, ", offs);
1591 ia32_emit_source_register(env, node, 0);
1593 ia32_emit_cstring(env, "\taddl $");
1594 ia32_emit_irprintf(env, "%u, ", -offs);
1595 ia32_emit_source_register(env, node, 0);
1597 ia32_emit_finish_line(env, node);
1601 * Emits code to set stack pointer.
1603 static void emit_be_SetSP(ia32_emit_env_t *env, const ir_node *node) {
1604 ia32_emit_cstring(env, "\tmovl ");
1605 ia32_emit_source_register(env, node, 2);
1606 ia32_emit_cstring(env, ", ");
1607 ia32_emit_dest_register(env, node, 0);
1608 ia32_emit_finish_line(env, node);
1612 * Emits code for Copy/CopyKeep.
1614 static void Copy_emitter(ia32_emit_env_t *env, const ir_node *node, const ir_node *op) {
1615 const arch_env_t *aenv = env->arch_env;
1617 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, node), arch_get_irn_register(aenv, op)) ||
1618 arch_register_type_is(arch_get_irn_register(aenv, op), virtual))
1621 if (mode_is_float(get_irn_mode(node))) {
1622 ia32_emit_cstring(env, "\tmovsd ");
1623 ia32_emit_source_register(env, node, 0);
1624 ia32_emit_cstring(env, ", ");
1625 ia32_emit_dest_register(env, node, 0);
1627 ia32_emit_cstring(env, "\tmovl ");
1628 ia32_emit_source_register(env, node, 0);
1629 ia32_emit_cstring(env, ", ");
1630 ia32_emit_dest_register(env, node, 0);
1632 ia32_emit_finish_line(env, node);
1635 static void emit_be_Copy(ia32_emit_env_t *env, const ir_node *node) {
1636 Copy_emitter(env, node, be_get_Copy_op(node));
1639 static void emit_be_CopyKeep(ia32_emit_env_t *env, const ir_node *node) {
1640 Copy_emitter(env, node, be_get_CopyKeep_op(node));
1644 * Emits code for exchange.
1646 static void emit_be_Perm(ia32_emit_env_t *env, const ir_node *node) {
1647 const arch_register_t *in1, *in2;
1648 const arch_register_class_t *cls1, *cls2;
1650 in1 = arch_get_irn_register(env->arch_env, get_irn_n(node, 0));
1651 in2 = arch_get_irn_register(env->arch_env, get_irn_n(node, 1));
1653 cls1 = arch_register_get_class(in1);
1654 cls2 = arch_register_get_class(in2);
1656 assert(cls1 == cls2 && "Register class mismatch at Perm");
1658 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1660 if(emit_env->isa->opt_arch == arch_athlon) {
1661 // xchg commands are Vector path on athlons and therefore stall the DirectPath pipeline
1662 // it is often beneficial to use the 3 xor trick instead of an xchg
1664 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1666 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %2S, %1S", irn, irn);
1668 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xor %1S, %2S", irn, irn);
1671 ia32_emit_cstring(env, "\txchg ");
1672 ia32_emit_source_register(env, node, 1);
1673 ia32_emit_cstring(env, ", ");
1674 ia32_emit_source_register(env, node, 0);
1675 ia32_emit_finish_line(env, node);
1679 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1680 ia32_emit_cstring(env, "\tpxorq ");
1681 ia32_emit_source_register(env, node, 1);
1682 ia32_emit_cstring(env, ", ");
1683 ia32_emit_source_register(env, node, 0);
1684 ia32_emit_finish_line(env, NULL);
1686 ia32_emit_cstring(env, "\tpxorq ");
1687 ia32_emit_source_register(env, node, 0);
1688 ia32_emit_cstring(env, ", ");
1689 ia32_emit_source_register(env, node, 1);
1690 ia32_emit_finish_line(env, NULL);
1692 ia32_emit_cstring(env, "\tpxorq ");
1693 ia32_emit_source_register(env, node, 1);
1694 ia32_emit_cstring(env, ", ");
1695 ia32_emit_source_register(env, node, 0);
1696 ia32_emit_finish_line(env, node);
1697 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1699 } else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1705 * Emits code for Constant loading.
1707 static void emit_ia32_Const(ia32_emit_env_t *env, const ir_node *node) {
1708 ir_mode *mode = get_irn_mode(node);
1709 ia32_immop_type_t imm_tp = get_ia32_immop_type(node);
1711 if (imm_tp == ia32_ImmSymConst) {
1712 ia32_emit_cstring(env, "\tmovl $");
1713 ia32_emit_immediate(env, node);
1714 ia32_emit_cstring(env, ", ");
1715 ia32_emit_dest_register(env, node, 0);
1717 tarval *tv = get_ia32_Immop_tarval(node);
1718 assert(mode == mode_Iu);
1719 /* beware: in some rare cases mode is mode_b which has no tarval_null() */
1720 if (tarval_is_null(tv)) {
1721 if (env->isa->opt_arch == arch_pentium_4) {
1722 /* P4 prefers sub r, r, others xor r, r */
1723 ia32_emit_cstring(env, "\tsubl ");
1725 ia32_emit_cstring(env, "\txorl ");
1727 ia32_emit_dest_register(env, node, 0);
1728 ia32_emit_cstring(env, ", ");
1729 ia32_emit_dest_register(env, node, 0);
1731 ia32_emit_cstring(env, "\tmovl $");
1732 ia32_emit_immediate(env, node);
1733 ia32_emit_cstring(env, ", ");
1734 ia32_emit_dest_register(env, node, 0);
1737 ia32_emit_finish_line(env, node);
1741 * Emits code to load the TLS base
1743 static void emit_ia32_LdTls(ia32_emit_env_t *env, const ir_node *node) {
1744 ia32_emit_cstring(env, "\tmovl %gs:0, ");
1745 ia32_emit_dest_register(env, node, 0);
1746 ia32_emit_finish_line(env, node);
1749 static void emit_be_Return(ia32_emit_env_t *env, const ir_node *node) {
1750 ia32_emit_cstring(env, "\tret");
1751 ia32_emit_finish_line(env, node);
1754 static void emit_Nothing(ia32_emit_env_t *env, const ir_node *node) {
1758 /***********************************************************************************
1761 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1762 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1763 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1764 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1766 ***********************************************************************************/
1769 * Enters the emitter functions for handled nodes into the generic
1770 * pointer of an opcode.
1772 static void ia32_register_emitters(void) {
1774 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1775 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1776 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1777 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1778 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1779 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1781 /* first clear the generic function pointer for all ops */
1782 clear_irp_opcodes_generic_func();
1784 /* register all emitter functions defined in spec */
1785 ia32_register_spec_emitters();
1787 /* other ia32 emitter functions */
1793 IA32_EMIT(PsiCondCMov);
1795 IA32_EMIT(PsiCondSet);
1796 IA32_EMIT(SwitchJmp);
1799 IA32_EMIT(Conv_I2FP);
1800 IA32_EMIT(Conv_FP2I);
1801 IA32_EMIT(Conv_FP2FP);
1802 IA32_EMIT(Conv_I2I);
1803 IA32_EMIT(Conv_I2I8Bit);
1808 IA32_EMIT(xCmpCMov);
1809 IA32_EMIT(xCondJmp);
1810 IA32_EMIT2(fcomJmp, x87CondJmp);
1811 IA32_EMIT2(fcompJmp, x87CondJmp);
1812 IA32_EMIT2(fcomppJmp, x87CondJmp);
1813 IA32_EMIT2(fcomrJmp, x87CondJmp);
1814 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1815 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1817 /* benode emitter */
1843 static const char *last_name = NULL;
1844 static unsigned last_line = -1;
1845 static unsigned num = -1;
1848 * Emit the debug support for node node.
1850 static void ia32_emit_dbg(ia32_emit_env_t *env, const ir_node *node) {
1851 dbg_info *db = get_irn_dbg_info(node);
1853 const char *fname = be_retrieve_dbg_info(db, &lineno);
1855 if (! env->cg->birg->main_env->options->stabs_debug_support)
1859 if (last_name != fname) {
1861 be_dbg_include_begin(env->cg->birg->main_env->db_handle, fname);
1864 if (last_line != lineno) {
1868 snprintf(name, sizeof(name), ".LM%u", ++num);
1870 be_dbg_line(env->cg->birg->main_env->db_handle, lineno, name);
1871 fprintf(F, "%s:\n", name);
1876 typedef void (*emit_func_ptr) (ia32_emit_env_t *, const ir_node *);
1879 * Emits code for a node.
1881 static void ia32_emit_node(ia32_emit_env_t *env, const ir_node *node) {
1882 ir_op *op = get_irn_op(node);
1883 DEBUG_ONLY(firm_dbg_module_t *mod = env->mod;)
1885 DBG((mod, LEVEL_1, "emitting code for %+F\n", node));
1887 if (op->ops.generic) {
1888 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1889 ia32_emit_dbg(env, node);
1890 (*func) (env, node);
1892 emit_Nothing(env, node);
1893 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", node, node);
1898 * Emits gas alignment directives
1900 static void ia32_emit_alignment(ia32_emit_env_t *env, unsigned align, unsigned skip) {
1901 ia32_emit_cstring(env, "\t.p2align ");
1902 ia32_emit_irprintf(env, "%u,,%u\n", align, skip);
1903 ia32_write_line(env);
1907 * Emits gas alignment directives for Functions depended on cpu architecture.
1909 static void ia32_emit_align_func(ia32_emit_env_t *env, cpu_support cpu) {
1911 unsigned maximum_skip;
1926 maximum_skip = (1 << align) - 1;
1927 ia32_emit_alignment(env, align, maximum_skip);
1931 * Emits gas alignment directives for Labels depended on cpu architecture.
1933 static void ia32_emit_align_label(ia32_emit_env_t *env, cpu_support cpu) {
1934 unsigned align; unsigned maximum_skip;
1949 maximum_skip = (1 << align) - 1;
1950 ia32_emit_alignment(env, align, maximum_skip);
1953 static int is_first_loop_block(ia32_emit_env_t *env, ir_node *block, ir_node *prev_block) {
1954 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
1955 double block_freq, prev_freq;
1956 static const double DELTA = .0001;
1957 cpu_support cpu = env->isa->opt_arch;
1959 if(exec_freq == NULL)
1961 if(cpu == arch_i386 || cpu == arch_i486)
1964 block_freq = get_block_execfreq(exec_freq, block);
1965 prev_freq = get_block_execfreq(exec_freq, prev_block);
1967 if(block_freq < DELTA || prev_freq < DELTA)
1970 block_freq /= prev_freq;
1974 case arch_athlon_64:
1976 return block_freq > 3;
1981 return block_freq > 2;
1985 * Walks over the nodes in a block connected by scheduling edges
1986 * and emits code for each node.
1988 static void ia32_gen_block(ia32_emit_env_t *env, ir_node *block, ir_node *last_block) {
1989 ir_graph *irg = get_irn_irg(block);
1990 ir_node *start_block = get_irg_start_block(irg);
1992 const ir_node *node;
1995 assert(is_Block(block));
1997 if (block == start_block)
2000 if (need_label && get_irn_arity(block) == 1) {
2001 ir_node *pred_block = get_Block_cfgpred_block(block, 0);
2003 if (pred_block == last_block && get_irn_n_edges_kind(pred_block, EDGE_KIND_BLOCK) <= 2)
2007 /* special case: if one of our cfg preds is a switch-jmp we need a label, */
2008 /* otherwise there might be jump table entries jumping to */
2009 /* non-existent (omitted) labels */
2010 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2011 ir_node *pred = get_Block_cfgpred(block, i);
2013 if (is_Proj(pred)) {
2014 assert(get_irn_mode(pred) == mode_X);
2015 if (is_ia32_SwitchJmp(get_Proj_pred(pred))) {
2025 ir_exec_freq *exec_freq = env->cg->birg->exec_freq;
2027 /* align the loop headers */
2028 if (! is_first_loop_block(env, block, last_block)) {
2029 /* align blocks where the previous block has no fallthrough */
2030 arity = get_irn_arity(block);
2032 for (i = 0; i < arity; ++i) {
2033 ir_node *predblock = get_Block_cfgpred_block(block, i);
2035 if (predblock == last_block) {
2043 ia32_emit_align_label(env, env->isa->opt_arch);
2045 ia32_emit_cstring(env, BLOCK_PREFIX);
2046 ia32_emit_irprintf(env, "%d:", get_irn_node_nr(block));
2047 ia32_pad_comment(env);
2048 ia32_emit_cstring(env, " /* preds:");
2050 /* emit list of pred blocks in comment */
2051 arity = get_irn_arity(block);
2052 for (i = 0; i < arity; ++i) {
2053 ir_node *predblock = get_Block_cfgpred_block(block, i);
2054 ia32_emit_irprintf(env, " %d", get_irn_node_nr(predblock));
2057 if (exec_freq != NULL) {
2058 ia32_emit_irprintf(env, " freq: %f", get_block_execfreq(exec_freq, block));
2060 ia32_emit_cstring(env, " */\n");
2061 ia32_write_line(env);
2064 /* emit the contents of the block */
2065 ia32_emit_dbg(env, block);
2066 sched_foreach(block, node) {
2067 ia32_emit_node(env, node);
2072 * Emits code for function start.
2074 static void ia32_emit_func_prolog(ia32_emit_env_t *env, ir_graph *irg) {
2076 ir_entity *irg_ent = get_irg_entity(irg);
2077 const char *irg_name = get_entity_ld_name(irg_ent);
2078 cpu_support cpu = env->isa->opt_arch;
2079 const be_irg_t *birg = env->cg->birg;
2082 ia32_switch_section(F, SECTION_TEXT);
2083 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2084 ia32_emit_align_func(env, cpu);
2085 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2086 fprintf(F, ".globl %s\n", irg_name);
2088 ia32_dump_function_object(F, irg_name);
2089 fprintf(F, "%s:\n", irg_name);
2093 * Emits code for function end
2095 static void ia32_emit_func_epilog(ia32_emit_env_t *env, ir_graph *irg) {
2096 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2097 const be_irg_t *birg = env->cg->birg;
2100 ia32_dump_function_size(F, irg_name);
2101 be_dbg_method_end(birg->main_env->db_handle);
2107 * Sets labels for control flow nodes (jump target)
2109 static void ia32_gen_labels(ir_node *block, void *data) {
2111 int n = get_Block_n_cfgpreds(block);
2113 for (n--; n >= 0; n--) {
2114 pred = get_Block_cfgpred(block, n);
2115 set_irn_link(pred, block);
2120 * Main driver. Emits the code for one routine.
2122 void ia32_gen_routine(ia32_code_gen_t *cg, FILE *F, ir_graph *irg) {
2123 ia32_emit_env_t env;
2125 ir_node *last_block = NULL;
2127 struct obstack obst;
2129 obstack_init(&obst);
2132 env.arch_env = cg->arch_env;
2134 env.isa = (ia32_isa_t *)cg->arch_env->isa;
2137 FIRM_DBG_REGISTER(env.mod, "firm.be.ia32.emitter");
2139 /* set the global arch_env (needed by print hooks) */
2140 arch_env = cg->arch_env;
2142 ia32_register_emitters();
2144 ia32_emit_func_prolog(&env, irg);
2145 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &env);
2147 n = ARR_LEN(cg->blk_sched);
2148 for (i = 0; i < n;) {
2151 block = cg->blk_sched[i];
2153 next_bl = i < n ? cg->blk_sched[i] : NULL;
2155 /* set here the link. the emitter expects to find the next block here */
2156 set_irn_link(block, next_bl);
2157 ia32_gen_block(&env, block, last_block);
2161 ia32_emit_func_epilog(&env, irg);