2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
55 #include "ia32_emitter.h"
56 #include "gen_ia32_emitter.h"
57 #include "gen_ia32_regalloc_if.h"
58 #include "ia32_nodes_attr.h"
59 #include "ia32_new_nodes.h"
60 #include "ia32_map_regs.h"
61 #include "ia32_architecture.h"
62 #include "bearch_ia32_t.h"
64 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
66 #define BLOCK_PREFIX ".L"
68 #define SNPRINTF_BUF_LEN 128
70 static const arch_env_t *arch_env;
71 static const ia32_isa_t *isa;
72 static ia32_code_gen_t *cg;
75 * Returns the register at in position pos.
77 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
80 const arch_register_t *reg = NULL;
82 assert(get_irn_arity(irn) > pos && "Invalid IN position");
84 /* The out register of the operator at position pos is the
85 in register we need. */
86 op = get_irn_n(irn, pos);
88 reg = arch_get_irn_register(arch_env, op);
90 assert(reg && "no in register found");
92 if(reg == &ia32_gp_regs[REG_GP_NOREG])
93 panic("trying to emit noreg for %+F input %d", irn, pos);
95 /* in case of unknown register: just return a valid register */
96 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
97 const arch_register_req_t *req;
99 /* ask for the requirements */
100 req = arch_get_register_req(arch_env, irn, pos);
102 if (arch_register_req_is(req, limited)) {
103 /* in case of limited requirements: get the first allowed register */
104 unsigned idx = rbitset_next(req->limited, 0, 1);
105 reg = arch_register_for_index(req->cls, idx);
107 /* otherwise get first register in class */
108 reg = arch_register_for_index(req->cls, 0);
116 * Returns the register at out position pos.
118 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
121 const arch_register_t *reg = NULL;
123 /* 1st case: irn is not of mode_T, so it has only */
124 /* one OUT register -> good */
125 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
126 /* Proj with the corresponding projnum for the register */
128 if (get_irn_mode(irn) != mode_T) {
130 reg = arch_get_irn_register(arch_env, irn);
131 } else if (is_ia32_irn(irn)) {
132 reg = get_ia32_out_reg(irn, pos);
134 const ir_edge_t *edge;
136 foreach_out_edge(irn, edge) {
137 proj = get_edge_src_irn(edge);
138 assert(is_Proj(proj) && "non-Proj from mode_T node");
139 if (get_Proj_proj(proj) == pos) {
140 reg = arch_get_irn_register(arch_env, proj);
146 assert(reg && "no out register found");
151 * Add a number to a prefix. This number will not be used a second time.
153 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
155 static unsigned long id = 0;
156 snprintf(buf, buflen, "%s%lu", prefix, ++id);
160 /*************************************************************
162 * (_) | | / _| | | | |
163 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
164 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
165 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
166 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
169 *************************************************************/
171 static void emit_8bit_register(const arch_register_t *reg)
173 const char *reg_name = arch_register_get_name(reg);
176 be_emit_char(reg_name[1]);
180 static void emit_16bit_register(const arch_register_t *reg)
182 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
185 be_emit_string(reg_name);
188 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
190 const char *reg_name;
193 int size = get_mode_size_bits(mode);
195 emit_8bit_register(reg);
197 } else if(size == 16) {
198 emit_16bit_register(reg);
201 assert(mode_is_float(mode) || size == 32);
205 reg_name = arch_register_get_name(reg);
208 be_emit_string(reg_name);
211 void ia32_emit_source_register(const ir_node *node, int pos)
213 const arch_register_t *reg = get_in_reg(node, pos);
215 emit_register(reg, NULL);
218 static void emit_ia32_Immediate(const ir_node *node);
220 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
222 const arch_register_t *reg;
223 ir_node *in = get_irn_n(node, pos);
224 if(is_ia32_Immediate(in)) {
225 emit_ia32_Immediate(in);
229 reg = get_in_reg(node, pos);
230 emit_8bit_register(reg);
233 void ia32_emit_dest_register(const ir_node *node, int pos)
235 const arch_register_t *reg = get_out_reg(node, pos);
237 emit_register(reg, NULL);
240 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
242 const arch_register_t *reg = get_out_reg(node, pos);
244 emit_register(reg, mode_Bu);
247 void ia32_emit_x87_register(const ir_node *node, int pos)
249 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
253 be_emit_string(attr->x87[pos]->name);
256 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
258 if(mode_is_float(mode)) {
259 switch(get_mode_size_bits(mode)) {
260 case 32: be_emit_char('s'); return;
261 case 64: be_emit_char('l'); return;
263 case 96: be_emit_char('t'); return;
266 assert(mode_is_int(mode) || mode_is_reference(mode));
267 switch(get_mode_size_bits(mode)) {
268 case 64: be_emit_cstring("ll"); return;
269 /* gas docu says q is the suffix but gcc, objdump and icc use
271 case 32: be_emit_char('l'); return;
272 case 16: be_emit_char('w'); return;
273 case 8: be_emit_char('b'); return;
276 panic("Can't output mode_suffix for %+F\n", mode);
279 void ia32_emit_mode_suffix(const ir_node *node)
281 ir_mode *mode = get_ia32_ls_mode(node);
285 ia32_emit_mode_suffix_mode(mode);
288 void ia32_emit_x87_mode_suffix(const ir_node *node)
290 ir_mode *mode = get_ia32_ls_mode(node);
291 assert(mode != NULL);
292 /* we only need to emit the mode on address mode */
293 if(get_ia32_op_type(node) != ia32_Normal)
294 ia32_emit_mode_suffix_mode(mode);
298 char get_xmm_mode_suffix(ir_mode *mode)
300 assert(mode_is_float(mode));
301 switch(get_mode_size_bits(mode)) {
312 void ia32_emit_xmm_mode_suffix(const ir_node *node)
314 ir_mode *mode = get_ia32_ls_mode(node);
315 assert(mode != NULL);
317 be_emit_char(get_xmm_mode_suffix(mode));
320 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
322 ir_mode *mode = get_ia32_ls_mode(node);
323 assert(mode != NULL);
324 be_emit_char(get_xmm_mode_suffix(mode));
327 void ia32_emit_extend_suffix(const ir_mode *mode)
329 if(get_mode_size_bits(mode) == 32)
331 if(mode_is_signed(mode)) {
339 void ia32_emit_function_object(const char *name)
341 switch (be_gas_flavour) {
342 case GAS_FLAVOUR_NORMAL:
343 be_emit_cstring("\t.type\t");
344 be_emit_string(name);
345 be_emit_cstring(", @function\n");
346 be_emit_write_line();
348 case GAS_FLAVOUR_MINGW:
349 be_emit_cstring("\t.def\t");
350 be_emit_string(name);
351 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
352 be_emit_write_line();
360 void ia32_emit_function_size(const char *name)
362 switch (be_gas_flavour) {
363 case GAS_FLAVOUR_NORMAL:
364 be_emit_cstring("\t.size\t");
365 be_emit_string(name);
366 be_emit_cstring(", .-");
367 be_emit_string(name);
369 be_emit_write_line();
377 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
379 ir_node *in = get_irn_n(node, pos);
380 if(is_ia32_Immediate(in)) {
381 emit_ia32_Immediate(in);
383 const ir_mode *mode = get_ia32_ls_mode(node);
384 const arch_register_t *reg = get_in_reg(node, pos);
385 emit_register(reg, mode);
390 * Emits registers and/or address mode of a binary operation.
392 void ia32_emit_binop(const ir_node *node) {
393 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
394 const ir_mode *mode = get_ia32_ls_mode(node);
395 const arch_register_t *reg_left;
397 switch(get_ia32_op_type(node)) {
399 reg_left = get_in_reg(node, n_ia32_binary_left);
400 if(is_ia32_Immediate(right_op)) {
401 emit_ia32_Immediate(right_op);
402 be_emit_cstring(", ");
403 emit_register(reg_left, mode);
406 const arch_register_t *reg_right
407 = get_in_reg(node, n_ia32_binary_right);
408 emit_register(reg_right, mode);
409 be_emit_cstring(", ");
410 emit_register(reg_left, mode);
414 if(is_ia32_Immediate(right_op)) {
415 emit_ia32_Immediate(right_op);
416 be_emit_cstring(", ");
419 reg_left = get_in_reg(node, n_ia32_binary_left);
421 be_emit_cstring(", ");
422 emit_register(reg_left, mode);
426 panic("DestMode can't be output by %%binop anymore");
429 assert(0 && "unsupported op type");
434 * Emits registers and/or address mode of a binary operation.
436 void ia32_emit_x87_binop(const ir_node *node) {
437 switch(get_ia32_op_type(node)) {
440 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
441 const arch_register_t *in1 = x87_attr->x87[0];
442 const arch_register_t *in2 = x87_attr->x87[1];
443 const arch_register_t *out = x87_attr->x87[2];
444 const arch_register_t *in;
446 in = out ? ((out == in2) ? in1 : in2) : in2;
447 out = out ? out : in1;
450 be_emit_string(arch_register_get_name(in));
451 be_emit_cstring(", %");
452 be_emit_string(arch_register_get_name(out));
460 assert(0 && "unsupported op type");
464 void ia32_emit_am_or_dest_register(const ir_node *node,
466 if(get_ia32_op_type(node) == ia32_Normal) {
467 ia32_emit_dest_register(node, pos);
469 assert(get_ia32_op_type(node) == ia32_AddrModeD);
475 * Emits registers and/or address mode of a unary operation.
477 void ia32_emit_unop(const ir_node *node, int pos) {
480 switch(get_ia32_op_type(node)) {
482 op = get_irn_n(node, pos);
483 if (is_ia32_Immediate(op)) {
484 emit_ia32_Immediate(op);
486 ia32_emit_source_register(node, pos);
494 assert(0 && "unsupported op type");
499 * Emits address mode.
501 void ia32_emit_am(const ir_node *node) {
502 ir_entity *ent = get_ia32_am_sc(node);
503 int offs = get_ia32_am_offs_int(node);
504 ir_node *base = get_irn_n(node, 0);
505 int has_base = !is_ia32_NoReg_GP(base);
506 ir_node *index = get_irn_n(node, 1);
507 int has_index = !is_ia32_NoReg_GP(index);
509 /* just to be sure... */
510 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
516 set_entity_backend_marked(ent, 1);
517 id = get_entity_ld_ident(ent);
518 if (is_ia32_am_sc_sign(node))
522 if(get_entity_owner(ent) == get_tls_type()) {
523 if (get_entity_visibility(ent) == visibility_external_allocated) {
524 be_emit_cstring("@INDNTPOFF");
526 be_emit_cstring("@NTPOFF");
533 be_emit_irprintf("%+d", offs);
535 be_emit_irprintf("%d", offs);
539 if (has_base || has_index) {
544 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
545 emit_register(reg, NULL);
548 /* emit index + scale */
550 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
553 emit_register(reg, NULL);
555 scale = get_ia32_am_scale(node);
557 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
563 /* special case if nothing is set */
564 if(ent == NULL && offs == 0 && !has_base && !has_index) {
569 static void emit_ia32_IMul(const ir_node *node)
571 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
572 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
574 be_emit_cstring("\timul");
575 ia32_emit_mode_suffix(node);
578 ia32_emit_binop(node);
580 /* do we need the 3-address form? */
581 if(is_ia32_NoReg_GP(left) ||
582 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
583 be_emit_cstring(", ");
584 emit_register(out_reg, get_ia32_ls_mode(node));
586 be_emit_finish_line_gas(node);
589 /*************************************************
592 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
593 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
594 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
595 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
597 *************************************************/
600 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
603 * coding of conditions
605 struct cmp2conditon_t {
611 * positive conditions for signed compares
613 static const struct cmp2conditon_t cmp2condition_s[] = {
614 { NULL, pn_Cmp_False }, /* always false */
615 { "e", pn_Cmp_Eq }, /* == */
616 { "l", pn_Cmp_Lt }, /* < */
617 { "le", pn_Cmp_Le }, /* <= */
618 { "g", pn_Cmp_Gt }, /* > */
619 { "ge", pn_Cmp_Ge }, /* >= */
620 { "ne", pn_Cmp_Lg }, /* != */
621 { NULL, pn_Cmp_Leg}, /* always true */
625 * positive conditions for unsigned compares
627 static const struct cmp2conditon_t cmp2condition_u[] = {
628 { NULL, pn_Cmp_False }, /* always false */
629 { "e", pn_Cmp_Eq }, /* == */
630 { "b", pn_Cmp_Lt }, /* < */
631 { "be", pn_Cmp_Le }, /* <= */
632 { "a", pn_Cmp_Gt }, /* > */
633 { "ae", pn_Cmp_Ge }, /* >= */
634 { "ne", pn_Cmp_Lg }, /* != */
635 { NULL, pn_Cmp_Leg }, /* always true */
639 ia32_pn_Cmp_unsigned = 0x1000,
640 ia32_pn_Cmp_float = 0x2000,
644 * walks up a tree of copies/perms/spills/reloads to find the original value
645 * that is moved around
647 static ir_node *find_original_value(ir_node *node)
649 inc_irg_visited(current_ir_graph);
651 mark_irn_visited(node);
652 if(be_is_Copy(node)) {
653 node = be_get_Copy_op(node);
654 } else if(be_is_CopyKeep(node)) {
655 node = be_get_CopyKeep_op(node);
656 } else if(is_Proj(node)) {
657 ir_node *pred = get_Proj_pred(node);
658 if(be_is_Perm(pred)) {
659 node = get_irn_n(pred, get_Proj_proj(node));
660 } else if(be_is_MemPerm(pred)) {
661 node = get_irn_n(pred, get_Proj_proj(node) + 1);
662 } else if(is_ia32_Load(pred)) {
663 node = get_irn_n(pred, n_ia32_Load_mem);
667 } else if(is_ia32_Store(node)) {
668 node = get_irn_n(node, n_ia32_Store_val);
669 } else if(is_Phi(node)) {
671 arity = get_irn_arity(node);
672 for(i = 0; i < arity; ++i) {
673 ir_node *in = get_irn_n(node, i);
686 static int determine_final_pnc(const ir_node *node, int flags_pos,
689 ir_node *flags = get_irn_n(node, flags_pos);
690 const ia32_attr_t *flags_attr;
691 flags = skip_Proj(flags);
693 if(is_ia32_Sahf(flags)) {
694 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
695 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
696 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
697 cmp = find_original_value(cmp);
698 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
699 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
702 flags_attr = get_ia32_attr_const(cmp);
703 if(flags_attr->data.ins_permuted)
704 pnc = get_mirrored_pnc(pnc);
705 pnc |= ia32_pn_Cmp_float;
706 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
707 || is_ia32_Fucompi(flags)) {
708 flags_attr = get_ia32_attr_const(flags);
710 if(flags_attr->data.ins_permuted)
711 pnc = get_mirrored_pnc(pnc);
712 pnc |= ia32_pn_Cmp_float;
715 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
716 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
718 flags_attr = get_ia32_attr_const(flags);
720 if(flags_attr->data.ins_permuted)
721 pnc = get_mirrored_pnc(pnc);
722 if(flags_attr->data.cmp_unsigned)
723 pnc |= ia32_pn_Cmp_unsigned;
729 static void ia32_emit_cmp_suffix(int pnc)
733 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
735 assert(cmp2condition_u[pnc].num == pnc);
736 str = cmp2condition_u[pnc].name;
739 assert(cmp2condition_s[pnc].num == pnc);
740 str = cmp2condition_s[pnc].name;
746 void ia32_emit_cmp_suffix_node(const ir_node *node,
749 const ia32_attr_t *attr = get_ia32_attr_const(node);
751 pn_Cmp pnc = get_ia32_condcode(node);
753 pnc = determine_final_pnc(node, flags_pos, pnc);
754 if(attr->data.ins_permuted) {
755 if(pnc & ia32_pn_Cmp_float) {
756 pnc = get_negated_pnc(pnc, mode_F);
758 pnc = get_negated_pnc(pnc, mode_Iu);
762 ia32_emit_cmp_suffix(pnc);
766 * Returns the target block for a control flow node.
769 ir_node *get_cfop_target_block(const ir_node *irn) {
770 return get_irn_link(irn);
774 * Emits a block label for the given block.
777 void ia32_emit_block_name(const ir_node *block)
779 if (has_Block_label(block)) {
780 be_emit_string(be_gas_label_prefix());
781 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
783 be_emit_cstring(BLOCK_PREFIX);
784 be_emit_irprintf("%d", get_irn_node_nr(block));
789 * Emits the target label for a control flow node.
791 static void ia32_emit_cfop_target(const ir_node *node)
793 ir_node *block = get_cfop_target_block(node);
795 ia32_emit_block_name(block);
798 /** Return the next block in Block schedule */
799 static ir_node *next_blk_sched(const ir_node *block)
801 return get_irn_link(block);
805 * Returns the Proj with projection number proj and NOT mode_M
807 static ir_node *get_proj(const ir_node *node, long proj) {
808 const ir_edge_t *edge;
811 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
813 foreach_out_edge(node, edge) {
814 src = get_edge_src_irn(edge);
816 assert(is_Proj(src) && "Proj expected");
817 if (get_irn_mode(src) == mode_M)
820 if (get_Proj_proj(src) == proj)
827 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
829 static void emit_ia32_Jcc(const ir_node *node)
831 const ir_node *proj_true;
832 const ir_node *proj_false;
833 const ir_node *block;
834 const ir_node *next_block;
835 pn_Cmp pnc = get_ia32_condcode(node);
837 pnc = determine_final_pnc(node, 0, pnc);
840 proj_true = get_proj(node, pn_ia32_Jcc_true);
841 assert(proj_true && "Jcc without true Proj");
843 proj_false = get_proj(node, pn_ia32_Jcc_false);
844 assert(proj_false && "Jcc without false Proj");
846 block = get_nodes_block(node);
847 next_block = next_blk_sched(block);
849 if (get_cfop_target_block(proj_true) == next_block) {
850 /* exchange both proj's so the second one can be omitted */
851 const ir_node *t = proj_true;
853 proj_true = proj_false;
855 if(pnc & ia32_pn_Cmp_float) {
856 pnc = get_negated_pnc(pnc, mode_F);
858 pnc = get_negated_pnc(pnc, mode_Iu);
862 if (pnc & ia32_pn_Cmp_float) {
863 /* Some floating point comparisons require a test of the parity flag,
864 * which indicates that the result is unordered */
867 be_emit_cstring("\tjp ");
868 ia32_emit_cfop_target(proj_true);
869 be_emit_finish_line_gas(proj_true);
873 be_emit_cstring("\tjnp ");
874 ia32_emit_cfop_target(proj_true);
875 be_emit_finish_line_gas(proj_true);
881 be_emit_cstring("\tjp ");
882 ia32_emit_cfop_target(proj_false);
883 be_emit_finish_line_gas(proj_false);
889 be_emit_cstring("\tjp ");
890 ia32_emit_cfop_target(proj_true);
891 be_emit_finish_line_gas(proj_true);
899 be_emit_cstring("\tj");
900 ia32_emit_cmp_suffix(pnc);
902 ia32_emit_cfop_target(proj_true);
903 be_emit_finish_line_gas(proj_true);
906 /* the second Proj might be a fallthrough */
907 if (get_cfop_target_block(proj_false) != next_block) {
908 be_emit_cstring("\tjmp ");
909 ia32_emit_cfop_target(proj_false);
910 be_emit_finish_line_gas(proj_false);
912 be_emit_cstring("\t/* fallthrough to ");
913 ia32_emit_cfop_target(proj_false);
914 be_emit_cstring(" */");
915 be_emit_finish_line_gas(proj_false);
919 static void emit_ia32_CMov(const ir_node *node)
921 const ia32_attr_t *attr = get_ia32_attr_const(node);
922 int ins_permuted = attr->data.ins_permuted;
923 const arch_register_t *out = arch_get_irn_register(arch_env, node);
924 pn_Cmp pnc = get_ia32_condcode(node);
925 const arch_register_t *in_true;
926 const arch_register_t *in_false;
928 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
930 in_true = arch_get_irn_register(arch_env,
931 get_irn_n(node, n_ia32_CMov_val_true));
932 in_false = arch_get_irn_register(arch_env,
933 get_irn_n(node, n_ia32_CMov_val_false));
935 /* should be same constraint fullfilled? */
936 if(out == in_false) {
937 /* yes -> nothing to do */
938 } else if(out == in_true) {
939 const arch_register_t *tmp;
941 assert(get_ia32_op_type(node) == ia32_Normal);
943 ins_permuted = !ins_permuted;
950 be_emit_cstring("\tmovl ");
951 emit_register(in_false, NULL);
952 be_emit_cstring(", ");
953 emit_register(out, NULL);
954 be_emit_finish_line_gas(node);
958 if(pnc & ia32_pn_Cmp_float) {
959 pnc = get_negated_pnc(pnc, mode_F);
961 pnc = get_negated_pnc(pnc, mode_Iu);
965 /* TODO: handling of Nans isn't correct yet */
967 be_emit_cstring("\tcmov");
968 ia32_emit_cmp_suffix(pnc);
970 if(get_ia32_op_type(node) == ia32_AddrModeS) {
973 emit_register(in_true, get_ia32_ls_mode(node));
975 be_emit_cstring(", ");
976 emit_register(out, get_ia32_ls_mode(node));
977 be_emit_finish_line_gas(node);
980 /*********************************************************
983 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
984 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
985 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
986 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
989 *********************************************************/
991 /* jump table entry (target and corresponding number) */
992 typedef struct _branch_t {
997 /* jump table for switch generation */
998 typedef struct _jmp_tbl_t {
999 ir_node *defProj; /**< default target */
1000 long min_value; /**< smallest switch case */
1001 long max_value; /**< largest switch case */
1002 long num_branches; /**< number of jumps */
1003 char *label; /**< label of the jump table */
1004 branch_t *branches; /**< jump array */
1008 * Compare two variables of type branch_t. Used to sort all switch cases
1011 int ia32_cmp_branch_t(const void *a, const void *b) {
1012 branch_t *b1 = (branch_t *)a;
1013 branch_t *b2 = (branch_t *)b;
1015 if (b1->value <= b2->value)
1022 * Emits code for a SwitchJmp (creates a jump table if
1023 * possible otherwise a cmp-jmp cascade). Port from
1026 static void emit_ia32_SwitchJmp(const ir_node *node)
1028 unsigned long interval;
1034 const ir_edge_t *edge;
1036 /* fill the table structure */
1037 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1038 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1040 tbl.num_branches = get_irn_n_edges(node) - 1;
1041 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1042 tbl.min_value = INT_MAX;
1043 tbl.max_value = INT_MIN;
1045 default_pn = get_ia32_condcode(node);
1047 /* go over all proj's and collect them */
1048 foreach_out_edge(node, edge) {
1049 proj = get_edge_src_irn(edge);
1050 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1052 pnc = get_Proj_proj(proj);
1054 /* check for default proj */
1055 if (pnc == default_pn) {
1056 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1059 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1060 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1062 /* create branch entry */
1063 tbl.branches[i].target = proj;
1064 tbl.branches[i].value = pnc;
1069 assert(i == tbl.num_branches);
1071 /* sort the branches by their number */
1072 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1074 /* two-complement's magic make this work without overflow */
1075 interval = tbl.max_value - tbl.min_value;
1077 /* emit the table */
1078 be_emit_cstring("\tcmpl $");
1079 be_emit_irprintf("%u, ", interval);
1080 ia32_emit_source_register(node, 0);
1081 be_emit_finish_line_gas(node);
1083 be_emit_cstring("\tja ");
1084 ia32_emit_cfop_target(tbl.defProj);
1085 be_emit_finish_line_gas(node);
1087 if (tbl.num_branches > 1) {
1089 be_emit_cstring("\tjmp *");
1090 be_emit_string(tbl.label);
1091 be_emit_cstring("(,");
1092 ia32_emit_source_register(node, 0);
1093 be_emit_cstring(",4)");
1094 be_emit_finish_line_gas(node);
1096 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1097 be_emit_cstring("\t.align 4\n");
1098 be_emit_write_line();
1100 be_emit_string(tbl.label);
1101 be_emit_cstring(":\n");
1102 be_emit_write_line();
1104 be_emit_cstring(".long ");
1105 ia32_emit_cfop_target(tbl.branches[0].target);
1106 be_emit_finish_line_gas(NULL);
1108 last_value = tbl.branches[0].value;
1109 for (i = 1; i < tbl.num_branches; ++i) {
1110 while (++last_value < tbl.branches[i].value) {
1111 be_emit_cstring(".long ");
1112 ia32_emit_cfop_target(tbl.defProj);
1113 be_emit_finish_line_gas(NULL);
1115 be_emit_cstring(".long ");
1116 ia32_emit_cfop_target(tbl.branches[i].target);
1117 be_emit_finish_line_gas(NULL);
1119 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1121 /* one jump is enough */
1122 be_emit_cstring("\tjmp ");
1123 ia32_emit_cfop_target(tbl.branches[0].target);
1124 be_emit_finish_line_gas(node);
1134 * Emits code for a unconditional jump.
1136 static void emit_Jmp(const ir_node *node)
1138 ir_node *block, *next_block;
1140 /* for now, the code works for scheduled and non-schedules blocks */
1141 block = get_nodes_block(node);
1143 /* we have a block schedule */
1144 next_block = next_blk_sched(block);
1145 if (get_cfop_target_block(node) != next_block) {
1146 be_emit_cstring("\tjmp ");
1147 ia32_emit_cfop_target(node);
1149 be_emit_cstring("\t/* fallthrough to ");
1150 ia32_emit_cfop_target(node);
1151 be_emit_cstring(" */");
1153 be_emit_finish_line_gas(node);
1156 static void emit_ia32_Immediate(const ir_node *node)
1158 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1161 if(attr->symconst != NULL) {
1162 ident *id = get_entity_ld_ident(attr->symconst);
1168 if(attr->symconst == NULL || attr->offset != 0) {
1169 if(attr->symconst != NULL) {
1170 be_emit_irprintf("%+d", attr->offset);
1172 be_emit_irprintf("0x%X", attr->offset);
1178 * Emit an inline assembler operand.
1180 * @param node the ia32_ASM node
1181 * @param s points to the operand (a %c)
1183 * @return pointer to the first char in s NOT in the current operand
1185 static const char* emit_asm_operand(const ir_node *node, const char *s)
1187 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1188 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1190 const arch_register_t *reg;
1191 const ia32_asm_reg_t *asm_regs = attr->register_map;
1192 const ia32_asm_reg_t *asm_reg;
1193 const char *reg_name;
1202 /* parse modifiers */
1205 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1229 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1230 "'%c' for asm op\n", node, c);
1236 sscanf(s, "%d%n", &num, &p);
1238 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1245 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1246 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1247 "input/output (%+F)\n", node);
1250 asm_reg = & asm_regs[num];
1251 assert(asm_reg->valid);
1254 if(asm_reg->use_input == 0) {
1255 reg = get_out_reg(node, asm_reg->inout_pos);
1257 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1259 /* might be an immediate value */
1260 if(is_ia32_Immediate(pred)) {
1261 emit_ia32_Immediate(pred);
1264 reg = get_in_reg(node, asm_reg->inout_pos);
1267 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1268 "(%+F)\n", num, node);
1272 if(asm_reg->memory) {
1281 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1284 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1287 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1290 panic("Invalid asm op modifier");
1292 be_emit_string(reg_name);
1294 emit_register(reg, asm_reg->mode);
1297 if(asm_reg->memory) {
1305 * Emits code for an ASM pseudo op.
1307 static void emit_ia32_Asm(const ir_node *node)
1309 const void *gen_attr = get_irn_generic_attr_const(node);
1310 const ia32_asm_attr_t *attr
1311 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1312 ident *asm_text = attr->asm_text;
1313 const char *s = get_id_str(asm_text);
1315 be_emit_cstring("# Begin ASM \t");
1316 be_emit_finish_line_gas(node);
1323 s = emit_asm_operand(node, s);
1332 be_emit_write_line();
1334 be_emit_cstring("# End ASM\n");
1335 be_emit_write_line();
1338 /**********************************
1341 * | | ___ _ __ _ _| |_) |
1342 * | | / _ \| '_ \| | | | _ <
1343 * | |___| (_) | |_) | |_| | |_) |
1344 * \_____\___/| .__/ \__, |____/
1347 **********************************/
1350 * Emit movsb/w instructions to make mov count divideable by 4
1352 static void emit_CopyB_prolog(unsigned size) {
1353 be_emit_cstring("\tcld");
1354 be_emit_finish_line_gas(NULL);
1358 be_emit_cstring("\tmovsb");
1359 be_emit_finish_line_gas(NULL);
1362 be_emit_cstring("\tmovsw");
1363 be_emit_finish_line_gas(NULL);
1366 be_emit_cstring("\tmovsb");
1367 be_emit_finish_line_gas(NULL);
1368 be_emit_cstring("\tmovsw");
1369 be_emit_finish_line_gas(NULL);
1375 * Emit rep movsd instruction for memcopy.
1377 static void emit_ia32_CopyB(const ir_node *node)
1379 unsigned size = get_ia32_copyb_size(node);
1381 emit_CopyB_prolog(size);
1383 be_emit_cstring("\trep movsd");
1384 be_emit_finish_line_gas(node);
1388 * Emits unrolled memcopy.
1390 static void emit_ia32_CopyB_i(const ir_node *node)
1392 unsigned size = get_ia32_copyb_size(node);
1394 emit_CopyB_prolog(size & 0x3);
1398 be_emit_cstring("\tmovsd");
1399 be_emit_finish_line_gas(NULL);
1405 /***************************
1409 * | | / _ \| '_ \ \ / /
1410 * | |___| (_) | | | \ V /
1411 * \_____\___/|_| |_|\_/
1413 ***************************/
1416 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1418 static void emit_ia32_Conv_with_FP(const ir_node *node)
1420 ir_mode *ls_mode = get_ia32_ls_mode(node);
1421 int ls_bits = get_mode_size_bits(ls_mode);
1423 be_emit_cstring("\tcvt");
1425 if(is_ia32_Conv_I2FP(node)) {
1427 be_emit_cstring("si2ss");
1429 be_emit_cstring("si2sd");
1431 } else if(is_ia32_Conv_FP2I(node)) {
1433 be_emit_cstring("ss2si");
1435 be_emit_cstring("sd2si");
1438 assert(is_ia32_Conv_FP2FP(node));
1440 be_emit_cstring("sd2ss");
1442 be_emit_cstring("ss2sd");
1447 switch(get_ia32_op_type(node)) {
1449 ia32_emit_source_register(node, n_ia32_unary_op);
1451 case ia32_AddrModeS:
1455 assert(0 && "unsupported op type for Conv");
1457 be_emit_cstring(", ");
1458 ia32_emit_dest_register(node, 0);
1459 be_emit_finish_line_gas(node);
1462 static void emit_ia32_Conv_I2FP(const ir_node *node)
1464 emit_ia32_Conv_with_FP(node);
1467 static void emit_ia32_Conv_FP2I(const ir_node *node)
1469 emit_ia32_Conv_with_FP(node);
1472 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1474 emit_ia32_Conv_with_FP(node);
1478 * Emits code for an Int conversion.
1480 static void emit_ia32_Conv_I2I(const ir_node *node)
1482 const char *sign_suffix;
1483 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1484 int smaller_bits = get_mode_size_bits(smaller_mode);
1486 const arch_register_t *in_reg, *out_reg;
1488 assert(!mode_is_float(smaller_mode));
1489 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1491 signed_mode = mode_is_signed(smaller_mode);
1492 if(smaller_bits == 32) {
1493 // this should not happen as it's no convert
1497 sign_suffix = signed_mode ? "s" : "z";
1500 out_reg = get_out_reg(node, 0);
1502 switch(get_ia32_op_type(node)) {
1504 in_reg = get_in_reg(node, n_ia32_unary_op);
1506 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1507 out_reg == &ia32_gp_regs[REG_EAX] &&
1511 /* argument and result are both in EAX and */
1512 /* signedness is ok: -> use the smaller cwtl opcode */
1513 be_emit_cstring("\tcwtl");
1515 be_emit_cstring("\tmov");
1516 be_emit_string(sign_suffix);
1517 ia32_emit_mode_suffix_mode(smaller_mode);
1518 be_emit_cstring("l ");
1519 emit_register(in_reg, smaller_mode);
1520 be_emit_cstring(", ");
1521 emit_register(out_reg, NULL);
1524 case ia32_AddrModeS: {
1525 be_emit_cstring("\tmov");
1526 be_emit_string(sign_suffix);
1527 ia32_emit_mode_suffix_mode(smaller_mode);
1528 be_emit_cstring("l ");
1530 be_emit_cstring(", ");
1531 emit_register(out_reg, NULL);
1535 assert(0 && "unsupported op type for Conv");
1537 be_emit_finish_line_gas(node);
1541 /*******************************************
1544 * | |__ ___ _ __ ___ __| | ___ ___
1545 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1546 * | |_) | __/ | | | (_) | (_| | __/\__ \
1547 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1549 *******************************************/
1552 * Emits a backend call
1554 static void emit_be_Call(const ir_node *node)
1556 ir_entity *ent = be_Call_get_entity(node);
1558 be_emit_cstring("\tcall ");
1560 set_entity_backend_marked(ent, 1);
1561 be_emit_string(get_entity_ld_name(ent));
1563 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1565 emit_register(reg, NULL);
1567 be_emit_finish_line_gas(node);
1571 * Emits code to increase stack pointer.
1573 static void emit_be_IncSP(const ir_node *node)
1575 int offs = be_get_IncSP_offset(node);
1576 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1582 be_emit_cstring("\tsubl $");
1583 be_emit_irprintf("%u, ", offs);
1584 emit_register(reg, NULL);
1586 be_emit_cstring("\taddl $");
1587 be_emit_irprintf("%u, ", -offs);
1588 emit_register(reg, NULL);
1590 be_emit_finish_line_gas(node);
1594 * Emits code for Copy/CopyKeep.
1596 static void Copy_emitter(const ir_node *node, const ir_node *op)
1598 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1599 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1605 if(is_unknown_reg(in))
1607 /* copies of vf nodes aren't real... */
1608 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1611 mode = get_irn_mode(node);
1612 if (mode == mode_E) {
1613 be_emit_cstring("\tmovsd ");
1614 emit_register(in, NULL);
1615 be_emit_cstring(", ");
1616 emit_register(out, NULL);
1618 be_emit_cstring("\tmovl ");
1619 emit_register(in, NULL);
1620 be_emit_cstring(", ");
1621 emit_register(out, NULL);
1623 be_emit_finish_line_gas(node);
1626 static void emit_be_Copy(const ir_node *node)
1628 Copy_emitter(node, be_get_Copy_op(node));
1631 static void emit_be_CopyKeep(const ir_node *node)
1633 Copy_emitter(node, be_get_CopyKeep_op(node));
1637 * Emits code for exchange.
1639 static void emit_be_Perm(const ir_node *node)
1641 const arch_register_t *in0, *in1;
1642 const arch_register_class_t *cls0, *cls1;
1644 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1645 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1647 cls0 = arch_register_get_class(in0);
1648 cls1 = arch_register_get_class(in1);
1650 assert(cls0 == cls1 && "Register class mismatch at Perm");
1652 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1653 be_emit_cstring("\txchg ");
1654 emit_register(in1, NULL);
1655 be_emit_cstring(", ");
1656 emit_register(in0, NULL);
1657 be_emit_finish_line_gas(node);
1658 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1659 be_emit_cstring("\txorpd ");
1660 emit_register(in1, NULL);
1661 be_emit_cstring(", ");
1662 emit_register(in0, NULL);
1663 be_emit_finish_line_gas(NULL);
1665 be_emit_cstring("\txorpd ");
1666 emit_register(in0, NULL);
1667 be_emit_cstring(", ");
1668 emit_register(in1, NULL);
1669 be_emit_finish_line_gas(NULL);
1671 be_emit_cstring("\txorpd ");
1672 emit_register(in1, NULL);
1673 be_emit_cstring(", ");
1674 emit_register(in0, NULL);
1675 be_emit_finish_line_gas(node);
1676 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1678 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1681 panic("unexpected register class in be_Perm (%+F)\n", node);
1686 * Emits code for Constant loading.
1688 static void emit_ia32_Const(const ir_node *node)
1690 be_emit_cstring("\tmovl ");
1691 emit_ia32_Immediate(node);
1692 be_emit_cstring(", ");
1693 ia32_emit_dest_register(node, 0);
1695 be_emit_finish_line_gas(node);
1699 * Emits code to load the TLS base
1701 static void emit_ia32_LdTls(const ir_node *node)
1703 be_emit_cstring("\tmovl %gs:0, ");
1704 ia32_emit_dest_register(node, 0);
1705 be_emit_finish_line_gas(node);
1708 /* helper function for emit_ia32_Minus64Bit */
1709 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1711 be_emit_cstring("\tmovl ");
1712 emit_register(src, NULL);
1713 be_emit_cstring(", ");
1714 emit_register(dst, NULL);
1715 be_emit_finish_line_gas(node);
1718 /* helper function for emit_ia32_Minus64Bit */
1719 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1721 be_emit_cstring("\tnegl ");
1722 emit_register(reg, NULL);
1723 be_emit_finish_line_gas(node);
1726 /* helper function for emit_ia32_Minus64Bit */
1727 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1729 be_emit_cstring("\tsbbl $0, ");
1730 emit_register(reg, NULL);
1731 be_emit_finish_line_gas(node);
1734 /* helper function for emit_ia32_Minus64Bit */
1735 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1737 be_emit_cstring("\tsbbl ");
1738 emit_register(src, NULL);
1739 be_emit_cstring(", ");
1740 emit_register(dst, NULL);
1741 be_emit_finish_line_gas(node);
1744 /* helper function for emit_ia32_Minus64Bit */
1745 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1747 be_emit_cstring("\txchgl ");
1748 emit_register(src, NULL);
1749 be_emit_cstring(", ");
1750 emit_register(dst, NULL);
1751 be_emit_finish_line_gas(node);
1754 /* helper function for emit_ia32_Minus64Bit */
1755 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1757 be_emit_cstring("\txorl ");
1758 emit_register(reg, NULL);
1759 be_emit_cstring(", ");
1760 emit_register(reg, NULL);
1761 be_emit_finish_line_gas(node);
1764 static void emit_ia32_Minus64Bit(const ir_node *node)
1766 const arch_register_t *in_lo = get_in_reg(node, 0);
1767 const arch_register_t *in_hi = get_in_reg(node, 1);
1768 const arch_register_t *out_lo = get_out_reg(node, 0);
1769 const arch_register_t *out_hi = get_out_reg(node, 1);
1771 if (out_lo == in_lo) {
1772 if (out_hi != in_hi) {
1773 /* a -> a, b -> d */
1776 /* a -> a, b -> b */
1779 } else if (out_lo == in_hi) {
1780 if (out_hi == in_lo) {
1781 /* a -> b, b -> a */
1782 emit_xchg(node, in_lo, in_hi);
1785 /* a -> b, b -> d */
1786 emit_mov(node, in_hi, out_hi);
1787 emit_mov(node, in_lo, out_lo);
1791 if (out_hi == in_lo) {
1792 /* a -> c, b -> a */
1793 emit_mov(node, in_lo, out_lo);
1795 } else if (out_hi == in_hi) {
1796 /* a -> c, b -> b */
1797 emit_mov(node, in_lo, out_lo);
1800 /* a -> c, b -> d */
1801 emit_mov(node, in_lo, out_lo);
1807 emit_neg( node, out_hi);
1808 emit_neg( node, out_lo);
1809 emit_sbb0(node, out_hi);
1813 emit_zero(node, out_hi);
1814 emit_neg( node, out_lo);
1815 emit_sbb( node, in_hi, out_hi);
1818 static void emit_be_Return(const ir_node *node)
1821 be_emit_cstring("\tret");
1823 pop = be_Return_get_pop(node);
1825 be_emit_irprintf(" $%d", pop);
1827 be_emit_finish_line_gas(node);
1830 static void emit_Nothing(const ir_node *node)
1836 /***********************************************************************************
1839 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1840 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1841 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1842 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1844 ***********************************************************************************/
1847 * Enters the emitter functions for handled nodes into the generic
1848 * pointer of an opcode.
1851 void ia32_register_emitters(void) {
1853 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1854 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1855 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1856 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1857 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1858 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1860 /* first clear the generic function pointer for all ops */
1861 clear_irp_opcodes_generic_func();
1863 /* register all emitter functions defined in spec */
1864 ia32_register_spec_emitters();
1866 /* other ia32 emitter functions */
1870 IA32_EMIT(SwitchJmp);
1873 IA32_EMIT(Conv_I2FP);
1874 IA32_EMIT(Conv_FP2I);
1875 IA32_EMIT(Conv_FP2FP);
1876 IA32_EMIT(Conv_I2I);
1877 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1880 IA32_EMIT(Minus64Bit);
1883 /* benode emitter */
1908 static const char *last_name = NULL;
1909 static unsigned last_line = -1;
1910 static unsigned num = -1;
1913 * Emit the debug support for node node.
1915 static void ia32_emit_dbg(const ir_node *node)
1917 dbg_info *db = get_irn_dbg_info(node);
1919 const char *fname = ir_retrieve_dbg_info(db, &lineno);
1921 if (! cg->birg->main_env->options->stabs_debug_support)
1925 if (last_name != fname) {
1927 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1930 if (last_line != lineno) {
1933 snprintf(name, sizeof(name), ".LM%u", ++num);
1935 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1936 be_emit_string(name);
1937 be_emit_cstring(":\n");
1938 be_emit_write_line();
1943 typedef void (*emit_func_ptr) (const ir_node *);
1946 * Emits code for a node.
1948 static void ia32_emit_node(const ir_node *node)
1950 ir_op *op = get_irn_op(node);
1952 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1954 if (op->ops.generic) {
1955 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1956 ia32_emit_dbg(node);
1960 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1966 * Emits gas alignment directives
1968 static void ia32_emit_alignment(unsigned align, unsigned skip)
1970 be_emit_cstring("\t.p2align ");
1971 be_emit_irprintf("%u,,%u\n", align, skip);
1972 be_emit_write_line();
1976 * Emits gas alignment directives for Functions depended on cpu architecture.
1978 static void ia32_emit_align_func(void)
1980 unsigned align = ia32_cg_config.function_alignment;
1981 unsigned maximum_skip = (1 << align) - 1;
1983 ia32_emit_alignment(align, maximum_skip);
1987 * Emits gas alignment directives for Labels depended on cpu architecture.
1989 static void ia32_emit_align_label(void)
1991 unsigned align = ia32_cg_config.label_alignment;
1992 unsigned maximum_skip = (1 << align) - 1;
1993 ia32_emit_alignment(align, maximum_skip);
1997 * Test wether a block should be aligned.
1998 * For cpus in the P4/Athlon class it is useful to align jump labels to
1999 * 16 bytes. However we should only do that if the alignment nops before the
2000 * label aren't executed more often than we have jumps to the label.
2002 static int should_align_block(ir_node *block, ir_node *prev)
2004 static const double DELTA = .0001;
2005 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2007 double prev_freq = 0; /**< execfreq of the fallthrough block */
2008 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2011 if(exec_freq == NULL)
2013 if(ia32_cg_config.label_alignment_factor <= 0)
2016 block_freq = get_block_execfreq(exec_freq, block);
2017 if(block_freq < DELTA)
2020 n_cfgpreds = get_Block_n_cfgpreds(block);
2021 for(i = 0; i < n_cfgpreds; ++i) {
2022 ir_node *pred = get_Block_cfgpred_block(block, i);
2023 double pred_freq = get_block_execfreq(exec_freq, pred);
2026 prev_freq += pred_freq;
2028 jmp_freq += pred_freq;
2032 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2035 jmp_freq /= prev_freq;
2037 return jmp_freq > ia32_cg_config.label_alignment_factor;
2040 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2045 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2047 n_cfgpreds = get_Block_n_cfgpreds(block);
2048 need_label = (n_cfgpreds != 0);
2050 if (should_align_block(block, prev)) {
2052 ia32_emit_align_label();
2056 ia32_emit_block_name(block);
2059 be_emit_pad_comment();
2060 be_emit_cstring(" /* preds:");
2062 /* emit list of pred blocks in comment */
2063 arity = get_irn_arity(block);
2064 for (i = 0; i < arity; ++i) {
2065 ir_node *predblock = get_Block_cfgpred_block(block, i);
2066 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2069 be_emit_cstring("\t/* ");
2070 ia32_emit_block_name(block);
2071 be_emit_cstring(": ");
2073 if (exec_freq != NULL) {
2074 be_emit_irprintf(" freq: %f",
2075 get_block_execfreq(exec_freq, block));
2077 be_emit_cstring(" */\n");
2078 be_emit_write_line();
2082 * Walks over the nodes in a block connected by scheduling edges
2083 * and emits code for each node.
2085 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2087 const ir_node *node;
2089 ia32_emit_block_header(block, last_block);
2091 /* emit the contents of the block */
2092 ia32_emit_dbg(block);
2093 sched_foreach(block, node) {
2094 ia32_emit_node(node);
2099 * Emits code for function start.
2101 static void ia32_emit_func_prolog(ir_graph *irg)
2103 ir_entity *irg_ent = get_irg_entity(irg);
2104 const char *irg_name = get_entity_ld_name(irg_ent);
2105 const be_irg_t *birg = cg->birg;
2107 /* write the begin line (used by scripts processing the assembler... */
2108 be_emit_write_line();
2109 be_emit_cstring("# -- Begin ");
2110 be_emit_string(irg_name);
2112 be_emit_write_line();
2114 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2115 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2116 ia32_emit_align_func();
2117 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2118 be_emit_cstring(".global ");
2119 be_emit_string(irg_name);
2121 be_emit_write_line();
2123 ia32_emit_function_object(irg_name);
2124 be_emit_string(irg_name);
2125 be_emit_cstring(":\n");
2126 be_emit_write_line();
2130 * Emits code for function end
2132 static void ia32_emit_func_epilog(ir_graph *irg)
2134 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2135 const be_irg_t *birg = cg->birg;
2137 ia32_emit_function_size(irg_name);
2138 be_dbg_method_end(birg->main_env->db_handle);
2140 be_emit_cstring("# -- End ");
2141 be_emit_string(irg_name);
2143 be_emit_write_line();
2146 be_emit_write_line();
2151 * Sets labels for control flow nodes (jump target)
2153 static void ia32_gen_labels(ir_node *block, void *data)
2156 int n = get_Block_n_cfgpreds(block);
2159 for (n--; n >= 0; n--) {
2160 pred = get_Block_cfgpred(block, n);
2161 set_irn_link(pred, block);
2166 * Emit an exception label if the current instruction can fail.
2168 void ia32_emit_exc_label(const ir_node *node)
2170 if (get_ia32_exc_label(node)) {
2171 be_emit_irprintf(".EXL%u\n", 0);
2172 be_emit_write_line();
2177 * Main driver. Emits the code for one routine.
2179 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2182 ir_node *last_block = NULL;
2186 isa = (const ia32_isa_t*) cg->arch_env->isa;
2187 arch_env = cg->arch_env;
2189 ia32_register_emitters();
2191 ia32_emit_func_prolog(irg);
2192 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2194 n = ARR_LEN(cg->blk_sched);
2195 for (i = 0; i < n;) {
2198 block = cg->blk_sched[i];
2200 next_bl = i < n ? cg->blk_sched[i] : NULL;
2202 /* set here the link. the emitter expects to find the next block here */
2203 set_irn_link(block, next_bl);
2204 ia32_gen_block(block, last_block);
2208 ia32_emit_func_epilog(irg);
2211 void ia32_init_emitter(void)
2213 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");