2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
27 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
35 * pnc_Leg => NP (ordered)
57 #include "iredges_t.h"
61 #include "raw_bitset.h"
65 #include "../besched.h"
66 #include "../benode.h"
68 #include "../be_dbgout.h"
69 #include "../beemitter.h"
70 #include "../begnuas.h"
72 #include "../be_dbgout.h"
74 #include "ia32_emitter.h"
75 #include "ia32_common_transform.h"
76 #include "gen_ia32_emitter.h"
77 #include "gen_ia32_regalloc_if.h"
78 #include "ia32_nodes_attr.h"
79 #include "ia32_new_nodes.h"
80 #include "ia32_architecture.h"
81 #include "bearch_ia32_t.h"
83 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
85 #define SNPRINTF_BUF_LEN 128
87 static const ia32_isa_t *isa;
88 static char pic_base_label[128];
89 static ir_label_t exc_label_id;
90 static int mark_spill_reload = 0;
93 /** Return the next block in Block schedule */
94 static ir_node *get_prev_block_sched(const ir_node *block)
96 return (ir_node*)get_irn_link(block);
99 /** Checks if the current block is a fall-through target. */
100 static int is_fallthrough(const ir_node *cfgpred)
104 if (!is_Proj(cfgpred))
106 pred = get_Proj_pred(cfgpred);
107 if (is_ia32_SwitchJmp(pred))
114 * returns non-zero if the given block needs a label
115 * because of being a jump-target (and not a fall-through)
117 static int block_needs_label(const ir_node *block)
120 int n_cfgpreds = get_Block_n_cfgpreds(block);
122 if (has_Block_entity(block))
125 if (n_cfgpreds == 0) {
127 } else if (n_cfgpreds == 1) {
128 ir_node *cfgpred = get_Block_cfgpred(block, 0);
129 ir_node *cfgpred_block = get_nodes_block(cfgpred);
131 if (get_prev_block_sched(block) == cfgpred_block
132 && is_fallthrough(cfgpred)) {
141 * Returns the register at in position pos.
143 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
145 ir_node *op = get_irn_n(irn, pos);
146 return arch_get_irn_register(op);
150 * Add a number to a prefix. This number will not be used a second time.
152 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
154 static unsigned long id = 0;
155 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
160 * Emit the name of the 8bit low register
162 static void emit_8bit_register(const arch_register_t *reg)
164 const char *reg_name = arch_register_get_name(reg);
165 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
166 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
169 be_emit_char(reg_name[1]); /* get the basic name of the register */
174 * Emit the name of the 8bit high register
176 static void emit_8bit_register_high(const arch_register_t *reg)
178 const char *reg_name = arch_register_get_name(reg);
179 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
180 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
183 be_emit_char(reg_name[1]); /* get the basic name of the register */
187 static void emit_16bit_register(const arch_register_t *reg)
189 const char *reg_name = arch_register_get_name(reg);
192 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
196 * emit a register, possible shortened by a mode
198 * @param reg the register
199 * @param mode the mode of the register or NULL for full register
201 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
203 const char *reg_name;
206 int size = get_mode_size_bits(mode);
208 case 8: emit_8bit_register(reg); return;
209 case 16: emit_16bit_register(reg); return;
211 assert(mode_is_float(mode) || size == 32);
214 reg_name = arch_register_get_name(reg);
217 be_emit_string(reg_name);
220 void ia32_emit_source_register(const ir_node *node, int pos)
222 const arch_register_t *reg = get_in_reg(node, pos);
224 emit_register(reg, NULL);
227 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
229 be_gas_emit_entity(entity);
231 if (get_entity_owner(entity) == get_tls_type()) {
232 if (get_entity_visibility(entity) == ir_visibility_external) {
233 be_emit_cstring("@INDNTPOFF");
235 be_emit_cstring("@NTPOFF");
239 if (do_pic && !no_pic_adjust) {
241 be_emit_string(pic_base_label);
245 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
247 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
249 if (attr->symconst != NULL) {
252 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
254 if (attr->symconst == NULL || attr->offset != 0) {
255 if (attr->symconst != NULL) {
256 be_emit_irprintf("%+d", attr->offset);
258 be_emit_irprintf("0x%X", attr->offset);
263 static void emit_ia32_Immediate(const ir_node *node)
266 emit_ia32_Immediate_no_prefix(node);
269 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
271 const arch_register_t *reg;
272 const ir_node *in = get_irn_n(node, pos);
273 if (is_ia32_Immediate(in)) {
274 emit_ia32_Immediate(in);
278 reg = get_in_reg(node, pos);
279 emit_8bit_register(reg);
282 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
284 const arch_register_t *reg = get_in_reg(node, pos);
285 emit_8bit_register_high(reg);
288 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
290 const arch_register_t *reg;
291 const ir_node *in = get_irn_n(node, pos);
292 if (is_ia32_Immediate(in)) {
293 emit_ia32_Immediate(in);
297 reg = get_in_reg(node, pos);
298 emit_16bit_register(reg);
301 void ia32_emit_dest_register(const ir_node *node, int pos)
303 const arch_register_t *reg = arch_irn_get_register(node, pos);
305 emit_register(reg, NULL);
308 void ia32_emit_dest_register_size(const ir_node *node, int pos)
310 const arch_register_t *reg = arch_irn_get_register(node, pos);
312 emit_register(reg, get_ia32_ls_mode(node));
315 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
317 const arch_register_t *reg = arch_irn_get_register(node, pos);
319 emit_register(reg, mode_Bu);
322 void ia32_emit_x87_register(const ir_node *node, int pos)
324 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
328 be_emit_string(attr->x87[pos]->name);
331 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
333 assert(mode_is_int(mode) || mode_is_reference(mode));
334 switch (get_mode_size_bits(mode)) {
335 case 8: be_emit_char('b'); return;
336 case 16: be_emit_char('w'); return;
337 case 32: be_emit_char('l'); return;
338 /* gas docu says q is the suffix but gcc, objdump and icc use ll
340 case 64: be_emit_cstring("ll"); return;
342 panic("Can't output mode_suffix for %+F", mode);
345 void ia32_emit_mode_suffix(const ir_node *node)
347 ir_mode *mode = get_ia32_ls_mode(node);
351 ia32_emit_mode_suffix_mode(mode);
354 void ia32_emit_x87_mode_suffix(const ir_node *node)
358 /* we only need to emit the mode on address mode */
359 if (get_ia32_op_type(node) == ia32_Normal)
362 mode = get_ia32_ls_mode(node);
363 assert(mode != NULL);
365 if (mode_is_float(mode)) {
366 switch (get_mode_size_bits(mode)) {
367 case 32: be_emit_char('s'); return;
368 case 64: be_emit_char('l'); return;
369 /* long doubles have different sizes due to alignment on different
373 case 128: be_emit_char('t'); return;
376 assert(mode_is_int(mode) || mode_is_reference(mode));
377 switch (get_mode_size_bits(mode)) {
378 case 16: be_emit_char('s'); return;
379 case 32: be_emit_char('l'); return;
380 /* gas docu says q is the suffix but gcc, objdump and icc use ll
382 case 64: be_emit_cstring("ll"); return;
385 panic("Can't output mode_suffix for %+F", mode);
388 static char get_xmm_mode_suffix(ir_mode *mode)
390 assert(mode_is_float(mode));
391 switch (get_mode_size_bits(mode)) {
394 default: panic("Invalid XMM mode");
398 void ia32_emit_xmm_mode_suffix(const ir_node *node)
400 ir_mode *mode = get_ia32_ls_mode(node);
401 assert(mode != NULL);
403 be_emit_char(get_xmm_mode_suffix(mode));
406 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
408 ir_mode *mode = get_ia32_ls_mode(node);
409 assert(mode != NULL);
410 be_emit_char(get_xmm_mode_suffix(mode));
413 void ia32_emit_extend_suffix(const ir_node *node)
415 ir_mode *mode = get_ia32_ls_mode(node);
416 if (get_mode_size_bits(mode) == 32)
418 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
419 ia32_emit_mode_suffix_mode(mode);
422 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
424 ir_node *in = get_irn_n(node, pos);
425 if (is_ia32_Immediate(in)) {
426 emit_ia32_Immediate(in);
428 const ir_mode *mode = get_ia32_ls_mode(node);
429 const arch_register_t *reg = get_in_reg(node, pos);
430 emit_register(reg, mode);
435 * Returns the target block for a control flow node.
437 static ir_node *get_cfop_target_block(const ir_node *irn)
439 assert(get_irn_mode(irn) == mode_X);
440 return (ir_node*)get_irn_link(irn);
444 * Emits the target label for a control flow node.
446 static void ia32_emit_cfop_target(const ir_node *node)
448 ir_node *block = get_cfop_target_block(node);
449 be_gas_emit_block_name(block);
453 * Emit the suffix for a compare instruction.
455 static void ia32_emit_condition_code(ia32_condition_code_t cc)
458 case ia32_cc_overflow: be_emit_cstring("o"); return;
459 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
460 case ia32_cc_float_below:
461 case ia32_cc_float_unordered_below:
462 case ia32_cc_below: be_emit_cstring("b"); return;
463 case ia32_cc_float_above_equal:
464 case ia32_cc_float_unordered_above_equal:
465 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
466 case ia32_cc_float_equal:
467 case ia32_cc_equal: be_emit_cstring("e"); return;
468 case ia32_cc_float_not_equal:
469 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
470 case ia32_cc_float_below_equal:
471 case ia32_cc_float_unordered_below_equal:
472 case ia32_cc_below_equal: be_emit_cstring("be"); return;
473 case ia32_cc_float_above:
474 case ia32_cc_float_unordered_above:
475 case ia32_cc_above: be_emit_cstring("a"); return;
476 case ia32_cc_sign: be_emit_cstring("s"); return;
477 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
478 case ia32_cc_parity: be_emit_cstring("p"); return;
479 case ia32_cc_not_parity: be_emit_cstring("np"); return;
480 case ia32_cc_less: be_emit_cstring("l"); return;
481 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
482 case ia32_cc_less_equal: be_emit_cstring("le"); return;
483 case ia32_cc_greater: be_emit_cstring("g"); return;
484 case ia32_cc_float_parity_cases:
485 case ia32_cc_additional_float_cases:
488 panic("Invalid ia32 condition code");
491 typedef enum ia32_emit_mod_t {
493 EMIT_RESPECT_LS = 1U << 0,
494 EMIT_ALTERNATE_AM = 1U << 1,
496 EMIT_HIGH_REG = 1U << 3,
497 EMIT_LOW_REG = 1U << 4
499 ENUM_BITSET(ia32_emit_mod_t)
502 * Emits address mode.
504 void ia32_emit_am(const ir_node *node)
506 ir_entity *ent = get_ia32_am_sc(node);
507 int offs = get_ia32_am_offs_int(node);
508 ir_node *base = get_irn_n(node, n_ia32_base);
509 int has_base = !is_ia32_NoReg_GP(base);
510 ir_node *idx = get_irn_n(node, n_ia32_index);
511 int has_index = !is_ia32_NoReg_GP(idx);
513 /* just to be sure... */
514 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
516 if (get_ia32_am_tls_segment(node))
517 be_emit_cstring("%gs:");
521 const ia32_attr_t *attr = get_ia32_attr_const(node);
522 if (is_ia32_am_sc_sign(node))
524 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
527 /* also handle special case if nothing is set */
528 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
530 be_emit_irprintf("%+d", offs);
532 be_emit_irprintf("%d", offs);
536 if (has_base || has_index) {
541 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
542 emit_register(reg, NULL);
545 /* emit index + scale */
547 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
550 emit_register(reg, NULL);
552 scale = get_ia32_am_scale(node);
554 be_emit_irprintf(",%d", 1 << scale);
562 * fmt parameter output
563 * ---- ---------------------- ---------------------------------------------
565 * %AM <node> address mode of the node
566 * %AR const arch_register_t* address mode of the node or register
567 * %ASx <node> address mode of the node or source register x
568 * %Dx <node> destination register x
569 * %I <node> immediate of the node
570 * %L <node> control flow target of the node
571 * %M <node> mode suffix of the node
572 * %P int condition code
573 * %R const arch_register_t* register
574 * %Sx <node> source register x
575 * %s const char* string
576 * %u unsigned int unsigned int
577 * %d signed int signed int
580 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
581 * * modifier does not prefix immediates with $, but AM with *
582 * l modifier for %lu and %ld
583 * > modifier to output high 8bit register (ah, bh)
584 * < modifier to output low 8bit register (al, bl)
586 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
592 const char *start = fmt;
593 ia32_emit_mod_t mod = EMIT_NONE;
595 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
598 be_emit_string_len(start, fmt - start);
602 be_emit_finish_line_gas(node);
615 case '*': mod |= EMIT_ALTERNATE_AM; break;
616 case '#': mod |= EMIT_RESPECT_LS; break;
617 case 'l': mod |= EMIT_LONG; break;
618 case '>': mod |= EMIT_HIGH_REG; break;
619 case '<': mod |= EMIT_LOW_REG; break;
628 arch_register_t const *reg;
639 if (mod & EMIT_ALTERNATE_AM)
645 reg = va_arg(ap, const arch_register_t*);
646 if (get_ia32_op_type(node) == ia32_AddrModeS) {
653 if (get_ia32_op_type(node) == ia32_AddrModeS) {
657 assert(get_ia32_op_type(node) == ia32_Normal);
661 default: goto unknown;
667 if (*fmt < '0' || '9' <= *fmt)
669 reg = arch_irn_get_register(node, *fmt++ - '0');
675 if (!(mod & EMIT_ALTERNATE_AM))
677 emit_ia32_Immediate_no_prefix(imm);
681 ia32_emit_cfop_target(node);
685 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
689 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
690 ia32_emit_condition_code(cc);
695 reg = va_arg(ap, const arch_register_t*);
697 if (mod & EMIT_ALTERNATE_AM)
699 if (mod & EMIT_HIGH_REG) {
700 emit_8bit_register_high(reg);
701 } else if (mod & EMIT_LOW_REG) {
702 emit_8bit_register(reg);
704 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
712 if (*fmt < '0' || '9' <= *fmt)
716 imm = get_irn_n(node, pos);
717 if (is_ia32_Immediate(imm)) {
720 reg = get_in_reg(node, pos);
726 const char *str = va_arg(ap, const char*);
732 if (mod & EMIT_LONG) {
733 unsigned long num = va_arg(ap, unsigned long);
734 be_emit_irprintf("%lu", num);
736 unsigned num = va_arg(ap, unsigned);
737 be_emit_irprintf("%u", num);
742 if (mod & EMIT_LONG) {
743 long num = va_arg(ap, long);
744 be_emit_irprintf("%ld", num);
746 int num = va_arg(ap, int);
747 be_emit_irprintf("%d", num);
753 panic("unknown format conversion in ia32_emitf()");
761 * Emits registers and/or address mode of a binary operation.
763 void ia32_emit_binop(const ir_node *node)
765 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
766 ia32_emitf(node, "%#S4, %#AS3");
768 ia32_emitf(node, "%#AS4, %#S3");
773 * Emits registers and/or address mode of a binary operation.
775 void ia32_emit_x87_binop(const ir_node *node)
777 switch (get_ia32_op_type(node)) {
780 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
781 const arch_register_t *in1 = x87_attr->x87[0];
782 const arch_register_t *in = x87_attr->x87[1];
783 const arch_register_t *out = x87_attr->x87[2];
787 } else if (out == in) {
792 be_emit_string(arch_register_get_name(in));
793 be_emit_cstring(", %");
794 be_emit_string(arch_register_get_name(out));
802 assert(0 && "unsupported op type");
807 * Emits registers and/or address mode of a unary operation.
809 void ia32_emit_unop(const ir_node *node, int pos)
813 ia32_emitf(node, fmt);
816 static void emit_ia32_IMul(const ir_node *node)
818 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
819 const arch_register_t *out_reg = arch_irn_get_register(node, pn_ia32_IMul_res);
821 /* do we need the 3-address form? */
822 if (is_ia32_NoReg_GP(left) ||
823 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
824 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
826 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
831 * walks up a tree of copies/perms/spills/reloads to find the original value
832 * that is moved around
834 static ir_node *find_original_value(ir_node *node)
836 if (irn_visited(node))
839 mark_irn_visited(node);
840 if (be_is_Copy(node)) {
841 return find_original_value(be_get_Copy_op(node));
842 } else if (be_is_CopyKeep(node)) {
843 return find_original_value(be_get_CopyKeep_op(node));
844 } else if (is_Proj(node)) {
845 ir_node *pred = get_Proj_pred(node);
846 if (be_is_Perm(pred)) {
847 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
848 } else if (be_is_MemPerm(pred)) {
849 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
850 } else if (is_ia32_Load(pred)) {
851 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
852 } else if (is_ia32_Store(pred)) {
853 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
857 } else if (is_Phi(node)) {
859 arity = get_irn_arity(node);
860 for (i = 0; i < arity; ++i) {
861 ir_node *in = get_irn_n(node, i);
862 ir_node *res = find_original_value(in);
873 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
875 ir_node *flags = get_irn_n(node, flags_pos);
876 const ia32_attr_t *flags_attr;
877 flags = skip_Proj(flags);
879 if (is_ia32_Sahf(flags)) {
880 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
881 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
882 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
883 inc_irg_visited(current_ir_graph);
884 cmp = find_original_value(cmp);
886 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
887 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
890 flags_attr = get_ia32_attr_const(cmp);
892 flags_attr = get_ia32_attr_const(flags);
895 if (flags_attr->data.ins_permuted)
896 cc = ia32_invert_condition_code(cc);
900 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
902 ia32_condition_code_t cc = get_ia32_condcode(node);
903 cc = determine_final_cc(node, flags_pos, cc);
905 ia32_emit_condition_code(cc);
909 * Emits an exception label for a given node.
911 static void ia32_emit_exc_label(const ir_node *node)
913 be_emit_string(be_gas_insn_label_prefix());
914 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
918 * Returns the Proj with projection number proj and NOT mode_M
920 static ir_node *get_proj(const ir_node *node, long proj)
922 const ir_edge_t *edge;
925 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
927 foreach_out_edge(node, edge) {
928 src = get_edge_src_irn(edge);
930 assert(is_Proj(src) && "Proj expected");
931 if (get_irn_mode(src) == mode_M)
934 if (get_Proj_proj(src) == proj)
940 static int can_be_fallthrough(const ir_node *node)
942 ir_node *target_block = get_cfop_target_block(node);
943 ir_node *block = get_nodes_block(node);
944 return get_prev_block_sched(target_block) == block;
948 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
950 static void emit_ia32_Jcc(const ir_node *node)
952 int need_parity_label = 0;
953 ia32_condition_code_t cc = get_ia32_condcode(node);
954 const ir_node *proj_true;
955 const ir_node *proj_false;
957 cc = determine_final_cc(node, 0, cc);
960 proj_true = get_proj(node, pn_ia32_Jcc_true);
961 assert(proj_true && "Jcc without true Proj");
963 proj_false = get_proj(node, pn_ia32_Jcc_false);
964 assert(proj_false && "Jcc without false Proj");
966 if (can_be_fallthrough(proj_true)) {
967 /* exchange both proj's so the second one can be omitted */
968 const ir_node *t = proj_true;
970 proj_true = proj_false;
972 cc = ia32_negate_condition_code(cc);
975 if (cc & ia32_cc_float_parity_cases) {
976 /* Some floating point comparisons require a test of the parity flag,
977 * which indicates that the result is unordered */
978 if (cc & ia32_cc_negated) {
979 ia32_emitf(proj_true, "\tjp %L\n");
981 /* we need a local label if the false proj is a fallthrough
982 * as the falseblock might have no label emitted then */
983 if (can_be_fallthrough(proj_false)) {
984 need_parity_label = 1;
985 ia32_emitf(proj_false, "\tjp 1f\n");
987 ia32_emitf(proj_false, "\tjp %L\n");
991 ia32_emitf(proj_true, "\tj%P %L\n", cc);
992 if (need_parity_label) {
993 ia32_emitf(NULL, "1:\n");
996 /* the second Proj might be a fallthrough */
997 if (can_be_fallthrough(proj_false)) {
998 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1000 ia32_emitf(proj_false, "\tjmp %L\n");
1005 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1008 static void emit_ia32_Setcc(const ir_node *node)
1010 const arch_register_t *dreg = arch_irn_get_register(node, pn_ia32_Setcc_res);
1012 ia32_condition_code_t cc = get_ia32_condcode(node);
1013 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1014 if (cc & ia32_cc_float_parity_cases) {
1015 if (cc & ia32_cc_negated) {
1016 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1017 ia32_emitf(node, "\tsetp %>R\n", dreg);
1018 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1020 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1021 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1022 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1025 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1029 static void emit_ia32_CMovcc(const ir_node *node)
1031 const ia32_attr_t *attr = get_ia32_attr_const(node);
1032 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1033 ia32_condition_code_t cc = get_ia32_condcode(node);
1034 const arch_register_t *in_true;
1035 const arch_register_t *in_false;
1037 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1038 /* although you can't set ins_permuted in the constructor it might still
1039 * be set by memory operand folding
1040 * Permuting inputs of a cmov means the condition is negated!
1042 if (attr->data.ins_permuted)
1043 cc = ia32_negate_condition_code(cc);
1045 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1046 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1048 /* should be same constraint fullfilled? */
1049 if (out == in_false) {
1050 /* yes -> nothing to do */
1051 } else if (out == in_true) {
1052 const arch_register_t *tmp;
1054 assert(get_ia32_op_type(node) == ia32_Normal);
1056 cc = ia32_negate_condition_code(cc);
1063 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1066 if (cc & ia32_cc_float_parity_cases) {
1067 panic("CMov with floatingpoint compare/parity not supported yet");
1070 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1074 * Emits code for a SwitchJmp
1076 static void emit_ia32_SwitchJmp(const ir_node *node)
1078 ir_entity *jump_table = get_ia32_am_sc(node);
1079 long default_pn = get_ia32_default_pn(node);
1081 ia32_emitf(node, "\tjmp %*AM\n");
1082 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
1086 * Emits code for a unconditional jump.
1088 static void emit_ia32_Jmp(const ir_node *node)
1090 /* we have a block schedule */
1091 if (can_be_fallthrough(node)) {
1092 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1094 ia32_emitf(node, "\tjmp %L\n");
1099 * Emit an inline assembler operand.
1101 * @param node the ia32_ASM node
1102 * @param s points to the operand (a %c)
1104 * @return pointer to the first char in s NOT in the current operand
1106 static const char* emit_asm_operand(const ir_node *node, const char *s)
1108 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1109 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1111 const arch_register_t *reg;
1112 const ia32_asm_reg_t *asm_regs = attr->register_map;
1113 const ia32_asm_reg_t *asm_reg;
1122 /* parse modifiers */
1125 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1150 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1157 if (sscanf(s, "%d%n", &num, &p) != 1) {
1158 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1165 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1167 "Error: Custom assembler references invalid input/output (%+F)\n",
1171 asm_reg = & asm_regs[num];
1172 assert(asm_reg->valid);
1175 if (asm_reg->use_input == 0) {
1176 reg = arch_irn_get_register(node, asm_reg->inout_pos);
1178 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1180 /* might be an immediate value */
1181 if (is_ia32_Immediate(pred)) {
1182 emit_ia32_Immediate(pred);
1185 reg = get_in_reg(node, asm_reg->inout_pos);
1189 "Warning: no register assigned for %d asm op (%+F)\n",
1194 if (asm_reg->memory) {
1199 if (modifier != 0) {
1202 emit_8bit_register(reg);
1205 emit_8bit_register_high(reg);
1208 emit_16bit_register(reg);
1211 panic("Invalid asm op modifier");
1214 emit_register(reg, asm_reg->mode);
1217 if (asm_reg->memory) {
1225 * Emits code for an ASM pseudo op.
1227 static void emit_ia32_Asm(const ir_node *node)
1229 const void *gen_attr = get_irn_generic_attr_const(node);
1230 const ia32_asm_attr_t *attr
1231 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1232 ident *asm_text = attr->asm_text;
1233 const char *s = get_id_str(asm_text);
1235 ia32_emitf(node, "#APP\t\n");
1242 s = emit_asm_operand(node, s);
1248 ia32_emitf(NULL, "\n#NO_APP\n");
1253 * Emit movsb/w instructions to make mov count divideable by 4
1255 static void emit_CopyB_prolog(unsigned size)
1258 ia32_emitf(NULL, "\tmovsb\n");
1260 ia32_emitf(NULL, "\tmovsw\n");
1264 * Emit rep movsd instruction for memcopy.
1266 static void emit_ia32_CopyB(const ir_node *node)
1268 unsigned size = get_ia32_copyb_size(node);
1270 emit_CopyB_prolog(size);
1271 ia32_emitf(node, "\trep movsd\n");
1275 * Emits unrolled memcopy.
1277 static void emit_ia32_CopyB_i(const ir_node *node)
1279 unsigned size = get_ia32_copyb_size(node);
1281 emit_CopyB_prolog(size);
1285 ia32_emitf(NULL, "\tmovsd\n");
1291 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1293 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1296 ir_mode *ls_mode = get_ia32_ls_mode(node);
1297 int ls_bits = get_mode_size_bits(ls_mode);
1298 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1300 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1303 static void emit_ia32_Conv_I2FP(const ir_node *node)
1305 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1308 static void emit_ia32_Conv_FP2I(const ir_node *node)
1310 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1313 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1315 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1319 * Emits code for an Int conversion.
1321 static void emit_ia32_Conv_I2I(const ir_node *node)
1323 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1324 int signed_mode = mode_is_signed(smaller_mode);
1325 const char *sign_suffix;
1327 assert(!mode_is_float(smaller_mode));
1329 sign_suffix = signed_mode ? "s" : "z";
1330 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1336 static void emit_ia32_Call(const ir_node *node)
1338 /* Special case: Call must not have its immediates prefixed by $, instead
1339 * address mode is prefixed by *. */
1340 ia32_emitf(node, "\tcall %*AS3\n");
1345 * Emits code to increase stack pointer.
1347 static void emit_be_IncSP(const ir_node *node)
1349 int offs = be_get_IncSP_offset(node);
1355 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1357 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1362 * Emits code for Copy/CopyKeep.
1364 static void Copy_emitter(const ir_node *node, const ir_node *op)
1366 const arch_register_t *in = arch_get_irn_register(op);
1367 const arch_register_t *out = arch_get_irn_register(node);
1372 /* copies of vf nodes aren't real... */
1373 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1376 if (get_irn_mode(node) == mode_E) {
1377 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1379 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1383 static void emit_be_Copy(const ir_node *node)
1385 Copy_emitter(node, be_get_Copy_op(node));
1388 static void emit_be_CopyKeep(const ir_node *node)
1390 Copy_emitter(node, be_get_CopyKeep_op(node));
1394 * Emits code for exchange.
1396 static void emit_be_Perm(const ir_node *node)
1398 const arch_register_t *in0, *in1;
1399 const arch_register_class_t *cls0, *cls1;
1401 in0 = arch_get_irn_register(get_irn_n(node, 0));
1402 in1 = arch_get_irn_register(get_irn_n(node, 1));
1404 cls0 = arch_register_get_class(in0);
1405 cls1 = arch_register_get_class(in1);
1407 assert(cls0 == cls1 && "Register class mismatch at Perm");
1409 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1410 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1411 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1412 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1413 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1414 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1415 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1417 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1420 panic("unexpected register class in be_Perm (%+F)", node);
1425 * Emits code for Constant loading.
1427 static void emit_ia32_Const(const ir_node *node)
1429 ia32_emitf(node, "\tmovl %I, %D0\n");
1432 /* helper function for emit_ia32_Minus64Bit */
1433 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1435 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1438 /* helper function for emit_ia32_Minus64Bit */
1439 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1441 ia32_emitf(node, "\tnegl %R\n", reg);
1444 /* helper function for emit_ia32_Minus64Bit */
1445 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1447 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1450 /* helper function for emit_ia32_Minus64Bit */
1451 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1453 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1456 /* helper function for emit_ia32_Minus64Bit */
1457 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1459 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1462 /* helper function for emit_ia32_Minus64Bit */
1463 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1465 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1468 static void emit_ia32_Minus64Bit(const ir_node *node)
1470 const arch_register_t *in_lo = get_in_reg(node, 0);
1471 const arch_register_t *in_hi = get_in_reg(node, 1);
1472 const arch_register_t *out_lo = arch_irn_get_register(node, 0);
1473 const arch_register_t *out_hi = arch_irn_get_register(node, 1);
1475 if (out_lo == in_lo) {
1476 if (out_hi != in_hi) {
1477 /* a -> a, b -> d */
1480 /* a -> a, b -> b */
1483 } else if (out_lo == in_hi) {
1484 if (out_hi == in_lo) {
1485 /* a -> b, b -> a */
1486 emit_xchg(node, in_lo, in_hi);
1489 /* a -> b, b -> d */
1490 emit_mov(node, in_hi, out_hi);
1491 emit_mov(node, in_lo, out_lo);
1495 if (out_hi == in_lo) {
1496 /* a -> c, b -> a */
1497 emit_mov(node, in_lo, out_lo);
1499 } else if (out_hi == in_hi) {
1500 /* a -> c, b -> b */
1501 emit_mov(node, in_lo, out_lo);
1504 /* a -> c, b -> d */
1505 emit_mov(node, in_lo, out_lo);
1511 emit_neg( node, out_hi);
1512 emit_neg( node, out_lo);
1513 emit_sbb0(node, out_hi);
1517 emit_zero(node, out_hi);
1518 emit_neg( node, out_lo);
1519 emit_sbb( node, in_hi, out_hi);
1522 static void emit_ia32_GetEIP(const ir_node *node)
1524 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1525 ia32_emitf(NULL, "%s:\n", pic_base_label);
1526 ia32_emitf(node, "\tpopl %D0\n");
1529 static void emit_ia32_ClimbFrame(const ir_node *node)
1531 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1533 ia32_emitf(node, "\tmovl %S0, %D0\n");
1534 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1535 be_gas_emit_block_name(node);
1536 be_emit_cstring(":\n");
1537 be_emit_write_line();
1538 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1539 ia32_emitf(node, "\tdec %S1\n");
1540 be_emit_cstring("\tjnz ");
1541 be_gas_emit_block_name(node);
1542 be_emit_finish_line_gas(node);
1545 static void emit_be_Return(const ir_node *node)
1547 unsigned pop = be_Return_get_pop(node);
1549 if (pop > 0 || be_Return_get_emit_pop(node)) {
1550 ia32_emitf(node, "\tret $%u\n", pop);
1552 ia32_emitf(node, "\tret\n");
1556 static void emit_Nothing(const ir_node *node)
1563 * Enters the emitter functions for handled nodes into the generic
1564 * pointer of an opcode.
1566 static void ia32_register_emitters(void)
1568 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1569 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1570 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1571 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1572 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1573 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1575 /* first clear the generic function pointer for all ops */
1576 clear_irp_opcodes_generic_func();
1578 /* register all emitter functions defined in spec */
1579 ia32_register_spec_emitters();
1581 /* other ia32 emitter functions */
1582 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1587 IA32_EMIT(Conv_FP2FP);
1588 IA32_EMIT(Conv_FP2I);
1589 IA32_EMIT(Conv_I2FP);
1590 IA32_EMIT(Conv_I2I);
1597 IA32_EMIT(Minus64Bit);
1598 IA32_EMIT(SwitchJmp);
1599 IA32_EMIT(ClimbFrame);
1602 /* benode emitter */
1622 typedef void (*emit_func_ptr) (const ir_node *);
1625 * Assign and emit an exception label if the current instruction can fail.
1627 static void ia32_assign_exc_label(ir_node *node)
1629 /* assign a new ID to the instruction */
1630 set_ia32_exc_label_id(node, ++exc_label_id);
1632 ia32_emit_exc_label(node);
1634 be_emit_pad_comment();
1635 be_emit_cstring("/* exception to Block ");
1636 ia32_emit_cfop_target(node);
1637 be_emit_cstring(" */\n");
1638 be_emit_write_line();
1642 * Emits code for a node.
1644 static void ia32_emit_node(ir_node *node)
1646 ir_op *op = get_irn_op(node);
1648 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1650 if (is_ia32_irn(node)) {
1651 if (get_ia32_exc_label(node)) {
1652 /* emit the exception label of this instruction */
1653 ia32_assign_exc_label(node);
1655 if (mark_spill_reload) {
1656 if (is_ia32_is_spill(node)) {
1657 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1659 if (is_ia32_is_reload(node)) {
1660 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1662 if (is_ia32_is_remat(node)) {
1663 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1667 if (op->ops.generic) {
1668 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1670 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1675 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1681 * Emits gas alignment directives
1683 static void ia32_emit_alignment(unsigned align, unsigned skip)
1685 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1689 * Emits gas alignment directives for Labels depended on cpu architecture.
1691 static void ia32_emit_align_label(void)
1693 unsigned align = ia32_cg_config.label_alignment;
1694 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1695 ia32_emit_alignment(align, maximum_skip);
1699 * Test whether a block should be aligned.
1700 * For cpus in the P4/Athlon class it is useful to align jump labels to
1701 * 16 bytes. However we should only do that if the alignment nops before the
1702 * label aren't executed more often than we have jumps to the label.
1704 static int should_align_block(const ir_node *block)
1706 static const double DELTA = .0001;
1707 ir_graph *irg = get_irn_irg(block);
1708 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1709 ir_node *prev = get_prev_block_sched(block);
1711 double prev_freq = 0; /**< execfreq of the fallthrough block */
1712 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1715 if (exec_freq == NULL)
1717 if (ia32_cg_config.label_alignment_factor <= 0)
1720 block_freq = get_block_execfreq(exec_freq, block);
1721 if (block_freq < DELTA)
1724 n_cfgpreds = get_Block_n_cfgpreds(block);
1725 for (i = 0; i < n_cfgpreds; ++i) {
1726 const ir_node *pred = get_Block_cfgpred_block(block, i);
1727 double pred_freq = get_block_execfreq(exec_freq, pred);
1730 prev_freq += pred_freq;
1732 jmp_freq += pred_freq;
1736 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1739 jmp_freq /= prev_freq;
1741 return jmp_freq > ia32_cg_config.label_alignment_factor;
1745 * Emit the block header for a block.
1747 * @param block the block
1748 * @param prev_block the previous block
1750 static void ia32_emit_block_header(ir_node *block)
1752 ir_graph *irg = current_ir_graph;
1753 int need_label = block_needs_label(block);
1754 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1757 if (block == get_irg_end_block(irg))
1760 if (ia32_cg_config.label_alignment > 0) {
1761 /* align the current block if:
1762 * a) if should be aligned due to its execution frequency
1763 * b) there is no fall-through here
1765 if (should_align_block(block)) {
1766 ia32_emit_align_label();
1768 /* if the predecessor block has no fall-through,
1769 we can always align the label. */
1771 int has_fallthrough = 0;
1773 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1774 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1775 if (can_be_fallthrough(cfg_pred)) {
1776 has_fallthrough = 1;
1781 if (!has_fallthrough)
1782 ia32_emit_align_label();
1787 be_gas_emit_block_name(block);
1790 be_emit_pad_comment();
1791 be_emit_cstring(" /* ");
1793 be_emit_cstring("\t/* ");
1794 be_gas_emit_block_name(block);
1795 be_emit_cstring(": ");
1798 be_emit_cstring("preds:");
1800 /* emit list of pred blocks in comment */
1801 arity = get_irn_arity(block);
1803 be_emit_cstring(" none");
1806 for (i = 0; i < arity; ++i) {
1807 ir_node *predblock = get_Block_cfgpred_block(block, i);
1808 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1811 if (exec_freq != NULL) {
1812 be_emit_irprintf(", freq: %f",
1813 get_block_execfreq(exec_freq, block));
1815 be_emit_cstring(" */\n");
1816 be_emit_write_line();
1820 * Walks over the nodes in a block connected by scheduling edges
1821 * and emits code for each node.
1823 static void ia32_gen_block(ir_node *block)
1827 ia32_emit_block_header(block);
1829 /* emit the contents of the block */
1830 be_dbg_set_dbg_info(get_irn_dbg_info(block));
1831 sched_foreach(block, node) {
1832 ia32_emit_node(node);
1836 typedef struct exc_entry {
1837 ir_node *exc_instr; /** The instruction that can issue an exception. */
1838 ir_node *block; /** The block to call then. */
1843 * Sets labels for control flow nodes (jump target).
1844 * Links control predecessors to there destination blocks.
1846 static void ia32_gen_labels(ir_node *block, void *data)
1848 exc_entry **exc_list = (exc_entry**)data;
1852 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1853 pred = get_Block_cfgpred(block, n);
1854 set_irn_link(pred, block);
1856 pred = skip_Proj(pred);
1857 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1862 ARR_APP1(exc_entry, *exc_list, e);
1863 set_irn_link(pred, block);
1869 * Compare two exception_entries.
1871 static int cmp_exc_entry(const void *a, const void *b)
1873 const exc_entry *ea = (const exc_entry*)a;
1874 const exc_entry *eb = (const exc_entry*)b;
1876 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1882 * Main driver. Emits the code for one routine.
1884 void ia32_gen_routine(ir_graph *irg)
1886 ir_entity *entity = get_irg_entity(irg);
1887 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1888 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1889 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1890 ir_node **blk_sched = irg_data->blk_sched;
1893 isa = (ia32_isa_t*) arch_env;
1894 do_pic = be_get_irg_options(irg)->pic;
1896 be_gas_elf_type_char = '@';
1898 ia32_register_emitters();
1900 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1902 be_dbg_method_begin(entity);
1903 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
1905 /* we use links to point to target blocks */
1906 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1907 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1909 /* initialize next block links */
1910 n = ARR_LEN(blk_sched);
1911 for (i = 0; i < n; ++i) {
1912 ir_node *block = blk_sched[i];
1913 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1915 set_irn_link(block, prev);
1918 for (i = 0; i < n; ++i) {
1919 ir_node *block = blk_sched[i];
1921 ia32_gen_block(block);
1924 be_gas_emit_function_epilog(entity);
1925 be_dbg_method_end();
1927 be_emit_write_line();
1929 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1931 /* Sort the exception table using the exception label id's.
1932 Those are ascending with ascending addresses. */
1933 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1937 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1938 be_emit_cstring("\t.long ");
1939 ia32_emit_exc_label(exc_list[e].exc_instr);
1941 be_emit_cstring("\t.long ");
1942 be_gas_emit_block_name(exc_list[e].block);
1946 DEL_ARR_F(exc_list);
1949 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1950 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1954 /* ==== Experimental binary emitter ==== */
1956 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1957 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1958 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1960 static void build_reg_map(void)
1962 reg_gp_map[REG_GP_EAX] = 0x0;
1963 reg_gp_map[REG_GP_ECX] = 0x1;
1964 reg_gp_map[REG_GP_EDX] = 0x2;
1965 reg_gp_map[REG_GP_EBX] = 0x3;
1966 reg_gp_map[REG_GP_ESP] = 0x4;
1967 reg_gp_map[REG_GP_EBP] = 0x5;
1968 reg_gp_map[REG_GP_ESI] = 0x6;
1969 reg_gp_map[REG_GP_EDI] = 0x7;
1972 /** Returns the encoding for a pnc field. */
1973 static unsigned char pnc2cc(ia32_condition_code_t cc)
1978 /** Sign extension bit values for binops */
1980 UNSIGNED_IMM = 0, /**< unsigned immediate */
1981 SIGNEXT_IMM = 2, /**< sign extended immediate */
1984 /** The mod encoding of the ModR/M */
1986 MOD_IND = 0x00, /**< [reg1] */
1987 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1988 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1989 MOD_REG = 0xC0 /**< reg1 */
1992 /** create R/M encoding for ModR/M */
1993 #define ENC_RM(x) (x)
1994 /** create REG encoding for ModR/M */
1995 #define ENC_REG(x) ((x) << 3)
1997 /** create encoding for a SIB byte */
1998 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2000 /* Node: The following routines are supposed to append bytes, words, dwords
2001 to the output stream.
2002 Currently the implementation is stupid in that it still creates output
2003 for an "assembler" in the form of .byte, .long
2004 We will change this when enough infrastructure is there to create complete
2005 machine code in memory/object files */
2007 static void bemit8(const unsigned char byte)
2009 be_emit_irprintf("\t.byte 0x%x\n", byte);
2010 be_emit_write_line();
2013 static void bemit16(const unsigned short u16)
2015 be_emit_irprintf("\t.word 0x%x\n", u16);
2016 be_emit_write_line();
2019 static void bemit32(const unsigned u32)
2021 be_emit_irprintf("\t.long 0x%x\n", u32);
2022 be_emit_write_line();
2026 * Emit address of an entity. If @p is_relative is true then a relative
2027 * offset from behind the address to the entity is created.
2029 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2032 if (entity == NULL) {
2037 /* the final version should remember the position in the bytestream
2038 and patch it with the correct address at linktime... */
2039 be_emit_cstring("\t.long ");
2042 be_gas_emit_entity(entity);
2044 if (get_entity_owner(entity) == get_tls_type()) {
2045 if (get_entity_visibility(entity) == ir_visibility_external) {
2046 be_emit_cstring("@INDNTPOFF");
2048 be_emit_cstring("@NTPOFF");
2053 be_emit_cstring("-.");
2058 be_emit_irprintf("%+d", offset);
2061 be_emit_write_line();
2064 static void bemit_jmp_destination(const ir_node *dest_block)
2066 be_emit_cstring("\t.long ");
2067 be_gas_emit_block_name(dest_block);
2068 be_emit_cstring(" - . - 4\n");
2069 be_emit_write_line();
2072 /* end emit routines, all emitters following here should only use the functions
2075 typedef enum reg_modifier {
2080 /** Create a ModR/M byte for src1,src2 registers */
2081 static void bemit_modrr(const arch_register_t *src1,
2082 const arch_register_t *src2)
2084 unsigned char modrm = MOD_REG;
2085 modrm |= ENC_RM(reg_gp_map[src1->index]);
2086 modrm |= ENC_REG(reg_gp_map[src2->index]);
2090 /** Create a ModR/M8 byte for src1,src2 registers */
2091 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2092 reg_modifier_t high_part2, const arch_register_t *src2)
2094 unsigned char modrm = MOD_REG;
2095 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2096 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2100 /** Create a ModR/M byte for one register and extension */
2101 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2103 unsigned char modrm = MOD_REG;
2105 modrm |= ENC_RM(reg_gp_map[reg->index]);
2106 modrm |= ENC_REG(ext);
2110 /** Create a ModR/M8 byte for one register */
2111 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2113 unsigned char modrm = MOD_REG;
2114 assert(reg_gp_map[reg->index] < 4);
2115 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2121 * Calculate the size of an signed immediate in bytes.
2123 * @param offset an offset
2125 static unsigned get_signed_imm_size(int offset)
2127 if (-128 <= offset && offset < 128) {
2129 } else if (-32768 <= offset && offset < 32768) {
2137 * Emit an address mode.
2139 * @param reg content of the reg field: either a register index or an opcode extension
2140 * @param node the node
2142 static void bemit_mod_am(unsigned reg, const ir_node *node)
2144 ir_entity *ent = get_ia32_am_sc(node);
2145 int offs = get_ia32_am_offs_int(node);
2146 ir_node *base = get_irn_n(node, n_ia32_base);
2147 int has_base = !is_ia32_NoReg_GP(base);
2148 ir_node *idx = get_irn_n(node, n_ia32_index);
2149 int has_index = !is_ia32_NoReg_GP(idx);
2152 unsigned emitoffs = 0;
2153 bool emitsib = false;
2156 /* set the mod part depending on displacement */
2158 modrm |= MOD_IND_WORD_OFS;
2160 } else if (offs == 0) {
2163 } else if (-128 <= offs && offs < 128) {
2164 modrm |= MOD_IND_BYTE_OFS;
2167 modrm |= MOD_IND_WORD_OFS;
2172 const arch_register_t *base_reg = arch_get_irn_register(base);
2173 base_enc = reg_gp_map[base_reg->index];
2175 /* Use the EBP encoding + MOD_IND if NO base register. There is
2176 * always a 32bit offset present in this case. */
2182 /* Determine if we need a SIB byte. */
2184 const arch_register_t *reg_index = arch_get_irn_register(idx);
2185 int scale = get_ia32_am_scale(node);
2187 /* R/M set to ESP means SIB in 32bit mode. */
2188 modrm |= ENC_RM(0x04);
2189 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2191 } else if (base_enc == 0x04) {
2192 /* for the above reason we are forced to emit a SIB when base is ESP.
2193 * Only the base is used, index must be ESP too, which means no index.
2195 modrm |= ENC_RM(0x04);
2196 sib = ENC_SIB(0, 0x04, 0x04);
2199 modrm |= ENC_RM(base_enc);
2202 /* We are forced to emit an 8bit offset as EBP base without offset is a
2203 * special case for SIB without base register. */
2204 if (base_enc == 0x05 && emitoffs == 0) {
2205 modrm |= MOD_IND_BYTE_OFS;
2209 modrm |= ENC_REG(reg);
2215 /* emit displacement */
2216 if (emitoffs == 8) {
2217 bemit8((unsigned) offs);
2218 } else if (emitoffs == 32) {
2219 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2224 * Emit a binop with a immediate operand.
2226 * @param node the node to emit
2227 * @param opcode_eax the opcode for the op eax, imm variant
2228 * @param opcode the opcode for the reg, imm variant
2229 * @param ruval the opcode extension for opcode
2231 static void bemit_binop_with_imm(
2232 const ir_node *node,
2233 unsigned char opcode_ax,
2234 unsigned char opcode, unsigned char ruval)
2236 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2237 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2238 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2241 /* Some instructions (test) have no short form with 32bit value + 8bit
2243 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2246 /* check for sign extension */
2247 size = get_signed_imm_size(attr->offset);
2252 bemit8(opcode | SIGNEXT_IMM);
2253 /* cmp has this special mode */
2254 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2255 bemit_mod_am(ruval, node);
2257 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2258 bemit_modru(reg, ruval);
2260 bemit8((unsigned char)attr->offset);
2264 /* check for eax variant: this variant is shorter for 32bit immediates only */
2265 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2267 bemit_mod_am(ruval, node);
2269 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2270 if (reg->index == REG_GP_EAX) {
2274 bemit_modru(reg, ruval);
2277 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2280 panic("invalid imm size?!?");
2286 static void bemit_binop_2(const ir_node *node, unsigned code)
2288 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2290 if (get_ia32_op_type(node) == ia32_Normal) {
2291 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2292 bemit_modrr(op2, out);
2294 bemit_mod_am(reg_gp_map[out->index], node);
2301 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2303 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2304 if (is_ia32_Immediate(right)) {
2305 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2307 bemit_binop_2(node, opcodes[0]);
2314 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2317 if (get_ia32_op_type(node) == ia32_Normal) {
2318 const arch_register_t *in = get_in_reg(node, input);
2319 bemit_modru(in, ext);
2321 bemit_mod_am(ext, node);
2325 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2327 const arch_register_t *out = arch_irn_get_register(node, 0);
2328 bemit_unop(node, code, reg_gp_map[out->index], input);
2331 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2333 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2336 bemit8(size == 8 ? code : code + 1);
2337 bemit_mod_am(ext, node);
2340 static void bemit_immediate(const ir_node *node, bool relative)
2342 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2343 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2346 static void bemit_copy(const ir_node *copy)
2348 const arch_register_t *in = get_in_reg(copy, 0);
2349 const arch_register_t *out = arch_irn_get_register(copy, 0);
2353 /* copies of vf nodes aren't real... */
2354 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2357 if (get_irn_mode(copy) == mode_E) {
2360 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2362 bemit_modrr(in, out);
2366 static void bemit_perm(const ir_node *node)
2368 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2369 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2370 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2372 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2374 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2375 if (in0->index == REG_GP_EAX) {
2376 bemit8(0x90 + reg_gp_map[in1->index]);
2377 } else if (in1->index == REG_GP_EAX) {
2378 bemit8(0x90 + reg_gp_map[in0->index]);
2381 bemit_modrr(in0, in1);
2383 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2384 panic("unimplemented"); // TODO implement
2385 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2386 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2387 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2388 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2390 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2393 panic("unexpected register class in be_Perm (%+F)", node);
2397 static void bemit_xor0(const ir_node *node)
2399 const arch_register_t *out = arch_irn_get_register(node, 0);
2401 bemit_modrr(out, out);
2404 static void bemit_mov_const(const ir_node *node)
2406 const arch_register_t *out = arch_irn_get_register(node, 0);
2407 bemit8(0xB8 + reg_gp_map[out->index]);
2408 bemit_immediate(node, false);
2412 * Creates a function for a Binop with 3 possible encodings.
2414 #define BINOP(op, op0, op1, op2, op2_ext) \
2415 static void bemit_ ## op(const ir_node *node) { \
2416 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2417 bemit_binop(node, op ## _codes); \
2420 /* insn def eax,imm imm */
2421 BINOP(add, 0x03, 0x05, 0x81, 0)
2422 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2423 BINOP(adc, 0x13, 0x15, 0x81, 2)
2424 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2425 BINOP(and, 0x23, 0x25, 0x81, 4)
2426 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2427 BINOP(xor, 0x33, 0x35, 0x81, 6)
2428 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2430 #define BINOPMEM(op, ext) \
2431 static void bemit_##op(const ir_node *node) \
2434 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2437 val = get_irn_n(node, n_ia32_unary_op); \
2438 if (is_ia32_Immediate(val)) { \
2439 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2440 int offset = attr->offset; \
2441 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2443 bemit_mod_am(ext, node); \
2447 bemit_mod_am(ext, node); \
2451 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2455 bemit8(ext << 3 | 1); \
2456 bemit_mod_am(reg_gp_map[arch_irn_get_register(val, 0)->index], node); \
2460 static void bemit_##op##8bit(const ir_node *node) \
2462 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2463 if (is_ia32_Immediate(val)) { \
2465 bemit_mod_am(ext, node); \
2466 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2469 bemit_mod_am(reg_gp_map[arch_irn_get_register(val, 0)->index], node); \
2481 * Creates a function for an Unop with code /ext encoding.
2483 #define UNOP(op, code, ext, input) \
2484 static void bemit_ ## op(const ir_node *node) { \
2485 bemit_unop(node, code, ext, input); \
2488 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2489 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2490 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2491 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2492 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2493 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2495 /* TODO: am support for IJmp */
2496 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2498 #define SHIFT(op, ext) \
2499 static void bemit_##op(const ir_node *node) \
2501 const arch_register_t *out = arch_irn_get_register(node, 0); \
2502 ir_node *count = get_irn_n(node, 1); \
2503 if (is_ia32_Immediate(count)) { \
2504 int offset = get_ia32_immediate_attr_const(count)->offset; \
2505 if (offset == 1) { \
2507 bemit_modru(out, ext); \
2510 bemit_modru(out, ext); \
2515 bemit_modru(out, ext); \
2519 static void bemit_##op##mem(const ir_node *node) \
2522 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2525 count = get_irn_n(node, 1); \
2526 if (is_ia32_Immediate(count)) { \
2527 int offset = get_ia32_immediate_attr_const(count)->offset; \
2528 if (offset == 1) { \
2529 bemit8(size == 8 ? 0xD0 : 0xD1); \
2530 bemit_mod_am(ext, node); \
2532 bemit8(size == 8 ? 0xC0 : 0xC1); \
2533 bemit_mod_am(ext, node); \
2537 bemit8(size == 8 ? 0xD2 : 0xD3); \
2538 bemit_mod_am(ext, node); \
2548 static void bemit_shld(const ir_node *node)
2550 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2551 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_ShlD_res);
2552 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2554 if (is_ia32_Immediate(count)) {
2556 bemit_modrr(out, in);
2557 bemit8(get_ia32_immediate_attr_const(count)->offset);
2560 bemit_modrr(out, in);
2564 static void bemit_shrd(const ir_node *node)
2566 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2567 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_ShrD_res);
2568 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2570 if (is_ia32_Immediate(count)) {
2572 bemit_modrr(out, in);
2573 bemit8(get_ia32_immediate_attr_const(count)->offset);
2576 bemit_modrr(out, in);
2581 * binary emitter for setcc.
2583 static void bemit_setcc(const ir_node *node)
2585 const arch_register_t *dreg = arch_irn_get_register(node, pn_ia32_Setcc_res);
2587 ia32_condition_code_t cc = get_ia32_condcode(node);
2588 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2589 if (cc & ia32_cc_float_parity_cases) {
2590 if (cc & ia32_cc_negated) {
2593 bemit8(0x90 | pnc2cc(cc));
2594 bemit_modrm8(REG_LOW, dreg);
2599 bemit_modrm8(REG_HIGH, dreg);
2601 /* orb %>dreg, %<dreg */
2603 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2607 bemit8(0x90 | pnc2cc(cc));
2608 bemit_modrm8(REG_LOW, dreg);
2613 bemit_modrm8(REG_HIGH, dreg);
2615 /* andb %>dreg, %<dreg */
2617 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2622 bemit8(0x90 | pnc2cc(cc));
2623 bemit_modrm8(REG_LOW, dreg);
2627 static void bemit_cmovcc(const ir_node *node)
2629 const ia32_attr_t *attr = get_ia32_attr_const(node);
2630 int ins_permuted = attr->data.ins_permuted;
2631 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
2632 ia32_condition_code_t cc = get_ia32_condcode(node);
2633 const arch_register_t *in_true;
2634 const arch_register_t *in_false;
2636 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2638 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2639 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2641 /* should be same constraint fullfilled? */
2642 if (out == in_false) {
2643 /* yes -> nothing to do */
2644 } else if (out == in_true) {
2645 assert(get_ia32_op_type(node) == ia32_Normal);
2646 ins_permuted = !ins_permuted;
2650 bemit8(0x8B); // mov %in_false, %out
2651 bemit_modrr(in_false, out);
2655 cc = ia32_negate_condition_code(cc);
2657 if (cc & ia32_cc_float_parity_cases)
2658 panic("cmov can't handle parity float cases");
2661 bemit8(0x40 | pnc2cc(cc));
2662 if (get_ia32_op_type(node) == ia32_Normal) {
2663 bemit_modrr(in_true, out);
2665 bemit_mod_am(reg_gp_map[out->index], node);
2669 static void bemit_cmp(const ir_node *node)
2671 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2677 right = get_irn_n(node, n_ia32_binary_right);
2678 if (is_ia32_Immediate(right)) {
2679 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2680 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2681 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2684 if (attr->symconst != NULL) {
2687 /* check for sign extension */
2688 size = get_signed_imm_size(attr->offset);
2693 bemit8(0x81 | SIGNEXT_IMM);
2694 /* cmp has this special mode */
2695 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2696 bemit_mod_am(7, node);
2698 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2699 bemit_modru(reg, 7);
2701 bemit8((unsigned char)attr->offset);
2705 /* check for eax variant: this variant is shorter for 32bit immediates only */
2706 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2708 bemit_mod_am(7, node);
2710 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2711 if (reg->index == REG_GP_EAX) {
2715 bemit_modru(reg, 7);
2718 if (ls_size == 16) {
2719 bemit16(attr->offset);
2721 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2725 panic("invalid imm size?!?");
2727 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2729 if (get_ia32_op_type(node) == ia32_Normal) {
2730 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2731 bemit_modrr(op2, out);
2733 bemit_mod_am(reg_gp_map[out->index], node);
2738 static void bemit_cmp8bit(const ir_node *node)
2740 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2741 if (is_ia32_Immediate(right)) {
2742 if (get_ia32_op_type(node) == ia32_Normal) {
2743 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2744 if (out->index == REG_GP_EAX) {
2748 bemit_modru(out, 7);
2752 bemit_mod_am(7, node);
2754 bemit8(get_ia32_immediate_attr_const(right)->offset);
2756 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
2758 if (get_ia32_op_type(node) == ia32_Normal) {
2759 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
2760 bemit_modrr(out, in);
2762 bemit_mod_am(reg_gp_map[out->index], node);
2767 static void bemit_test8bit(const ir_node *node)
2769 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2770 if (is_ia32_Immediate(right)) {
2771 if (get_ia32_op_type(node) == ia32_Normal) {
2772 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2773 if (out->index == REG_GP_EAX) {
2777 bemit_modru(out, 0);
2781 bemit_mod_am(0, node);
2783 bemit8(get_ia32_immediate_attr_const(right)->offset);
2785 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
2787 if (get_ia32_op_type(node) == ia32_Normal) {
2788 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
2789 bemit_modrr(out, in);
2791 bemit_mod_am(reg_gp_map[out->index], node);
2796 static void bemit_imul(const ir_node *node)
2798 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2799 /* Do we need the immediate form? */
2800 if (is_ia32_Immediate(right)) {
2801 int imm = get_ia32_immediate_attr_const(right)->offset;
2802 if (get_signed_imm_size(imm) == 1) {
2803 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2806 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2811 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2815 static void bemit_dec(const ir_node *node)
2817 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_Dec_res);
2818 bemit8(0x48 + reg_gp_map[out->index]);
2821 static void bemit_inc(const ir_node *node)
2823 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_Inc_res);
2824 bemit8(0x40 + reg_gp_map[out->index]);
2827 #define UNOPMEM(op, code, ext) \
2828 static void bemit_##op(const ir_node *node) \
2830 bemit_unop_mem(node, code, ext); \
2833 UNOPMEM(notmem, 0xF6, 2)
2834 UNOPMEM(negmem, 0xF6, 3)
2835 UNOPMEM(incmem, 0xFE, 0)
2836 UNOPMEM(decmem, 0xFE, 1)
2838 static void bemit_ldtls(const ir_node *node)
2840 const arch_register_t *out = arch_irn_get_register(node, 0);
2842 bemit8(0x65); // gs:
2843 if (out->index == REG_GP_EAX) {
2844 bemit8(0xA1); // movl 0, %eax
2846 bemit8(0x8B); // movl 0, %reg
2847 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2855 static void bemit_lea(const ir_node *node)
2857 const arch_register_t *out = arch_irn_get_register(node, 0);
2859 bemit_mod_am(reg_gp_map[out->index], node);
2862 /* helper function for bemit_minus64bit */
2863 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2865 bemit8(0x8B); // movl %src, %dst
2866 bemit_modrr(src, dst);
2869 /* helper function for bemit_minus64bit */
2870 static void bemit_helper_neg(const arch_register_t *reg)
2872 bemit8(0xF7); // negl %reg
2873 bemit_modru(reg, 3);
2876 /* helper function for bemit_minus64bit */
2877 static void bemit_helper_sbb0(const arch_register_t *reg)
2879 bemit8(0x83); // sbbl $0, %reg
2880 bemit_modru(reg, 3);
2884 /* helper function for bemit_minus64bit */
2885 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2887 bemit8(0x1B); // sbbl %src, %dst
2888 bemit_modrr(src, dst);
2891 /* helper function for bemit_minus64bit */
2892 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2894 if (src->index == REG_GP_EAX) {
2895 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2896 } else if (dst->index == REG_GP_EAX) {
2897 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2899 bemit8(0x87); // xchgl %src, %dst
2900 bemit_modrr(src, dst);
2904 /* helper function for bemit_minus64bit */
2905 static void bemit_helper_zero(const arch_register_t *reg)
2907 bemit8(0x33); // xorl %reg, %reg
2908 bemit_modrr(reg, reg);
2911 static void bemit_minus64bit(const ir_node *node)
2913 const arch_register_t *in_lo = get_in_reg(node, 0);
2914 const arch_register_t *in_hi = get_in_reg(node, 1);
2915 const arch_register_t *out_lo = arch_irn_get_register(node, 0);
2916 const arch_register_t *out_hi = arch_irn_get_register(node, 1);
2918 if (out_lo == in_lo) {
2919 if (out_hi != in_hi) {
2920 /* a -> a, b -> d */
2923 /* a -> a, b -> b */
2926 } else if (out_lo == in_hi) {
2927 if (out_hi == in_lo) {
2928 /* a -> b, b -> a */
2929 bemit_helper_xchg(in_lo, in_hi);
2932 /* a -> b, b -> d */
2933 bemit_helper_mov(in_hi, out_hi);
2934 bemit_helper_mov(in_lo, out_lo);
2938 if (out_hi == in_lo) {
2939 /* a -> c, b -> a */
2940 bemit_helper_mov(in_lo, out_lo);
2942 } else if (out_hi == in_hi) {
2943 /* a -> c, b -> b */
2944 bemit_helper_mov(in_lo, out_lo);
2947 /* a -> c, b -> d */
2948 bemit_helper_mov(in_lo, out_lo);
2954 bemit_helper_neg( out_hi);
2955 bemit_helper_neg( out_lo);
2956 bemit_helper_sbb0(out_hi);
2960 bemit_helper_zero(out_hi);
2961 bemit_helper_neg( out_lo);
2962 bemit_helper_sbb( in_hi, out_hi);
2966 * Emit a single opcode.
2968 #define EMIT_SINGLEOP(op, code) \
2969 static void bemit_ ## op(const ir_node *node) { \
2974 //EMIT_SINGLEOP(daa, 0x27)
2975 //EMIT_SINGLEOP(das, 0x2F)
2976 //EMIT_SINGLEOP(aaa, 0x37)
2977 //EMIT_SINGLEOP(aas, 0x3F)
2978 //EMIT_SINGLEOP(nop, 0x90)
2979 EMIT_SINGLEOP(cwtl, 0x98)
2980 EMIT_SINGLEOP(cltd, 0x99)
2981 //EMIT_SINGLEOP(fwait, 0x9B)
2982 EMIT_SINGLEOP(sahf, 0x9E)
2983 //EMIT_SINGLEOP(popf, 0x9D)
2984 EMIT_SINGLEOP(leave, 0xC9)
2985 EMIT_SINGLEOP(int3, 0xCC)
2986 //EMIT_SINGLEOP(iret, 0xCF)
2987 //EMIT_SINGLEOP(xlat, 0xD7)
2988 //EMIT_SINGLEOP(lock, 0xF0)
2989 EMIT_SINGLEOP(rep, 0xF3)
2990 //EMIT_SINGLEOP(halt, 0xF4)
2991 EMIT_SINGLEOP(cmc, 0xF5)
2992 EMIT_SINGLEOP(stc, 0xF9)
2993 //EMIT_SINGLEOP(cli, 0xFA)
2994 //EMIT_SINGLEOP(sti, 0xFB)
2995 //EMIT_SINGLEOP(std, 0xFD)
2998 * Emits a MOV out, [MEM].
3000 static void bemit_load(const ir_node *node)
3002 const arch_register_t *out = arch_irn_get_register(node, 0);
3004 if (out->index == REG_GP_EAX) {
3005 ir_node *base = get_irn_n(node, n_ia32_base);
3006 int has_base = !is_ia32_NoReg_GP(base);
3007 ir_node *idx = get_irn_n(node, n_ia32_index);
3008 int has_index = !is_ia32_NoReg_GP(idx);
3009 if (!has_base && !has_index) {
3010 ir_entity *ent = get_ia32_am_sc(node);
3011 int offs = get_ia32_am_offs_int(node);
3012 /* load from constant address to EAX can be encoded
3015 bemit_entity(ent, 0, offs, false);
3020 bemit_mod_am(reg_gp_map[out->index], node);
3024 * Emits a MOV [mem], in.
3026 static void bemit_store(const ir_node *node)
3028 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3029 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3031 if (is_ia32_Immediate(value)) {
3034 bemit_mod_am(0, node);
3035 bemit8(get_ia32_immediate_attr_const(value)->offset);
3036 } else if (size == 16) {
3039 bemit_mod_am(0, node);
3040 bemit16(get_ia32_immediate_attr_const(value)->offset);
3043 bemit_mod_am(0, node);
3044 bemit_immediate(value, false);
3047 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3049 if (in->index == REG_GP_EAX) {
3050 ir_node *base = get_irn_n(node, n_ia32_base);
3051 int has_base = !is_ia32_NoReg_GP(base);
3052 ir_node *idx = get_irn_n(node, n_ia32_index);
3053 int has_index = !is_ia32_NoReg_GP(idx);
3054 if (!has_base && !has_index) {
3055 ir_entity *ent = get_ia32_am_sc(node);
3056 int offs = get_ia32_am_offs_int(node);
3057 /* store to constant address from EAX can be encoded as
3058 * 0xA2/0xA3 [offset]*/
3066 bemit_entity(ent, 0, offs, false);
3078 bemit_mod_am(reg_gp_map[in->index], node);
3082 static void bemit_conv_i2i(const ir_node *node)
3084 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3093 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3094 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3095 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3101 static void bemit_push(const ir_node *node)
3103 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3105 if (is_ia32_Immediate(value)) {
3106 const ia32_immediate_attr_t *attr
3107 = get_ia32_immediate_attr_const(value);
3108 unsigned size = get_signed_imm_size(attr->offset);
3114 bemit8((unsigned char)attr->offset);
3119 bemit_immediate(value, false);
3122 } else if (is_ia32_NoReg_GP(value)) {
3124 bemit_mod_am(6, node);
3126 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3127 bemit8(0x50 + reg_gp_map[reg->index]);
3134 static void bemit_pop(const ir_node *node)
3136 const arch_register_t *reg = arch_irn_get_register(node, pn_ia32_Pop_res);
3137 bemit8(0x58 + reg_gp_map[reg->index]);
3140 static void bemit_popmem(const ir_node *node)
3143 bemit_mod_am(0, node);
3146 static void bemit_call(const ir_node *node)
3148 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3150 if (is_ia32_Immediate(proc)) {
3152 bemit_immediate(proc, true);
3154 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3158 static void bemit_jmp(const ir_node *dest_block)
3161 bemit_jmp_destination(dest_block);
3164 static void bemit_jump(const ir_node *node)
3166 if (can_be_fallthrough(node))
3169 bemit_jmp(get_cfop_target_block(node));
3172 static void bemit_jcc(int pnc, const ir_node *dest_block)
3174 unsigned char cc = pnc2cc(pnc);
3177 bemit_jmp_destination(dest_block);
3180 static void bemit_jp(bool odd, const ir_node *dest_block)
3184 bemit_jmp_destination(dest_block);
3187 static void bemit_ia32_jcc(const ir_node *node)
3189 ia32_condition_code_t cc = get_ia32_condcode(node);
3190 const ir_node *proj_true;
3191 const ir_node *proj_false;
3192 const ir_node *dest_true;
3193 const ir_node *dest_false;
3195 cc = determine_final_cc(node, 0, cc);
3197 /* get both Projs */
3198 proj_true = get_proj(node, pn_ia32_Jcc_true);
3199 assert(proj_true && "Jcc without true Proj");
3201 proj_false = get_proj(node, pn_ia32_Jcc_false);
3202 assert(proj_false && "Jcc without false Proj");
3204 if (can_be_fallthrough(proj_true)) {
3205 /* exchange both proj's so the second one can be omitted */
3206 const ir_node *t = proj_true;
3208 proj_true = proj_false;
3210 cc = ia32_negate_condition_code(cc);
3213 dest_true = get_cfop_target_block(proj_true);
3214 dest_false = get_cfop_target_block(proj_false);
3216 if (cc & ia32_cc_float_parity_cases) {
3217 /* Some floating point comparisons require a test of the parity flag,
3218 * which indicates that the result is unordered */
3219 if (cc & ia32_cc_negated) {
3220 bemit_jp(false, dest_true);
3222 /* we need a local label if the false proj is a fallthrough
3223 * as the falseblock might have no label emitted then */
3224 if (can_be_fallthrough(proj_false)) {
3226 bemit8(0x06); // jp + 6
3228 bemit_jp(false, dest_false);
3232 bemit_jcc(cc, dest_true);
3234 /* the second Proj might be a fallthrough */
3235 if (can_be_fallthrough(proj_false)) {
3236 /* it's a fallthrough */
3238 bemit_jmp(dest_false);
3242 static void bemit_switchjmp(const ir_node *node)
3244 ir_entity *jump_table = get_ia32_am_sc(node);
3245 long default_pn = get_ia32_default_pn(node);
3247 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3248 bemit_mod_am(0x05, node);
3250 emit_jump_table(node, default_pn, jump_table, get_cfop_target_block);
3256 static void bemit_return(const ir_node *node)
3258 unsigned pop = be_Return_get_pop(node);
3259 if (pop > 0 || be_Return_get_emit_pop(node)) {
3261 assert(pop <= 0xffff);
3268 static void bemit_subsp(const ir_node *node)
3270 const arch_register_t *out;
3273 /* mov %esp, %out */
3275 out = arch_irn_get_register(node, 1);
3276 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3279 static void bemit_incsp(const ir_node *node)
3282 const arch_register_t *reg;
3286 offs = be_get_IncSP_offset(node);
3297 size = get_signed_imm_size(offs);
3298 bemit8(size == 1 ? 0x83 : 0x81);
3300 reg = arch_irn_get_register(node, 0);
3301 bemit_modru(reg, ext);
3310 static void bemit_copybi(const ir_node *node)
3312 unsigned size = get_ia32_copyb_size(node);
3314 bemit8(0xA4); // movsb
3317 bemit8(0xA5); // movsw
3321 bemit8(0xA5); // movsl
3325 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3327 if (get_ia32_op_type(node) == ia32_Normal) {
3328 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3329 const arch_register_t *in1 = x87_attr->x87[0];
3330 const arch_register_t *in = x87_attr->x87[1];
3331 const arch_register_t *out = x87_attr->x87[2];
3335 } else if (out == in) {
3339 if (out->index == 0) {
3341 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3344 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3347 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3352 bemit_mod_am(code, node);
3356 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3358 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3359 const arch_register_t *out = x87_attr->x87[2];
3361 bemit8(code + out->index);
3364 static void bemit_fabs(const ir_node *node)
3372 static void bemit_fadd(const ir_node *node)
3374 bemit_fbinop(node, 0, 0);
3377 static void bemit_faddp(const ir_node *node)
3379 bemit_fbinopp(node, 0xC0);
3382 static void bemit_fchs(const ir_node *node)
3390 static void bemit_fdiv(const ir_node *node)
3392 bemit_fbinop(node, 6, 7);
3395 static void bemit_fdivp(const ir_node *node)
3397 bemit_fbinopp(node, 0xF8);
3400 static void bemit_fdivr(const ir_node *node)
3402 bemit_fbinop(node, 7, 6);
3405 static void bemit_fdivrp(const ir_node *node)
3407 bemit_fbinopp(node, 0xF0);
3410 static void bemit_fild(const ir_node *node)
3412 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3414 bemit8(0xDF); // filds
3415 bemit_mod_am(0, node);
3419 bemit8(0xDB); // fildl
3420 bemit_mod_am(0, node);
3424 bemit8(0xDF); // fildll
3425 bemit_mod_am(5, node);
3429 panic("invalid mode size");
3433 static void bemit_fist(const ir_node *node)
3435 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3437 bemit8(0xDF); // fists
3441 bemit8(0xDB); // fistl
3445 panic("invalid mode size");
3447 bemit_mod_am(2, node);
3450 static void bemit_fistp(const ir_node *node)
3452 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3454 bemit8(0xDF); // fistps
3455 bemit_mod_am(3, node);
3459 bemit8(0xDB); // fistpl
3460 bemit_mod_am(3, node);
3464 bemit8(0xDF); // fistpll
3465 bemit_mod_am(7, node);
3469 panic("invalid mode size");
3473 static void bemit_fld(const ir_node *node)
3475 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3477 bemit8(0xD9); // flds
3478 bemit_mod_am(0, node);
3482 bemit8(0xDD); // fldl
3483 bemit_mod_am(0, node);
3488 bemit8(0xDB); // fldt
3489 bemit_mod_am(5, node);
3493 panic("invalid mode size");
3497 static void bemit_fld1(const ir_node *node)
3501 bemit8(0xE8); // fld1
3504 static void bemit_fldcw(const ir_node *node)
3506 bemit8(0xD9); // fldcw
3507 bemit_mod_am(5, node);
3510 static void bemit_fldz(const ir_node *node)
3514 bemit8(0xEE); // fldz
3517 static void bemit_fmul(const ir_node *node)
3519 bemit_fbinop(node, 1, 1);
3522 static void bemit_fmulp(const ir_node *node)
3524 bemit_fbinopp(node, 0xC8);
3527 static void bemit_fpop(const ir_node *node)
3529 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3531 bemit8(0xD8 + attr->x87[0]->index);
3534 static void bemit_fpush(const ir_node *node)
3536 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3538 bemit8(0xC0 + attr->x87[0]->index);
3541 static void bemit_fpushcopy(const ir_node *node)
3543 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3545 bemit8(0xC0 + attr->x87[0]->index);
3548 static void bemit_fst(const ir_node *node)
3550 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3552 bemit8(0xD9); // fsts
3556 bemit8(0xDD); // fstl
3560 panic("invalid mode size");
3562 bemit_mod_am(2, node);
3565 static void bemit_fstp(const ir_node *node)
3567 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3569 bemit8(0xD9); // fstps
3570 bemit_mod_am(3, node);
3574 bemit8(0xDD); // fstpl
3575 bemit_mod_am(3, node);
3580 bemit8(0xDB); // fstpt
3581 bemit_mod_am(7, node);
3585 panic("invalid mode size");
3589 static void bemit_fsub(const ir_node *node)
3591 bemit_fbinop(node, 4, 5);
3594 static void bemit_fsubp(const ir_node *node)
3596 bemit_fbinopp(node, 0xE8);
3599 static void bemit_fsubr(const ir_node *node)
3601 bemit_fbinop(node, 5, 4);
3604 static void bemit_fsubrp(const ir_node *node)
3606 bemit_fbinopp(node, 0xE0);
3609 static void bemit_fnstcw(const ir_node *node)
3611 bemit8(0xD9); // fnstcw
3612 bemit_mod_am(7, node);
3615 static void bemit_fnstsw(void)
3617 bemit8(0xDF); // fnstsw %ax
3621 static void bemit_ftstfnstsw(const ir_node *node)
3625 bemit8(0xD9); // ftst
3630 static void bemit_fucomi(const ir_node *node)
3632 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3633 bemit8(0xDB); // fucomi
3634 bemit8(0xE8 + attr->x87[1]->index);
3637 static void bemit_fucomip(const ir_node *node)
3639 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3640 bemit8(0xDF); // fucomip
3641 bemit8(0xE8 + attr->x87[1]->index);
3644 static void bemit_fucomfnstsw(const ir_node *node)
3646 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3647 bemit8(0xDD); // fucom
3648 bemit8(0xE0 + attr->x87[1]->index);
3652 static void bemit_fucompfnstsw(const ir_node *node)
3654 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3655 bemit8(0xDD); // fucomp
3656 bemit8(0xE8 + attr->x87[1]->index);
3660 static void bemit_fucomppfnstsw(const ir_node *node)
3664 bemit8(0xDA); // fucompp
3669 static void bemit_fxch(const ir_node *node)
3671 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3673 bemit8(0xC8 + attr->x87[0]->index);
3677 * The type of a emitter function.
3679 typedef void (*emit_func) (const ir_node *);
3682 * Set a node emitter. Make it a bit more type safe.
3684 static void register_emitter(ir_op *op, emit_func func)
3686 op->ops.generic = (op_func) func;
3689 static void ia32_register_binary_emitters(void)
3691 /* first clear the generic function pointer for all ops */
3692 clear_irp_opcodes_generic_func();
3694 /* benode emitter */
3695 register_emitter(op_be_Copy, bemit_copy);
3696 register_emitter(op_be_CopyKeep, bemit_copy);
3697 register_emitter(op_be_IncSP, bemit_incsp);
3698 register_emitter(op_be_Perm, bemit_perm);
3699 register_emitter(op_be_Return, bemit_return);
3700 register_emitter(op_ia32_Adc, bemit_adc);
3701 register_emitter(op_ia32_Add, bemit_add);
3702 register_emitter(op_ia32_AddMem, bemit_addmem);
3703 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3704 register_emitter(op_ia32_And, bemit_and);
3705 register_emitter(op_ia32_AndMem, bemit_andmem);
3706 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3707 register_emitter(op_ia32_Breakpoint, bemit_int3);
3708 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3709 register_emitter(op_ia32_Call, bemit_call);
3710 register_emitter(op_ia32_Cltd, bemit_cltd);
3711 register_emitter(op_ia32_Cmc, bemit_cmc);
3712 register_emitter(op_ia32_Cmp, bemit_cmp);
3713 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3714 register_emitter(op_ia32_Const, bemit_mov_const);
3715 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3716 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3717 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3718 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3719 register_emitter(op_ia32_Dec, bemit_dec);
3720 register_emitter(op_ia32_DecMem, bemit_decmem);
3721 register_emitter(op_ia32_Div, bemit_div);
3722 register_emitter(op_ia32_FldCW, bemit_fldcw);
3723 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3724 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3725 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3726 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3727 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3728 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3729 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3730 register_emitter(op_ia32_IDiv, bemit_idiv);
3731 register_emitter(op_ia32_IJmp, bemit_ijmp);
3732 register_emitter(op_ia32_IMul, bemit_imul);
3733 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3734 register_emitter(op_ia32_Inc, bemit_inc);
3735 register_emitter(op_ia32_IncMem, bemit_incmem);
3736 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3737 register_emitter(op_ia32_Jmp, bemit_jump);
3738 register_emitter(op_ia32_LdTls, bemit_ldtls);
3739 register_emitter(op_ia32_Lea, bemit_lea);
3740 register_emitter(op_ia32_Leave, bemit_leave);
3741 register_emitter(op_ia32_Load, bemit_load);
3742 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3743 register_emitter(op_ia32_Mul, bemit_mul);
3744 register_emitter(op_ia32_Neg, bemit_neg);
3745 register_emitter(op_ia32_NegMem, bemit_negmem);
3746 register_emitter(op_ia32_Not, bemit_not);
3747 register_emitter(op_ia32_NotMem, bemit_notmem);
3748 register_emitter(op_ia32_Or, bemit_or);
3749 register_emitter(op_ia32_OrMem, bemit_ormem);
3750 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3751 register_emitter(op_ia32_Pop, bemit_pop);
3752 register_emitter(op_ia32_PopEbp, bemit_pop);
3753 register_emitter(op_ia32_PopMem, bemit_popmem);
3754 register_emitter(op_ia32_Push, bemit_push);
3755 register_emitter(op_ia32_RepPrefix, bemit_rep);
3756 register_emitter(op_ia32_Rol, bemit_rol);
3757 register_emitter(op_ia32_RolMem, bemit_rolmem);
3758 register_emitter(op_ia32_Ror, bemit_ror);
3759 register_emitter(op_ia32_RorMem, bemit_rormem);
3760 register_emitter(op_ia32_Sahf, bemit_sahf);
3761 register_emitter(op_ia32_Sar, bemit_sar);
3762 register_emitter(op_ia32_SarMem, bemit_sarmem);
3763 register_emitter(op_ia32_Sbb, bemit_sbb);
3764 register_emitter(op_ia32_Setcc, bemit_setcc);
3765 register_emitter(op_ia32_Shl, bemit_shl);
3766 register_emitter(op_ia32_ShlD, bemit_shld);
3767 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3768 register_emitter(op_ia32_Shr, bemit_shr);
3769 register_emitter(op_ia32_ShrD, bemit_shrd);
3770 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3771 register_emitter(op_ia32_Stc, bemit_stc);
3772 register_emitter(op_ia32_Store, bemit_store);
3773 register_emitter(op_ia32_Store8Bit, bemit_store);
3774 register_emitter(op_ia32_Sub, bemit_sub);
3775 register_emitter(op_ia32_SubMem, bemit_submem);
3776 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3777 register_emitter(op_ia32_SubSP, bemit_subsp);
3778 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3779 register_emitter(op_ia32_Test, bemit_test);
3780 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3781 register_emitter(op_ia32_Xor, bemit_xor);
3782 register_emitter(op_ia32_Xor0, bemit_xor0);
3783 register_emitter(op_ia32_XorMem, bemit_xormem);
3784 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3785 register_emitter(op_ia32_fabs, bemit_fabs);
3786 register_emitter(op_ia32_fadd, bemit_fadd);
3787 register_emitter(op_ia32_faddp, bemit_faddp);
3788 register_emitter(op_ia32_fchs, bemit_fchs);
3789 register_emitter(op_ia32_fdiv, bemit_fdiv);
3790 register_emitter(op_ia32_fdivp, bemit_fdivp);
3791 register_emitter(op_ia32_fdivr, bemit_fdivr);
3792 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3793 register_emitter(op_ia32_fild, bemit_fild);
3794 register_emitter(op_ia32_fist, bemit_fist);
3795 register_emitter(op_ia32_fistp, bemit_fistp);
3796 register_emitter(op_ia32_fld, bemit_fld);
3797 register_emitter(op_ia32_fld1, bemit_fld1);
3798 register_emitter(op_ia32_fldz, bemit_fldz);
3799 register_emitter(op_ia32_fmul, bemit_fmul);
3800 register_emitter(op_ia32_fmulp, bemit_fmulp);
3801 register_emitter(op_ia32_fpop, bemit_fpop);
3802 register_emitter(op_ia32_fpush, bemit_fpush);
3803 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3804 register_emitter(op_ia32_fst, bemit_fst);
3805 register_emitter(op_ia32_fstp, bemit_fstp);
3806 register_emitter(op_ia32_fsub, bemit_fsub);
3807 register_emitter(op_ia32_fsubp, bemit_fsubp);
3808 register_emitter(op_ia32_fsubr, bemit_fsubr);
3809 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3810 register_emitter(op_ia32_fxch, bemit_fxch);
3812 /* ignore the following nodes */
3813 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3814 register_emitter(op_be_Keep, emit_Nothing);
3815 register_emitter(op_be_Start, emit_Nothing);
3816 register_emitter(op_Phi, emit_Nothing);
3817 register_emitter(op_Start, emit_Nothing);
3820 static void gen_binary_block(ir_node *block)
3824 ia32_emit_block_header(block);
3826 /* emit the contents of the block */
3827 sched_foreach(block, node) {
3828 ia32_emit_node(node);
3832 void ia32_gen_binary_routine(ir_graph *irg)
3834 ir_entity *entity = get_irg_entity(irg);
3835 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3836 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3837 ir_node **blk_sched = irg_data->blk_sched;
3840 isa = (ia32_isa_t*) arch_env;
3842 ia32_register_binary_emitters();
3844 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
3846 /* we use links to point to target blocks */
3847 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3848 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3850 /* initialize next block links */
3851 n = ARR_LEN(blk_sched);
3852 for (i = 0; i < n; ++i) {
3853 ir_node *block = blk_sched[i];
3854 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3856 set_irn_link(block, prev);
3859 for (i = 0; i < n; ++i) {
3860 ir_node *block = blk_sched[i];
3861 gen_binary_block(block);
3864 be_gas_emit_function_epilog(entity);
3865 be_dbg_method_end();
3867 be_emit_write_line();
3869 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3873 void ia32_init_emitter(void)
3875 lc_opt_entry_t *be_grp;
3876 lc_opt_entry_t *ia32_grp;
3878 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3879 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3881 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3885 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");