2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
39 #include "iredges_t.h"
42 #include "raw_bitset.h"
45 #include "../besched_t.h"
46 #include "../benode_t.h"
48 #include "../be_dbgout.h"
49 #include "../beemitter.h"
50 #include "../begnuas.h"
51 #include "../beirg_t.h"
52 #include "../be_dbgout.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "ia32_architecture.h"
61 #include "bearch_ia32_t.h"
63 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
65 #define BLOCK_PREFIX ".L"
67 #define SNPRINTF_BUF_LEN 128
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
72 static char pic_base_label[128];
73 static ir_label_t exc_label_id;
74 static int mark_spill_reload = 0;
76 /** Return the next block in Block schedule */
77 static ir_node *get_prev_block_sched(const ir_node *block)
79 return get_irn_link(block);
82 /** Checks if the current block is a fall-through target. */
83 static int is_fallthrough(const ir_node *cfgpred)
87 if (!is_Proj(cfgpred))
89 pred = get_Proj_pred(cfgpred);
90 if (is_ia32_SwitchJmp(pred))
97 * returns non-zero if the given block needs a label
98 * because of being a jump-target (and not a fall-through)
100 static int block_needs_label(const ir_node *block)
103 int n_cfgpreds = get_Block_n_cfgpreds(block);
105 if (n_cfgpreds == 0) {
107 } else if (n_cfgpreds == 1) {
108 ir_node *cfgpred = get_Block_cfgpred(block, 0);
109 ir_node *cfgpred_block = get_nodes_block(cfgpred);
111 if (get_prev_block_sched(block) == cfgpred_block
112 && is_fallthrough(cfgpred)) {
121 * Returns the register at in position pos.
123 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
126 const arch_register_t *reg = NULL;
128 assert(get_irn_arity(irn) > pos && "Invalid IN position");
130 /* The out register of the operator at position pos is the
131 in register we need. */
132 op = get_irn_n(irn, pos);
134 reg = arch_get_irn_register(op);
136 assert(reg && "no in register found");
138 if (reg == &ia32_gp_regs[REG_GP_NOREG])
139 panic("trying to emit noreg for %+F input %d", irn, pos);
141 /* in case of unknown register: just return a valid register */
142 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
143 const arch_register_req_t *req = arch_get_register_req(irn, pos);
145 if (arch_register_req_is(req, limited)) {
146 /* in case of limited requirements: get the first allowed register */
147 unsigned idx = rbitset_next(req->limited, 0, 1);
148 reg = arch_register_for_index(req->cls, idx);
150 /* otherwise get first register in class */
151 reg = arch_register_for_index(req->cls, 0);
159 * Returns the register at out position pos.
161 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
164 const arch_register_t *reg = NULL;
166 /* 1st case: irn is not of mode_T, so it has only */
167 /* one OUT register -> good */
168 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
169 /* Proj with the corresponding projnum for the register */
171 if (get_irn_mode(irn) != mode_T) {
173 reg = arch_get_irn_register(irn);
174 } else if (is_ia32_irn(irn)) {
175 reg = arch_irn_get_register(irn, pos);
177 const ir_edge_t *edge;
179 foreach_out_edge(irn, edge) {
180 proj = get_edge_src_irn(edge);
181 assert(is_Proj(proj) && "non-Proj from mode_T node");
182 if (get_Proj_proj(proj) == pos) {
183 reg = arch_get_irn_register(proj);
189 assert(reg && "no out register found");
194 * Add a number to a prefix. This number will not be used a second time.
196 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
198 static unsigned long id = 0;
199 snprintf(buf, buflen, "%s%lu", prefix, ++id);
203 /*************************************************************
205 * (_) | | / _| | | | |
206 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
207 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
208 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
209 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
212 *************************************************************/
215 * Emit the name of the 8bit low register
217 static void emit_8bit_register(const arch_register_t *reg)
219 const char *reg_name = arch_register_get_name(reg);
222 be_emit_char(reg_name[1]);
227 * Emit the name of the 8bit high register
229 static void emit_8bit_register_high(const arch_register_t *reg)
231 const char *reg_name = arch_register_get_name(reg);
234 be_emit_char(reg_name[1]);
238 static void emit_16bit_register(const arch_register_t *reg)
240 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
243 be_emit_string(reg_name);
246 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
248 const char *reg_name;
251 int size = get_mode_size_bits(mode);
253 case 8: emit_8bit_register(reg); return;
254 case 16: emit_16bit_register(reg); return;
256 assert(mode_is_float(mode) || size == 32);
259 reg_name = arch_register_get_name(reg);
262 be_emit_string(reg_name);
265 void ia32_emit_source_register(const ir_node *node, int pos)
267 const arch_register_t *reg = get_in_reg(node, pos);
269 emit_register(reg, NULL);
272 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
276 set_entity_backend_marked(entity, 1);
277 id = get_entity_ld_ident(entity);
280 if (get_entity_owner(entity) == get_tls_type()) {
281 if (get_entity_visibility(entity) == visibility_external_allocated) {
282 be_emit_cstring("@INDNTPOFF");
284 be_emit_cstring("@NTPOFF");
288 if (!no_pic_adjust && do_pic) {
289 /* TODO: only do this when necessary */
291 be_emit_string(pic_base_label);
295 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
297 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
299 if (attr->symconst != NULL) {
302 ia32_emit_entity(attr->symconst, 0);
304 if (attr->symconst == NULL || attr->offset != 0) {
305 if (attr->symconst != NULL) {
306 be_emit_irprintf("%+d", attr->offset);
308 be_emit_irprintf("0x%X", attr->offset);
313 static void emit_ia32_Immediate(const ir_node *node)
316 emit_ia32_Immediate_no_prefix(node);
319 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
321 const arch_register_t *reg;
322 const ir_node *in = get_irn_n(node, pos);
323 if (is_ia32_Immediate(in)) {
324 emit_ia32_Immediate(in);
328 reg = get_in_reg(node, pos);
329 emit_8bit_register(reg);
332 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
334 const arch_register_t *reg = get_in_reg(node, pos);
335 emit_8bit_register_high(reg);
338 void ia32_emit_dest_register(const ir_node *node, int pos)
340 const arch_register_t *reg = get_out_reg(node, pos);
342 emit_register(reg, NULL);
345 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
347 const arch_register_t *reg = get_out_reg(node, pos);
349 emit_register(reg, mode_Bu);
352 void ia32_emit_x87_register(const ir_node *node, int pos)
354 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
358 be_emit_string(attr->x87[pos]->name);
361 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
363 assert(mode_is_int(mode) || mode_is_reference(mode));
364 switch (get_mode_size_bits(mode)) {
365 case 8: be_emit_char('b'); return;
366 case 16: be_emit_char('w'); return;
367 case 32: be_emit_char('l'); return;
368 /* gas docu says q is the suffix but gcc, objdump and icc use ll
370 case 64: be_emit_cstring("ll"); return;
372 panic("Can't output mode_suffix for %+F", mode);
375 void ia32_emit_mode_suffix(const ir_node *node)
377 ir_mode *mode = get_ia32_ls_mode(node);
381 ia32_emit_mode_suffix_mode(mode);
384 void ia32_emit_x87_mode_suffix(const ir_node *node)
388 /* we only need to emit the mode on address mode */
389 if (get_ia32_op_type(node) == ia32_Normal)
392 mode = get_ia32_ls_mode(node);
393 assert(mode != NULL);
395 if (mode_is_float(mode)) {
396 switch (get_mode_size_bits(mode)) {
397 case 32: be_emit_char('s'); return;
398 case 64: be_emit_char('l'); return;
400 case 96: be_emit_char('t'); return;
403 assert(mode_is_int(mode));
404 switch (get_mode_size_bits(mode)) {
405 case 16: be_emit_char('s'); return;
406 case 32: be_emit_char('l'); return;
407 /* gas docu says q is the suffix but gcc, objdump and icc use ll
409 case 64: be_emit_cstring("ll"); return;
412 panic("Can't output mode_suffix for %+F", mode);
415 static char get_xmm_mode_suffix(ir_mode *mode)
417 assert(mode_is_float(mode));
418 switch(get_mode_size_bits(mode)) {
421 default: panic("Invalid XMM mode");
425 void ia32_emit_xmm_mode_suffix(const ir_node *node)
427 ir_mode *mode = get_ia32_ls_mode(node);
428 assert(mode != NULL);
430 be_emit_char(get_xmm_mode_suffix(mode));
433 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
435 ir_mode *mode = get_ia32_ls_mode(node);
436 assert(mode != NULL);
437 be_emit_char(get_xmm_mode_suffix(mode));
440 void ia32_emit_extend_suffix(const ir_node *node)
442 ir_mode *mode = get_ia32_ls_mode(node);
443 if (get_mode_size_bits(mode) == 32)
445 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
446 ia32_emit_mode_suffix_mode(mode);
449 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
451 ir_node *in = get_irn_n(node, pos);
452 if (is_ia32_Immediate(in)) {
453 emit_ia32_Immediate(in);
455 const ir_mode *mode = get_ia32_ls_mode(node);
456 const arch_register_t *reg = get_in_reg(node, pos);
457 emit_register(reg, mode);
462 * Returns the target block for a control flow node.
464 static ir_node *get_cfop_target_block(const ir_node *irn)
466 assert(get_irn_mode(irn) == mode_X);
467 return get_irn_link(irn);
471 * Emits a block label for the given block.
473 static void ia32_emit_block_name(const ir_node *block)
475 if (has_Block_label(block)) {
476 be_emit_string(be_gas_block_label_prefix());
477 be_emit_irprintf("%lu", get_Block_label(block));
479 be_emit_cstring(BLOCK_PREFIX);
480 be_emit_irprintf("%ld", get_irn_node_nr(block));
485 * Emits the target label for a control flow node.
487 static void ia32_emit_cfop_target(const ir_node *node)
489 ir_node *block = get_cfop_target_block(node);
490 ia32_emit_block_name(block);
494 * positive conditions for signed compares
496 static const char *const cmp2condition_s[] = {
497 NULL, /* always false */
504 NULL /* always true */
508 * positive conditions for unsigned compares
510 static const char *const cmp2condition_u[] = {
511 NULL, /* always false */
518 NULL /* always true */
521 static void ia32_emit_cmp_suffix(int pnc)
525 if (pnc == ia32_pn_Cmp_parity) {
529 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
530 str = cmp2condition_u[pnc & 7];
532 str = cmp2condition_s[pnc & 7];
538 typedef enum ia32_emit_mod_t {
539 EMIT_RESPECT_LS = 1U << 0,
540 EMIT_ALTERNATE_AM = 1U << 1,
545 * fmt parameter output
546 * ---- ---------------------- ---------------------------------------------
548 * %AM <node> address mode of the node
549 * %AR const arch_register_t* address mode of the node or register
550 * %ASx <node> address mode of the node or source register x
551 * %Dx <node> destination register x
552 * %I <node> immediate of the node
553 * %L <node> control flow target of the node
554 * %M <node> mode suffix of the node
555 * %P int condition code
556 * %R const arch_register_t* register
557 * %Sx <node> source register x
558 * %s const char* string
559 * %u unsigned int unsigned int
560 * %d signed int signed int
563 * # modifier for %ASx, %D and %S uses ls mode of node to alter register width
564 * * modifier does not prefix immediates with $, but AM with *
565 * l modifier for %lu and %ld
567 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
573 const char *start = fmt;
574 ia32_emit_mod_t mod = 0;
576 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
579 be_emit_string_len(start, fmt - start);
583 be_emit_finish_line_gas(node);
595 mod |= EMIT_ALTERNATE_AM;
600 mod |= EMIT_RESPECT_LS;
617 if (mod & EMIT_ALTERNATE_AM)
623 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
624 if (mod & EMIT_ALTERNATE_AM)
626 if (get_ia32_op_type(node) == ia32_AddrModeS) {
629 emit_register(reg, NULL);
635 if (get_ia32_op_type(node) == ia32_AddrModeS) {
636 if (mod & EMIT_ALTERNATE_AM)
641 assert(get_ia32_op_type(node) == ia32_Normal);
646 default: goto unknown;
653 const arch_register_t *reg;
655 if (*fmt < '0' || '9' <= *fmt)
659 reg = get_out_reg(node, pos);
660 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
665 if (!(mod & EMIT_ALTERNATE_AM))
667 emit_ia32_Immediate_no_prefix(node);
671 ia32_emit_cfop_target(node);
675 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
680 int pnc = va_arg(ap, int);
681 ia32_emit_cmp_suffix(pnc);
686 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
687 emit_register(reg, NULL);
696 if (*fmt < '0' || '9' <= *fmt)
700 in = get_irn_n(node, pos);
701 if (is_ia32_Immediate(in)) {
702 if (!(mod & EMIT_ALTERNATE_AM))
704 emit_ia32_Immediate_no_prefix(in);
706 const arch_register_t *reg;
708 if (mod & EMIT_ALTERNATE_AM)
710 reg = get_in_reg(node, pos);
711 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
717 const char *str = va_arg(ap, const char*);
723 if (mod & EMIT_LONG) {
724 unsigned long num = va_arg(ap, unsigned long);
725 be_emit_irprintf("%lu", num);
727 unsigned num = va_arg(ap, unsigned);
728 be_emit_irprintf("%u", num);
733 if (mod & EMIT_LONG) {
734 long num = va_arg(ap, long);
735 be_emit_irprintf("%ld", num);
737 int num = va_arg(ap, int);
738 be_emit_irprintf("%d", num);
744 panic("unknown format conversion in ia32_emitf()");
752 * Emits registers and/or address mode of a binary operation.
754 void ia32_emit_binop(const ir_node *node)
756 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
757 ia32_emitf(node, "%#S4, %#AS3");
759 ia32_emitf(node, "%#AS4, %#S3");
764 * Emits registers and/or address mode of a binary operation.
766 void ia32_emit_x87_binop(const ir_node *node)
768 switch(get_ia32_op_type(node)) {
771 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
772 const arch_register_t *in1 = x87_attr->x87[0];
773 const arch_register_t *in = x87_attr->x87[1];
774 const arch_register_t *out = x87_attr->x87[2];
778 } else if (out == in) {
783 be_emit_string(arch_register_get_name(in));
784 be_emit_cstring(", %");
785 be_emit_string(arch_register_get_name(out));
793 assert(0 && "unsupported op type");
798 * Emits registers and/or address mode of a unary operation.
800 void ia32_emit_unop(const ir_node *node, int pos)
804 ia32_emitf(node, fmt);
808 * Emits address mode.
810 void ia32_emit_am(const ir_node *node)
812 ir_entity *ent = get_ia32_am_sc(node);
813 int offs = get_ia32_am_offs_int(node);
814 ir_node *base = get_irn_n(node, n_ia32_base);
815 int has_base = !is_ia32_NoReg_GP(base);
816 ir_node *index = get_irn_n(node, n_ia32_index);
817 int has_index = !is_ia32_NoReg_GP(index);
819 /* just to be sure... */
820 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
824 if (is_ia32_am_sc_sign(node))
826 ia32_emit_entity(ent, 0);
829 /* also handle special case if nothing is set */
830 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
832 be_emit_irprintf("%+d", offs);
834 be_emit_irprintf("%d", offs);
838 if (has_base || has_index) {
843 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
844 emit_register(reg, NULL);
847 /* emit index + scale */
849 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
852 emit_register(reg, NULL);
854 scale = get_ia32_am_scale(node);
856 be_emit_irprintf(",%d", 1 << scale);
863 static void emit_ia32_IMul(const ir_node *node)
865 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
866 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
868 /* do we need the 3-address form? */
869 if (is_ia32_NoReg_GP(left) ||
870 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
871 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
873 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
878 * walks up a tree of copies/perms/spills/reloads to find the original value
879 * that is moved around
881 static ir_node *find_original_value(ir_node *node)
883 if (irn_visited(node))
886 mark_irn_visited(node);
887 if (be_is_Copy(node)) {
888 return find_original_value(be_get_Copy_op(node));
889 } else if (be_is_CopyKeep(node)) {
890 return find_original_value(be_get_CopyKeep_op(node));
891 } else if (is_Proj(node)) {
892 ir_node *pred = get_Proj_pred(node);
893 if (be_is_Perm(pred)) {
894 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
895 } else if (be_is_MemPerm(pred)) {
896 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
897 } else if (is_ia32_Load(pred)) {
898 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
902 } else if (is_ia32_Store(node)) {
903 return find_original_value(get_irn_n(node, n_ia32_Store_val));
904 } else if (is_Phi(node)) {
906 arity = get_irn_arity(node);
907 for (i = 0; i < arity; ++i) {
908 ir_node *in = get_irn_n(node, i);
909 ir_node *res = find_original_value(in);
920 static int determine_final_pnc(const ir_node *node, int flags_pos,
923 ir_node *flags = get_irn_n(node, flags_pos);
924 const ia32_attr_t *flags_attr;
925 flags = skip_Proj(flags);
927 if (is_ia32_Sahf(flags)) {
928 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
929 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
930 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
931 inc_irg_visited(current_ir_graph);
932 cmp = find_original_value(cmp);
934 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
935 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
938 flags_attr = get_ia32_attr_const(cmp);
939 if (flags_attr->data.ins_permuted)
940 pnc = get_mirrored_pnc(pnc);
941 pnc |= ia32_pn_Cmp_float;
942 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
943 || is_ia32_Fucompi(flags)) {
944 flags_attr = get_ia32_attr_const(flags);
946 if (flags_attr->data.ins_permuted)
947 pnc = get_mirrored_pnc(pnc);
948 pnc |= ia32_pn_Cmp_float;
950 flags_attr = get_ia32_attr_const(flags);
952 if (flags_attr->data.ins_permuted)
953 pnc = get_mirrored_pnc(pnc);
954 if (flags_attr->data.cmp_unsigned)
955 pnc |= ia32_pn_Cmp_unsigned;
961 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
963 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
964 return get_negated_pnc(pnc, mode);
967 void ia32_emit_cmp_suffix_node(const ir_node *node,
970 const ia32_attr_t *attr = get_ia32_attr_const(node);
972 pn_Cmp pnc = get_ia32_condcode(node);
974 pnc = determine_final_pnc(node, flags_pos, pnc);
975 if (attr->data.ins_permuted)
976 pnc = ia32_get_negated_pnc(pnc);
978 ia32_emit_cmp_suffix(pnc);
982 * Emits an exception label for a given node.
984 static void ia32_emit_exc_label(const ir_node *node)
986 be_emit_string(be_gas_insn_label_prefix());
987 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
991 * Returns the Proj with projection number proj and NOT mode_M
993 static ir_node *get_proj(const ir_node *node, long proj)
995 const ir_edge_t *edge;
998 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1000 foreach_out_edge(node, edge) {
1001 src = get_edge_src_irn(edge);
1003 assert(is_Proj(src) && "Proj expected");
1004 if (get_irn_mode(src) == mode_M)
1007 if (get_Proj_proj(src) == proj)
1013 static int can_be_fallthrough(const ir_node *node)
1015 ir_node *target_block = get_cfop_target_block(node);
1016 ir_node *block = get_nodes_block(node);
1017 return get_prev_block_sched(target_block) == block;
1021 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1023 static void emit_ia32_Jcc(const ir_node *node)
1025 int need_parity_label = 0;
1026 const ir_node *proj_true;
1027 const ir_node *proj_false;
1028 const ir_node *block;
1029 pn_Cmp pnc = get_ia32_condcode(node);
1031 pnc = determine_final_pnc(node, 0, pnc);
1033 /* get both Projs */
1034 proj_true = get_proj(node, pn_ia32_Jcc_true);
1035 assert(proj_true && "Jcc without true Proj");
1037 proj_false = get_proj(node, pn_ia32_Jcc_false);
1038 assert(proj_false && "Jcc without false Proj");
1040 block = get_nodes_block(node);
1042 if (can_be_fallthrough(proj_true)) {
1043 /* exchange both proj's so the second one can be omitted */
1044 const ir_node *t = proj_true;
1046 proj_true = proj_false;
1048 pnc = ia32_get_negated_pnc(pnc);
1051 if (pnc & ia32_pn_Cmp_float) {
1052 /* Some floating point comparisons require a test of the parity flag,
1053 * which indicates that the result is unordered */
1056 ia32_emitf(proj_true, "\tjp %L\n");
1061 ia32_emitf(proj_true, "\tjnp %L\n");
1067 /* we need a local label if the false proj is a fallthrough
1068 * as the falseblock might have no label emitted then */
1069 if (can_be_fallthrough(proj_false)) {
1070 need_parity_label = 1;
1071 ia32_emitf(proj_false, "\tjp 1f\n");
1073 ia32_emitf(proj_false, "\tjp %L\n");
1080 ia32_emitf(proj_true, "\tjp %L\n");
1088 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1091 if (need_parity_label) {
1092 ia32_emitf(NULL, "1:\n");
1095 /* the second Proj might be a fallthrough */
1096 if (can_be_fallthrough(proj_false)) {
1097 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1099 ia32_emitf(proj_false, "\tjmp %L\n");
1103 static void emit_ia32_CMov(const ir_node *node)
1105 const ia32_attr_t *attr = get_ia32_attr_const(node);
1106 int ins_permuted = attr->data.ins_permuted;
1107 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1108 pn_Cmp pnc = get_ia32_condcode(node);
1109 const arch_register_t *in_true;
1110 const arch_register_t *in_false;
1112 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
1114 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_true));
1115 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMov_val_false));
1117 /* should be same constraint fullfilled? */
1118 if (out == in_false) {
1119 /* yes -> nothing to do */
1120 } else if (out == in_true) {
1121 const arch_register_t *tmp;
1123 assert(get_ia32_op_type(node) == ia32_Normal);
1125 ins_permuted = !ins_permuted;
1132 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1136 pnc = ia32_get_negated_pnc(pnc);
1138 /* TODO: handling of Nans isn't correct yet */
1140 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1143 /*********************************************************
1146 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1147 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1148 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1149 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1152 *********************************************************/
1154 /* jump table entry (target and corresponding number) */
1155 typedef struct _branch_t {
1160 /* jump table for switch generation */
1161 typedef struct _jmp_tbl_t {
1162 ir_node *defProj; /**< default target */
1163 long min_value; /**< smallest switch case */
1164 long max_value; /**< largest switch case */
1165 long num_branches; /**< number of jumps */
1166 char *label; /**< label of the jump table */
1167 branch_t *branches; /**< jump array */
1171 * Compare two variables of type branch_t. Used to sort all switch cases
1173 static int ia32_cmp_branch_t(const void *a, const void *b)
1175 branch_t *b1 = (branch_t *)a;
1176 branch_t *b2 = (branch_t *)b;
1178 if (b1->value <= b2->value)
1185 * Emits code for a SwitchJmp (creates a jump table if
1186 * possible otherwise a cmp-jmp cascade). Port from
1189 static void emit_ia32_SwitchJmp(const ir_node *node)
1191 unsigned long interval;
1197 const ir_edge_t *edge;
1199 /* fill the table structure */
1200 tbl.label = XMALLOCN(char, SNPRINTF_BUF_LEN);
1201 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1203 tbl.num_branches = get_irn_n_edges(node) - 1;
1204 tbl.branches = XMALLOCNZ(branch_t, tbl.num_branches);
1205 tbl.min_value = INT_MAX;
1206 tbl.max_value = INT_MIN;
1208 default_pn = get_ia32_condcode(node);
1210 /* go over all proj's and collect them */
1211 foreach_out_edge(node, edge) {
1212 proj = get_edge_src_irn(edge);
1213 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1215 pnc = get_Proj_proj(proj);
1217 /* check for default proj */
1218 if (pnc == default_pn) {
1219 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1222 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1223 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1225 /* create branch entry */
1226 tbl.branches[i].target = proj;
1227 tbl.branches[i].value = pnc;
1232 assert(i == tbl.num_branches);
1234 /* sort the branches by their number */
1235 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1237 /* two-complement's magic make this work without overflow */
1238 interval = tbl.max_value - tbl.min_value;
1240 /* emit the table */
1241 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1242 ia32_emitf(tbl.defProj, "\tja %L\n");
1244 if (tbl.num_branches > 1) {
1246 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1248 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1249 ia32_emitf(NULL, "\t.align 4\n");
1250 ia32_emitf(NULL, "%s:\n", tbl.label);
1252 last_value = tbl.branches[0].value;
1253 for (i = 0; i != tbl.num_branches; ++i) {
1254 while (last_value != tbl.branches[i].value) {
1255 ia32_emitf(tbl.defProj, ".long %L\n");
1258 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1261 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1263 /* one jump is enough */
1264 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1274 * Emits code for a unconditional jump.
1276 static void emit_Jmp(const ir_node *node)
1280 /* for now, the code works for scheduled and non-schedules blocks */
1281 block = get_nodes_block(node);
1283 /* we have a block schedule */
1284 if (can_be_fallthrough(node)) {
1285 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1287 ia32_emitf(node, "\tjmp %L\n");
1292 * Emit an inline assembler operand.
1294 * @param node the ia32_ASM node
1295 * @param s points to the operand (a %c)
1297 * @return pointer to the first char in s NOT in the current operand
1299 static const char* emit_asm_operand(const ir_node *node, const char *s)
1301 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1302 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1304 const arch_register_t *reg;
1305 const ia32_asm_reg_t *asm_regs = attr->register_map;
1306 const ia32_asm_reg_t *asm_reg;
1307 const char *reg_name;
1316 /* parse modifiers */
1319 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1344 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1351 sscanf(s, "%d%n", &num, &p);
1353 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1360 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1362 "Error: Custom assembler references invalid input/output (%+F)\n",
1366 asm_reg = & asm_regs[num];
1367 assert(asm_reg->valid);
1370 if (asm_reg->use_input == 0) {
1371 reg = get_out_reg(node, asm_reg->inout_pos);
1373 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1375 /* might be an immediate value */
1376 if (is_ia32_Immediate(pred)) {
1377 emit_ia32_Immediate(pred);
1380 reg = get_in_reg(node, asm_reg->inout_pos);
1384 "Warning: no register assigned for %d asm op (%+F)\n",
1389 if (asm_reg->memory) {
1394 if (modifier != 0) {
1398 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1401 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1404 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1407 panic("Invalid asm op modifier");
1409 be_emit_string(reg_name);
1411 emit_register(reg, asm_reg->mode);
1414 if (asm_reg->memory) {
1422 * Emits code for an ASM pseudo op.
1424 static void emit_ia32_Asm(const ir_node *node)
1426 const void *gen_attr = get_irn_generic_attr_const(node);
1427 const ia32_asm_attr_t *attr
1428 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1429 ident *asm_text = attr->asm_text;
1430 const char *s = get_id_str(asm_text);
1432 ia32_emitf(node, "#APP\t\n");
1439 s = emit_asm_operand(node, s);
1445 ia32_emitf(NULL, "\n#NO_APP\n");
1448 /**********************************
1451 * | | ___ _ __ _ _| |_) |
1452 * | | / _ \| '_ \| | | | _ <
1453 * | |___| (_) | |_) | |_| | |_) |
1454 * \_____\___/| .__/ \__, |____/
1457 **********************************/
1460 * Emit movsb/w instructions to make mov count divideable by 4
1462 static void emit_CopyB_prolog(unsigned size)
1465 ia32_emitf(NULL, "\tmovsb\n");
1467 ia32_emitf(NULL, "\tmovsw\n");
1471 * Emit rep movsd instruction for memcopy.
1473 static void emit_ia32_CopyB(const ir_node *node)
1475 unsigned size = get_ia32_copyb_size(node);
1477 emit_CopyB_prolog(size);
1478 ia32_emitf(node, "\trep movsd\n");
1482 * Emits unrolled memcopy.
1484 static void emit_ia32_CopyB_i(const ir_node *node)
1486 unsigned size = get_ia32_copyb_size(node);
1488 emit_CopyB_prolog(size);
1492 ia32_emitf(NULL, "\tmovsd\n");
1498 /***************************
1502 * | | / _ \| '_ \ \ / /
1503 * | |___| (_) | | | \ V /
1504 * \_____\___/|_| |_|\_/
1506 ***************************/
1509 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1511 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1514 ir_mode *ls_mode = get_ia32_ls_mode(node);
1515 int ls_bits = get_mode_size_bits(ls_mode);
1516 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1518 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1521 static void emit_ia32_Conv_I2FP(const ir_node *node)
1523 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1526 static void emit_ia32_Conv_FP2I(const ir_node *node)
1528 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1531 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1533 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1537 * Emits code for an Int conversion.
1539 static void emit_ia32_Conv_I2I(const ir_node *node)
1541 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1542 int signed_mode = mode_is_signed(smaller_mode);
1543 const char *sign_suffix;
1545 assert(!mode_is_float(smaller_mode));
1547 sign_suffix = signed_mode ? "s" : "z";
1548 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1554 static void emit_ia32_Call(const ir_node *node)
1556 /* Special case: Call must not have its immediates prefixed by $, instead
1557 * address mode is prefixed by *. */
1558 ia32_emitf(node, "\tcall %*AS3\n");
1562 /*******************************************
1565 * | |__ ___ _ __ ___ __| | ___ ___
1566 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1567 * | |_) | __/ | | | (_) | (_| | __/\__ \
1568 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1570 *******************************************/
1573 * Emits code to increase stack pointer.
1575 static void emit_be_IncSP(const ir_node *node)
1577 int offs = be_get_IncSP_offset(node);
1583 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1585 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1590 * Emits code for Copy/CopyKeep.
1592 static void Copy_emitter(const ir_node *node, const ir_node *op)
1594 const arch_register_t *in = arch_get_irn_register(op);
1595 const arch_register_t *out = arch_get_irn_register(node);
1600 if (is_unknown_reg(in))
1602 /* copies of vf nodes aren't real... */
1603 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1606 if (get_irn_mode(node) == mode_E) {
1607 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1609 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1613 static void emit_be_Copy(const ir_node *node)
1615 Copy_emitter(node, be_get_Copy_op(node));
1618 static void emit_be_CopyKeep(const ir_node *node)
1620 Copy_emitter(node, be_get_CopyKeep_op(node));
1624 * Emits code for exchange.
1626 static void emit_be_Perm(const ir_node *node)
1628 const arch_register_t *in0, *in1;
1629 const arch_register_class_t *cls0, *cls1;
1631 in0 = arch_get_irn_register(get_irn_n(node, 0));
1632 in1 = arch_get_irn_register(get_irn_n(node, 1));
1634 cls0 = arch_register_get_class(in0);
1635 cls1 = arch_register_get_class(in1);
1637 assert(cls0 == cls1 && "Register class mismatch at Perm");
1639 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1640 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1641 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1642 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1643 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1644 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1645 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1647 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1650 panic("unexpected register class in be_Perm (%+F)", node);
1655 * Emits code for Constant loading.
1657 static void emit_ia32_Const(const ir_node *node)
1659 ia32_emitf(node, "\tmovl %I, %D0\n");
1663 * Emits code to load the TLS base
1665 static void emit_ia32_LdTls(const ir_node *node)
1667 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1670 /* helper function for emit_ia32_Minus64Bit */
1671 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1673 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1676 /* helper function for emit_ia32_Minus64Bit */
1677 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1679 ia32_emitf(node, "\tnegl %R\n", reg);
1682 /* helper function for emit_ia32_Minus64Bit */
1683 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1685 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1688 /* helper function for emit_ia32_Minus64Bit */
1689 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1691 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1694 /* helper function for emit_ia32_Minus64Bit */
1695 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1697 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1700 /* helper function for emit_ia32_Minus64Bit */
1701 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1703 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1706 static void emit_ia32_Minus64Bit(const ir_node *node)
1708 const arch_register_t *in_lo = get_in_reg(node, 0);
1709 const arch_register_t *in_hi = get_in_reg(node, 1);
1710 const arch_register_t *out_lo = get_out_reg(node, 0);
1711 const arch_register_t *out_hi = get_out_reg(node, 1);
1713 if (out_lo == in_lo) {
1714 if (out_hi != in_hi) {
1715 /* a -> a, b -> d */
1718 /* a -> a, b -> b */
1721 } else if (out_lo == in_hi) {
1722 if (out_hi == in_lo) {
1723 /* a -> b, b -> a */
1724 emit_xchg(node, in_lo, in_hi);
1727 /* a -> b, b -> d */
1728 emit_mov(node, in_hi, out_hi);
1729 emit_mov(node, in_lo, out_lo);
1733 if (out_hi == in_lo) {
1734 /* a -> c, b -> a */
1735 emit_mov(node, in_lo, out_lo);
1737 } else if (out_hi == in_hi) {
1738 /* a -> c, b -> b */
1739 emit_mov(node, in_lo, out_lo);
1742 /* a -> c, b -> d */
1743 emit_mov(node, in_lo, out_lo);
1749 emit_neg( node, out_hi);
1750 emit_neg( node, out_lo);
1751 emit_sbb0(node, out_hi);
1755 emit_zero(node, out_hi);
1756 emit_neg( node, out_lo);
1757 emit_sbb( node, in_hi, out_hi);
1760 static void emit_ia32_GetEIP(const ir_node *node)
1762 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1763 ia32_emitf(NULL, "%s:\n", pic_base_label);
1764 ia32_emitf(node, "\tpopl %D0\n");
1767 static void emit_ia32_ClimbFrame(const ir_node *node)
1769 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1771 ia32_emitf(node, "\tmovl %S0, %D0\n");
1772 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1773 ia32_emitf(NULL, BLOCK_PREFIX "%ld:\n", get_irn_node_nr(node));
1774 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1775 ia32_emitf(node, "\tdec %S1\n");
1776 ia32_emitf(node, "\tjnz " BLOCK_PREFIX "%ld\n", get_irn_node_nr(node));
1779 static void emit_be_Return(const ir_node *node)
1781 unsigned pop = be_Return_get_pop(node);
1783 if (pop > 0 || be_Return_get_emit_pop(node)) {
1784 ia32_emitf(node, "\tret $%u\n", pop);
1786 ia32_emitf(node, "\tret\n");
1790 static void emit_Nothing(const ir_node *node)
1796 /***********************************************************************************
1799 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1800 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1801 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1802 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1804 ***********************************************************************************/
1807 * Enters the emitter functions for handled nodes into the generic
1808 * pointer of an opcode.
1810 static void ia32_register_emitters(void)
1812 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1813 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1814 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1815 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1816 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1817 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1819 /* first clear the generic function pointer for all ops */
1820 clear_irp_opcodes_generic_func();
1822 /* register all emitter functions defined in spec */
1823 ia32_register_spec_emitters();
1825 /* other ia32 emitter functions */
1826 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1831 IA32_EMIT(Conv_FP2FP);
1832 IA32_EMIT(Conv_FP2I);
1833 IA32_EMIT(Conv_I2FP);
1834 IA32_EMIT(Conv_I2I);
1841 IA32_EMIT(Minus64Bit);
1842 IA32_EMIT(SwitchJmp);
1843 IA32_EMIT(ClimbFrame);
1845 /* benode emitter */
1868 typedef void (*emit_func_ptr) (const ir_node *);
1871 * Assign and emit an exception label if the current instruction can fail.
1873 static void ia32_assign_exc_label(ir_node *node)
1875 /* assign a new ID to the instruction */
1876 set_ia32_exc_label_id(node, ++exc_label_id);
1878 ia32_emit_exc_label(node);
1880 be_emit_pad_comment();
1881 be_emit_cstring("/* exception to Block ");
1882 ia32_emit_cfop_target(node);
1883 be_emit_cstring(" */\n");
1884 be_emit_write_line();
1888 * Emits code for a node.
1890 static void ia32_emit_node(ir_node *node)
1892 ir_op *op = get_irn_op(node);
1894 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1896 if (is_ia32_irn(node)) {
1897 if (get_ia32_exc_label(node)) {
1898 /* emit the exception label of this instruction */
1899 ia32_assign_exc_label(node);
1901 if (mark_spill_reload) {
1902 if (is_ia32_is_spill(node)) {
1903 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1905 if (is_ia32_is_reload(node)) {
1906 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1908 if (is_ia32_is_remat(node)) {
1909 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1913 if (op->ops.generic) {
1914 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1916 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1921 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1927 * Emits gas alignment directives
1929 static void ia32_emit_alignment(unsigned align, unsigned skip)
1931 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1935 * Emits gas alignment directives for Labels depended on cpu architecture.
1937 static void ia32_emit_align_label(void)
1939 unsigned align = ia32_cg_config.label_alignment;
1940 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1941 ia32_emit_alignment(align, maximum_skip);
1945 * Test whether a block should be aligned.
1946 * For cpus in the P4/Athlon class it is useful to align jump labels to
1947 * 16 bytes. However we should only do that if the alignment nops before the
1948 * label aren't executed more often than we have jumps to the label.
1950 static int should_align_block(const ir_node *block)
1952 static const double DELTA = .0001;
1953 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1954 ir_node *prev = get_prev_block_sched(block);
1956 double prev_freq = 0; /**< execfreq of the fallthrough block */
1957 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1960 if (exec_freq == NULL)
1962 if (ia32_cg_config.label_alignment_factor <= 0)
1965 block_freq = get_block_execfreq(exec_freq, block);
1966 if (block_freq < DELTA)
1969 n_cfgpreds = get_Block_n_cfgpreds(block);
1970 for(i = 0; i < n_cfgpreds; ++i) {
1971 const ir_node *pred = get_Block_cfgpred_block(block, i);
1972 double pred_freq = get_block_execfreq(exec_freq, pred);
1975 prev_freq += pred_freq;
1977 jmp_freq += pred_freq;
1981 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1984 jmp_freq /= prev_freq;
1986 return jmp_freq > ia32_cg_config.label_alignment_factor;
1990 * Emit the block header for a block.
1992 * @param block the block
1993 * @param prev_block the previous block
1995 static void ia32_emit_block_header(ir_node *block)
1997 ir_graph *irg = current_ir_graph;
1998 int need_label = block_needs_label(block);
2000 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2002 if (block == get_irg_end_block(irg))
2005 if (ia32_cg_config.label_alignment > 0) {
2006 /* align the current block if:
2007 * a) if should be aligned due to its execution frequency
2008 * b) there is no fall-through here
2010 if (should_align_block(block)) {
2011 ia32_emit_align_label();
2013 /* if the predecessor block has no fall-through,
2014 we can always align the label. */
2016 int has_fallthrough = 0;
2018 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2019 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2020 if (can_be_fallthrough(cfg_pred)) {
2021 has_fallthrough = 1;
2026 if (!has_fallthrough)
2027 ia32_emit_align_label();
2031 if (need_label || has_Block_label(block)) {
2032 ia32_emit_block_name(block);
2035 be_emit_pad_comment();
2036 be_emit_cstring(" /* ");
2038 be_emit_cstring("\t/* ");
2039 ia32_emit_block_name(block);
2040 be_emit_cstring(": ");
2043 be_emit_cstring("preds:");
2045 /* emit list of pred blocks in comment */
2046 arity = get_irn_arity(block);
2048 be_emit_cstring(" none");
2050 for (i = 0; i < arity; ++i) {
2051 ir_node *predblock = get_Block_cfgpred_block(block, i);
2052 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2055 if (exec_freq != NULL) {
2056 be_emit_irprintf(", freq: %f",
2057 get_block_execfreq(exec_freq, block));
2059 be_emit_cstring(" */\n");
2060 be_emit_write_line();
2064 * Walks over the nodes in a block connected by scheduling edges
2065 * and emits code for each node.
2067 static void ia32_gen_block(ir_node *block)
2071 ia32_emit_block_header(block);
2073 /* emit the contents of the block */
2074 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2075 sched_foreach(block, node) {
2076 ia32_emit_node(node);
2080 typedef struct exc_entry {
2081 ir_node *exc_instr; /** The instruction that can issue an exception. */
2082 ir_node *block; /** The block to call then. */
2087 * Sets labels for control flow nodes (jump target).
2088 * Links control predecessors to there destination blocks.
2090 static void ia32_gen_labels(ir_node *block, void *data)
2092 exc_entry **exc_list = data;
2096 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2097 pred = get_Block_cfgpred(block, n);
2098 set_irn_link(pred, block);
2100 pred = skip_Proj(pred);
2101 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2106 ARR_APP1(exc_entry, *exc_list, e);
2107 set_irn_link(pred, block);
2113 * Compare two exception_entries.
2115 static int cmp_exc_entry(const void *a, const void *b)
2117 const exc_entry *ea = a;
2118 const exc_entry *eb = b;
2120 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2126 * Main driver. Emits the code for one routine.
2128 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2130 ir_entity *entity = get_irg_entity(irg);
2131 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2136 do_pic = cg->birg->main_env->options->pic;
2138 ia32_register_emitters();
2140 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2142 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2143 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2145 /* we use links to point to target blocks */
2146 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2147 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2149 /* initialize next block links */
2150 n = ARR_LEN(cg->blk_sched);
2151 for (i = 0; i < n; ++i) {
2152 ir_node *block = cg->blk_sched[i];
2153 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2155 set_irn_link(block, prev);
2158 for (i = 0; i < n; ++i) {
2159 ir_node *block = cg->blk_sched[i];
2161 ia32_gen_block(block);
2164 be_gas_emit_function_epilog(entity);
2165 be_dbg_method_end();
2167 be_emit_write_line();
2169 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2171 /* Sort the exception table using the exception label id's.
2172 Those are ascending with ascending addresses. */
2173 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2177 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2178 be_emit_cstring("\t.long ");
2179 ia32_emit_exc_label(exc_list[i].exc_instr);
2181 be_emit_cstring("\t.long ");
2182 ia32_emit_block_name(exc_list[i].block);
2186 DEL_ARR_F(exc_list);
2189 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2190 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2194 void ia32_init_emitter(void)
2196 lc_opt_entry_t *be_grp;
2197 lc_opt_entry_t *ia32_grp;
2199 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
2200 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
2202 lc_opt_add_table(ia32_grp, ia32_emitter_options);
2204 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");