2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
157 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
160 be_emit_char(reg->name[1]); /* get the basic name of the register */
165 * Emit the name of the 8bit high register
167 static void emit_8bit_register_high(const arch_register_t *reg)
169 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
170 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
173 be_emit_char(reg->name[1]); /* get the basic name of the register */
177 static void emit_16bit_register(const arch_register_t *reg)
180 be_emit_string(reg->name + 1); /* skip the 'e' prefix of the 32bit names */
184 * emit a register, possible shortened by a mode
186 * @param reg the register
187 * @param mode the mode of the register or NULL for full register
189 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
192 int size = get_mode_size_bits(mode);
194 case 8: emit_8bit_register(reg); return;
195 case 16: emit_16bit_register(reg); return;
197 assert(mode_is_float(mode) || size == 32);
201 be_emit_string(reg->name);
204 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
206 be_gas_emit_entity(entity);
208 if (get_entity_owner(entity) == get_tls_type()) {
209 if (!entity_has_definition(entity)) {
210 be_emit_cstring("@INDNTPOFF");
212 be_emit_cstring("@NTPOFF");
216 if (do_pic && !no_pic_adjust) {
218 be_emit_string(pic_base_label);
222 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
224 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
226 if (attr->symconst != NULL) {
229 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
231 if (attr->symconst == NULL || attr->offset != 0) {
232 if (attr->symconst != NULL) {
233 be_emit_irprintf("%+d", attr->offset);
235 be_emit_irprintf("0x%X", attr->offset);
240 static void emit_ia32_Immediate(const ir_node *node)
243 emit_ia32_Immediate_no_prefix(node);
246 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
248 assert(mode_is_int(mode) || mode_is_reference(mode));
249 switch (get_mode_size_bits(mode)) {
250 case 8: be_emit_char('b'); return;
251 case 16: be_emit_char('w'); return;
252 case 32: be_emit_char('l'); return;
253 /* gas docu says q is the suffix but gcc, objdump and icc use ll
255 case 64: be_emit_cstring("ll"); return;
257 panic("Can't output mode_suffix for %+F", mode);
260 static void ia32_emit_x87_mode_suffix(ir_node const *const node)
264 /* we only need to emit the mode on address mode */
265 if (get_ia32_op_type(node) == ia32_Normal)
268 mode = get_ia32_ls_mode(node);
269 assert(mode != NULL);
271 if (mode_is_float(mode)) {
272 switch (get_mode_size_bits(mode)) {
273 case 32: be_emit_char('s'); return;
274 case 64: be_emit_char('l'); return;
275 /* long doubles have different sizes due to alignment on different
279 case 128: be_emit_char('t'); return;
282 assert(mode_is_int(mode) || mode_is_reference(mode));
283 switch (get_mode_size_bits(mode)) {
284 case 16: be_emit_char('s'); return;
285 case 32: be_emit_char('l'); return;
286 /* gas docu says q is the suffix but gcc, objdump and icc use ll
288 case 64: be_emit_cstring("ll"); return;
291 panic("Can't output mode_suffix for %+F", mode);
294 static char get_xmm_mode_suffix(ir_mode *mode)
296 assert(mode_is_float(mode));
297 switch (get_mode_size_bits(mode)) {
300 default: panic("Invalid XMM mode");
304 static void ia32_emit_xmm_mode_suffix(ir_node const *const node)
306 ir_mode *mode = get_ia32_ls_mode(node);
307 assert(mode != NULL);
308 be_emit_char(get_xmm_mode_suffix(mode));
312 * Returns the target block for a control flow node.
314 static ir_node *get_cfop_target_block(const ir_node *irn)
316 assert(get_irn_mode(irn) == mode_X);
317 return (ir_node*)get_irn_link(irn);
321 * Emits the target label for a control flow node.
323 static void ia32_emit_cfop_target(const ir_node *node)
325 ir_node *block = get_cfop_target_block(node);
326 be_gas_emit_block_name(block);
330 * Emit the suffix for a compare instruction.
332 static void ia32_emit_condition_code(ia32_condition_code_t cc)
335 case ia32_cc_overflow: be_emit_cstring("o"); return;
336 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
337 case ia32_cc_float_below:
338 case ia32_cc_float_unordered_below:
339 case ia32_cc_below: be_emit_cstring("b"); return;
340 case ia32_cc_float_above_equal:
341 case ia32_cc_float_unordered_above_equal:
342 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
343 case ia32_cc_float_equal:
344 case ia32_cc_equal: be_emit_cstring("e"); return;
345 case ia32_cc_float_not_equal:
346 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
347 case ia32_cc_float_below_equal:
348 case ia32_cc_float_unordered_below_equal:
349 case ia32_cc_below_equal: be_emit_cstring("be"); return;
350 case ia32_cc_float_above:
351 case ia32_cc_float_unordered_above:
352 case ia32_cc_above: be_emit_cstring("a"); return;
353 case ia32_cc_sign: be_emit_cstring("s"); return;
354 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
355 case ia32_cc_parity: be_emit_cstring("p"); return;
356 case ia32_cc_not_parity: be_emit_cstring("np"); return;
357 case ia32_cc_less: be_emit_cstring("l"); return;
358 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
359 case ia32_cc_less_equal: be_emit_cstring("le"); return;
360 case ia32_cc_greater: be_emit_cstring("g"); return;
361 case ia32_cc_float_parity_cases:
362 case ia32_cc_additional_float_cases:
365 panic("Invalid ia32 condition code");
368 typedef enum ia32_emit_mod_t {
370 EMIT_RESPECT_LS = 1U << 0,
371 EMIT_ALTERNATE_AM = 1U << 1,
373 EMIT_HIGH_REG = 1U << 3,
374 EMIT_LOW_REG = 1U << 4,
375 EMIT_16BIT_REG = 1U << 5
377 ENUM_BITSET(ia32_emit_mod_t)
380 * Emits address mode.
382 static void ia32_emit_am(ir_node const *const node)
384 ir_entity *ent = get_ia32_am_sc(node);
385 int offs = get_ia32_am_offs_int(node);
386 ir_node *base = get_irn_n(node, n_ia32_base);
387 int has_base = !is_ia32_NoReg_GP(base);
388 ir_node *idx = get_irn_n(node, n_ia32_index);
389 int has_index = !is_ia32_NoReg_GP(idx);
391 /* just to be sure... */
392 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
394 if (get_ia32_am_tls_segment(node))
395 be_emit_cstring("%gs:");
399 const ia32_attr_t *attr = get_ia32_attr_const(node);
400 if (is_ia32_am_sc_sign(node))
402 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
405 /* also handle special case if nothing is set */
406 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
408 be_emit_irprintf("%+d", offs);
410 be_emit_irprintf("%d", offs);
414 if (has_base || has_index) {
419 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
420 emit_register(reg, NULL);
423 /* emit index + scale */
425 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
428 emit_register(reg, NULL);
430 scale = get_ia32_am_scale(node);
432 be_emit_irprintf(",%d", 1 << scale);
439 static ia32_condition_code_t determine_final_cc(ir_node const *node, int flags_pos, ia32_condition_code_t cc);
441 void ia32_emitf(ir_node const *const node, char const *fmt, ...)
448 const char *start = fmt;
449 ia32_emit_mod_t mod = EMIT_NONE;
451 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
454 be_emit_string_len(start, fmt - start);
459 be_emit_write_line();
473 case '*': mod |= EMIT_ALTERNATE_AM; break;
474 case '#': mod |= EMIT_RESPECT_LS; break;
475 case 'l': mod |= EMIT_LONG; break;
476 case '>': mod |= EMIT_HIGH_REG; break;
477 case '<': mod |= EMIT_LOW_REG; break;
478 case '^': mod |= EMIT_16BIT_REG; break;
487 arch_register_t const *reg;
497 if (get_ia32_op_type(node) == ia32_AddrModeS) {
500 assert(get_ia32_op_type(node) == ia32_Normal);
501 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
502 char const *const fmt = attr->res_in_reg ? "%%st, %%%s" : "%%%s, %%st";
503 be_emit_irprintf(fmt, attr->reg->name);
509 if (mod & EMIT_ALTERNATE_AM)
515 reg = va_arg(ap, const arch_register_t*);
516 if (get_ia32_op_type(node) == ia32_AddrModeS) {
523 if (get_ia32_op_type(node) == ia32_AddrModeS) {
527 assert(get_ia32_op_type(node) == ia32_Normal);
531 default: goto unknown;
537 imm = get_irn_n(node, n_ia32_binary_right);
538 if (is_ia32_Immediate(imm)) {
539 emit_ia32_Immediate(imm);
540 be_emit_cstring(", ");
541 if (get_ia32_op_type(node) == ia32_AddrModeS) {
544 assert(get_ia32_op_type(node) == ia32_Normal);
545 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
546 emit_register(reg, get_ia32_ls_mode(node));
549 if (get_ia32_op_type(node) == ia32_AddrModeS) {
552 assert(get_ia32_op_type(node) == ia32_Normal);
553 reg = arch_get_irn_register_in(node, n_ia32_binary_right);
554 emit_register(reg, get_ia32_ls_mode(node));
556 be_emit_cstring(", ");
557 reg = arch_get_irn_register_in(node, n_ia32_binary_left);
558 emit_register(reg, get_ia32_ls_mode(node));
563 if (*fmt < '0' || '9' < *fmt)
565 reg = arch_get_irn_register_out(node, *fmt++ - '0');
570 ia32_emit_x87_mode_suffix(node);
571 } else if (*fmt == 'P') {
572 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
575 } else if (*fmt == 'R') {
576 /* NOTE: Work around a gas quirk for non-commutative operations if the
577 * destination register is not %st0. In this case r/non-r is swapped.
578 * %st0 = %st0 - %st1 -> fsub %st1, %st0 (as expected)
579 * %st0 = %st1 - %st0 -> fsubr %st1, %st0 (as expected)
580 * %st1 = %st0 - %st1 -> fsub %st0, %st1 (expected: fsubr)
581 * %st1 = %st1 - %st0 -> fsubr %st0, %st1 (expected: fsub)
582 * In fact this corresponds to the encoding of the instruction:
583 * - The r suffix selects whether %st0 is on the left (no r) or on the
584 * right (r) side of the executed operation.
585 * - The placement of %st0 selects whether the result is written to
586 * %st0 (right) or the other register (left).
587 * This means that it is sufficient to test whether the operands are
588 * permuted. In particular it is not necessary to consider wether the
589 * result is to be placed into the explicit register operand. */
590 if (get_ia32_x87_attr_const(node)->attr.data.ins_permuted)
592 } else if (*fmt == 'X') {
593 ia32_emit_xmm_mode_suffix(node);
594 } else if (*fmt == '0') {
596 be_emit_string(get_ia32_x87_attr_const(node)->reg->name);
606 if (!(mod & EMIT_ALTERNATE_AM))
608 emit_ia32_Immediate_no_prefix(imm);
612 ia32_emit_cfop_target(node);
616 ir_mode *mode = get_ia32_ls_mode(node);
619 if (mod & EMIT_RESPECT_LS) {
620 if (get_mode_size_bits(mode) == 32)
622 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
624 ia32_emit_mode_suffix_mode(mode);
629 ia32_condition_code_t cc;
632 cc = (ia32_condition_code_t)va_arg(ap, int);
633 } else if ('0' <= *fmt && *fmt <= '9') {
634 cc = get_ia32_condcode(node);
635 cc = determine_final_cc(node, *fmt - '0', cc);
640 ia32_emit_condition_code(cc);
645 reg = va_arg(ap, const arch_register_t*);
647 if (mod & EMIT_ALTERNATE_AM)
649 if (mod & EMIT_HIGH_REG) {
650 emit_8bit_register_high(reg);
651 } else if (mod & EMIT_LOW_REG) {
652 emit_8bit_register(reg);
653 } else if (mod & EMIT_16BIT_REG) {
654 emit_16bit_register(reg);
656 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
664 if (*fmt < '0' || '9' < *fmt)
668 imm = get_irn_n(node, pos);
669 if (is_ia32_Immediate(imm)) {
672 reg = arch_get_irn_register_in(node, pos);
678 const char *str = va_arg(ap, const char*);
684 if (mod & EMIT_LONG) {
685 unsigned long num = va_arg(ap, unsigned long);
686 be_emit_irprintf("%lu", num);
688 unsigned num = va_arg(ap, unsigned);
689 be_emit_irprintf("%u", num);
694 if (mod & EMIT_LONG) {
695 long num = va_arg(ap, long);
696 be_emit_irprintf("%ld", num);
698 int num = va_arg(ap, int);
699 be_emit_irprintf("%d", num);
705 panic("unknown format conversion");
709 be_emit_finish_line_gas(node);
713 static void emit_ia32_IMul(const ir_node *node)
715 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
716 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
718 /* do we need the 3-address form? */
719 if (is_ia32_NoReg_GP(left) ||
720 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
721 ia32_emitf(node, "imul%M %#S4, %#AS3, %#D0");
723 ia32_emitf(node, "imul%M %#AS4, %#S3");
728 * walks up a tree of copies/perms/spills/reloads to find the original value
729 * that is moved around
731 static ir_node *find_original_value(ir_node *node)
733 if (irn_visited(node))
736 mark_irn_visited(node);
737 if (be_is_Copy(node)) {
738 return find_original_value(be_get_Copy_op(node));
739 } else if (be_is_CopyKeep(node)) {
740 return find_original_value(be_get_CopyKeep_op(node));
741 } else if (is_Proj(node)) {
742 ir_node *pred = get_Proj_pred(node);
743 if (be_is_Perm(pred)) {
744 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
745 } else if (be_is_MemPerm(pred)) {
746 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
747 } else if (is_ia32_Load(pred)) {
748 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
749 } else if (is_ia32_Store(pred)) {
750 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
754 } else if (is_Phi(node)) {
756 arity = get_irn_arity(node);
757 for (i = 0; i < arity; ++i) {
758 ir_node *in = get_irn_n(node, i);
759 ir_node *res = find_original_value(in);
770 static ia32_condition_code_t determine_final_cc(const ir_node *node,
771 int flags_pos, ia32_condition_code_t cc)
773 ir_node *flags = get_irn_n(node, flags_pos);
774 const ia32_attr_t *flags_attr;
775 flags = skip_Proj(flags);
777 if (is_ia32_Sahf(flags)) {
778 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
779 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
780 inc_irg_visited(current_ir_graph);
781 cmp = find_original_value(cmp);
783 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
786 flags_attr = get_ia32_attr_const(cmp);
788 flags_attr = get_ia32_attr_const(flags);
791 if (flags_attr->data.ins_permuted)
792 cc = ia32_invert_condition_code(cc);
797 * Emits an exception label for a given node.
799 static void ia32_emit_exc_label(const ir_node *node)
801 be_emit_string(be_gas_insn_label_prefix());
802 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
806 * Returns the Proj with projection number proj and NOT mode_M
808 static ir_node *get_proj(const ir_node *node, long proj)
812 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
814 foreach_out_edge(node, edge) {
815 src = get_edge_src_irn(edge);
817 assert(is_Proj(src) && "Proj expected");
818 if (get_irn_mode(src) == mode_M)
821 if (get_Proj_proj(src) == proj)
827 static int can_be_fallthrough(const ir_node *node)
829 ir_node *target_block = get_cfop_target_block(node);
830 ir_node *block = get_nodes_block(node);
831 return get_prev_block_sched(target_block) == block;
835 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
837 static void emit_ia32_Jcc(const ir_node *node)
839 int need_parity_label = 0;
840 ia32_condition_code_t cc = get_ia32_condcode(node);
841 const ir_node *proj_true;
842 const ir_node *proj_false;
844 cc = determine_final_cc(node, 0, cc);
847 proj_true = get_proj(node, pn_ia32_Jcc_true);
848 assert(proj_true && "Jcc without true Proj");
850 proj_false = get_proj(node, pn_ia32_Jcc_false);
851 assert(proj_false && "Jcc without false Proj");
853 if (can_be_fallthrough(proj_true)) {
854 /* exchange both proj's so the second one can be omitted */
855 const ir_node *t = proj_true;
857 proj_true = proj_false;
859 cc = ia32_negate_condition_code(cc);
862 if (cc & ia32_cc_float_parity_cases) {
863 /* Some floating point comparisons require a test of the parity flag,
864 * which indicates that the result is unordered */
865 if (cc & ia32_cc_negated) {
866 ia32_emitf(proj_true, "jp %L");
868 /* we need a local label if the false proj is a fallthrough
869 * as the falseblock might have no label emitted then */
870 if (can_be_fallthrough(proj_false)) {
871 need_parity_label = 1;
872 ia32_emitf(proj_false, "jp 1f");
874 ia32_emitf(proj_false, "jp %L");
878 ia32_emitf(proj_true, "j%PX %L", (int)cc);
879 if (need_parity_label) {
880 be_emit_cstring("1:\n");
881 be_emit_write_line();
884 /* the second Proj might be a fallthrough */
885 if (can_be_fallthrough(proj_false)) {
886 if (be_options.verbose_asm)
887 ia32_emitf(proj_false, "/* fallthrough to %L */");
889 ia32_emitf(proj_false, "jmp %L");
894 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
897 static void emit_ia32_Setcc(const ir_node *node)
899 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
901 ia32_condition_code_t cc = get_ia32_condcode(node);
902 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
903 if (cc & ia32_cc_float_parity_cases) {
904 if (cc & ia32_cc_negated) {
905 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
906 ia32_emitf(node, "setp %>R", dreg);
907 ia32_emitf(node, "orb %>R, %<R", dreg, dreg);
909 ia32_emitf(node, "set%PX %<R", (int)cc, dreg);
910 ia32_emitf(node, "setnp %>R", dreg);
911 ia32_emitf(node, "andb %>R, %<R", dreg, dreg);
914 ia32_emitf(node, "set%PX %#R", (int)cc, dreg);
918 static void emit_ia32_CMovcc(const ir_node *node)
920 const ia32_attr_t *attr = get_ia32_attr_const(node);
921 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
922 ia32_condition_code_t cc = get_ia32_condcode(node);
923 const arch_register_t *in_true;
924 const arch_register_t *in_false;
926 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
927 /* although you can't set ins_permuted in the constructor it might still
928 * be set by memory operand folding
929 * Permuting inputs of a cmov means the condition is negated!
931 if (attr->data.ins_permuted)
932 cc = ia32_negate_condition_code(cc);
934 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
935 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
937 /* should be same constraint fullfilled? */
938 if (out == in_false) {
939 /* yes -> nothing to do */
940 } else if (out == in_true) {
941 const arch_register_t *tmp;
943 assert(get_ia32_op_type(node) == ia32_Normal);
945 cc = ia32_negate_condition_code(cc);
952 ia32_emitf(node, "movl %R, %R", in_false, out);
955 if (cc & ia32_cc_float_parity_cases) {
956 panic("CMov with floatingpoint compare/parity not supported yet");
959 ia32_emitf(node, "cmov%PX %#AR, %#R", (int)cc, in_true, out);
963 * Emits code for a SwitchJmp
965 static void emit_ia32_SwitchJmp(const ir_node *node)
967 ir_entity *jump_table = get_ia32_am_sc(node);
968 const ir_switch_table *table = get_ia32_switch_table(node);
970 ia32_emitf(node, "jmp %*AM");
971 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
975 * Emits code for a unconditional jump.
977 static void emit_ia32_Jmp(const ir_node *node)
979 /* we have a block schedule */
980 if (can_be_fallthrough(node)) {
981 if (be_options.verbose_asm)
982 ia32_emitf(node, "/* fallthrough to %L */");
984 ia32_emitf(node, "jmp %L");
989 * Emit an inline assembler operand.
991 * @param node the ia32_ASM node
992 * @param s points to the operand (a %c)
994 * @return pointer to the first char in s NOT in the current operand
996 static const char* emit_asm_operand(const ir_node *node, const char *s)
998 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
999 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1001 const arch_register_t *reg;
1002 const ia32_asm_reg_t *asm_regs = attr->register_map;
1003 const ia32_asm_reg_t *asm_reg;
1012 /* parse modifiers */
1015 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1040 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1047 if (sscanf(s, "%d%n", &num, &p) != 1) {
1048 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1055 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1057 "Error: Custom assembler references invalid input/output (%+F)\n",
1061 asm_reg = & asm_regs[num];
1062 assert(asm_reg->valid);
1065 if (asm_reg->use_input == 0) {
1066 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1068 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1070 /* might be an immediate value */
1071 if (is_ia32_Immediate(pred)) {
1072 emit_ia32_Immediate(pred);
1075 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1079 "Warning: no register assigned for %d asm op (%+F)\n",
1084 if (asm_reg->memory) {
1089 if (modifier != 0) {
1092 emit_8bit_register(reg);
1095 emit_8bit_register_high(reg);
1098 emit_16bit_register(reg);
1101 panic("Invalid asm op modifier");
1104 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1107 if (asm_reg->memory) {
1115 * Emits code for an ASM pseudo op.
1117 static void emit_ia32_Asm(const ir_node *node)
1119 const void *gen_attr = get_irn_generic_attr_const(node);
1120 const ia32_asm_attr_t *attr
1121 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1122 ident *asm_text = attr->asm_text;
1123 const char *s = get_id_str(asm_text);
1125 be_emit_cstring("#APP\n");
1126 be_emit_write_line();
1133 s = emit_asm_operand(node, s);
1139 be_emit_cstring("\n#NO_APP\n");
1140 be_emit_write_line();
1145 * Emit movsb/w instructions to make mov count divideable by 4
1147 static void emit_CopyB_prolog(unsigned size)
1150 ia32_emitf(NULL, "movsb");
1152 ia32_emitf(NULL, "movsw");
1156 * Emit rep movsd instruction for memcopy.
1158 static void emit_ia32_CopyB(const ir_node *node)
1160 unsigned size = get_ia32_copyb_size(node);
1162 emit_CopyB_prolog(size);
1163 ia32_emitf(node, "rep movsd");
1167 * Emits unrolled memcopy.
1169 static void emit_ia32_CopyB_i(const ir_node *node)
1171 unsigned size = get_ia32_copyb_size(node);
1173 emit_CopyB_prolog(size);
1177 ia32_emitf(NULL, "movsd");
1183 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1185 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1188 ir_mode *ls_mode = get_ia32_ls_mode(node);
1189 int ls_bits = get_mode_size_bits(ls_mode);
1190 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1192 ia32_emitf(node, "cvt%s %AS3, %D0", conv);
1195 static void emit_ia32_Conv_I2FP(const ir_node *node)
1197 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1200 static void emit_ia32_Conv_FP2I(const ir_node *node)
1202 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1205 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1207 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1211 * Emits code to increase stack pointer.
1213 static void emit_be_IncSP(const ir_node *node)
1215 int offs = be_get_IncSP_offset(node);
1221 ia32_emitf(node, "subl $%u, %D0", offs);
1223 ia32_emitf(node, "addl $%u, %D0", -offs);
1228 * Emits code for Copy/CopyKeep.
1230 static void Copy_emitter(const ir_node *node, const ir_node *op)
1232 const arch_register_t *in = arch_get_irn_register(op);
1233 const arch_register_t *out = arch_get_irn_register(node);
1238 /* copies of vf nodes aren't real... */
1239 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
1242 ia32_emitf(node, "movl %R, %R", in, out);
1245 static void emit_be_Copy(const ir_node *node)
1247 Copy_emitter(node, be_get_Copy_op(node));
1250 static void emit_be_CopyKeep(const ir_node *node)
1252 Copy_emitter(node, be_get_CopyKeep_op(node));
1256 * Emits code for exchange.
1258 static void emit_be_Perm(const ir_node *node)
1260 const arch_register_t *in0, *in1;
1262 in0 = arch_get_irn_register(get_irn_n(node, 0));
1263 in1 = arch_get_irn_register(get_irn_n(node, 1));
1265 arch_register_class_t const *const cls0 = in0->reg_class;
1266 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
1268 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1269 ia32_emitf(node, "xchg %R, %R", in1, in0);
1270 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1271 ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
1272 ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
1273 ia32_emitf(node, "xorpd %R, %R", in1, in0);
1274 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1276 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1279 panic("unexpected register class in be_Perm (%+F)", node);
1283 /* helper function for emit_ia32_Minus64Bit */
1284 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1286 ia32_emitf(node, "movl %R, %R", src, dst);
1289 /* helper function for emit_ia32_Minus64Bit */
1290 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1292 ia32_emitf(node, "negl %R", reg);
1295 /* helper function for emit_ia32_Minus64Bit */
1296 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1298 ia32_emitf(node, "sbbl $0, %R", reg);
1301 /* helper function for emit_ia32_Minus64Bit */
1302 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1304 ia32_emitf(node, "sbbl %R, %R", src, dst);
1307 /* helper function for emit_ia32_Minus64Bit */
1308 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1310 ia32_emitf(node, "xchgl %R, %R", src, dst);
1313 /* helper function for emit_ia32_Minus64Bit */
1314 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1316 ia32_emitf(node, "xorl %R, %R", reg, reg);
1319 static void emit_ia32_Minus64Bit(const ir_node *node)
1321 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1322 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1323 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1324 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1326 if (out_lo == in_lo) {
1327 if (out_hi != in_hi) {
1328 /* a -> a, b -> d */
1331 /* a -> a, b -> b */
1334 } else if (out_lo == in_hi) {
1335 if (out_hi == in_lo) {
1336 /* a -> b, b -> a */
1337 emit_xchg(node, in_lo, in_hi);
1340 /* a -> b, b -> d */
1341 emit_mov(node, in_hi, out_hi);
1342 emit_mov(node, in_lo, out_lo);
1346 if (out_hi == in_lo) {
1347 /* a -> c, b -> a */
1348 emit_mov(node, in_lo, out_lo);
1350 } else if (out_hi == in_hi) {
1351 /* a -> c, b -> b */
1352 emit_mov(node, in_lo, out_lo);
1355 /* a -> c, b -> d */
1356 emit_mov(node, in_lo, out_lo);
1362 emit_neg( node, out_hi);
1363 emit_neg( node, out_lo);
1364 emit_sbb0(node, out_hi);
1368 emit_zero(node, out_hi);
1369 emit_neg( node, out_lo);
1370 emit_sbb( node, in_hi, out_hi);
1373 static void emit_ia32_GetEIP(const ir_node *node)
1375 ia32_emitf(node, "call %s", pic_base_label);
1376 be_emit_irprintf("%s:\n", pic_base_label);
1377 be_emit_write_line();
1378 ia32_emitf(node, "popl %D0");
1381 static void emit_ia32_ClimbFrame(const ir_node *node)
1383 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1385 ia32_emitf(node, "movl %S0, %D0");
1386 ia32_emitf(node, "movl $%u, %S1", attr->count);
1387 be_gas_emit_block_name(node);
1388 be_emit_cstring(":\n");
1389 be_emit_write_line();
1390 ia32_emitf(node, "movl (%D0), %D0");
1391 ia32_emitf(node, "dec %S1");
1392 be_emit_cstring("\tjnz ");
1393 be_gas_emit_block_name(node);
1394 be_emit_finish_line_gas(node);
1397 static void emit_be_Return(const ir_node *node)
1399 unsigned pop = be_Return_get_pop(node);
1401 if (pop > 0 || be_Return_get_emit_pop(node)) {
1402 ia32_emitf(node, "ret $%u", pop);
1404 ia32_emitf(node, "ret");
1408 static void emit_Nothing(const ir_node *node)
1415 * Enters the emitter functions for handled nodes into the generic
1416 * pointer of an opcode.
1418 static void ia32_register_emitters(void)
1420 #define IA32_EMIT(a) op_ia32_##a->ops.generic = (op_func)emit_ia32_##a
1421 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1422 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1423 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1424 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1426 /* first clear the generic function pointer for all ops */
1427 ir_clear_opcodes_generic_func();
1429 /* register all emitter functions defined in spec */
1430 ia32_register_spec_emitters();
1432 /* other ia32 emitter functions */
1435 IA32_EMIT(Conv_FP2FP);
1436 IA32_EMIT(Conv_FP2I);
1437 IA32_EMIT(Conv_I2FP);
1444 IA32_EMIT(Minus64Bit);
1445 IA32_EMIT(SwitchJmp);
1446 IA32_EMIT(ClimbFrame);
1449 /* benode emitter */
1468 typedef void (*emit_func_ptr) (const ir_node *);
1471 * Assign and emit an exception label if the current instruction can fail.
1473 static void ia32_assign_exc_label(ir_node *node)
1475 /* assign a new ID to the instruction */
1476 set_ia32_exc_label_id(node, ++exc_label_id);
1478 ia32_emit_exc_label(node);
1480 be_emit_pad_comment();
1481 be_emit_cstring("/* exception to Block ");
1482 ia32_emit_cfop_target(node);
1483 be_emit_cstring(" */\n");
1484 be_emit_write_line();
1488 * Emits code for a node.
1490 static void ia32_emit_node(ir_node *node)
1492 ir_op *op = get_irn_op(node);
1494 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1496 if (is_ia32_irn(node)) {
1497 if (get_ia32_exc_label(node)) {
1498 /* emit the exception label of this instruction */
1499 ia32_assign_exc_label(node);
1501 if (mark_spill_reload) {
1502 if (is_ia32_is_spill(node)) {
1503 ia32_emitf(NULL, "xchg %ebx, %ebx /* spill mark */");
1505 if (is_ia32_is_reload(node)) {
1506 ia32_emitf(NULL, "xchg %edx, %edx /* reload mark */");
1508 if (is_ia32_is_remat(node)) {
1509 ia32_emitf(NULL, "xchg %ecx, %ecx /* remat mark */");
1513 if (op->ops.generic) {
1514 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1516 be_dwarf_location(get_irn_dbg_info(node));
1521 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1526 int sp_change = arch_get_sp_bias(node);
1527 if (sp_change != 0) {
1528 assert(sp_change != SP_BIAS_RESET);
1529 callframe_offset += sp_change;
1530 be_dwarf_callframe_offset(callframe_offset);
1536 * Emits gas alignment directives
1538 static void ia32_emit_alignment(unsigned align, unsigned skip)
1540 ia32_emitf(NULL, ".p2align %u,,%u", align, skip);
1544 * Emits gas alignment directives for Labels depended on cpu architecture.
1546 static void ia32_emit_align_label(void)
1548 unsigned align = ia32_cg_config.label_alignment;
1549 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1550 ia32_emit_alignment(align, maximum_skip);
1554 * Test whether a block should be aligned.
1555 * For cpus in the P4/Athlon class it is useful to align jump labels to
1556 * 16 bytes. However we should only do that if the alignment nops before the
1557 * label aren't executed more often than we have jumps to the label.
1559 static int should_align_block(const ir_node *block)
1561 static const double DELTA = .0001;
1562 ir_node *prev = get_prev_block_sched(block);
1563 double prev_freq = 0; /**< execfreq of the fallthrough block */
1564 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1568 if (ia32_cg_config.label_alignment_factor <= 0)
1571 block_freq = get_block_execfreq(block);
1572 if (block_freq < DELTA)
1575 n_cfgpreds = get_Block_n_cfgpreds(block);
1576 for (i = 0; i < n_cfgpreds; ++i) {
1577 const ir_node *pred = get_Block_cfgpred_block(block, i);
1578 double pred_freq = get_block_execfreq(pred);
1581 prev_freq += pred_freq;
1583 jmp_freq += pred_freq;
1587 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1590 jmp_freq /= prev_freq;
1592 return jmp_freq > ia32_cg_config.label_alignment_factor;
1596 * Emit the block header for a block.
1598 * @param block the block
1599 * @param prev_block the previous block
1601 static void ia32_emit_block_header(ir_node *block)
1603 ir_graph *irg = current_ir_graph;
1604 int need_label = block_needs_label(block);
1606 if (block == get_irg_end_block(irg))
1609 if (ia32_cg_config.label_alignment > 0) {
1610 /* align the current block if:
1611 * a) if should be aligned due to its execution frequency
1612 * b) there is no fall-through here
1614 if (should_align_block(block)) {
1615 ia32_emit_align_label();
1617 /* if the predecessor block has no fall-through,
1618 we can always align the label. */
1620 int has_fallthrough = 0;
1622 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1623 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1624 if (can_be_fallthrough(cfg_pred)) {
1625 has_fallthrough = 1;
1630 if (!has_fallthrough)
1631 ia32_emit_align_label();
1635 be_gas_begin_block(block, need_label);
1639 * Walks over the nodes in a block connected by scheduling edges
1640 * and emits code for each node.
1642 static void ia32_gen_block(ir_node *block)
1644 ia32_emit_block_header(block);
1647 ir_graph *irg = get_irn_irg(block);
1648 callframe_offset = 4; /* 4 bytes for the return address */
1649 /* ESP guessing, TODO perform a real ESP simulation */
1650 if (block != get_irg_start_block(irg)) {
1651 callframe_offset += frame_type_size;
1653 be_dwarf_callframe_offset(callframe_offset);
1656 /* emit the contents of the block */
1657 be_dwarf_location(get_irn_dbg_info(block));
1658 sched_foreach(block, node) {
1659 ia32_emit_node(node);
1663 typedef struct exc_entry {
1664 ir_node *exc_instr; /** The instruction that can issue an exception. */
1665 ir_node *block; /** The block to call then. */
1670 * Sets labels for control flow nodes (jump target).
1671 * Links control predecessors to there destination blocks.
1673 static void ia32_gen_labels(ir_node *block, void *data)
1675 exc_entry **exc_list = (exc_entry**)data;
1679 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1680 pred = get_Block_cfgpred(block, n);
1681 set_irn_link(pred, block);
1683 pred = skip_Proj(pred);
1684 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1689 ARR_APP1(exc_entry, *exc_list, e);
1690 set_irn_link(pred, block);
1696 * Compare two exception_entries.
1698 static int cmp_exc_entry(const void *a, const void *b)
1700 const exc_entry *ea = (const exc_entry*)a;
1701 const exc_entry *eb = (const exc_entry*)b;
1703 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1708 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1710 ir_entity *entity = get_irg_entity(irg);
1711 ir_type *type = get_entity_type(entity);
1712 size_t n_params = get_method_n_params(type);
1713 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1714 ir_type *arg_type = layout->arg_type;
1715 size_t n_members = get_compound_n_members(arg_type);
1716 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1719 for (i = 0; i < n_members; ++i) {
1720 ir_entity *member = get_compound_member(arg_type, i);
1722 if (!is_parameter_entity(member))
1724 param = get_entity_parameter_number(member);
1725 if (param == IR_VA_START_PARAMETER_NUMBER)
1727 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1728 infos[param].reg = NULL;
1729 infos[param].entity = member;
1736 * Main driver. Emits the code for one routine.
1738 void ia32_gen_routine(ir_graph *irg)
1740 ir_entity *entity = get_irg_entity(irg);
1741 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1742 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1743 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1744 ir_node **blk_sched = irg_data->blk_sched;
1745 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1746 parameter_dbg_info_t *infos;
1749 isa = (ia32_isa_t*) arch_env;
1750 do_pic = be_options.pic;
1752 be_gas_elf_type_char = '@';
1754 ia32_register_emitters();
1756 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1758 infos = construct_parameter_infos(irg);
1759 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1763 sp_relative = layout->sp_relative;
1764 if (layout->sp_relative) {
1765 ir_type *frame_type = get_irg_frame_type(irg);
1766 frame_type_size = get_type_size_bytes(frame_type);
1767 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1769 /* well not entirely correct here, we should emit this after the
1770 * "movl esp, ebp" */
1771 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1772 /* TODO: do not hardcode the following */
1773 be_dwarf_callframe_offset(8);
1774 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1777 /* we use links to point to target blocks */
1778 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1779 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1781 /* initialize next block links */
1782 n = ARR_LEN(blk_sched);
1783 for (i = 0; i < n; ++i) {
1784 ir_node *block = blk_sched[i];
1785 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1787 set_irn_link(block, prev);
1790 for (i = 0; i < n; ++i) {
1791 ir_node *block = blk_sched[i];
1793 ia32_gen_block(block);
1796 be_gas_emit_function_epilog(entity);
1798 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1800 /* Sort the exception table using the exception label id's.
1801 Those are ascending with ascending addresses. */
1802 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1806 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1807 be_emit_cstring("\t.long ");
1808 ia32_emit_exc_label(exc_list[e].exc_instr);
1810 be_emit_cstring("\t.long ");
1811 be_gas_emit_block_name(exc_list[e].block);
1815 DEL_ARR_F(exc_list);
1818 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1819 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
1823 /* ==== Experimental binary emitter ==== */
1825 static unsigned char reg_gp_map[N_ia32_gp_REGS];
1826 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
1827 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
1829 static void build_reg_map(void)
1831 reg_gp_map[REG_GP_EAX] = 0x0;
1832 reg_gp_map[REG_GP_ECX] = 0x1;
1833 reg_gp_map[REG_GP_EDX] = 0x2;
1834 reg_gp_map[REG_GP_EBX] = 0x3;
1835 reg_gp_map[REG_GP_ESP] = 0x4;
1836 reg_gp_map[REG_GP_EBP] = 0x5;
1837 reg_gp_map[REG_GP_ESI] = 0x6;
1838 reg_gp_map[REG_GP_EDI] = 0x7;
1841 /** Returns the encoding for a pnc field. */
1842 static unsigned char pnc2cc(ia32_condition_code_t cc)
1847 /** Sign extension bit values for binops */
1849 UNSIGNED_IMM = 0, /**< unsigned immediate */
1850 SIGNEXT_IMM = 2, /**< sign extended immediate */
1853 /** The mod encoding of the ModR/M */
1855 MOD_IND = 0x00, /**< [reg1] */
1856 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
1857 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
1858 MOD_REG = 0xC0 /**< reg1 */
1861 /** create R/M encoding for ModR/M */
1862 #define ENC_RM(x) (x)
1863 /** create REG encoding for ModR/M */
1864 #define ENC_REG(x) ((x) << 3)
1866 /** create encoding for a SIB byte */
1867 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
1869 /* Node: The following routines are supposed to append bytes, words, dwords
1870 to the output stream.
1871 Currently the implementation is stupid in that it still creates output
1872 for an "assembler" in the form of .byte, .long
1873 We will change this when enough infrastructure is there to create complete
1874 machine code in memory/object files */
1876 static void bemit8(const unsigned char byte)
1878 be_emit_irprintf("\t.byte 0x%x\n", byte);
1879 be_emit_write_line();
1882 static void bemit16(const unsigned short u16)
1884 be_emit_irprintf("\t.word 0x%x\n", u16);
1885 be_emit_write_line();
1888 static void bemit32(const unsigned u32)
1890 be_emit_irprintf("\t.long 0x%x\n", u32);
1891 be_emit_write_line();
1895 * Emit address of an entity. If @p is_relative is true then a relative
1896 * offset from behind the address to the entity is created.
1898 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
1901 if (entity == NULL) {
1906 /* the final version should remember the position in the bytestream
1907 and patch it with the correct address at linktime... */
1908 be_emit_cstring("\t.long ");
1911 be_gas_emit_entity(entity);
1913 if (get_entity_owner(entity) == get_tls_type()) {
1914 if (!entity_has_definition(entity)) {
1915 be_emit_cstring("@INDNTPOFF");
1917 be_emit_cstring("@NTPOFF");
1922 be_emit_cstring("-.");
1927 be_emit_irprintf("%+d", offset);
1930 be_emit_write_line();
1933 static void bemit_jmp_destination(const ir_node *dest_block)
1935 be_emit_cstring("\t.long ");
1936 be_gas_emit_block_name(dest_block);
1937 be_emit_cstring(" - . - 4\n");
1938 be_emit_write_line();
1941 /* end emit routines, all emitters following here should only use the functions
1944 typedef enum reg_modifier {
1949 /** Create a ModR/M byte for src1,src2 registers */
1950 static void bemit_modrr(const arch_register_t *src1,
1951 const arch_register_t *src2)
1953 unsigned char modrm = MOD_REG;
1954 modrm |= ENC_RM(reg_gp_map[src1->index]);
1955 modrm |= ENC_REG(reg_gp_map[src2->index]);
1959 /** Create a ModR/M8 byte for src1,src2 registers */
1960 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
1961 reg_modifier_t high_part2, const arch_register_t *src2)
1963 unsigned char modrm = MOD_REG;
1964 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
1965 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
1969 /** Create a ModR/M byte for one register and extension */
1970 static void bemit_modru(const arch_register_t *reg, unsigned ext)
1972 unsigned char modrm = MOD_REG;
1974 modrm |= ENC_RM(reg_gp_map[reg->index]);
1975 modrm |= ENC_REG(ext);
1979 /** Create a ModR/M8 byte for one register */
1980 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
1982 unsigned char modrm = MOD_REG;
1983 assert(reg_gp_map[reg->index] < 4);
1984 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
1990 * Calculate the size of an signed immediate in bytes.
1992 * @param offset an offset
1994 static unsigned get_signed_imm_size(int offset)
1996 if (-128 <= offset && offset < 128) {
1998 } else if (-32768 <= offset && offset < 32768) {
2006 * Emit an address mode.
2008 * @param reg content of the reg field: either a register index or an opcode extension
2009 * @param node the node
2011 static void bemit_mod_am(unsigned reg, const ir_node *node)
2013 ir_entity *ent = get_ia32_am_sc(node);
2014 int offs = get_ia32_am_offs_int(node);
2015 ir_node *base = get_irn_n(node, n_ia32_base);
2016 int has_base = !is_ia32_NoReg_GP(base);
2017 ir_node *idx = get_irn_n(node, n_ia32_index);
2018 int has_index = !is_ia32_NoReg_GP(idx);
2021 unsigned emitoffs = 0;
2022 bool emitsib = false;
2025 /* set the mod part depending on displacement */
2027 modrm |= MOD_IND_WORD_OFS;
2029 } else if (offs == 0) {
2032 } else if (-128 <= offs && offs < 128) {
2033 modrm |= MOD_IND_BYTE_OFS;
2036 modrm |= MOD_IND_WORD_OFS;
2041 const arch_register_t *base_reg = arch_get_irn_register(base);
2042 base_enc = reg_gp_map[base_reg->index];
2044 /* Use the EBP encoding + MOD_IND if NO base register. There is
2045 * always a 32bit offset present in this case. */
2051 /* Determine if we need a SIB byte. */
2053 const arch_register_t *reg_index = arch_get_irn_register(idx);
2054 int scale = get_ia32_am_scale(node);
2056 /* R/M set to ESP means SIB in 32bit mode. */
2057 modrm |= ENC_RM(0x04);
2058 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2060 } else if (base_enc == 0x04) {
2061 /* for the above reason we are forced to emit a SIB when base is ESP.
2062 * Only the base is used, index must be ESP too, which means no index.
2064 modrm |= ENC_RM(0x04);
2065 sib = ENC_SIB(0, 0x04, 0x04);
2068 modrm |= ENC_RM(base_enc);
2071 /* We are forced to emit an 8bit offset as EBP base without offset is a
2072 * special case for SIB without base register. */
2073 if (base_enc == 0x05 && emitoffs == 0) {
2074 modrm |= MOD_IND_BYTE_OFS;
2078 modrm |= ENC_REG(reg);
2084 /* emit displacement */
2085 if (emitoffs == 8) {
2086 bemit8((unsigned) offs);
2087 } else if (emitoffs == 32) {
2088 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2093 * Emit a binop with a immediate operand.
2095 * @param node the node to emit
2096 * @param opcode_eax the opcode for the op eax, imm variant
2097 * @param opcode the opcode for the reg, imm variant
2098 * @param ruval the opcode extension for opcode
2100 static void bemit_binop_with_imm(
2101 const ir_node *node,
2102 unsigned char opcode_ax,
2103 unsigned char opcode, unsigned char ruval)
2105 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2106 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2107 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2110 /* Some instructions (test) have no short form with 32bit value + 8bit
2112 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2115 /* check for sign extension */
2116 size = get_signed_imm_size(attr->offset);
2121 bemit8(opcode | SIGNEXT_IMM);
2122 /* cmp has this special mode */
2123 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2124 bemit_mod_am(ruval, node);
2126 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2127 bemit_modru(reg, ruval);
2129 bemit8((unsigned char)attr->offset);
2133 /* check for eax variant: this variant is shorter for 32bit immediates only */
2134 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2136 bemit_mod_am(ruval, node);
2138 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2139 if (reg->index == REG_GP_EAX) {
2143 bemit_modru(reg, ruval);
2146 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2149 panic("invalid imm size?!?");
2155 static void bemit_binop_2(const ir_node *node, unsigned code)
2157 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2159 if (get_ia32_op_type(node) == ia32_Normal) {
2160 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2161 bemit_modrr(op2, out);
2163 bemit_mod_am(reg_gp_map[out->index], node);
2170 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2172 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2173 if (is_ia32_Immediate(right)) {
2174 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2176 bemit_binop_2(node, opcodes[0]);
2183 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2186 if (get_ia32_op_type(node) == ia32_Normal) {
2187 const arch_register_t *in = arch_get_irn_register_in(node, input);
2188 bemit_modru(in, ext);
2190 bemit_mod_am(ext, node);
2194 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2196 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2197 bemit_unop(node, code, reg_gp_map[out->index], input);
2200 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2202 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2205 bemit8(size == 8 ? code : code + 1);
2206 bemit_mod_am(ext, node);
2209 static void bemit_0f_unop_reg(ir_node const *const node, unsigned char const code, int const input)
2212 bemit_unop_reg(node, code, input);
2215 static void bemit_immediate(const ir_node *node, bool relative)
2217 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2218 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2221 static void bemit_copy(const ir_node *copy)
2223 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2224 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2228 /* copies of vf nodes aren't real... */
2229 if (in->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
2232 assert(in->reg_class == &ia32_reg_classes[CLASS_ia32_gp]);
2234 bemit_modrr(in, out);
2237 static void bemit_perm(const ir_node *node)
2239 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2240 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2241 const arch_register_class_t *cls0 = in0->reg_class;
2243 assert(cls0 == in1->reg_class && "Register class mismatch at Perm");
2245 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2246 if (in0->index == REG_GP_EAX) {
2247 bemit8(0x90 + reg_gp_map[in1->index]);
2248 } else if (in1->index == REG_GP_EAX) {
2249 bemit8(0x90 + reg_gp_map[in0->index]);
2252 bemit_modrr(in0, in1);
2254 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2255 panic("unimplemented"); // TODO implement
2256 //ia32_emitf(NULL, "xorpd %R, %R", in1, in0);
2257 //ia32_emitf(NULL, "xorpd %R, %R", in0, in1);
2258 //ia32_emitf(node, "xorpd %R, %R", in1, in0);
2259 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2261 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2264 panic("unexpected register class in be_Perm (%+F)", node);
2268 static void bemit_xor0(const ir_node *node)
2270 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2272 bemit_modrr(out, out);
2275 static void bemit_mov_const(const ir_node *node)
2277 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2278 bemit8(0xB8 + reg_gp_map[out->index]);
2279 bemit_immediate(node, false);
2283 * Creates a function for a Binop with 3 possible encodings.
2285 #define BINOP(op, op0, op1, op2, op2_ext) \
2286 static void bemit_ ## op(const ir_node *node) { \
2287 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2288 bemit_binop(node, op ## _codes); \
2291 /* insn def eax,imm imm */
2292 BINOP(add, 0x03, 0x05, 0x81, 0)
2293 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2294 BINOP(adc, 0x13, 0x15, 0x81, 2)
2295 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2296 BINOP(and, 0x23, 0x25, 0x81, 4)
2297 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2298 BINOP(xor, 0x33, 0x35, 0x81, 6)
2299 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2301 #define BINOPMEM(op, ext) \
2302 static void bemit_##op(const ir_node *node) \
2305 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2308 val = get_irn_n(node, n_ia32_unary_op); \
2309 if (is_ia32_Immediate(val)) { \
2310 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2311 int offset = attr->offset; \
2312 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2314 bemit_mod_am(ext, node); \
2318 bemit_mod_am(ext, node); \
2322 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2326 bemit8(ext << 3 | 1); \
2327 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2331 static void bemit_##op##8bit(const ir_node *node) \
2333 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2334 if (is_ia32_Immediate(val)) { \
2336 bemit_mod_am(ext, node); \
2337 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2340 bemit_mod_am(reg_gp_map[arch_get_irn_register(val)->index], node); \
2352 * Creates a function for an Unop with code /ext encoding.
2354 #define UNOP(op, code, ext, input) \
2355 static void bemit_ ## op(const ir_node *node) { \
2356 bemit_unop(node, code, ext, input); \
2359 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2360 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2361 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2362 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2363 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2364 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2366 /* TODO: am support for IJmp */
2367 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2369 #define SHIFT(op, ext) \
2370 static void bemit_##op(const ir_node *node) \
2372 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2373 ir_node *count = get_irn_n(node, 1); \
2374 if (is_ia32_Immediate(count)) { \
2375 int offset = get_ia32_immediate_attr_const(count)->offset; \
2376 if (offset == 1) { \
2378 bemit_modru(out, ext); \
2381 bemit_modru(out, ext); \
2386 bemit_modru(out, ext); \
2390 static void bemit_##op##mem(const ir_node *node) \
2393 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2396 count = get_irn_n(node, 1); \
2397 if (is_ia32_Immediate(count)) { \
2398 int offset = get_ia32_immediate_attr_const(count)->offset; \
2399 if (offset == 1) { \
2400 bemit8(size == 8 ? 0xD0 : 0xD1); \
2401 bemit_mod_am(ext, node); \
2403 bemit8(size == 8 ? 0xC0 : 0xC1); \
2404 bemit_mod_am(ext, node); \
2408 bemit8(size == 8 ? 0xD2 : 0xD3); \
2409 bemit_mod_am(ext, node); \
2419 static void bemit_shld(const ir_node *node)
2421 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2422 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2423 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2425 if (is_ia32_Immediate(count)) {
2427 bemit_modrr(out, in);
2428 bemit8(get_ia32_immediate_attr_const(count)->offset);
2431 bemit_modrr(out, in);
2435 static void bemit_shrd(const ir_node *node)
2437 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2438 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2439 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2441 if (is_ia32_Immediate(count)) {
2443 bemit_modrr(out, in);
2444 bemit8(get_ia32_immediate_attr_const(count)->offset);
2447 bemit_modrr(out, in);
2451 static void bemit_sbb0(ir_node const *const node)
2453 arch_register_t const *const out = arch_get_irn_register_out(node, pn_ia32_Sbb0_res);
2454 unsigned char const reg = reg_gp_map[out->index];
2456 bemit8(MOD_REG | ENC_REG(reg) | ENC_RM(reg));
2460 * binary emitter for setcc.
2462 static void bemit_setcc(const ir_node *node)
2464 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2466 ia32_condition_code_t cc = get_ia32_condcode(node);
2467 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2468 if (cc & ia32_cc_float_parity_cases) {
2469 if (cc & ia32_cc_negated) {
2472 bemit8(0x90 | pnc2cc(cc));
2473 bemit_modrm8(REG_LOW, dreg);
2478 bemit_modrm8(REG_HIGH, dreg);
2480 /* orb %>dreg, %<dreg */
2482 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2486 bemit8(0x90 | pnc2cc(cc));
2487 bemit_modrm8(REG_LOW, dreg);
2492 bemit_modrm8(REG_HIGH, dreg);
2494 /* andb %>dreg, %<dreg */
2496 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2501 bemit8(0x90 | pnc2cc(cc));
2502 bemit_modrm8(REG_LOW, dreg);
2506 static void bemit_bsf(ir_node const *const node)
2508 bemit_0f_unop_reg(node, 0xBC, n_ia32_Bsf_operand);
2511 static void bemit_bsr(ir_node const *const node)
2513 bemit_0f_unop_reg(node, 0xBD, n_ia32_Bsr_operand);
2516 static void bemit_bswap(ir_node const *const node)
2519 bemit_modru(arch_get_irn_register_out(node, pn_ia32_Bswap_res), 1);
2522 static void bemit_bt(ir_node const *const node)
2525 arch_register_t const *const lreg = arch_get_irn_register_in(node, n_ia32_Bt_left);
2526 ir_node const *const right = get_irn_n(node, n_ia32_Bt_right);
2527 if (is_ia32_Immediate(right)) {
2528 ia32_immediate_attr_t const *const attr = get_ia32_immediate_attr_const(right);
2529 int const offset = attr->offset;
2530 assert(!attr->symconst);
2531 assert(get_signed_imm_size(offset) == 1);
2533 bemit_modru(lreg, 4);
2537 bemit_modrr(lreg, arch_get_irn_register(right));
2541 static void bemit_cmovcc(const ir_node *node)
2543 const ia32_attr_t *attr = get_ia32_attr_const(node);
2544 int ins_permuted = attr->data.ins_permuted;
2545 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2546 ia32_condition_code_t cc = get_ia32_condcode(node);
2547 const arch_register_t *in_true;
2548 const arch_register_t *in_false;
2550 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2552 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2553 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2555 /* should be same constraint fullfilled? */
2556 if (out == in_false) {
2557 /* yes -> nothing to do */
2558 } else if (out == in_true) {
2559 assert(get_ia32_op_type(node) == ia32_Normal);
2560 ins_permuted = !ins_permuted;
2564 bemit8(0x8B); // mov %in_false, %out
2565 bemit_modrr(in_false, out);
2569 cc = ia32_negate_condition_code(cc);
2571 if (cc & ia32_cc_float_parity_cases)
2572 panic("cmov can't handle parity float cases");
2575 bemit8(0x40 | pnc2cc(cc));
2576 if (get_ia32_op_type(node) == ia32_Normal) {
2577 bemit_modrr(in_true, out);
2579 bemit_mod_am(reg_gp_map[out->index], node);
2583 static void bemit_cmp(const ir_node *node)
2585 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2591 right = get_irn_n(node, n_ia32_binary_right);
2592 if (is_ia32_Immediate(right)) {
2593 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2594 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2595 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2598 if (attr->symconst != NULL) {
2601 /* check for sign extension */
2602 size = get_signed_imm_size(attr->offset);
2607 bemit8(0x81 | SIGNEXT_IMM);
2608 /* cmp has this special mode */
2609 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2610 bemit_mod_am(7, node);
2612 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2613 bemit_modru(reg, 7);
2615 bemit8((unsigned char)attr->offset);
2619 /* check for eax variant: this variant is shorter for 32bit immediates only */
2620 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2622 bemit_mod_am(7, node);
2624 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2625 if (reg->index == REG_GP_EAX) {
2629 bemit_modru(reg, 7);
2632 if (ls_size == 16) {
2633 bemit16(attr->offset);
2635 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2639 panic("invalid imm size?!?");
2641 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2643 if (get_ia32_op_type(node) == ia32_Normal) {
2644 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2645 bemit_modrr(op2, out);
2647 bemit_mod_am(reg_gp_map[out->index], node);
2652 static void bemit_cmp8bit(const ir_node *node)
2654 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2655 if (is_ia32_Immediate(right)) {
2656 if (get_ia32_op_type(node) == ia32_Normal) {
2657 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2658 if (out->index == REG_GP_EAX) {
2662 bemit_modru(out, 7);
2666 bemit_mod_am(7, node);
2668 bemit8(get_ia32_immediate_attr_const(right)->offset);
2670 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2672 if (get_ia32_op_type(node) == ia32_Normal) {
2673 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2674 bemit_modrr(out, in);
2676 bemit_mod_am(reg_gp_map[out->index], node);
2681 static void bemit_test8bit(const ir_node *node)
2683 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2684 if (is_ia32_Immediate(right)) {
2685 if (get_ia32_op_type(node) == ia32_Normal) {
2686 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2687 if (out->index == REG_GP_EAX) {
2691 bemit_modru(out, 0);
2695 bemit_mod_am(0, node);
2697 bemit8(get_ia32_immediate_attr_const(right)->offset);
2699 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2701 if (get_ia32_op_type(node) == ia32_Normal) {
2702 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2703 bemit_modrr(out, in);
2705 bemit_mod_am(reg_gp_map[out->index], node);
2710 static void bemit_imul(const ir_node *node)
2712 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2713 /* Do we need the immediate form? */
2714 if (is_ia32_Immediate(right)) {
2715 int imm = get_ia32_immediate_attr_const(right)->offset;
2716 if (get_signed_imm_size(imm) == 1) {
2717 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2720 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2724 bemit_0f_unop_reg(node, 0xAF, n_ia32_IMul_right);
2728 static void bemit_dec(const ir_node *node)
2730 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2731 bemit8(0x48 + reg_gp_map[out->index]);
2734 static void bemit_inc(const ir_node *node)
2736 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2737 bemit8(0x40 + reg_gp_map[out->index]);
2740 #define UNOPMEM(op, code, ext) \
2741 static void bemit_##op(const ir_node *node) \
2743 bemit_unop_mem(node, code, ext); \
2746 UNOPMEM(notmem, 0xF6, 2)
2747 UNOPMEM(negmem, 0xF6, 3)
2748 UNOPMEM(incmem, 0xFE, 0)
2749 UNOPMEM(decmem, 0xFE, 1)
2751 static void bemit_ldtls(const ir_node *node)
2753 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2755 bemit8(0x65); // gs:
2756 if (out->index == REG_GP_EAX) {
2757 bemit8(0xA1); // movl 0, %eax
2759 bemit8(0x8B); // movl 0, %reg
2760 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2768 static void bemit_lea(const ir_node *node)
2770 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2772 bemit_mod_am(reg_gp_map[out->index], node);
2775 /* helper function for bemit_minus64bit */
2776 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2778 bemit8(0x8B); // movl %src, %dst
2779 bemit_modrr(src, dst);
2782 /* helper function for bemit_minus64bit */
2783 static void bemit_helper_neg(const arch_register_t *reg)
2785 bemit8(0xF7); // negl %reg
2786 bemit_modru(reg, 3);
2789 /* helper function for bemit_minus64bit */
2790 static void bemit_helper_sbb0(const arch_register_t *reg)
2792 bemit8(0x83); // sbbl $0, %reg
2793 bemit_modru(reg, 3);
2797 /* helper function for bemit_minus64bit */
2798 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2800 bemit8(0x1B); // sbbl %src, %dst
2801 bemit_modrr(src, dst);
2804 /* helper function for bemit_minus64bit */
2805 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2807 if (src->index == REG_GP_EAX) {
2808 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2809 } else if (dst->index == REG_GP_EAX) {
2810 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2812 bemit8(0x87); // xchgl %src, %dst
2813 bemit_modrr(src, dst);
2817 /* helper function for bemit_minus64bit */
2818 static void bemit_helper_zero(const arch_register_t *reg)
2820 bemit8(0x33); // xorl %reg, %reg
2821 bemit_modrr(reg, reg);
2824 static void bemit_minus64bit(const ir_node *node)
2826 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2827 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2828 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2829 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2831 if (out_lo == in_lo) {
2832 if (out_hi != in_hi) {
2833 /* a -> a, b -> d */
2836 /* a -> a, b -> b */
2839 } else if (out_lo == in_hi) {
2840 if (out_hi == in_lo) {
2841 /* a -> b, b -> a */
2842 bemit_helper_xchg(in_lo, in_hi);
2845 /* a -> b, b -> d */
2846 bemit_helper_mov(in_hi, out_hi);
2847 bemit_helper_mov(in_lo, out_lo);
2851 if (out_hi == in_lo) {
2852 /* a -> c, b -> a */
2853 bemit_helper_mov(in_lo, out_lo);
2855 } else if (out_hi == in_hi) {
2856 /* a -> c, b -> b */
2857 bemit_helper_mov(in_lo, out_lo);
2860 /* a -> c, b -> d */
2861 bemit_helper_mov(in_lo, out_lo);
2867 bemit_helper_neg( out_hi);
2868 bemit_helper_neg( out_lo);
2869 bemit_helper_sbb0(out_hi);
2873 bemit_helper_zero(out_hi);
2874 bemit_helper_neg( out_lo);
2875 bemit_helper_sbb( in_hi, out_hi);
2879 * Emit a single opcode.
2881 #define EMIT_SINGLEOP(op, code) \
2882 static void bemit_ ## op(const ir_node *node) { \
2887 //EMIT_SINGLEOP(daa, 0x27)
2888 //EMIT_SINGLEOP(das, 0x2F)
2889 //EMIT_SINGLEOP(aaa, 0x37)
2890 //EMIT_SINGLEOP(aas, 0x3F)
2891 //EMIT_SINGLEOP(nop, 0x90)
2892 EMIT_SINGLEOP(cwtl, 0x98)
2893 EMIT_SINGLEOP(cltd, 0x99)
2894 //EMIT_SINGLEOP(fwait, 0x9B)
2895 EMIT_SINGLEOP(sahf, 0x9E)
2896 //EMIT_SINGLEOP(popf, 0x9D)
2897 EMIT_SINGLEOP(leave, 0xC9)
2898 EMIT_SINGLEOP(int3, 0xCC)
2899 //EMIT_SINGLEOP(iret, 0xCF)
2900 //EMIT_SINGLEOP(xlat, 0xD7)
2901 //EMIT_SINGLEOP(lock, 0xF0)
2902 EMIT_SINGLEOP(rep, 0xF3)
2903 //EMIT_SINGLEOP(halt, 0xF4)
2904 EMIT_SINGLEOP(cmc, 0xF5)
2905 EMIT_SINGLEOP(stc, 0xF9)
2906 //EMIT_SINGLEOP(cli, 0xFA)
2907 //EMIT_SINGLEOP(sti, 0xFB)
2908 //EMIT_SINGLEOP(std, 0xFD)
2911 * Emits a MOV out, [MEM].
2913 static void bemit_load(const ir_node *node)
2915 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2917 if (out->index == REG_GP_EAX) {
2918 ir_node *base = get_irn_n(node, n_ia32_base);
2919 int has_base = !is_ia32_NoReg_GP(base);
2920 ir_node *idx = get_irn_n(node, n_ia32_index);
2921 int has_index = !is_ia32_NoReg_GP(idx);
2922 if (!has_base && !has_index) {
2923 ir_entity *ent = get_ia32_am_sc(node);
2924 int offs = get_ia32_am_offs_int(node);
2925 /* load from constant address to EAX can be encoded
2928 bemit_entity(ent, 0, offs, false);
2933 bemit_mod_am(reg_gp_map[out->index], node);
2937 * Emits a MOV [mem], in.
2939 static void bemit_store(const ir_node *node)
2941 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
2942 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2944 if (is_ia32_Immediate(value)) {
2947 bemit_mod_am(0, node);
2948 bemit8(get_ia32_immediate_attr_const(value)->offset);
2949 } else if (size == 16) {
2952 bemit_mod_am(0, node);
2953 bemit16(get_ia32_immediate_attr_const(value)->offset);
2956 bemit_mod_am(0, node);
2957 bemit_immediate(value, false);
2960 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
2962 if (in->index == REG_GP_EAX) {
2963 ir_node *base = get_irn_n(node, n_ia32_base);
2964 int has_base = !is_ia32_NoReg_GP(base);
2965 ir_node *idx = get_irn_n(node, n_ia32_index);
2966 int has_index = !is_ia32_NoReg_GP(idx);
2967 if (!has_base && !has_index) {
2968 ir_entity *ent = get_ia32_am_sc(node);
2969 int offs = get_ia32_am_offs_int(node);
2970 /* store to constant address from EAX can be encoded as
2971 * 0xA2/0xA3 [offset]*/
2979 bemit_entity(ent, 0, offs, false);
2991 bemit_mod_am(reg_gp_map[in->index], node);
2995 static void bemit_conv_i2i(const ir_node *node)
3000 ir_mode *const smaller_mode = get_ia32_ls_mode(node);
3001 unsigned opcode = 0xB6;
3002 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3003 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3004 bemit_0f_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3007 static void bemit_popcnt(ir_node const *const node)
3010 bemit_0f_unop_reg(node, 0xB8, n_ia32_Popcnt_operand);
3016 static void bemit_push(const ir_node *node)
3018 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3020 if (is_ia32_Immediate(value)) {
3021 const ia32_immediate_attr_t *attr
3022 = get_ia32_immediate_attr_const(value);
3023 unsigned size = get_signed_imm_size(attr->offset);
3029 bemit8((unsigned char)attr->offset);
3034 bemit_immediate(value, false);
3037 } else if (is_ia32_NoReg_GP(value)) {
3039 bemit_mod_am(6, node);
3041 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3042 bemit8(0x50 + reg_gp_map[reg->index]);
3049 static void bemit_pop(const ir_node *node)
3051 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3052 bemit8(0x58 + reg_gp_map[reg->index]);
3055 static void bemit_popmem(const ir_node *node)
3058 bemit_mod_am(0, node);
3061 static void bemit_call(const ir_node *node)
3063 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3065 if (is_ia32_Immediate(proc)) {
3067 bemit_immediate(proc, true);
3069 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3073 static void bemit_jmp(const ir_node *dest_block)
3076 bemit_jmp_destination(dest_block);
3079 static void bemit_jump(const ir_node *node)
3081 if (can_be_fallthrough(node))
3084 bemit_jmp(get_cfop_target_block(node));
3087 static void bemit_jcc(ia32_condition_code_t pnc, const ir_node *dest_block)
3089 unsigned char cc = pnc2cc(pnc);
3092 bemit_jmp_destination(dest_block);
3095 static void bemit_jp(bool odd, const ir_node *dest_block)
3099 bemit_jmp_destination(dest_block);
3102 static void bemit_ia32_jcc(const ir_node *node)
3104 ia32_condition_code_t cc = get_ia32_condcode(node);
3105 const ir_node *proj_true;
3106 const ir_node *proj_false;
3107 const ir_node *dest_true;
3108 const ir_node *dest_false;
3110 cc = determine_final_cc(node, 0, cc);
3112 /* get both Projs */
3113 proj_true = get_proj(node, pn_ia32_Jcc_true);
3114 assert(proj_true && "Jcc without true Proj");
3116 proj_false = get_proj(node, pn_ia32_Jcc_false);
3117 assert(proj_false && "Jcc without false Proj");
3119 if (can_be_fallthrough(proj_true)) {
3120 /* exchange both proj's so the second one can be omitted */
3121 const ir_node *t = proj_true;
3123 proj_true = proj_false;
3125 cc = ia32_negate_condition_code(cc);
3128 dest_true = get_cfop_target_block(proj_true);
3129 dest_false = get_cfop_target_block(proj_false);
3131 if (cc & ia32_cc_float_parity_cases) {
3132 /* Some floating point comparisons require a test of the parity flag,
3133 * which indicates that the result is unordered */
3134 if (cc & ia32_cc_negated) {
3135 bemit_jp(false, dest_true);
3137 /* we need a local label if the false proj is a fallthrough
3138 * as the falseblock might have no label emitted then */
3139 if (can_be_fallthrough(proj_false)) {
3141 bemit8(0x06); // jp + 6
3143 bemit_jp(false, dest_false);
3147 bemit_jcc(cc, dest_true);
3149 /* the second Proj might be a fallthrough */
3150 if (can_be_fallthrough(proj_false)) {
3151 /* it's a fallthrough */
3153 bemit_jmp(dest_false);
3157 static void bemit_switchjmp(const ir_node *node)
3159 ir_entity *jump_table = get_ia32_am_sc(node);
3160 const ir_switch_table *table = get_ia32_switch_table(node);
3162 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3163 bemit_mod_am(0x05, node);
3165 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3171 static void bemit_return(const ir_node *node)
3173 unsigned pop = be_Return_get_pop(node);
3174 if (pop > 0 || be_Return_get_emit_pop(node)) {
3176 assert(pop <= 0xffff);
3183 static void bemit_subsp(const ir_node *node)
3185 const arch_register_t *out;
3188 /* mov %esp, %out */
3190 out = arch_get_irn_register_out(node, 1);
3191 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3194 static void bemit_incsp(const ir_node *node)
3197 const arch_register_t *reg;
3201 offs = be_get_IncSP_offset(node);
3212 size = get_signed_imm_size(offs);
3213 bemit8(size == 1 ? 0x83 : 0x81);
3215 reg = arch_get_irn_register_out(node, 0);
3216 bemit_modru(reg, ext);
3225 static void bemit_copybi(const ir_node *node)
3227 unsigned size = get_ia32_copyb_size(node);
3229 bemit8(0xA4); // movsb
3232 bemit8(0xA5); // movsw
3236 bemit8(0xA5); // movsl
3240 static void bemit_fbinop(ir_node const *const node, unsigned const op_fwd, unsigned const op_rev)
3242 ia32_x87_attr_t const *const attr = get_ia32_x87_attr_const(node);
3243 unsigned const op = attr->attr.data.ins_permuted ? op_rev : op_fwd;
3244 if (get_ia32_op_type(node) == ia32_Normal) {
3245 assert(!attr->pop || attr->res_in_reg);
3247 unsigned char op0 = 0xD8;
3248 if (attr->res_in_reg) op0 |= 0x04;
3249 if (attr->pop) op0 |= 0x02;
3252 bemit8(MOD_REG | ENC_REG(op) | ENC_RM(attr->reg->index));
3257 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3258 bemit8(size == 32 ? 0xD8 : 0xDC);
3259 bemit_mod_am(op, node);
3263 static void bemit_fop_reg(ir_node const *const node, unsigned char const op0, unsigned char const op1)
3266 bemit8(op1 + get_ia32_x87_attr_const(node)->reg->index);
3269 static void bemit_fabs(const ir_node *node)
3277 static void bemit_fadd(const ir_node *node)
3279 bemit_fbinop(node, 0, 0);
3282 static void bemit_fchs(const ir_node *node)
3290 static void bemit_fdiv(const ir_node *node)
3292 bemit_fbinop(node, 6, 7);
3295 static void bemit_ffreep(ir_node const *const node)
3297 bemit_fop_reg(node, 0xDF, 0xC0);
3300 static void bemit_fild(const ir_node *node)
3302 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3304 bemit8(0xDF); // filds
3305 bemit_mod_am(0, node);
3309 bemit8(0xDB); // fildl
3310 bemit_mod_am(0, node);
3314 bemit8(0xDF); // fildll
3315 bemit_mod_am(5, node);
3319 panic("invalid mode size");
3323 static void bemit_fist(const ir_node *node)
3326 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3328 case 16: bemit8(0xDF); op = 2; break; // fist[p]s
3329 case 32: bemit8(0xDB); op = 2; break; // fist[p]l
3330 case 64: bemit8(0xDF); op = 6; break; // fistpll
3331 default: panic("invalid mode size");
3333 if (get_ia32_x87_attr_const(node)->pop)
3335 // There is only a pop variant for 64 bit integer store.
3336 assert(size < 64 || get_ia32_x87_attr_const(node)->pop);
3337 bemit_mod_am(op, node);
3340 static void bemit_fisttp(ir_node const *const node)
3342 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3343 case 16: bemit8(0xDF); break; // fisttps
3344 case 32: bemit8(0xDB); break; // fisttpl
3345 case 64: bemit8(0xDD); break; // fisttpll
3346 default: panic("Invalid mode size");
3348 bemit_mod_am(1, node);
3351 static void bemit_fld(const ir_node *node)
3353 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3355 bemit8(0xD9); // flds
3356 bemit_mod_am(0, node);
3360 bemit8(0xDD); // fldl
3361 bemit_mod_am(0, node);
3366 bemit8(0xDB); // fldt
3367 bemit_mod_am(5, node);
3371 panic("invalid mode size");
3375 static void bemit_fld1(const ir_node *node)
3379 bemit8(0xE8); // fld1
3382 static void bemit_fldcw(const ir_node *node)
3384 bemit8(0xD9); // fldcw
3385 bemit_mod_am(5, node);
3388 static void bemit_fldz(const ir_node *node)
3392 bemit8(0xEE); // fldz
3395 static void bemit_fmul(const ir_node *node)
3397 bemit_fbinop(node, 1, 1);
3400 static void bemit_fpop(const ir_node *node)
3402 bemit_fop_reg(node, 0xDD, 0xD8);
3405 static void bemit_fpush(const ir_node *node)
3407 bemit_fop_reg(node, 0xD9, 0xC0);
3410 static void bemit_fpushcopy(const ir_node *node)
3412 bemit_fop_reg(node, 0xD9, 0xC0);
3415 static void bemit_fst(const ir_node *node)
3418 unsigned const size = get_mode_size_bits(get_ia32_ls_mode(node));
3420 case 32: bemit8(0xD9); op = 2; break; // fst[p]s
3421 case 64: bemit8(0xDD); op = 2; break; // fst[p]l
3423 case 96: bemit8(0xDB); op = 6; break; // fstpt
3424 default: panic("invalid mode size");
3426 if (get_ia32_x87_attr_const(node)->pop)
3428 // There is only a pop variant for long double store.
3429 assert(size < 80 || get_ia32_x87_attr_const(node)->pop);
3430 bemit_mod_am(op, node);
3433 static void bemit_fsub(const ir_node *node)
3435 bemit_fbinop(node, 4, 5);
3438 static void bemit_fnstcw(const ir_node *node)
3440 bemit8(0xD9); // fnstcw
3441 bemit_mod_am(7, node);
3444 static void bemit_fnstsw(void)
3446 bemit8(0xDF); // fnstsw %ax
3450 static void bemit_ftstfnstsw(const ir_node *node)
3454 bemit8(0xD9); // ftst
3459 static void bemit_fucomi(const ir_node *node)
3461 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3462 bemit8(attr->pop ? 0xDF : 0xDB); // fucom[p]i
3463 bemit8(0xE8 + attr->reg->index);
3466 static void bemit_fucomfnstsw(const ir_node *node)
3468 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3469 bemit8(0xDD); // fucom[p]
3470 bemit8((attr->pop ? 0xE8 : 0xE0) + attr->reg->index);
3474 static void bemit_fucomppfnstsw(const ir_node *node)
3478 bemit8(0xDA); // fucompp
3483 static void bemit_fxch(const ir_node *node)
3485 bemit_fop_reg(node, 0xD9, 0xC8);
3489 * The type of a emitter function.
3491 typedef void (*emit_func) (const ir_node *);
3494 * Set a node emitter. Make it a bit more type safe.
3496 static void register_emitter(ir_op *op, emit_func func)
3498 op->ops.generic = (op_func) func;
3501 static void ia32_register_binary_emitters(void)
3503 /* first clear the generic function pointer for all ops */
3504 ir_clear_opcodes_generic_func();
3506 /* benode emitter */
3507 register_emitter(op_be_Copy, bemit_copy);
3508 register_emitter(op_be_CopyKeep, bemit_copy);
3509 register_emitter(op_be_IncSP, bemit_incsp);
3510 register_emitter(op_be_Perm, bemit_perm);
3511 register_emitter(op_be_Return, bemit_return);
3512 register_emitter(op_ia32_Adc, bemit_adc);
3513 register_emitter(op_ia32_Add, bemit_add);
3514 register_emitter(op_ia32_AddMem, bemit_addmem);
3515 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3516 register_emitter(op_ia32_And, bemit_and);
3517 register_emitter(op_ia32_AndMem, bemit_andmem);
3518 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3519 register_emitter(op_ia32_Asm, emit_ia32_Asm); // TODO implement binary emitter
3520 register_emitter(op_ia32_Breakpoint, bemit_int3);
3521 register_emitter(op_ia32_Bsf, bemit_bsf);
3522 register_emitter(op_ia32_Bsr, bemit_bsr);
3523 register_emitter(op_ia32_Bswap, bemit_bswap);
3524 register_emitter(op_ia32_Bt, bemit_bt);
3525 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3526 register_emitter(op_ia32_Call, bemit_call);
3527 register_emitter(op_ia32_Cltd, bemit_cltd);
3528 register_emitter(op_ia32_Cmc, bemit_cmc);
3529 register_emitter(op_ia32_Cmp, bemit_cmp);
3530 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3531 register_emitter(op_ia32_Const, bemit_mov_const);
3532 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3533 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3534 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3535 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3536 register_emitter(op_ia32_Dec, bemit_dec);
3537 register_emitter(op_ia32_DecMem, bemit_decmem);
3538 register_emitter(op_ia32_Div, bemit_div);
3539 register_emitter(op_ia32_FldCW, bemit_fldcw);
3540 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3541 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3542 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3543 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3544 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3545 register_emitter(op_ia32_IDiv, bemit_idiv);
3546 register_emitter(op_ia32_IJmp, bemit_ijmp);
3547 register_emitter(op_ia32_IMul, bemit_imul);
3548 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3549 register_emitter(op_ia32_Inc, bemit_inc);
3550 register_emitter(op_ia32_IncMem, bemit_incmem);
3551 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3552 register_emitter(op_ia32_Jmp, bemit_jump);
3553 register_emitter(op_ia32_LdTls, bemit_ldtls);
3554 register_emitter(op_ia32_Lea, bemit_lea);
3555 register_emitter(op_ia32_Leave, bemit_leave);
3556 register_emitter(op_ia32_Load, bemit_load);
3557 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3558 register_emitter(op_ia32_Mul, bemit_mul);
3559 register_emitter(op_ia32_Neg, bemit_neg);
3560 register_emitter(op_ia32_NegMem, bemit_negmem);
3561 register_emitter(op_ia32_Not, bemit_not);
3562 register_emitter(op_ia32_NotMem, bemit_notmem);
3563 register_emitter(op_ia32_Or, bemit_or);
3564 register_emitter(op_ia32_OrMem, bemit_ormem);
3565 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3566 register_emitter(op_ia32_Pop, bemit_pop);
3567 register_emitter(op_ia32_PopEbp, bemit_pop);
3568 register_emitter(op_ia32_PopMem, bemit_popmem);
3569 register_emitter(op_ia32_Popcnt, bemit_popcnt);
3570 register_emitter(op_ia32_Push, bemit_push);
3571 register_emitter(op_ia32_RepPrefix, bemit_rep);
3572 register_emitter(op_ia32_Rol, bemit_rol);
3573 register_emitter(op_ia32_RolMem, bemit_rolmem);
3574 register_emitter(op_ia32_Ror, bemit_ror);
3575 register_emitter(op_ia32_RorMem, bemit_rormem);
3576 register_emitter(op_ia32_Sahf, bemit_sahf);
3577 register_emitter(op_ia32_Sar, bemit_sar);
3578 register_emitter(op_ia32_SarMem, bemit_sarmem);
3579 register_emitter(op_ia32_Sbb, bemit_sbb);
3580 register_emitter(op_ia32_Sbb0, bemit_sbb0);
3581 register_emitter(op_ia32_Setcc, bemit_setcc);
3582 register_emitter(op_ia32_Shl, bemit_shl);
3583 register_emitter(op_ia32_ShlD, bemit_shld);
3584 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3585 register_emitter(op_ia32_Shr, bemit_shr);
3586 register_emitter(op_ia32_ShrD, bemit_shrd);
3587 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3588 register_emitter(op_ia32_Stc, bemit_stc);
3589 register_emitter(op_ia32_Store, bemit_store);
3590 register_emitter(op_ia32_Store8Bit, bemit_store);
3591 register_emitter(op_ia32_Sub, bemit_sub);
3592 register_emitter(op_ia32_SubMem, bemit_submem);
3593 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3594 register_emitter(op_ia32_SubSP, bemit_subsp);
3595 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3596 register_emitter(op_ia32_Test, bemit_test);
3597 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3598 register_emitter(op_ia32_Xor, bemit_xor);
3599 register_emitter(op_ia32_Xor0, bemit_xor0);
3600 register_emitter(op_ia32_XorMem, bemit_xormem);
3601 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3602 register_emitter(op_ia32_fabs, bemit_fabs);
3603 register_emitter(op_ia32_fadd, bemit_fadd);
3604 register_emitter(op_ia32_fchs, bemit_fchs);
3605 register_emitter(op_ia32_fdiv, bemit_fdiv);
3606 register_emitter(op_ia32_ffreep, bemit_ffreep);
3607 register_emitter(op_ia32_fild, bemit_fild);
3608 register_emitter(op_ia32_fist, bemit_fist);
3609 register_emitter(op_ia32_fisttp, bemit_fisttp);
3610 register_emitter(op_ia32_fld, bemit_fld);
3611 register_emitter(op_ia32_fld1, bemit_fld1);
3612 register_emitter(op_ia32_fldz, bemit_fldz);
3613 register_emitter(op_ia32_fmul, bemit_fmul);
3614 register_emitter(op_ia32_fpop, bemit_fpop);
3615 register_emitter(op_ia32_fpush, bemit_fpush);
3616 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3617 register_emitter(op_ia32_fst, bemit_fst);
3618 register_emitter(op_ia32_fsub, bemit_fsub);
3619 register_emitter(op_ia32_fxch, bemit_fxch);
3621 /* ignore the following nodes */
3622 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3623 register_emitter(op_ia32_Unknown, emit_Nothing);
3624 register_emitter(op_be_Keep, emit_Nothing);
3625 register_emitter(op_be_Start, emit_Nothing);
3626 register_emitter(op_Phi, emit_Nothing);
3627 register_emitter(op_Start, emit_Nothing);
3630 static void gen_binary_block(ir_node *block)
3632 ia32_emit_block_header(block);
3634 /* emit the contents of the block */
3635 sched_foreach(block, node) {
3636 ia32_emit_node(node);
3640 void ia32_gen_binary_routine(ir_graph *irg)
3642 ir_entity *entity = get_irg_entity(irg);
3643 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3644 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3645 ir_node **blk_sched = irg_data->blk_sched;
3647 parameter_dbg_info_t *infos;
3649 isa = (ia32_isa_t*) arch_env;
3651 ia32_register_binary_emitters();
3653 infos = construct_parameter_infos(irg);
3654 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3658 /* we use links to point to target blocks */
3659 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3660 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3662 /* initialize next block links */
3663 n = ARR_LEN(blk_sched);
3664 for (i = 0; i < n; ++i) {
3665 ir_node *block = blk_sched[i];
3666 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3668 set_irn_link(block, prev);
3671 for (i = 0; i < n; ++i) {
3672 ir_node *block = blk_sched[i];
3673 gen_binary_block(block);
3676 be_gas_emit_function_epilog(entity);
3678 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3682 void ia32_init_emitter(void)
3684 lc_opt_entry_t *be_grp;
3685 lc_opt_entry_t *ia32_grp;
3687 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3688 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3690 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3694 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");