2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
68 static const arch_env_t *arch_env;
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
73 * Returns the register at in position pos.
75 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
78 const arch_register_t *reg = NULL;
80 assert(get_irn_arity(irn) > pos && "Invalid IN position");
82 /* The out register of the operator at position pos is the
83 in register we need. */
84 op = get_irn_n(irn, pos);
86 reg = arch_get_irn_register(arch_env, op);
88 assert(reg && "no in register found");
90 if(reg == &ia32_gp_regs[REG_GP_NOREG])
91 panic("trying to emit noreg for %+F input %d", irn, pos);
93 /* in case of unknown register: just return a valid register */
94 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
95 const arch_register_req_t *req;
97 /* ask for the requirements */
98 req = arch_get_register_req(arch_env, irn, pos);
100 if (arch_register_req_is(req, limited)) {
101 /* in case of limited requirements: get the first allowed register */
102 unsigned idx = rbitset_next(req->limited, 0, 1);
103 reg = arch_register_for_index(req->cls, idx);
105 /* otherwise get first register in class */
106 reg = arch_register_for_index(req->cls, 0);
114 * Returns the register at out position pos.
116 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
119 const arch_register_t *reg = NULL;
121 /* 1st case: irn is not of mode_T, so it has only */
122 /* one OUT register -> good */
123 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
124 /* Proj with the corresponding projnum for the register */
126 if (get_irn_mode(irn) != mode_T) {
128 reg = arch_get_irn_register(arch_env, irn);
129 } else if (is_ia32_irn(irn)) {
130 reg = get_ia32_out_reg(irn, pos);
132 const ir_edge_t *edge;
134 foreach_out_edge(irn, edge) {
135 proj = get_edge_src_irn(edge);
136 assert(is_Proj(proj) && "non-Proj from mode_T node");
137 if (get_Proj_proj(proj) == pos) {
138 reg = arch_get_irn_register(arch_env, proj);
144 assert(reg && "no out register found");
149 * Add a number to a prefix. This number will not be used a second time.
151 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
153 static unsigned long id = 0;
154 snprintf(buf, buflen, "%s%lu", prefix, ++id);
158 /*************************************************************
160 * (_) | | / _| | | | |
161 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
162 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
163 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
164 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
167 *************************************************************/
169 static void emit_8bit_register(const arch_register_t *reg)
171 const char *reg_name = arch_register_get_name(reg);
174 be_emit_char(reg_name[1]);
178 static void emit_16bit_register(const arch_register_t *reg)
180 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
183 be_emit_string(reg_name);
186 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
188 const char *reg_name;
191 int size = get_mode_size_bits(mode);
193 emit_8bit_register(reg);
195 } else if(size == 16) {
196 emit_16bit_register(reg);
199 assert(mode_is_float(mode) || size == 32);
203 reg_name = arch_register_get_name(reg);
206 be_emit_string(reg_name);
209 void ia32_emit_source_register(const ir_node *node, int pos)
211 const arch_register_t *reg = get_in_reg(node, pos);
213 emit_register(reg, NULL);
216 static void emit_ia32_Immediate(const ir_node *node);
218 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
220 const arch_register_t *reg;
221 ir_node *in = get_irn_n(node, pos);
222 if(is_ia32_Immediate(in)) {
223 emit_ia32_Immediate(in);
227 reg = get_in_reg(node, pos);
228 emit_8bit_register(reg);
231 void ia32_emit_dest_register(const ir_node *node, int pos)
233 const arch_register_t *reg = get_out_reg(node, pos);
235 emit_register(reg, NULL);
238 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
240 const arch_register_t *reg = get_out_reg(node, pos);
242 emit_register(reg, mode_Bu);
245 void ia32_emit_x87_register(const ir_node *node, int pos)
247 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
251 be_emit_string(attr->x87[pos]->name);
254 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
256 if(mode_is_float(mode)) {
257 switch(get_mode_size_bits(mode)) {
258 case 32: be_emit_char('s'); return;
259 case 64: be_emit_char('l'); return;
261 case 96: be_emit_char('t'); return;
264 assert(mode_is_int(mode) || mode_is_reference(mode));
265 switch(get_mode_size_bits(mode)) {
266 case 64: be_emit_cstring("ll"); return;
267 /* gas docu says q is the suffix but gcc, objdump and icc use
269 case 32: be_emit_char('l'); return;
270 case 16: be_emit_char('w'); return;
271 case 8: be_emit_char('b'); return;
274 panic("Can't output mode_suffix for %+F\n", mode);
277 void ia32_emit_mode_suffix(const ir_node *node)
279 ir_mode *mode = get_ia32_ls_mode(node);
283 ia32_emit_mode_suffix_mode(mode);
286 void ia32_emit_x87_mode_suffix(const ir_node *node)
288 ir_mode *mode = get_ia32_ls_mode(node);
289 assert(mode != NULL);
290 /* we only need to emit the mode on address mode */
291 if(get_ia32_op_type(node) != ia32_Normal)
292 ia32_emit_mode_suffix_mode(mode);
296 char get_xmm_mode_suffix(ir_mode *mode)
298 assert(mode_is_float(mode));
299 switch(get_mode_size_bits(mode)) {
310 void ia32_emit_xmm_mode_suffix(const ir_node *node)
312 ir_mode *mode = get_ia32_ls_mode(node);
313 assert(mode != NULL);
315 be_emit_char(get_xmm_mode_suffix(mode));
318 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
320 ir_mode *mode = get_ia32_ls_mode(node);
321 assert(mode != NULL);
322 be_emit_char(get_xmm_mode_suffix(mode));
325 void ia32_emit_extend_suffix(const ir_mode *mode)
327 if(get_mode_size_bits(mode) == 32)
329 if(mode_is_signed(mode)) {
337 void ia32_emit_function_object(const char *name)
339 switch (be_gas_flavour) {
340 case GAS_FLAVOUR_NORMAL:
341 be_emit_cstring("\t.type\t");
342 be_emit_string(name);
343 be_emit_cstring(", @function\n");
344 be_emit_write_line();
346 case GAS_FLAVOUR_MINGW:
347 be_emit_cstring("\t.def\t");
348 be_emit_string(name);
349 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
350 be_emit_write_line();
358 void ia32_emit_function_size(const char *name)
360 switch (be_gas_flavour) {
361 case GAS_FLAVOUR_NORMAL:
362 be_emit_cstring("\t.size\t");
363 be_emit_string(name);
364 be_emit_cstring(", .-");
365 be_emit_string(name);
367 be_emit_write_line();
375 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
377 ir_node *in = get_irn_n(node, pos);
378 if(is_ia32_Immediate(in)) {
379 emit_ia32_Immediate(in);
381 const ir_mode *mode = get_ia32_ls_mode(node);
382 const arch_register_t *reg = get_in_reg(node, pos);
383 emit_register(reg, mode);
388 * Emits registers and/or address mode of a binary operation.
390 void ia32_emit_binop(const ir_node *node) {
391 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
392 const ir_mode *mode = get_ia32_ls_mode(node);
393 const arch_register_t *reg_left;
395 switch(get_ia32_op_type(node)) {
397 reg_left = get_in_reg(node, n_ia32_binary_left);
398 if(is_ia32_Immediate(right_op)) {
399 emit_ia32_Immediate(right_op);
400 be_emit_cstring(", ");
401 emit_register(reg_left, mode);
404 const arch_register_t *reg_right
405 = get_in_reg(node, n_ia32_binary_right);
406 emit_register(reg_right, mode);
407 be_emit_cstring(", ");
408 emit_register(reg_left, mode);
412 if(is_ia32_Immediate(right_op)) {
413 emit_ia32_Immediate(right_op);
414 be_emit_cstring(", ");
417 reg_left = get_in_reg(node, n_ia32_binary_left);
419 be_emit_cstring(", ");
420 emit_register(reg_left, mode);
424 panic("DestMode can't be output by %%binop anymore");
427 assert(0 && "unsupported op type");
432 * Emits registers and/or address mode of a binary operation.
434 void ia32_emit_x87_binop(const ir_node *node) {
435 switch(get_ia32_op_type(node)) {
438 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
439 const arch_register_t *in1 = x87_attr->x87[0];
440 const arch_register_t *in2 = x87_attr->x87[1];
441 const arch_register_t *out = x87_attr->x87[2];
442 const arch_register_t *in;
444 in = out ? ((out == in2) ? in1 : in2) : in2;
445 out = out ? out : in1;
448 be_emit_string(arch_register_get_name(in));
449 be_emit_cstring(", %");
450 be_emit_string(arch_register_get_name(out));
458 assert(0 && "unsupported op type");
462 void ia32_emit_am_or_dest_register(const ir_node *node,
464 if(get_ia32_op_type(node) == ia32_Normal) {
465 ia32_emit_dest_register(node, pos);
467 assert(get_ia32_op_type(node) == ia32_AddrModeD);
473 * Emits registers and/or address mode of a unary operation.
475 void ia32_emit_unop(const ir_node *node, int pos) {
478 switch(get_ia32_op_type(node)) {
480 op = get_irn_n(node, pos);
481 if (is_ia32_Immediate(op)) {
482 emit_ia32_Immediate(op);
484 ia32_emit_source_register(node, pos);
492 assert(0 && "unsupported op type");
497 * Emits address mode.
499 void ia32_emit_am(const ir_node *node) {
500 ir_entity *ent = get_ia32_am_sc(node);
501 int offs = get_ia32_am_offs_int(node);
502 ir_node *base = get_irn_n(node, 0);
503 int has_base = !is_ia32_NoReg_GP(base);
504 ir_node *index = get_irn_n(node, 1);
505 int has_index = !is_ia32_NoReg_GP(index);
507 /* just to be sure... */
508 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
514 set_entity_backend_marked(ent, 1);
515 id = get_entity_ld_ident(ent);
516 if (is_ia32_am_sc_sign(node))
520 if(get_entity_owner(ent) == get_tls_type()) {
521 if (get_entity_visibility(ent) == visibility_external_allocated) {
522 be_emit_cstring("@INDNTPOFF");
524 be_emit_cstring("@NTPOFF");
531 be_emit_irprintf("%+d", offs);
533 be_emit_irprintf("%d", offs);
537 if (has_base || has_index) {
542 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
543 emit_register(reg, NULL);
546 /* emit index + scale */
548 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
551 emit_register(reg, NULL);
553 scale = get_ia32_am_scale(node);
555 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
561 /* special case if nothing is set */
562 if(ent == NULL && offs == 0 && !has_base && !has_index) {
567 static void emit_ia32_IMul(const ir_node *node)
569 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
570 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
572 be_emit_cstring("\timul");
573 ia32_emit_mode_suffix(node);
576 ia32_emit_binop(node);
578 /* do we need the 3-address form? */
579 if(is_ia32_NoReg_GP(left) ||
580 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
581 be_emit_cstring(", ");
582 emit_register(out_reg, get_ia32_ls_mode(node));
584 be_emit_finish_line_gas(node);
587 /*************************************************
590 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
591 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
592 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
593 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
595 *************************************************/
598 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
601 * coding of conditions
603 struct cmp2conditon_t {
609 * positive conditions for signed compares
611 static const struct cmp2conditon_t cmp2condition_s[] = {
612 { NULL, pn_Cmp_False }, /* always false */
613 { "e", pn_Cmp_Eq }, /* == */
614 { "l", pn_Cmp_Lt }, /* < */
615 { "le", pn_Cmp_Le }, /* <= */
616 { "g", pn_Cmp_Gt }, /* > */
617 { "ge", pn_Cmp_Ge }, /* >= */
618 { "ne", pn_Cmp_Lg }, /* != */
619 { NULL, pn_Cmp_Leg}, /* always true */
623 * positive conditions for unsigned compares
625 static const struct cmp2conditon_t cmp2condition_u[] = {
626 { NULL, pn_Cmp_False }, /* always false */
627 { "e", pn_Cmp_Eq }, /* == */
628 { "b", pn_Cmp_Lt }, /* < */
629 { "be", pn_Cmp_Le }, /* <= */
630 { "a", pn_Cmp_Gt }, /* > */
631 { "ae", pn_Cmp_Ge }, /* >= */
632 { "ne", pn_Cmp_Lg }, /* != */
633 { NULL, pn_Cmp_Leg }, /* always true */
637 ia32_pn_Cmp_unsigned = 0x1000,
638 ia32_pn_Cmp_float = 0x2000,
642 * walks up a tree of copies/perms/spills/reloads to find the original value
643 * that is moved around
645 static ir_node *find_original_value(ir_node *node)
647 inc_irg_visited(current_ir_graph);
649 mark_irn_visited(node);
650 if(be_is_Copy(node)) {
651 node = be_get_Copy_op(node);
652 } else if(be_is_CopyKeep(node)) {
653 node = be_get_CopyKeep_op(node);
654 } else if(is_Proj(node)) {
655 ir_node *pred = get_Proj_pred(node);
656 if(be_is_Perm(pred)) {
657 node = get_irn_n(pred, get_Proj_proj(node));
658 } else if(be_is_MemPerm(pred)) {
659 node = get_irn_n(pred, get_Proj_proj(node) + 1);
660 } else if(is_ia32_Load(pred)) {
661 node = get_irn_n(pred, n_ia32_Load_mem);
665 } else if(is_ia32_Store(node)) {
666 node = get_irn_n(node, n_ia32_Store_val);
667 } else if(is_Phi(node)) {
669 arity = get_irn_arity(node);
670 for(i = 0; i < arity; ++i) {
671 ir_node *in = get_irn_n(node, i);
684 static int determine_final_pnc(const ir_node *node, int flags_pos,
687 ir_node *flags = get_irn_n(node, flags_pos);
688 const ia32_attr_t *flags_attr;
689 flags = skip_Proj(flags);
691 if(is_ia32_Sahf(flags)) {
692 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
693 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
694 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
695 cmp = find_original_value(cmp);
696 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
697 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
700 flags_attr = get_ia32_attr_const(cmp);
701 if(flags_attr->data.ins_permuted)
702 pnc = get_mirrored_pnc(pnc);
703 pnc |= ia32_pn_Cmp_float;
704 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
705 || is_ia32_Fucompi(flags)) {
706 flags_attr = get_ia32_attr_const(flags);
708 if(flags_attr->data.ins_permuted)
709 pnc = get_mirrored_pnc(pnc);
710 pnc |= ia32_pn_Cmp_float;
712 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
713 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
714 flags_attr = get_ia32_attr_const(flags);
716 if(flags_attr->data.ins_permuted)
717 pnc = get_mirrored_pnc(pnc);
718 if(flags_attr->data.cmp_unsigned)
719 pnc |= ia32_pn_Cmp_unsigned;
725 static void ia32_emit_cmp_suffix(int pnc)
729 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
731 assert(cmp2condition_u[pnc].num == pnc);
732 str = cmp2condition_u[pnc].name;
735 assert(cmp2condition_s[pnc].num == pnc);
736 str = cmp2condition_s[pnc].name;
742 void ia32_emit_cmp_suffix_node(const ir_node *node,
745 const ia32_attr_t *attr = get_ia32_attr_const(node);
747 pn_Cmp pnc = get_ia32_condcode(node);
749 pnc = determine_final_pnc(node, flags_pos, pnc);
750 if(attr->data.ins_permuted) {
751 if(pnc & ia32_pn_Cmp_float) {
752 pnc = get_negated_pnc(pnc, mode_F);
754 pnc = get_negated_pnc(pnc, mode_Iu);
758 ia32_emit_cmp_suffix(pnc);
762 * Returns the target block for a control flow node.
765 ir_node *get_cfop_target_block(const ir_node *irn) {
766 return get_irn_link(irn);
770 * Emits a block label for the given block.
773 void ia32_emit_block_name(const ir_node *block)
775 if (has_Block_label(block)) {
776 be_emit_string(be_gas_label_prefix());
777 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
779 be_emit_cstring(BLOCK_PREFIX);
780 be_emit_irprintf("%d", get_irn_node_nr(block));
785 * Emits the target label for a control flow node.
787 static void ia32_emit_cfop_target(const ir_node *node)
789 ir_node *block = get_cfop_target_block(node);
791 ia32_emit_block_name(block);
794 /** Return the next block in Block schedule */
795 static ir_node *next_blk_sched(const ir_node *block)
797 return get_irn_link(block);
801 * Returns the Proj with projection number proj and NOT mode_M
803 static ir_node *get_proj(const ir_node *node, long proj) {
804 const ir_edge_t *edge;
807 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
809 foreach_out_edge(node, edge) {
810 src = get_edge_src_irn(edge);
812 assert(is_Proj(src) && "Proj expected");
813 if (get_irn_mode(src) == mode_M)
816 if (get_Proj_proj(src) == proj)
823 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
825 static void emit_ia32_Jcc(const ir_node *node)
827 const ir_node *proj_true;
828 const ir_node *proj_false;
829 const ir_node *block;
830 const ir_node *next_block;
831 pn_Cmp pnc = get_ia32_condcode(node);
833 pnc = determine_final_pnc(node, 0, pnc);
836 proj_true = get_proj(node, pn_ia32_Jcc_true);
837 assert(proj_true && "Jcc without true Proj");
839 proj_false = get_proj(node, pn_ia32_Jcc_false);
840 assert(proj_false && "Jcc without false Proj");
842 block = get_nodes_block(node);
843 next_block = next_blk_sched(block);
845 if (get_cfop_target_block(proj_true) == next_block) {
846 /* exchange both proj's so the second one can be omitted */
847 const ir_node *t = proj_true;
849 proj_true = proj_false;
851 if(pnc & ia32_pn_Cmp_float) {
852 pnc = get_negated_pnc(pnc, mode_F);
854 pnc = get_negated_pnc(pnc, mode_Iu);
858 if (pnc & ia32_pn_Cmp_float) {
859 /* Some floating point comparisons require a test of the parity flag,
860 * which indicates that the result is unordered */
863 be_emit_cstring("\tjp ");
864 ia32_emit_cfop_target(proj_true);
865 be_emit_finish_line_gas(proj_true);
869 be_emit_cstring("\tjnp ");
870 ia32_emit_cfop_target(proj_true);
871 be_emit_finish_line_gas(proj_true);
877 be_emit_cstring("\tjp ");
878 ia32_emit_cfop_target(proj_false);
879 be_emit_finish_line_gas(proj_false);
885 be_emit_cstring("\tjp ");
886 ia32_emit_cfop_target(proj_true);
887 be_emit_finish_line_gas(proj_true);
895 be_emit_cstring("\tj");
896 ia32_emit_cmp_suffix(pnc);
898 ia32_emit_cfop_target(proj_true);
899 be_emit_finish_line_gas(proj_true);
902 /* the second Proj might be a fallthrough */
903 if (get_cfop_target_block(proj_false) != next_block) {
904 be_emit_cstring("\tjmp ");
905 ia32_emit_cfop_target(proj_false);
906 be_emit_finish_line_gas(proj_false);
908 be_emit_cstring("\t/* fallthrough to ");
909 ia32_emit_cfop_target(proj_false);
910 be_emit_cstring(" */");
911 be_emit_finish_line_gas(proj_false);
915 static void emit_ia32_CMov(const ir_node *node)
917 const ia32_attr_t *attr = get_ia32_attr_const(node);
918 int ins_permuted = attr->data.ins_permuted;
919 const arch_register_t *out = arch_get_irn_register(arch_env, node);
920 pn_Cmp pnc = get_ia32_condcode(node);
921 const arch_register_t *in_true;
922 const arch_register_t *in_false;
924 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
926 in_true = arch_get_irn_register(arch_env,
927 get_irn_n(node, n_ia32_CMov_val_true));
928 in_false = arch_get_irn_register(arch_env,
929 get_irn_n(node, n_ia32_CMov_val_false));
931 /* should be same constraint fullfilled? */
932 if(out == in_false) {
933 /* yes -> nothing to do */
934 } else if(out == in_true) {
935 const arch_register_t *tmp;
937 assert(get_ia32_op_type(node) == ia32_Normal);
939 ins_permuted = !ins_permuted;
946 be_emit_cstring("\tmovl ");
947 emit_register(in_false, NULL);
948 be_emit_cstring(", ");
949 emit_register(out, NULL);
950 be_emit_finish_line_gas(node);
954 if(pnc & ia32_pn_Cmp_float) {
955 pnc = get_negated_pnc(pnc, mode_F);
957 pnc = get_negated_pnc(pnc, mode_Iu);
961 /* TODO: handling of Nans isn't correct yet */
963 be_emit_cstring("\tcmov");
964 ia32_emit_cmp_suffix(pnc);
966 if(get_ia32_op_type(node) == ia32_AddrModeS) {
969 emit_register(in_true, get_ia32_ls_mode(node));
971 be_emit_cstring(", ");
972 emit_register(out, get_ia32_ls_mode(node));
973 be_emit_finish_line_gas(node);
976 /*********************************************************
979 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
980 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
981 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
982 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
985 *********************************************************/
987 /* jump table entry (target and corresponding number) */
988 typedef struct _branch_t {
993 /* jump table for switch generation */
994 typedef struct _jmp_tbl_t {
995 ir_node *defProj; /**< default target */
996 long min_value; /**< smallest switch case */
997 long max_value; /**< largest switch case */
998 long num_branches; /**< number of jumps */
999 char *label; /**< label of the jump table */
1000 branch_t *branches; /**< jump array */
1004 * Compare two variables of type branch_t. Used to sort all switch cases
1007 int ia32_cmp_branch_t(const void *a, const void *b) {
1008 branch_t *b1 = (branch_t *)a;
1009 branch_t *b2 = (branch_t *)b;
1011 if (b1->value <= b2->value)
1018 * Emits code for a SwitchJmp (creates a jump table if
1019 * possible otherwise a cmp-jmp cascade). Port from
1023 void emit_ia32_SwitchJmp(const ir_node *node) {
1024 unsigned long interval;
1029 const ir_edge_t *edge;
1031 /* fill the table structure */
1032 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1033 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1035 tbl.num_branches = get_irn_n_edges(node);
1036 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1037 tbl.min_value = INT_MAX;
1038 tbl.max_value = INT_MIN;
1041 /* go over all proj's and collect them */
1042 foreach_out_edge(node, edge) {
1043 proj = get_edge_src_irn(edge);
1044 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1046 pnc = get_Proj_proj(proj);
1048 /* create branch entry */
1049 tbl.branches[i].target = proj;
1050 tbl.branches[i].value = pnc;
1052 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1053 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1055 /* check for default proj */
1056 if (pnc == get_ia32_condcode(node)) {
1057 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1064 /* sort the branches by their number */
1065 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1067 /* two-complement's magic make this work without overflow */
1068 interval = tbl.max_value - tbl.min_value;
1070 /* emit the table */
1071 be_emit_cstring("\tcmpl $");
1072 be_emit_irprintf("%u, ", interval);
1073 ia32_emit_source_register(node, 0);
1074 be_emit_finish_line_gas(node);
1076 be_emit_cstring("\tja ");
1077 ia32_emit_cfop_target(tbl.defProj);
1078 be_emit_finish_line_gas(node);
1080 if (tbl.num_branches > 1) {
1082 be_emit_cstring("\tjmp *");
1083 be_emit_string(tbl.label);
1084 be_emit_cstring("(,");
1085 ia32_emit_source_register(node, 0);
1086 be_emit_cstring(",4)");
1087 be_emit_finish_line_gas(node);
1089 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1090 be_emit_cstring("\t.align 4\n");
1091 be_emit_write_line();
1093 be_emit_string(tbl.label);
1094 be_emit_cstring(":\n");
1095 be_emit_write_line();
1097 be_emit_cstring(".long ");
1098 ia32_emit_cfop_target(tbl.branches[0].target);
1099 be_emit_finish_line_gas(NULL);
1101 last_value = tbl.branches[0].value;
1102 for (i = 1; i < tbl.num_branches; ++i) {
1103 while (++last_value < tbl.branches[i].value) {
1104 be_emit_cstring(".long ");
1105 ia32_emit_cfop_target(tbl.defProj);
1106 be_emit_finish_line_gas(NULL);
1108 be_emit_cstring(".long ");
1109 ia32_emit_cfop_target(tbl.branches[i].target);
1110 be_emit_finish_line_gas(NULL);
1112 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1114 /* one jump is enough */
1115 be_emit_cstring("\tjmp ");
1116 ia32_emit_cfop_target(tbl.branches[0].target);
1117 be_emit_finish_line_gas(node);
1127 * Emits code for a unconditional jump.
1129 static void emit_Jmp(const ir_node *node)
1131 ir_node *block, *next_block;
1133 /* for now, the code works for scheduled and non-schedules blocks */
1134 block = get_nodes_block(node);
1136 /* we have a block schedule */
1137 next_block = next_blk_sched(block);
1138 if (get_cfop_target_block(node) != next_block) {
1139 be_emit_cstring("\tjmp ");
1140 ia32_emit_cfop_target(node);
1142 be_emit_cstring("\t/* fallthrough to ");
1143 ia32_emit_cfop_target(node);
1144 be_emit_cstring(" */");
1146 be_emit_finish_line_gas(node);
1149 static void emit_ia32_Immediate(const ir_node *node)
1151 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1154 if(attr->symconst != NULL) {
1155 ident *id = get_entity_ld_ident(attr->symconst);
1161 if(attr->symconst == NULL || attr->offset != 0) {
1162 if(attr->symconst != NULL) {
1163 be_emit_irprintf("%+d", attr->offset);
1165 be_emit_irprintf("0x%X", attr->offset);
1171 * Emit an inline assembler operand.
1173 * @param node the ia32_ASM node
1174 * @param s points to the operand (a %c)
1176 * @return pointer to the first char in s NOT in the current operand
1178 static const char* emit_asm_operand(const ir_node *node, const char *s)
1180 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1181 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1183 const arch_register_t *reg;
1184 const ia32_asm_reg_t *asm_regs = attr->register_map;
1185 const ia32_asm_reg_t *asm_reg;
1186 const char *reg_name;
1195 /* parse modifiers */
1198 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1222 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1223 "'%c' for asm op\n", node, c);
1229 sscanf(s, "%d%n", &num, &p);
1231 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1238 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1239 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1240 "input/output (%+F)\n", node);
1243 asm_reg = & asm_regs[num];
1244 assert(asm_reg->valid);
1247 if(asm_reg->use_input == 0) {
1248 reg = get_out_reg(node, asm_reg->inout_pos);
1250 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1252 /* might be an immediate value */
1253 if(is_ia32_Immediate(pred)) {
1254 emit_ia32_Immediate(pred);
1257 reg = get_in_reg(node, asm_reg->inout_pos);
1260 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1261 "(%+F)\n", num, node);
1265 if(asm_reg->memory) {
1274 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1277 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1280 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1283 panic("Invalid asm op modifier");
1285 be_emit_string(reg_name);
1287 emit_register(reg, asm_reg->mode);
1290 if(asm_reg->memory) {
1298 * Emits code for an ASM pseudo op.
1300 static void emit_ia32_Asm(const ir_node *node)
1302 const void *gen_attr = get_irn_generic_attr_const(node);
1303 const ia32_asm_attr_t *attr
1304 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1305 ident *asm_text = attr->asm_text;
1306 const char *s = get_id_str(asm_text);
1308 be_emit_cstring("# Begin ASM \t");
1309 be_emit_finish_line_gas(node);
1316 s = emit_asm_operand(node, s);
1325 be_emit_write_line();
1327 be_emit_cstring("# End ASM\n");
1328 be_emit_write_line();
1331 /**********************************
1334 * | | ___ _ __ _ _| |_) |
1335 * | | / _ \| '_ \| | | | _ <
1336 * | |___| (_) | |_) | |_| | |_) |
1337 * \_____\___/| .__/ \__, |____/
1340 **********************************/
1343 * Emit movsb/w instructions to make mov count divideable by 4
1345 static void emit_CopyB_prolog(unsigned size) {
1346 be_emit_cstring("\tcld");
1347 be_emit_finish_line_gas(NULL);
1351 be_emit_cstring("\tmovsb");
1352 be_emit_finish_line_gas(NULL);
1355 be_emit_cstring("\tmovsw");
1356 be_emit_finish_line_gas(NULL);
1359 be_emit_cstring("\tmovsb");
1360 be_emit_finish_line_gas(NULL);
1361 be_emit_cstring("\tmovsw");
1362 be_emit_finish_line_gas(NULL);
1368 * Emit rep movsd instruction for memcopy.
1370 static void emit_ia32_CopyB(const ir_node *node)
1372 unsigned size = get_ia32_copyb_size(node);
1374 emit_CopyB_prolog(size);
1376 be_emit_cstring("\trep movsd");
1377 be_emit_finish_line_gas(node);
1381 * Emits unrolled memcopy.
1383 static void emit_ia32_CopyB_i(const ir_node *node)
1385 unsigned size = get_ia32_copyb_size(node);
1387 emit_CopyB_prolog(size & 0x3);
1391 be_emit_cstring("\tmovsd");
1392 be_emit_finish_line_gas(NULL);
1398 /***************************
1402 * | | / _ \| '_ \ \ / /
1403 * | |___| (_) | | | \ V /
1404 * \_____\___/|_| |_|\_/
1406 ***************************/
1409 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1411 static void emit_ia32_Conv_with_FP(const ir_node *node)
1413 ir_mode *ls_mode = get_ia32_ls_mode(node);
1414 int ls_bits = get_mode_size_bits(ls_mode);
1416 be_emit_cstring("\tcvt");
1418 if(is_ia32_Conv_I2FP(node)) {
1420 be_emit_cstring("si2ss");
1422 be_emit_cstring("si2sd");
1424 } else if(is_ia32_Conv_FP2I(node)) {
1426 be_emit_cstring("ss2si");
1428 be_emit_cstring("sd2si");
1431 assert(is_ia32_Conv_FP2FP(node));
1433 be_emit_cstring("sd2ss");
1435 be_emit_cstring("ss2sd");
1440 switch(get_ia32_op_type(node)) {
1442 ia32_emit_source_register(node, n_ia32_unary_op);
1444 case ia32_AddrModeS:
1448 assert(0 && "unsupported op type for Conv");
1450 be_emit_cstring(", ");
1451 ia32_emit_dest_register(node, 0);
1452 be_emit_finish_line_gas(node);
1455 static void emit_ia32_Conv_I2FP(const ir_node *node)
1457 emit_ia32_Conv_with_FP(node);
1460 static void emit_ia32_Conv_FP2I(const ir_node *node)
1462 emit_ia32_Conv_with_FP(node);
1465 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1467 emit_ia32_Conv_with_FP(node);
1471 * Emits code for an Int conversion.
1473 static void emit_ia32_Conv_I2I(const ir_node *node)
1475 const char *sign_suffix;
1476 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1477 int smaller_bits = get_mode_size_bits(smaller_mode);
1479 const arch_register_t *in_reg, *out_reg;
1481 assert(!mode_is_float(smaller_mode));
1482 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1484 signed_mode = mode_is_signed(smaller_mode);
1485 if(smaller_bits == 32) {
1486 // this should not happen as it's no convert
1490 sign_suffix = signed_mode ? "s" : "z";
1493 out_reg = get_out_reg(node, 0);
1495 switch(get_ia32_op_type(node)) {
1497 in_reg = get_in_reg(node, n_ia32_unary_op);
1499 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1500 out_reg == &ia32_gp_regs[REG_EAX] &&
1504 /* argument and result are both in EAX and */
1505 /* signedness is ok: -> use the smaller cwtl opcode */
1506 be_emit_cstring("\tcwtl");
1508 be_emit_cstring("\tmov");
1509 be_emit_string(sign_suffix);
1510 ia32_emit_mode_suffix_mode(smaller_mode);
1511 be_emit_cstring("l ");
1512 emit_register(in_reg, smaller_mode);
1513 be_emit_cstring(", ");
1514 emit_register(out_reg, NULL);
1517 case ia32_AddrModeS: {
1518 be_emit_cstring("\tmov");
1519 be_emit_string(sign_suffix);
1520 ia32_emit_mode_suffix_mode(smaller_mode);
1521 be_emit_cstring("l ");
1523 be_emit_cstring(", ");
1524 emit_register(out_reg, NULL);
1528 assert(0 && "unsupported op type for Conv");
1530 be_emit_finish_line_gas(node);
1534 /*******************************************
1537 * | |__ ___ _ __ ___ __| | ___ ___
1538 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1539 * | |_) | __/ | | | (_) | (_| | __/\__ \
1540 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1542 *******************************************/
1545 * Emits a backend call
1547 static void emit_be_Call(const ir_node *node)
1549 ir_entity *ent = be_Call_get_entity(node);
1551 be_emit_cstring("\tcall ");
1553 set_entity_backend_marked(ent, 1);
1554 be_emit_string(get_entity_ld_name(ent));
1556 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1558 emit_register(reg, NULL);
1560 be_emit_finish_line_gas(node);
1564 * Emits code to increase stack pointer.
1566 static void emit_be_IncSP(const ir_node *node)
1568 int offs = be_get_IncSP_offset(node);
1569 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1575 be_emit_cstring("\tsubl $");
1576 be_emit_irprintf("%u, ", offs);
1577 emit_register(reg, NULL);
1579 be_emit_cstring("\taddl $");
1580 be_emit_irprintf("%u, ", -offs);
1581 emit_register(reg, NULL);
1583 be_emit_finish_line_gas(node);
1587 * Emits code for Copy/CopyKeep.
1589 static void Copy_emitter(const ir_node *node, const ir_node *op)
1591 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1592 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1598 if(is_unknown_reg(in))
1600 /* copies of vf nodes aren't real... */
1601 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1604 mode = get_irn_mode(node);
1605 if (mode == mode_E) {
1606 be_emit_cstring("\tmovsd ");
1607 emit_register(in, NULL);
1608 be_emit_cstring(", ");
1609 emit_register(out, NULL);
1611 be_emit_cstring("\tmovl ");
1612 emit_register(in, NULL);
1613 be_emit_cstring(", ");
1614 emit_register(out, NULL);
1616 be_emit_finish_line_gas(node);
1619 static void emit_be_Copy(const ir_node *node)
1621 Copy_emitter(node, be_get_Copy_op(node));
1624 static void emit_be_CopyKeep(const ir_node *node)
1626 Copy_emitter(node, be_get_CopyKeep_op(node));
1630 * Emits code for exchange.
1632 static void emit_be_Perm(const ir_node *node)
1634 const arch_register_t *in0, *in1;
1635 const arch_register_class_t *cls0, *cls1;
1637 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1638 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1640 cls0 = arch_register_get_class(in0);
1641 cls1 = arch_register_get_class(in1);
1643 assert(cls0 == cls1 && "Register class mismatch at Perm");
1645 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1646 be_emit_cstring("\txchg ");
1647 emit_register(in1, NULL);
1648 be_emit_cstring(", ");
1649 emit_register(in0, NULL);
1650 be_emit_finish_line_gas(node);
1651 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1652 be_emit_cstring("\txorpd ");
1653 emit_register(in1, NULL);
1654 be_emit_cstring(", ");
1655 emit_register(in0, NULL);
1656 be_emit_finish_line_gas(NULL);
1658 be_emit_cstring("\txorpd ");
1659 emit_register(in0, NULL);
1660 be_emit_cstring(", ");
1661 emit_register(in1, NULL);
1662 be_emit_finish_line_gas(NULL);
1664 be_emit_cstring("\txorpd ");
1665 emit_register(in1, NULL);
1666 be_emit_cstring(", ");
1667 emit_register(in0, NULL);
1668 be_emit_finish_line_gas(node);
1669 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1671 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1674 panic("unexpected register class in be_Perm (%+F)\n", node);
1679 * Emits code for Constant loading.
1681 static void emit_ia32_Const(const ir_node *node)
1683 be_emit_cstring("\tmovl ");
1684 emit_ia32_Immediate(node);
1685 be_emit_cstring(", ");
1686 ia32_emit_dest_register(node, 0);
1688 be_emit_finish_line_gas(node);
1692 * Emits code to load the TLS base
1694 static void emit_ia32_LdTls(const ir_node *node)
1696 be_emit_cstring("\tmovl %gs:0, ");
1697 ia32_emit_dest_register(node, 0);
1698 be_emit_finish_line_gas(node);
1701 /* helper function for emit_ia32_Minus64Bit */
1702 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1704 be_emit_cstring("\tmovl ");
1705 emit_register(src, NULL);
1706 be_emit_cstring(", ");
1707 emit_register(dst, NULL);
1708 be_emit_finish_line_gas(node);
1711 /* helper function for emit_ia32_Minus64Bit */
1712 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1714 be_emit_cstring("\tnegl ");
1715 emit_register(reg, NULL);
1716 be_emit_finish_line_gas(node);
1719 /* helper function for emit_ia32_Minus64Bit */
1720 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1722 be_emit_cstring("\tsbbl $0, ");
1723 emit_register(reg, NULL);
1724 be_emit_finish_line_gas(node);
1727 /* helper function for emit_ia32_Minus64Bit */
1728 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1730 be_emit_cstring("\tsbbl ");
1731 emit_register(src, NULL);
1732 be_emit_cstring(", ");
1733 emit_register(dst, NULL);
1734 be_emit_finish_line_gas(node);
1737 /* helper function for emit_ia32_Minus64Bit */
1738 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1740 be_emit_cstring("\txchgl ");
1741 emit_register(src, NULL);
1742 be_emit_cstring(", ");
1743 emit_register(dst, NULL);
1744 be_emit_finish_line_gas(node);
1747 /* helper function for emit_ia32_Minus64Bit */
1748 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1750 be_emit_cstring("\txorl ");
1751 emit_register(reg, NULL);
1752 be_emit_cstring(", ");
1753 emit_register(reg, NULL);
1754 be_emit_finish_line_gas(node);
1757 static void emit_ia32_Minus64Bit(const ir_node *node)
1759 const arch_register_t *in_lo = get_in_reg(node, 0);
1760 const arch_register_t *in_hi = get_in_reg(node, 1);
1761 const arch_register_t *out_lo = get_out_reg(node, 0);
1762 const arch_register_t *out_hi = get_out_reg(node, 1);
1764 if (out_lo == in_lo) {
1765 if (out_hi != in_hi) {
1766 /* a -> a, b -> d */
1769 /* a -> a, b -> b */
1772 } else if (out_lo == in_hi) {
1773 if (out_hi == in_lo) {
1774 /* a -> b, b -> a */
1775 emit_xchg(node, in_lo, in_hi);
1778 /* a -> b, b -> d */
1779 emit_mov(node, in_hi, out_hi);
1780 emit_mov(node, in_lo, out_lo);
1784 if (out_hi == in_lo) {
1785 /* a -> c, b -> a */
1786 emit_mov(node, in_lo, out_lo);
1788 } else if (out_hi == in_hi) {
1789 /* a -> c, b -> b */
1790 emit_mov(node, in_lo, out_lo);
1793 /* a -> c, b -> d */
1794 emit_mov(node, in_lo, out_lo);
1800 emit_neg( node, out_hi);
1801 emit_neg( node, out_lo);
1802 emit_sbb0(node, out_hi);
1806 emit_zero(node, out_hi);
1807 emit_neg( node, out_lo);
1808 emit_sbb( node, in_hi, out_hi);
1811 static void emit_be_Return(const ir_node *node)
1814 be_emit_cstring("\tret");
1816 pop = be_Return_get_pop(node);
1818 be_emit_irprintf(" $%d", pop);
1820 be_emit_finish_line_gas(node);
1823 static void emit_Nothing(const ir_node *node)
1829 /***********************************************************************************
1832 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1833 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1834 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1835 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1837 ***********************************************************************************/
1840 * Enters the emitter functions for handled nodes into the generic
1841 * pointer of an opcode.
1844 void ia32_register_emitters(void) {
1846 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1847 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1848 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1849 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1850 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1851 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1853 /* first clear the generic function pointer for all ops */
1854 clear_irp_opcodes_generic_func();
1856 /* register all emitter functions defined in spec */
1857 ia32_register_spec_emitters();
1859 /* other ia32 emitter functions */
1863 IA32_EMIT(SwitchJmp);
1866 IA32_EMIT(Conv_I2FP);
1867 IA32_EMIT(Conv_FP2I);
1868 IA32_EMIT(Conv_FP2FP);
1869 IA32_EMIT(Conv_I2I);
1870 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1873 IA32_EMIT(Minus64Bit);
1876 /* benode emitter */
1901 static const char *last_name = NULL;
1902 static unsigned last_line = -1;
1903 static unsigned num = -1;
1906 * Emit the debug support for node node.
1908 static void ia32_emit_dbg(const ir_node *node)
1910 dbg_info *db = get_irn_dbg_info(node);
1912 const char *fname = be_retrieve_dbg_info(db, &lineno);
1914 if (! cg->birg->main_env->options->stabs_debug_support)
1918 if (last_name != fname) {
1920 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1923 if (last_line != lineno) {
1926 snprintf(name, sizeof(name), ".LM%u", ++num);
1928 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1929 be_emit_string(name);
1930 be_emit_cstring(":\n");
1931 be_emit_write_line();
1936 typedef void (*emit_func_ptr) (const ir_node *);
1939 * Emits code for a node.
1941 static void ia32_emit_node(const ir_node *node)
1943 ir_op *op = get_irn_op(node);
1945 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1947 if (op->ops.generic) {
1948 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1949 ia32_emit_dbg(node);
1953 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1959 * Emits gas alignment directives
1961 static void ia32_emit_alignment(unsigned align, unsigned skip)
1963 be_emit_cstring("\t.p2align ");
1964 be_emit_irprintf("%u,,%u\n", align, skip);
1965 be_emit_write_line();
1969 * Emits gas alignment directives for Functions depended on cpu architecture.
1971 static void ia32_emit_align_func(cpu_support cpu)
1974 unsigned maximum_skip;
1989 maximum_skip = (1 << align) - 1;
1990 ia32_emit_alignment(align, maximum_skip);
1994 * Emits gas alignment directives for Labels depended on cpu architecture.
1996 static void ia32_emit_align_label(cpu_support cpu)
1998 unsigned align; unsigned maximum_skip;
2013 maximum_skip = (1 << align) - 1;
2014 ia32_emit_alignment(align, maximum_skip);
2018 * Test wether a block should be aligned.
2019 * For cpus in the P4/Athlon class it is useful to align jump labels to
2020 * 16 bytes. However we should only do that if the alignment nops before the
2021 * label aren't executed more often than we have jumps to the label.
2023 static int should_align_block(ir_node *block, ir_node *prev)
2025 static const double DELTA = .0001;
2026 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2028 double prev_freq = 0; /**< execfreq of the fallthrough block */
2029 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2030 cpu_support cpu = isa->opt_arch;
2033 if(exec_freq == NULL)
2035 if(cpu == arch_i386 || cpu == arch_i486)
2038 block_freq = get_block_execfreq(exec_freq, block);
2039 if(block_freq < DELTA)
2042 n_cfgpreds = get_Block_n_cfgpreds(block);
2043 for(i = 0; i < n_cfgpreds; ++i) {
2044 ir_node *pred = get_Block_cfgpred_block(block, i);
2045 double pred_freq = get_block_execfreq(exec_freq, pred);
2048 prev_freq += pred_freq;
2050 jmp_freq += pred_freq;
2054 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2057 jmp_freq /= prev_freq;
2061 case arch_athlon_64:
2063 return jmp_freq > 3;
2065 return jmp_freq > 2;
2069 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2074 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2076 n_cfgpreds = get_Block_n_cfgpreds(block);
2077 need_label = (n_cfgpreds != 0);
2079 if (should_align_block(block, prev)) {
2081 ia32_emit_align_label(isa->opt_arch);
2085 ia32_emit_block_name(block);
2088 be_emit_pad_comment();
2089 be_emit_cstring(" /* preds:");
2091 /* emit list of pred blocks in comment */
2092 arity = get_irn_arity(block);
2093 for (i = 0; i < arity; ++i) {
2094 ir_node *predblock = get_Block_cfgpred_block(block, i);
2095 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2098 be_emit_cstring("\t/* ");
2099 ia32_emit_block_name(block);
2100 be_emit_cstring(": ");
2102 if (exec_freq != NULL) {
2103 be_emit_irprintf(" freq: %f",
2104 get_block_execfreq(exec_freq, block));
2106 be_emit_cstring(" */\n");
2107 be_emit_write_line();
2111 * Walks over the nodes in a block connected by scheduling edges
2112 * and emits code for each node.
2114 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2116 const ir_node *node;
2118 ia32_emit_block_header(block, last_block);
2120 /* emit the contents of the block */
2121 ia32_emit_dbg(block);
2122 sched_foreach(block, node) {
2123 ia32_emit_node(node);
2128 * Emits code for function start.
2130 static void ia32_emit_func_prolog(ir_graph *irg)
2132 ir_entity *irg_ent = get_irg_entity(irg);
2133 const char *irg_name = get_entity_ld_name(irg_ent);
2134 cpu_support cpu = isa->opt_arch;
2135 const be_irg_t *birg = cg->birg;
2137 /* write the begin line (used by scripts processing the assembler... */
2138 be_emit_write_line();
2139 be_emit_cstring("# -- Begin ");
2140 be_emit_string(irg_name);
2142 be_emit_write_line();
2144 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2145 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2146 ia32_emit_align_func(cpu);
2147 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2148 be_emit_cstring(".global ");
2149 be_emit_string(irg_name);
2151 be_emit_write_line();
2153 ia32_emit_function_object(irg_name);
2154 be_emit_string(irg_name);
2155 be_emit_cstring(":\n");
2156 be_emit_write_line();
2160 * Emits code for function end
2162 static void ia32_emit_func_epilog(ir_graph *irg)
2164 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2165 const be_irg_t *birg = cg->birg;
2167 ia32_emit_function_size(irg_name);
2168 be_dbg_method_end(birg->main_env->db_handle);
2170 be_emit_cstring("# -- End ");
2171 be_emit_string(irg_name);
2173 be_emit_write_line();
2176 be_emit_write_line();
2181 * Sets labels for control flow nodes (jump target)
2183 static void ia32_gen_labels(ir_node *block, void *data)
2186 int n = get_Block_n_cfgpreds(block);
2189 for (n--; n >= 0; n--) {
2190 pred = get_Block_cfgpred(block, n);
2191 set_irn_link(pred, block);
2196 * Emit an exception label if the current instruction can fail.
2198 void ia32_emit_exc_label(const ir_node *node)
2200 if (get_ia32_exc_label(node)) {
2201 be_emit_irprintf(".EXL%u\n", 0);
2202 be_emit_write_line();
2207 * Main driver. Emits the code for one routine.
2209 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2212 ir_node *last_block = NULL;
2216 isa = (const ia32_isa_t*) cg->arch_env->isa;
2217 arch_env = cg->arch_env;
2219 ia32_register_emitters();
2221 ia32_emit_func_prolog(irg);
2222 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2224 n = ARR_LEN(cg->blk_sched);
2225 for (i = 0; i < n;) {
2228 block = cg->blk_sched[i];
2230 next_bl = i < n ? cg->blk_sched[i] : NULL;
2232 /* set here the link. the emitter expects to find the next block here */
2233 set_irn_link(block, next_bl);
2234 ia32_gen_block(block, last_block);
2238 ia32_emit_func_epilog(irg);
2241 void ia32_init_emitter(void)
2243 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");