2 * This file implements the node emitter.
3 * @author Christian Wuerdig
22 #include "iredges_t.h"
24 #include "../besched_t.h"
25 #include "../benode_t.h"
27 #include "ia32_emitter.h"
28 #include "gen_ia32_emitter.h"
29 #include "gen_ia32_regalloc_if.h"
30 #include "ia32_nodes_attr.h"
31 #include "ia32_new_nodes.h"
32 #include "ia32_map_regs.h"
33 #include "bearch_ia32_t.h"
35 #define BLOCK_PREFIX(x) ".L" x
37 #define SNPRINTF_BUF_LEN 128
39 /* global arch_env for lc_printf functions */
40 static const arch_env_t *arch_env = NULL;
42 /** by default, we generate assembler code for the Linux gas */
43 asm_flavour_t asm_flavour = ASM_LINUX_GAS;
46 * Switch to a new section
48 void ia32_switch_section(FILE *F, section_t sec) {
49 static section_t curr_sec = NO_SECTION;
50 static const char *text[ASM_MAX][SECTION_MAX] = {
52 ".section\t.text", ".section\t.data", ".section\t.rodata", ".section\t.text"
55 ".section\t.text", ".section\t.data", ".section .rdata,\"dr\"", ".section\t.text"
72 fprintf(F, "\t%s\n", text[asm_flavour][sec]);
80 static void ia32_dump_function_object(FILE *F, const char *name)
82 switch (asm_flavour) {
84 fprintf(F, "\t.type\t%s, @function\n", name);
87 fprintf(F, "\t.def\t%s;\t.scl\t2;\t.type\t32;\t.endef\n", name);
94 static void ia32_dump_function_size(FILE *F, const char *name)
96 switch (asm_flavour) {
98 fprintf(F, "\t.size\t%s, .-%s\n", name, name);
105 /*************************************************************
107 * (_) | | / _| | | | |
108 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
109 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
110 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
111 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
114 *************************************************************/
116 static INLINE int be_is_unknown_reg(const arch_register_t *reg) {
118 REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]) || \
119 REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]) || \
120 REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]);
124 * returns true if a node has x87 registers
126 static INLINE int has_x87_register(const ir_node *n) {
127 return is_irn_machine_user(n, 0);
130 /* We always pass the ir_node which is a pointer. */
131 static int ia32_get_arg_type(const lc_arg_occ_t *occ) {
132 return lc_arg_type_ptr;
137 * Returns the register at in position pos.
139 static const arch_register_t *get_in_reg(const ir_node *irn, int pos) {
141 const arch_register_t *reg = NULL;
143 assert(get_irn_arity(irn) > pos && "Invalid IN position");
145 /* The out register of the operator at position pos is the
146 in register we need. */
147 op = get_irn_n(irn, pos);
149 reg = arch_get_irn_register(arch_env, op);
151 assert(reg && "no in register found");
153 /* in case of unknown: just return a register */
154 if (REGS_ARE_EQUAL(reg, &ia32_gp_regs[REG_GP_UKNWN]))
155 reg = &ia32_gp_regs[REG_EAX];
156 else if (REGS_ARE_EQUAL(reg, &ia32_xmm_regs[REG_XMM_UKNWN]))
157 reg = &ia32_xmm_regs[REG_XMM0];
158 else if (REGS_ARE_EQUAL(reg, &ia32_vfp_regs[REG_VFP_UKNWN]))
159 reg = &ia32_vfp_regs[REG_VF0];
165 * Returns the register at out position pos.
167 static const arch_register_t *get_out_reg(const ir_node *irn, int pos) {
169 const arch_register_t *reg = NULL;
171 /* 1st case: irn is not of mode_T, so it has only */
172 /* one OUT register -> good */
173 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
174 /* Proj with the corresponding projnum for the register */
176 if (get_irn_mode(irn) != mode_T) {
177 reg = arch_get_irn_register(arch_env, irn);
179 else if (is_ia32_irn(irn)) {
180 reg = get_ia32_out_reg(irn, pos);
183 const ir_edge_t *edge;
185 foreach_out_edge(irn, edge) {
186 proj = get_edge_src_irn(edge);
187 assert(is_Proj(proj) && "non-Proj from mode_T node");
188 if (get_Proj_proj(proj) == pos) {
189 reg = arch_get_irn_register(arch_env, proj);
195 assert(reg && "no out register found");
205 * Returns the name of the in register at position pos.
207 static const char *get_ia32_reg_name(ir_node *irn, int pos, enum io_direction in_out) {
208 const arch_register_t *reg;
210 if (in_out == IN_REG) {
211 reg = get_in_reg(irn, pos);
213 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp]) {
214 /* FIXME: works for binop only */
215 assert(2 <= pos && pos <= 3);
216 reg = get_ia32_attr(irn)->x87[pos - 2];
220 /* destination address mode nodes don't have outputs */
221 if (is_ia32_irn(irn) && get_ia32_op_type(irn) == ia32_AddrModeD) {
225 reg = get_out_reg(irn, pos);
226 if (reg->reg_class == &ia32_reg_classes[CLASS_ia32_vfp])
227 reg = get_ia32_attr(irn)->x87[pos + 2];
229 return arch_register_get_name(reg);
233 * Get the register name for a node.
235 static int ia32_get_reg_name(lc_appendable_t *app,
236 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
239 ir_node *irn = arg->v_ptr;
240 int nr = occ->width - 1;
243 return lc_appendable_snadd(app, "(null)", 6);
245 buf = get_ia32_reg_name(irn, nr, occ->conversion == 'S' ? IN_REG : OUT_REG);
247 /* append the stupid % to register names */
248 lc_appendable_chadd(app, '%');
249 return lc_appendable_snadd(app, buf, strlen(buf));
253 * Get the x87 register name for a node.
255 static int ia32_get_x87_name(lc_appendable_t *app,
256 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
259 ir_node *irn = arg->v_ptr;
260 int nr = occ->width - 1;
264 return lc_appendable_snadd(app, "(null)", 6);
266 attr = get_ia32_attr(irn);
267 buf = attr->x87[nr]->name;
268 lc_appendable_chadd(app, '%');
269 return lc_appendable_snadd(app, buf, strlen(buf));
273 * Returns the tarval, offset or scale of an ia32 as a string.
275 static int ia32_const_to_str(lc_appendable_t *app,
276 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
279 ir_node *irn = arg->v_ptr;
282 return lc_arg_append(app, occ, "(null)", 6);
284 if (occ->conversion == 'C') {
285 buf = get_ia32_cnst(irn);
288 buf = get_ia32_am_offs(irn);
291 return buf ? lc_appendable_snadd(app, buf, strlen(buf)) : 0;
295 * Determines the SSE suffix depending on the mode.
297 static int ia32_get_mode_suffix(lc_appendable_t *app,
298 const lc_arg_occ_t *occ, const lc_arg_value_t *arg)
300 ir_node *irn = arg->v_ptr;
301 ir_mode *mode = get_irn_mode(irn);
303 if (mode == mode_T) {
304 mode = get_ia32_res_mode(irn);
306 mode = get_ia32_ls_mode(irn);
310 return lc_arg_append(app, occ, "(null)", 6);
312 if (mode_is_float(mode)) {
313 return lc_appendable_chadd(app, get_mode_size_bits(mode) == 32 ? 's' : 'd');
316 return lc_appendable_chadd(app, mode_is_signed(mode) ? 's' : 'z');
321 * Return the ia32 printf arg environment.
322 * We use the firm environment with some additional handlers.
324 const lc_arg_env_t *ia32_get_arg_env(void) {
325 static lc_arg_env_t *env = NULL;
327 static const lc_arg_handler_t ia32_reg_handler = { ia32_get_arg_type, ia32_get_reg_name };
328 static const lc_arg_handler_t ia32_const_handler = { ia32_get_arg_type, ia32_const_to_str };
329 static const lc_arg_handler_t ia32_mode_handler = { ia32_get_arg_type, ia32_get_mode_suffix };
330 static const lc_arg_handler_t ia32_x87_handler = { ia32_get_arg_type, ia32_get_x87_name };
333 /* extend the firm printer */
334 env = firm_get_arg_env();
336 lc_arg_register(env, "ia32:sreg", 'S', &ia32_reg_handler);
337 lc_arg_register(env, "ia32:dreg", 'D', &ia32_reg_handler);
338 lc_arg_register(env, "ia32:cnst", 'C', &ia32_const_handler);
339 lc_arg_register(env, "ia32:offs", 'O', &ia32_const_handler);
340 lc_arg_register(env, "ia32:mode", 'M', &ia32_mode_handler);
341 lc_arg_register(env, "ia32:x87", 'X', &ia32_x87_handler);
347 static const char *ia32_get_reg_name_for_mode(ia32_emit_env_t *env, ir_mode *mode, const arch_register_t *reg) {
348 switch(get_mode_size_bits(mode)) {
350 return ia32_get_mapped_reg_name(env->isa->regs_8bit, reg);
352 return ia32_get_mapped_reg_name(env->isa->regs_16bit, reg);
354 return (char *)arch_register_get_name(reg);
359 * Emits registers and/or address mode of a binary operation.
361 const char *ia32_emit_binop(const ir_node *n, ia32_emit_env_t *env) {
362 static char *buf = NULL;
364 /* verify that this function is never called on non-AM supporting operations */
365 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
367 #define PRODUCES_RESULT(n) \
368 (!(is_ia32_St(n) || \
369 is_ia32_Store8Bit(n) || \
370 is_ia32_CondJmp(n) || \
371 is_ia32_xCondJmp(n) || \
372 is_ia32_CmpSet(n) || \
373 is_ia32_xCmpSet(n) || \
374 is_ia32_SwitchJmp(n)))
377 buf = xcalloc(1, SNPRINTF_BUF_LEN);
380 memset(buf, 0, SNPRINTF_BUF_LEN);
383 switch(get_ia32_op_type(n)) {
385 if (is_ia32_ImmConst(n)) {
386 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, get_ia32_cnst(n));
388 else if (is_ia32_ImmSymConst(n)) {
389 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, OFFSET FLAT:%s", n, get_ia32_cnst(n));
392 const arch_register_t *in1 = get_in_reg(n, 2);
393 const arch_register_t *in2 = get_in_reg(n, 3);
394 const arch_register_t *out = PRODUCES_RESULT(n) ? get_out_reg(n, 0) : NULL;
395 const arch_register_t *in;
398 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
399 out = out ? out : in1;
400 in_name = arch_register_get_name(in);
402 if (is_ia32_emit_cl(n)) {
403 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in) && "shift operation needs ecx");
407 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
411 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
412 assert(! PRODUCES_RESULT(n) && "Source AM with Const must not produce result");
413 snprintf(buf, SNPRINTF_BUF_LEN, "%s, %s", get_ia32_cnst(n), ia32_emit_am(n, env));
416 if (PRODUCES_RESULT(n)) {
417 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D, %s", n, ia32_emit_am(n, env));
420 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%3S, %s", n, ia32_emit_am(n, env));
425 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
426 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s,%s%s",
427 ia32_emit_am(n, env),
428 is_ia32_ImmSymConst(n) ? " OFFSET FLAT:" : " ", /* In case of a symconst we must add OFFSET to */
429 get_ia32_cnst(n)); /* tell the assembler to store it's address. */
432 const arch_register_t *in1 = get_in_reg(n, get_irn_arity(n) == 5 ? 3 : 2);
433 ir_mode *mode = get_ia32_res_mode(n);
436 mode = mode ? mode : get_ia32_ls_mode(n);
437 in_name = ia32_get_reg_name_for_mode(env, mode, in1);
439 if (is_ia32_emit_cl(n)) {
440 assert(REGS_ARE_EQUAL(&ia32_gp_regs[REG_ECX], in1) && "shift operation needs ecx");
444 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s, %%%s", ia32_emit_am(n, env), in_name);
448 assert(0 && "unsupported op type");
451 #undef PRODUCES_RESULT
457 * Returns the xxx PTR string for a given mode
459 * @param mode the mode
460 * @param x87_insn if non-zero returns the string for a x87 instruction
461 * else for a SSE instruction
463 static const char *pointer_size(ir_mode *mode, int x87_insn)
466 switch (get_mode_size_bits(mode)) {
467 case 8: return "BYTE PTR";
468 case 16: return "WORD PTR";
469 case 32: return "DWORD PTR";
475 case 96: return "XWORD PTR";
476 default: return NULL;
483 * Emits registers and/or address mode of a binary operation.
485 const char *ia32_emit_x87_binop(const ir_node *n, ia32_emit_env_t *env) {
486 static char *buf = NULL;
488 /* verify that this function is never called on non-AM supporting operations */
489 //assert(get_ia32_am_support(n) != ia32_am_None && "emit binop expects addressmode support");
492 buf = xcalloc(1, SNPRINTF_BUF_LEN);
495 memset(buf, 0, SNPRINTF_BUF_LEN);
498 switch(get_ia32_op_type(n)) {
500 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
501 ir_mode *mode = get_ia32_ls_mode(n);
502 const char *p = pointer_size(mode, 1);
503 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s %s", p, get_ia32_cnst(n));
506 ia32_attr_t *attr = get_ia32_attr(n);
507 const arch_register_t *in1 = attr->x87[0];
508 const arch_register_t *in2 = attr->x87[1];
509 const arch_register_t *out = attr->x87[2];
510 const arch_register_t *in;
513 in = out ? (REGS_ARE_EQUAL(out, in2) ? in1 : in2) : in2;
514 out = out ? out : in1;
515 in_name = arch_register_get_name(in);
517 snprintf(buf, SNPRINTF_BUF_LEN, "%%%s, %%%s", arch_register_get_name(out), in_name);
522 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
525 assert(0 && "unsupported op type");
532 * Emits registers and/or address mode of a unary operation.
534 const char *ia32_emit_unop(const ir_node *n, ia32_emit_env_t *env) {
535 static char *buf = NULL;
538 buf = xcalloc(1, SNPRINTF_BUF_LEN);
541 memset(buf, 0, SNPRINTF_BUF_LEN);
544 switch(get_ia32_op_type(n)) {
546 if (is_ia32_ImmConst(n) || is_ia32_ImmSymConst(n)) {
547 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%C", n);
550 if (is_ia32_MulS(n) || is_ia32_Mulh(n)) {
551 /* MulS and Mulh implicitly multiply by EAX */
552 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%4S", n);
555 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%1D", n);
559 snprintf(buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
563 Mulh is emitted via emit_unop
564 imul [MEM] means EDX:EAX <- EAX * [MEM]
566 assert((is_ia32_Mulh(n) || is_ia32_MulS(n)) && "Only MulS and Mulh can have AM source as unop");
567 lc_esnprintf(ia32_get_arg_env(), buf, SNPRINTF_BUF_LEN, "%s", ia32_emit_am(n, env));
570 assert(0 && "unsupported op type");
577 * Emits address mode.
579 const char *ia32_emit_am(const ir_node *n, ia32_emit_env_t *env) {
580 ia32_am_flavour_t am_flav = get_ia32_am_flavour(n);
584 static struct obstack *obst = NULL;
585 ir_mode *mode = get_ia32_ls_mode(n);
587 if (! is_ia32_Lea(n))
588 assert(mode && "AM node must have ls_mode attribute set.");
591 obst = xcalloc(1, sizeof(*obst));
594 obstack_free(obst, NULL);
597 /* obstack_free with NULL results in an uninitialized obstack */
600 p = pointer_size(mode, has_x87_register(n) || is_ia32_GetST0(n) || is_ia32_SetST0(n));
602 obstack_printf(obst, "%s ", p);
604 /* emit address mode symconst */
605 if (get_ia32_am_sc(n)) {
606 if (is_ia32_am_sc_sign(n))
607 obstack_printf(obst, "-");
608 obstack_printf(obst, "%s", get_id_str(get_ia32_am_sc(n)));
611 if (am_flav & ia32_B) {
612 obstack_printf(obst, "[");
613 lc_eoprintf(ia32_get_arg_env(), obst, "%1S", n);
617 if (am_flav & ia32_I) {
619 obstack_printf(obst, "+");
622 obstack_printf(obst, "[");
625 lc_eoprintf(ia32_get_arg_env(), obst, "%2S", n);
627 if (am_flav & ia32_S) {
628 obstack_printf(obst, "*%d", 1 << get_ia32_am_scale(n));
634 if (am_flav & ia32_O) {
635 s = get_ia32_am_offs(n);
638 /* omit explicit + if there was no base or index */
640 obstack_printf(obst, "[");
645 obstack_printf(obst, s);
651 obstack_printf(obst, "] ");
653 obstack_1grow(obst, '\0');
654 s = obstack_finish(obst);
662 const char *ia32_emit_adr(const ir_node *irn, ia32_emit_env_t *env)
664 static char buf[SNPRINTF_BUF_LEN];
665 ir_mode *mode = get_ia32_ls_mode(irn);
666 const char *adr = get_ia32_cnst(irn);
667 const char *pref = pointer_size(mode, has_x87_register(irn));
669 snprintf(buf, SNPRINTF_BUF_LEN, "%s %s", pref ? pref : "", adr);
674 * Formated print of commands and comments.
676 static void ia32_fprintf_format(FILE *F, const ir_node *irn, char *cmd_buf, char *cmnt_buf) {
678 const char *name = irn ? be_retrieve_dbg_info(get_irn_dbg_info((ir_node *)irn), &lineno) : NULL;
681 fprintf(F, "\t%-35s %-60s /* %s:%u */\n", cmd_buf, cmnt_buf, name, lineno);
683 fprintf(F, "\t%-35s %-60s\n", cmd_buf, cmnt_buf);
689 * Add a number to a prefix. This number will not be used a second time.
691 static char *get_unique_label(char *buf, size_t buflen, const char *prefix) {
692 static unsigned long id = 0;
693 snprintf(buf, buflen, "%s%lu", prefix, ++id);
699 /*************************************************
702 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
703 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
704 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
705 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
707 *************************************************/
710 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
713 * coding of conditions
715 struct cmp2conditon_t {
721 * positive conditions for signed compares
723 static const struct cmp2conditon_t cmp2condition_s[] = {
724 { NULL, pn_Cmp_False }, /* always false */
725 { "e", pn_Cmp_Eq }, /* == */
726 { "l", pn_Cmp_Lt }, /* < */
727 { "le", pn_Cmp_Le }, /* <= */
728 { "g", pn_Cmp_Gt }, /* > */
729 { "ge", pn_Cmp_Ge }, /* >= */
730 { "ne", pn_Cmp_Lg }, /* != */
731 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
732 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
733 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
734 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
735 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
736 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
737 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
738 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
739 { NULL, pn_Cmp_True }, /* always true */
743 * positive conditions for unsigned compares
745 static const struct cmp2conditon_t cmp2condition_u[] = {
746 { NULL, pn_Cmp_False }, /* always false */
747 { "e", pn_Cmp_Eq }, /* == */
748 { "b", pn_Cmp_Lt }, /* < */
749 { "be", pn_Cmp_Le }, /* <= */
750 { "a", pn_Cmp_Gt }, /* > */
751 { "ae", pn_Cmp_Ge }, /* >= */
752 { "ne", pn_Cmp_Lg }, /* != */
753 { "ordered", pn_Cmp_Leg }, /* Floating point: ordered */
754 { "unordered", pn_Cmp_Uo }, /* FLoting point: unordered */
755 { "e", pn_Cmp_Ue }, /* Floating point: unordered or == */
756 { "b", pn_Cmp_Ul }, /* Floating point: unordered or < */
757 { "be", pn_Cmp_Ule }, /* Floating point: unordered or <= */
758 { "a", pn_Cmp_Ug }, /* Floating point: unordered or > */
759 { "ae", pn_Cmp_Uge }, /* Floating point: unordered or >= */
760 { "ne", pn_Cmp_Ne }, /* Floating point: unordered or != */
761 { NULL, pn_Cmp_True }, /* always true */
765 * returns the condition code
767 static const char *get_cmp_suffix(int cmp_code, int unsigned_cmp)
769 assert(cmp2condition_s[cmp_code].num == cmp_code);
770 assert(cmp2condition_u[cmp_code].num == cmp_code);
772 return unsigned_cmp ? cmp2condition_u[cmp_code & 7].name : cmp2condition_s[cmp_code & 7].name;
776 * Returns the target block for a control flow node.
778 static ir_node *get_cfop_target_block(const ir_node *irn) {
779 return get_irn_link(irn);
783 * Returns the target label for a control flow node.
785 static char *get_cfop_target(const ir_node *irn, char *buf) {
786 ir_node *bl = get_cfop_target_block(irn);
788 snprintf(buf, SNPRINTF_BUF_LEN, BLOCK_PREFIX("%ld"), get_irn_node_nr(bl));
792 /** Return the next block in Block schedule */
793 static ir_node *next_blk_sched(const ir_node *block) {
794 return get_irn_link(block);
798 * Returns the Proj with projection number proj and NOT mode_M
800 static ir_node *get_proj(const ir_node *irn, long proj) {
801 const ir_edge_t *edge;
804 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
806 foreach_out_edge(irn, edge) {
807 src = get_edge_src_irn(edge);
809 assert(is_Proj(src) && "Proj expected");
810 if (get_irn_mode(src) == mode_M)
813 if (get_Proj_proj(src) == proj)
820 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
822 static void finish_CondJmp(FILE *F, const ir_node *irn, ir_mode *mode) {
823 const ir_node *proj1, *proj2 = NULL;
824 const ir_node *block, *next_bl = NULL;
825 char buf[SNPRINTF_BUF_LEN];
826 char cmd_buf[SNPRINTF_BUF_LEN];
827 char cmnt_buf[SNPRINTF_BUF_LEN];
830 /* get both Proj's */
831 proj1 = get_proj(irn, pn_Cond_true);
832 assert(proj1 && "CondJmp without true Proj");
834 proj2 = get_proj(irn, pn_Cond_false);
835 assert(proj2 && "CondJmp without false Proj");
837 /* for now, the code works for scheduled and non-schedules blocks */
838 block = get_nodes_block(irn);
840 /* we have a block schedule */
841 next_bl = next_blk_sched(block);
843 if (get_cfop_target_block(proj1) == next_bl) {
844 /* exchange both proj's so the second one can be omitted */
845 const ir_node *t = proj1;
850 /* the first Proj must always be created */
851 is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
852 if (get_Proj_proj(proj1) == pn_Cond_true) {
853 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
854 get_cmp_suffix(get_ia32_pncode(irn), is_unsigned),
855 get_cfop_target(proj1, buf));
856 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == TRUE */");
859 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "j%s %s",
860 get_cmp_suffix(get_negated_pnc(get_ia32_pncode(irn), mode), is_unsigned),
861 get_cfop_target(proj1, buf));
862 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* cmp(a, b) == FALSE */");
866 /* the second Proj might be a fallthrough */
867 if (get_cfop_target_block(proj2) != next_bl) {
868 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(proj2, buf));
869 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* otherwise */");
873 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(proj2, buf));
879 * Emits code for conditional jump.
881 static void CondJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
883 char cmd_buf[SNPRINTF_BUF_LEN];
884 char cmnt_buf[SNPRINTF_BUF_LEN];
886 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
887 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
889 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
893 * Emits code for conditional jump with two variables.
895 static void emit_ia32_CondJmp(const ir_node *irn, ia32_emit_env_t *env) {
896 CondJmp_emitter(irn, env);
900 * Emits code for conditional test and jump.
902 static void TestJmp_emitter(const ir_node *irn, ia32_emit_env_t *env) {
904 #define IA32_IS_IMMOP (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn))
907 const char *op1 = arch_register_get_name(get_in_reg(irn, 0));
908 const char *op2 = IA32_IS_IMMOP ? get_ia32_cnst(irn) : NULL;
909 char cmd_buf[SNPRINTF_BUF_LEN];
910 char cmnt_buf[SNPRINTF_BUF_LEN];
913 op2 = arch_register_get_name(get_in_reg(irn, 1));
915 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "test %%%s,%s%s ", op1, IA32_IS_IMMOP ? " " : " %", op2);
916 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
919 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
925 * Emits code for conditional test and jump with two variables.
927 static void emit_ia32_TestJmp(const ir_node *irn, ia32_emit_env_t *env) {
928 TestJmp_emitter(irn, env);
931 static void emit_ia32_CJmp(const ir_node *irn, ia32_emit_env_t *env) {
933 char cmd_buf[SNPRINTF_BUF_LEN];
934 char cmnt_buf[SNPRINTF_BUF_LEN];
936 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
937 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test */", irn);
939 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
942 static void emit_ia32_CJmpAM(const ir_node *irn, ia32_emit_env_t *env) {
944 char cmd_buf[SNPRINTF_BUF_LEN];
945 char cmnt_buf[SNPRINTF_BUF_LEN];
947 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
948 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F omitted redundant test/cmp */", irn);
950 finish_CondJmp(F, irn, get_ia32_res_mode(irn));
954 * Emits code for conditional SSE floating point jump with two variables.
956 static void emit_ia32_xCondJmp(ir_node *irn, ia32_emit_env_t *env) {
958 char cmd_buf[SNPRINTF_BUF_LEN];
959 char cmnt_buf[SNPRINTF_BUF_LEN];
961 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", irn, ia32_emit_binop(irn, env));
962 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
964 finish_CondJmp(F, irn, mode_F);
969 * Emits code for conditional x87 floating point jump with two variables.
971 static void emit_ia32_x87CondJmp(ir_node *irn, ia32_emit_env_t *env) {
973 char cmd_buf[SNPRINTF_BUF_LEN];
974 char cmnt_buf[SNPRINTF_BUF_LEN];
975 ia32_attr_t *attr = get_ia32_attr(irn);
976 const char *reg = attr->x87[1]->name;
977 const char *instr = "fcom";
980 switch (get_ia32_irn_opcode(irn)) {
981 case iro_ia32_fcomrJmp:
983 case iro_ia32_fcomJmp:
987 case iro_ia32_fcomrpJmp:
989 case iro_ia32_fcompJmp:
992 case iro_ia32_fcomrppJmp:
994 case iro_ia32_fcomppJmp:
1001 set_ia32_pncode(irn, (long)get_inversed_pnc(get_ia32_pncode(irn)));
1003 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "%s %%%s", instr, reg);
1004 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1006 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "fnstsw %%ax", irn);
1007 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store x87 FPU Control Word */");
1009 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sahf");
1010 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Store ah into flags */");
1013 /* the compare flags must be evaluated using carry , ie unsigned */
1014 finish_CondJmp(F, irn, mode_Iu);
1017 static void CMov_emitter(ir_node *irn, ia32_emit_env_t *env) {
1019 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1020 ir_mode *mode = get_irn_mode(get_irn_n(irn, 0));
1021 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1022 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1023 int is_PsiCondCMov = is_ia32_PsiCondCMov(irn);
1025 char cmd_buf[SNPRINTF_BUF_LEN];
1026 char cmnt_buf[SNPRINTF_BUF_LEN];
1027 const arch_register_t *in1, *in2, *out;
1029 out = arch_get_irn_register(env->arch_env, irn);
1030 in1 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 2 - is_PsiCondCMov));
1031 in2 = arch_get_irn_register(env->arch_env, get_irn_n(irn, 3 - is_PsiCondCMov));
1033 /* we have to emit the cmp first, because the destination register */
1034 /* could be one of the compare registers */
1035 if (is_ia32_CmpCMov(irn)) {
1036 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %2S", irn, irn);
1038 else if (is_ia32_xCmpCMov(irn)) {
1039 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %1S, %2S", get_irn_n(irn, 0), irn, irn);
1041 else if (is_PsiCondCMov) {
1042 /* omit compare because flags are already set by And/Or */
1043 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1046 assert(0 && "unsupported CMov");
1048 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* Psi condition */" );
1051 if (REGS_ARE_EQUAL(out, in2)) {
1052 /* best case: default in == out -> do nothing */
1054 else if (REGS_ARE_EQUAL(out, in1)) {
1055 /* true in == out -> need complement compare and exchange true and default in */
1056 ir_node *t = get_irn_n(irn, 2);
1057 set_irn_n(irn, 2, get_irn_n(irn, 3));
1058 set_irn_n(irn, 3, t);
1060 cmp_suffix = get_cmp_suffix(get_inversed_pnc(get_ia32_pncode(irn)), is_unsigned);
1064 /* out is different from in: need copy default -> out */
1065 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %4S", irn, irn);
1066 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* copy default -> out */" );
1070 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmov%s %1D, %3S", cmp_suffix, irn, irn);
1071 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* condition is true case */" );
1075 static void emit_ia32_CmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1076 CMov_emitter(irn, env);
1079 static void emit_ia32_PsiCondCMov(ir_node *irn, ia32_emit_env_t *env) {
1080 CMov_emitter(irn, env);
1083 static void emit_ia32_xCmpCMov(ir_node *irn, ia32_emit_env_t *env) {
1084 CMov_emitter(irn, env);
1087 static void Set_emitter(ir_node *irn, ir_mode *mode, ia32_emit_env_t *env) {
1089 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1090 int is_unsigned = mode_is_float(mode) || ! mode_is_signed(mode);
1091 const char *cmp_suffix = get_cmp_suffix(get_ia32_pncode(irn), is_unsigned);
1092 const char *reg8bit;
1094 char cmd_buf[SNPRINTF_BUF_LEN];
1095 char cmnt_buf[SNPRINTF_BUF_LEN];
1096 const arch_register_t *out;
1098 out = arch_get_irn_register(env->arch_env, irn);
1099 reg8bit = ia32_get_mapped_reg_name(env->isa->regs_8bit, out);
1101 if (is_ia32_CmpSet(irn)) {
1102 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %s", ia32_emit_binop(irn, env));
1104 else if (is_ia32_xCmpSet(irn)) {
1105 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "ucomis%M %s", get_irn_n(irn, 2), ia32_emit_binop(irn, env));
1107 else if (is_ia32_PsiCondSet(irn)) {
1108 /* omit compare because flags are already set by And/Or */
1109 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1112 assert(0 && "unsupported Set");
1114 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* calculate Psi condition */" );
1117 /* use mov to clear target because it doesn't affect the eflags */
1118 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "mov %%%s, 0", arch_register_get_name(out));
1119 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* clear target as set modifies only lower 8 bit */");
1122 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "set%s %%%s", cmp_suffix, reg8bit);
1123 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* set 1 iff true, 0 otherweise */" );
1127 static void emit_ia32_CmpSet(ir_node *irn, ia32_emit_env_t *env) {
1128 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1131 static void emit_ia32_PsiCondSet(ir_node *irn, ia32_emit_env_t *env) {
1132 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 0)), env);
1135 static void emit_ia32_xCmpSet(ir_node *irn, ia32_emit_env_t *env) {
1136 Set_emitter(irn, get_irn_mode(get_irn_n(irn, 2)), env);
1139 static void emit_ia32_xCmp(ir_node *irn, ia32_emit_env_t *env) {
1141 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1143 long pnc = get_ia32_pncode(irn);
1144 long unord = pnc & pn_Cmp_Uo;
1145 char cmd_buf[SNPRINTF_BUF_LEN];
1146 char cmnt_buf[SNPRINTF_BUF_LEN];
1149 case pn_Cmp_Leg: /* odered */
1152 case pn_Cmp_Uo: /* unordered */
1156 case pn_Cmp_Eq: /* == */
1160 case pn_Cmp_Lt: /* < */
1164 case pn_Cmp_Le: /* <= */
1168 case pn_Cmp_Gt: /* > */
1172 case pn_Cmp_Ge: /* >= */
1176 case pn_Cmp_Lg: /* != */
1181 assert(sse_pnc >= 0 && "unsupported compare");
1183 if (unord && sse_pnc != 3) {
1185 We need a separate compare against unordered.
1186 Quick and Dirty solution:
1187 - get some memory on stack
1191 - and result and stored result
1194 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "sub %%esp, 8");
1195 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve some space for unordered compare result */");
1197 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, 3", ia32_emit_binop(irn, env));
1198 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare: unordered */");
1200 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "movsd [%%esp], %1D", irn);
1201 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* store compare result */");
1205 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cmpsd %s, %d", ia32_emit_binop(irn, env), sse_pnc);
1206 lc_esnprintf(arg_env, cmnt_buf, SNPRINTF_BUF_LEN, "/* SSE compare (%+F) with result in %1D */", irn, irn);
1209 if (unord && sse_pnc != 3) {
1210 lc_esnprintf(arg_env, cmd_buf, SNPRINTF_BUF_LEN, "andpd %1D, [%%esp]", irn);
1211 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* build the final result */");
1213 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "add %%esp, 8");
1214 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* free allocated space */");
1219 /*********************************************************
1222 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1223 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1224 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1225 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1228 *********************************************************/
1230 /* jump table entry (target and corresponding number) */
1231 typedef struct _branch_t {
1236 /* jump table for switch generation */
1237 typedef struct _jmp_tbl_t {
1238 ir_node *defProj; /**< default target */
1239 int min_value; /**< smallest switch case */
1240 int max_value; /**< largest switch case */
1241 int num_branches; /**< number of jumps */
1242 char *label; /**< label of the jump table */
1243 branch_t *branches; /**< jump array */
1247 * Compare two variables of type branch_t. Used to sort all switch cases
1249 static int ia32_cmp_branch_t(const void *a, const void *b) {
1250 branch_t *b1 = (branch_t *)a;
1251 branch_t *b2 = (branch_t *)b;
1253 if (b1->value <= b2->value)
1260 * Emits code for a SwitchJmp (creates a jump table if
1261 * possible otherwise a cmp-jmp cascade). Port from
1264 static void emit_ia32_SwitchJmp(const ir_node *irn, ia32_emit_env_t *emit_env) {
1265 unsigned long interval;
1266 char buf[SNPRINTF_BUF_LEN];
1267 int last_value, i, pn;
1270 const ir_edge_t *edge;
1271 const lc_arg_env_t *env = ia32_get_arg_env();
1272 FILE *F = emit_env->out;
1273 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1275 /* fill the table structure */
1276 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1277 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1279 tbl.num_branches = get_irn_n_edges(irn);
1280 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1281 tbl.min_value = INT_MAX;
1282 tbl.max_value = INT_MIN;
1285 /* go over all proj's and collect them */
1286 foreach_out_edge(irn, edge) {
1287 proj = get_edge_src_irn(edge);
1288 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1290 pn = get_Proj_proj(proj);
1292 /* create branch entry */
1293 tbl.branches[i].target = proj;
1294 tbl.branches[i].value = pn;
1296 tbl.min_value = pn < tbl.min_value ? pn : tbl.min_value;
1297 tbl.max_value = pn > tbl.max_value ? pn : tbl.max_value;
1299 /* check for default proj */
1300 if (pn == get_ia32_pncode(irn)) {
1301 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1308 /* sort the branches by their number */
1309 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1311 /* two-complement's magic make this work without overflow */
1312 interval = tbl.max_value - tbl.min_value;
1314 /* emit the table */
1315 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "cmp %1S, %u", irn, interval);
1316 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* compare for switch */");
1319 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "ja %s", get_cfop_target(tbl.defProj, buf));
1320 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default jump if out of range */");
1323 if (tbl.num_branches > 1) {
1326 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "jmp %s[%1S*4]", tbl.label, irn);
1327 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* get jump table entry as target */");
1330 ia32_switch_section(F, SECTION_RODATA);
1331 fprintf(F, "\t.align 4\n");
1333 fprintf(F, "%s:\n", tbl.label);
1335 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[0].target, buf));
1336 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", tbl.branches[0].value);
1339 last_value = tbl.branches[0].value;
1340 for (i = 1; i < tbl.num_branches; ++i) {
1341 while (++last_value < tbl.branches[i].value) {
1342 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.defProj, buf));
1343 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* default case */");
1346 snprintf(cmd_buf, SNPRINTF_BUF_LEN, ".long %s", get_cfop_target(tbl.branches[i].target, buf));
1347 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* case %d */", last_value);
1350 ia32_switch_section(F, SECTION_TEXT);
1353 /* one jump is enough */
1354 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(tbl.branches[0].target, buf));
1355 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* only one case given */");
1366 * Emits code for a unconditional jump.
1368 static void emit_Jmp(const ir_node *irn, ia32_emit_env_t *env) {
1369 ir_node *block, *next_bl;
1371 char buf[SNPRINTF_BUF_LEN], cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1373 /* for now, the code works for scheduled and non-schedules blocks */
1374 block = get_nodes_block(irn);
1376 /* we have a block schedule */
1377 next_bl = next_blk_sched(block);
1378 if (get_cfop_target_block(irn) != next_bl) {
1379 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "jmp %s", get_cfop_target(irn, buf));
1380 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F) */", irn, get_cfop_target_block(irn));
1384 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* fallthrough %s */", get_cfop_target(irn, buf));
1389 /****************************
1392 * _ __ _ __ ___ _ ___
1393 * | '_ \| '__/ _ \| |/ __|
1394 * | |_) | | | (_) | |\__ \
1395 * | .__/|_| \___/| ||___/
1398 ****************************/
1401 * Emits code for a proj -> node
1403 static void emit_Proj(const ir_node *irn, ia32_emit_env_t *env) {
1404 ir_node *pred = get_Proj_pred(irn);
1406 if (get_irn_op(pred) == op_Start) {
1407 switch(get_Proj_proj(irn)) {
1408 case pn_Start_X_initial_exec:
1417 /**********************************
1420 * | | ___ _ __ _ _| |_) |
1421 * | | / _ \| '_ \| | | | _ <
1422 * | |___| (_) | |_) | |_| | |_) |
1423 * \_____\___/| .__/ \__, |____/
1426 **********************************/
1429 * Emit movsb/w instructions to make mov count divideable by 4
1431 static void emit_CopyB_prolog(FILE *F, const ir_node *irn, int rem) {
1432 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1434 ir_fprintf(F, "\t/* memcopy prolog %+F */\n", irn);
1436 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cld");
1437 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* copy direction forward */");
1442 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1443 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 1 */");
1447 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1448 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 2 */");
1452 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsb");
1453 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1455 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsw");
1456 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy remainder 3 */");
1464 * Emit rep movsd instruction for memcopy.
1466 static void emit_ia32_CopyB(const ir_node *irn, ia32_emit_env_t *emit_env) {
1467 FILE *F = emit_env->out;
1468 tarval *tv = get_ia32_Immop_tarval(irn);
1469 int rem = get_tarval_long(tv);
1470 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1472 emit_CopyB_prolog(F, irn, rem);
1474 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "rep movsd");
1475 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy */");
1480 * Emits unrolled memcopy.
1482 static void emit_ia32_CopyB_i(const ir_node *irn, ia32_emit_env_t *emit_env) {
1483 tarval *tv = get_ia32_Immop_tarval(irn);
1484 int size = get_tarval_long(tv);
1485 FILE *F = emit_env->out;
1486 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1488 emit_CopyB_prolog(F, irn, size & 0x3);
1492 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "movsd");
1493 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* memcopy unrolled */");
1500 /***************************
1504 * | | / _ \| '_ \ \ / /
1505 * | |___| (_) | | | \ V /
1506 * \_____\___/|_| |_|\_/
1508 ***************************/
1511 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1513 static void emit_ia32_Conv_with_FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1514 FILE *F = emit_env->out;
1515 const lc_arg_env_t *env = ia32_get_arg_env();
1516 ir_mode *src_mode = get_ia32_src_mode(irn);
1517 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1518 char *from, *to, buf[64];
1519 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1521 from = mode_is_float(src_mode) ? (get_mode_size_bits(src_mode) == 32 ? "ss" : "sd") : "si";
1522 to = mode_is_float(tgt_mode) ? (get_mode_size_bits(tgt_mode) == 32 ? "ss" : "sd") : "si";
1524 switch(get_ia32_op_type(irn)) {
1526 lc_esnprintf(env, buf, sizeof(buf), "%1D, %3S", irn, irn);
1528 case ia32_AddrModeS:
1529 lc_esnprintf(env, buf, sizeof(buf), "%1D, %s", irn, ia32_emit_am(irn, emit_env));
1532 assert(0 && "unsupported op type for Conv");
1535 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "cvt%s2%s %s", from, to, buf);
1536 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%+F, %+F) */", irn, src_mode, tgt_mode);
1540 static void emit_ia32_Conv_I2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1541 emit_ia32_Conv_with_FP(irn, emit_env);
1544 static void emit_ia32_Conv_FP2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1545 emit_ia32_Conv_with_FP(irn, emit_env);
1548 static void emit_ia32_Conv_FP2FP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1549 emit_ia32_Conv_with_FP(irn, emit_env);
1553 * Emits code for an Int conversion.
1555 static void emit_ia32_Conv_I2I(const ir_node *irn, ia32_emit_env_t *emit_env) {
1556 FILE *F = emit_env->out;
1557 const lc_arg_env_t *env = ia32_get_arg_env();
1558 char *move_cmd = "movzx";
1559 char *conv_cmd = NULL;
1560 ir_mode *src_mode = get_ia32_src_mode(irn);
1561 ir_mode *tgt_mode = get_ia32_tgt_mode(irn);
1563 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1564 const arch_register_t *in_reg, *out_reg;
1566 n = get_mode_size_bits(src_mode);
1567 m = get_mode_size_bits(tgt_mode);
1569 if (mode_is_signed(n < m ? src_mode : tgt_mode)) {
1571 if (n == 8 || m == 8)
1573 else if (n == 16 || m == 16)
1576 assert(0 && "unsupported Conv_I2I");
1579 switch(get_ia32_op_type(irn)) {
1581 in_reg = get_in_reg(irn, 2);
1582 out_reg = get_out_reg(irn, 0);
1584 if (REGS_ARE_EQUAL(in_reg, &ia32_gp_regs[REG_EAX]) &&
1585 REGS_ARE_EQUAL(out_reg, in_reg) &&
1586 mode_is_signed(n < m ? src_mode : tgt_mode))
1588 /* argument and result are both in EAX and */
1589 /* signedness is ok: -> use converts */
1590 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s", conv_cmd);
1592 else if (REGS_ARE_EQUAL(out_reg, in_reg) &&
1593 ! mode_is_signed(n < m ? src_mode : tgt_mode))
1595 /* argument and result are in the same register */
1596 /* and signedness is ok: -> use and with mask */
1597 int mask = (1 << (n < m ? n : m)) - 1;
1598 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "and %1D, 0x%x", irn, mask);
1601 /* use move w/o sign extension */
1602 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %%%s",
1603 move_cmd, irn, ia32_get_reg_name_for_mode(emit_env, n < m ? src_mode : tgt_mode, in_reg));
1607 case ia32_AddrModeS:
1608 lc_esnprintf(env, cmd_buf, SNPRINTF_BUF_LEN, "%s %1D, %s",
1609 move_cmd, irn, ia32_emit_am(irn, emit_env));
1612 assert(0 && "unsupported op type for Conv");
1615 lc_esnprintf(env, cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%d Bit mode_%F -> %d Bit mode_%F) */",
1616 irn, n, src_mode, m, tgt_mode);
1622 * Emits code for an 8Bit Int conversion.
1624 void emit_ia32_Conv_I2I8Bit(const ir_node *irn, ia32_emit_env_t *emit_env) {
1625 emit_ia32_Conv_I2I(irn, emit_env);
1629 /*******************************************
1632 * | |__ ___ _ __ ___ __| | ___ ___
1633 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1634 * | |_) | __/ | | | (_) | (_| | __/\__ \
1635 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1637 *******************************************/
1640 * Emits a backend call
1642 static void emit_be_Call(const ir_node *irn, ia32_emit_env_t *emit_env) {
1643 FILE *F = emit_env->out;
1644 entity *ent = be_Call_get_entity(irn);
1645 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1648 snprintf(cmd_buf, SNPRINTF_BUF_LEN, "call %s", get_entity_ld_name(ent));
1651 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "call %1D", get_irn_n(irn, be_pos_Call_ptr));
1654 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (be_Call) */", irn);
1660 * Emits code to increase stack pointer.
1662 static void emit_be_IncSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1663 FILE *F = emit_env->out;
1664 int offs = be_get_IncSP_offset(irn);
1665 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1669 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1S, %u", irn, offs);
1671 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "add %1S, %u", irn, -offs);
1672 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (IncSP) */", irn);
1675 snprintf(cmd_buf, SNPRINTF_BUF_LEN, " ");
1676 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* omitted %+F (IncSP) with 0 */", irn);
1683 * Emits code to set stack pointer.
1685 static void emit_be_SetSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1686 FILE *F = emit_env->out;
1687 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1689 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %3S", irn, irn);
1690 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F (restore SP) */", irn);
1695 * Emits code for Copy/CopyKeep.
1697 static void Copy_emitter(const ir_node *irn, ir_node *op, ia32_emit_env_t *emit_env) {
1698 FILE *F = emit_env->out;
1699 const arch_env_t *aenv = emit_env->arch_env;
1700 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1702 if (REGS_ARE_EQUAL(arch_get_irn_register(aenv, irn), arch_get_irn_register(aenv, op)) ||
1703 be_is_unknown_reg(arch_get_irn_register(aenv, op)))
1706 if (mode_is_float(get_irn_mode(irn)))
1707 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "movs%M %1D, %1S", irn, irn, irn);
1709 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "mov %1D, %1S", irn, irn);
1710 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F */", irn);
1714 static void emit_be_Copy(const ir_node *irn, ia32_emit_env_t *emit_env) {
1715 Copy_emitter(irn, be_get_Copy_op(irn), emit_env);
1718 static void emit_be_CopyKeep(const ir_node *irn, ia32_emit_env_t *emit_env) {
1719 Copy_emitter(irn, be_get_CopyKeep_op(irn), emit_env);
1723 * Emits code for exchange.
1725 static void emit_be_Perm(const ir_node *irn, ia32_emit_env_t *emit_env) {
1726 FILE *F = emit_env->out;
1727 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1728 const arch_register_t *in1, *in2;
1729 const arch_register_class_t *cls1, *cls2;
1731 in1 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 0));
1732 in2 = arch_get_irn_register(emit_env->arch_env, get_irn_n(irn, 1));
1734 cls1 = arch_register_get_class(in1);
1735 cls2 = arch_register_get_class(in2);
1737 assert(cls1 == cls2 && "Register class mismatch at Perm");
1739 if (cls1 == &ia32_reg_classes[CLASS_ia32_gp]) {
1740 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "xchg %1S, %2S", irn, irn);
1742 else if (cls1 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1743 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN,
1744 "pxor %1S, %2S\n\tpxor %2S, %1S\n\tpxor %1S, %2S", irn, irn, irn, irn, irn, irn);
1746 else if (cls1 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1750 else if (cls1 == &ia32_reg_classes[CLASS_ia32_st]) {
1755 lc_esnprintf(ia32_get_arg_env(), cmnt_buf, SNPRINTF_BUF_LEN, "/* %+F(%1A, %2A) */", irn, irn, irn);
1760 * Emits code for Constant loading.
1762 static void emit_ia32_Const(const ir_node *n, ia32_emit_env_t *env) {
1764 char cmd_buf[256], cmnt_buf[256];
1765 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1767 if (get_ia32_Immop_tarval(n) == get_tarval_null(get_irn_mode(n))) {
1768 const char *instr = "xor";
1769 if (env->isa->opt_arch == arch_pentium_4) {
1770 /* P4 prefers sub r, r, others xor r, r */
1773 lc_esnprintf(arg_env, cmd_buf, 256, "%s %1D, %1D ", instr, n, n);
1774 lc_esnprintf(arg_env, cmnt_buf, 256, "/* optimized mov 0 to register */");
1777 if (get_ia32_op_type(n) == ia32_SymConst) {
1778 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, OFFSET FLAT:%C ", n, n);
1779 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Move address of SymConst into register */");
1782 lc_esnprintf(arg_env, cmd_buf, 256, "mov %1D, %C ", n, n);
1783 lc_esnprintf(arg_env, cmnt_buf, 256, "/* Mov Const into register */");
1786 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", cmd_buf, cmnt_buf, n, n);
1790 * Emits code to increase stack pointer.
1792 static void emit_ia32_AddSP(const ir_node *irn, ia32_emit_env_t *emit_env) {
1793 FILE *F = emit_env->out;
1794 char cmd_buf[SNPRINTF_BUF_LEN], cmnt_buf[SNPRINTF_BUF_LEN];
1796 if (is_ia32_ImmConst(irn)) {
1797 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %C", irn, irn);
1799 else if (is_ia32_ImmSymConst(irn)) {
1800 if (get_ia32_op_type(irn) == ia32_Normal)
1801 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, OFFSET_FLAT:%C", irn, irn);
1802 else /* source address mode */
1803 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, [%s%s]", irn, get_id_str(get_ia32_am_sc(irn)), get_ia32_am_offs(irn));
1806 lc_esnprintf(ia32_get_arg_env(), cmd_buf, SNPRINTF_BUF_LEN, "sub %1D, %2S", irn, irn);
1808 snprintf(cmnt_buf, SNPRINTF_BUF_LEN, "/* reserve space on stack */");
1813 static void emit_be_Return(const ir_node *n, ia32_emit_env_t *env) {
1815 const lc_arg_env_t *arg_env = ia32_get_arg_env();
1817 lc_efprintf(arg_env, F, "\t%-35s %-60s /* %+F (%+G) */\n", "ret", "/* be_Return */", n, n);
1820 static void emit_Nothing(const ir_node *n, ia32_emit_env_t *env) {
1823 ir_fprintf(F, "\t%35s /* %+F (%+G) */\n", " ", n, n);
1827 /***********************************************************************************
1830 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1831 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1832 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1833 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1835 ***********************************************************************************/
1838 * Enters the emitter functions for handled nodes into the generic
1839 * pointer of an opcode.
1841 static void ia32_register_emitters(void) {
1843 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1844 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1845 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1846 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1847 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1848 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1850 /* first clear the generic function pointer for all ops */
1851 clear_irp_opcodes_generic_func();
1853 /* register all emitter functions defined in spec */
1854 ia32_register_spec_emitters();
1856 /* other ia32 emitter functions */
1862 IA32_EMIT(PsiCondCMov);
1864 IA32_EMIT(PsiCondSet);
1865 IA32_EMIT(SwitchJmp);
1868 IA32_EMIT(Conv_I2FP);
1869 IA32_EMIT(Conv_FP2I);
1870 IA32_EMIT(Conv_FP2FP);
1871 IA32_EMIT(Conv_I2I);
1872 IA32_EMIT(Conv_I2I8Bit);
1877 IA32_EMIT(xCmpCMov);
1878 IA32_EMIT(xCondJmp);
1879 IA32_EMIT2(fcomJmp, x87CondJmp);
1880 IA32_EMIT2(fcompJmp, x87CondJmp);
1881 IA32_EMIT2(fcomppJmp, x87CondJmp);
1882 IA32_EMIT2(fcomrJmp, x87CondJmp);
1883 IA32_EMIT2(fcomrpJmp, x87CondJmp);
1884 IA32_EMIT2(fcomrppJmp, x87CondJmp);
1886 /* benode emitter */
1913 * Emits code for a node.
1915 static void ia32_emit_node(const ir_node *irn, void *env) {
1916 ia32_emit_env_t *emit_env = env;
1917 ir_op *op = get_irn_op(irn);
1918 DEBUG_ONLY(firm_dbg_module_t *mod = emit_env->mod;)
1920 DBG((mod, LEVEL_1, "emitting code for %+F\n", irn));
1922 if (op->ops.generic) {
1923 void (*emit)(const ir_node *, void *) = (void (*)(const ir_node *, void *))op->ops.generic;
1927 emit_Nothing(irn, env);
1928 ir_fprintf(stderr, "Warning: No emit handler for node %+F (%+G)\n", irn, irn);
1933 * Emits gas alignment directives
1935 static void ia32_emit_alignment(FILE *F, unsigned align, unsigned skip) {
1936 fprintf(F, "\t.p2align %u,,%u\n", align, skip);
1940 * Emits gas alignment directives for Functions depended on cpu architecture.
1942 static void ia32_emit_align_func(FILE *F, cpu_support cpu) {
1943 unsigned align; unsigned maximum_skip;
1945 /* gcc doesn't emit alignment for p4 ?*/
1946 if (cpu == arch_pentium_4)
1951 align = 2; maximum_skip = 3;
1954 align = 4; maximum_skip = 15;
1957 align = 5; maximum_skip = 31;
1960 align = 4; maximum_skip = 15;
1962 ia32_emit_alignment(F, align, maximum_skip);
1966 * Emits gas alignment directives for Labels depended on cpu architecture.
1968 static void ia32_emit_align_label(FILE *F, cpu_support cpu) {
1969 unsigned align; unsigned maximum_skip;
1971 /* gcc doesn't emit alignment for p4 ?*/
1972 if (cpu == arch_pentium_4)
1977 align = 2; maximum_skip = 3;
1980 align = 4; maximum_skip = 15;
1983 align = 5; maximum_skip = 7;
1986 align = 4; maximum_skip = 7;
1988 ia32_emit_alignment(F, align, maximum_skip);
1992 * Walks over the nodes in a block connected by scheduling edges
1993 * and emits code for each node.
1995 static void ia32_gen_block(ir_node *block, void *env) {
1996 ia32_emit_env_t *emit_env = env;
1998 int need_label = block != get_irg_start_block(get_irn_irg(block));
1999 FILE *F = emit_env->out;
2001 if (! is_Block(block))
2004 if (need_label && (emit_env->cg->opt & IA32_OPT_EXTBB)) {
2005 /* if the extended block scheduler is used, only leader blocks need
2007 need_label = (block == get_extbb_leader(get_nodes_extbb(block)));
2011 char cmd_buf[SNPRINTF_BUF_LEN];
2014 ia32_emit_align_label(emit_env->out, emit_env->isa->opt_arch);
2016 ir_snprintf(cmd_buf, sizeof(cmd_buf), BLOCK_PREFIX("%d:"),
2017 get_irn_node_nr(block));
2018 fprintf(F, "%-43s ", cmd_buf);
2020 /* emit list of pred blocks in comment */
2021 fprintf(F, "/* preds:");
2023 arity = get_irn_arity(block);
2024 for(i = 0; i < arity; ++i) {
2025 ir_node *predblock = get_Block_cfgpred_block(block, i);
2026 fprintf(F, " %ld", get_irn_node_nr(predblock));
2028 fprintf(F, " */\n");
2031 /* emit the contents of the block */
2032 sched_foreach(block, irn) {
2033 ia32_emit_node(irn, env);
2038 * Emits code for function start.
2040 static void ia32_emit_func_prolog(FILE *F, ir_graph *irg, cpu_support cpu) {
2041 entity *irg_ent = get_irg_entity(irg);
2042 const char *irg_name = get_entity_ld_name(irg_ent);
2045 ia32_switch_section(F, SECTION_TEXT);
2046 ia32_emit_align_func(F, cpu);
2047 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2048 fprintf(F, ".globl %s\n", irg_name);
2050 ia32_dump_function_object(F, irg_name);
2051 fprintf(F, "%s:\n", irg_name);
2055 * Emits code for function end
2057 static void ia32_emit_func_epilog(FILE *F, ir_graph *irg) {
2058 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2060 ia32_dump_function_size(F, irg_name);
2066 * Sets labels for control flow nodes (jump target)
2067 * TODO: Jump optimization
2069 static void ia32_gen_labels(ir_node *block, void *env) {
2071 int n = get_Block_n_cfgpreds(block);
2073 for (n--; n >= 0; n--) {
2074 pred = get_Block_cfgpred(block, n);
2075 set_irn_link(pred, block);
2080 * Main driver. Emits the code for one routine.
2082 void ia32_gen_routine(FILE *F, ir_graph *irg, const ia32_code_gen_t *cg) {
2083 ia32_emit_env_t emit_env;
2087 emit_env.arch_env = cg->arch_env;
2089 emit_env.isa = (ia32_isa_t *)cg->arch_env->isa;
2090 FIRM_DBG_REGISTER(emit_env.mod, "firm.be.ia32.emitter");
2092 /* set the global arch_env (needed by print hooks) */
2093 arch_env = cg->arch_env;
2095 ia32_register_emitters();
2097 ia32_emit_func_prolog(F, irg, emit_env.isa->opt_arch);
2098 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &emit_env);
2100 if ((cg->opt & IA32_OPT_EXTBB) && cg->blk_sched) {
2101 int i, n = ARR_LEN(cg->blk_sched);
2103 for (i = 0; i < n;) {
2106 block = cg->blk_sched[i];
2108 next_bl = i < n ? cg->blk_sched[i] : NULL;
2110 /* set here the link. the emitter expects to find the next block here */
2111 set_irn_link(block, next_bl);
2112 ia32_gen_block(block, &emit_env);
2116 /* "normal" block schedule: Note the get_next_block() returns the NUMBER of the block
2117 in the block schedule. As this number should NEVER be equal the next block,
2118 we does not need a clear block link here. */
2119 irg_walk_blkwise_graph(irg, NULL, ia32_gen_block, &emit_env);
2122 ia32_emit_func_epilog(F, irg);