2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
46 #include "../besched_t.h"
47 #include "../benode_t.h"
49 #include "../be_dbgout.h"
50 #include "../beemitter.h"
51 #include "../begnuas.h"
52 #include "../beirg_t.h"
54 #include "ia32_emitter.h"
55 #include "gen_ia32_emitter.h"
56 #include "gen_ia32_regalloc_if.h"
57 #include "ia32_nodes_attr.h"
58 #include "ia32_new_nodes.h"
59 #include "ia32_map_regs.h"
60 #include "bearch_ia32_t.h"
62 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
64 #define BLOCK_PREFIX ".L"
66 #define SNPRINTF_BUF_LEN 128
68 static const arch_env_t *arch_env;
69 static const ia32_isa_t *isa;
70 static ia32_code_gen_t *cg;
73 * Returns the register at in position pos.
75 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
78 const arch_register_t *reg = NULL;
80 assert(get_irn_arity(irn) > pos && "Invalid IN position");
82 /* The out register of the operator at position pos is the
83 in register we need. */
84 op = get_irn_n(irn, pos);
86 reg = arch_get_irn_register(arch_env, op);
88 assert(reg && "no in register found");
90 if(reg == &ia32_gp_regs[REG_GP_NOREG])
91 panic("trying to emit noreg for %+F input %d", irn, pos);
93 /* in case of unknown register: just return a valid register */
94 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
95 const arch_register_req_t *req;
97 /* ask for the requirements */
98 req = arch_get_register_req(arch_env, irn, pos);
100 if (arch_register_req_is(req, limited)) {
101 /* in case of limited requirements: get the first allowed register */
102 unsigned idx = rbitset_next(req->limited, 0, 1);
103 reg = arch_register_for_index(req->cls, idx);
105 /* otherwise get first register in class */
106 reg = arch_register_for_index(req->cls, 0);
114 * Returns the register at out position pos.
116 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
119 const arch_register_t *reg = NULL;
121 /* 1st case: irn is not of mode_T, so it has only */
122 /* one OUT register -> good */
123 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
124 /* Proj with the corresponding projnum for the register */
126 if (get_irn_mode(irn) != mode_T) {
128 reg = arch_get_irn_register(arch_env, irn);
129 } else if (is_ia32_irn(irn)) {
130 reg = get_ia32_out_reg(irn, pos);
132 const ir_edge_t *edge;
134 foreach_out_edge(irn, edge) {
135 proj = get_edge_src_irn(edge);
136 assert(is_Proj(proj) && "non-Proj from mode_T node");
137 if (get_Proj_proj(proj) == pos) {
138 reg = arch_get_irn_register(arch_env, proj);
144 assert(reg && "no out register found");
149 * Add a number to a prefix. This number will not be used a second time.
151 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
153 static unsigned long id = 0;
154 snprintf(buf, buflen, "%s%lu", prefix, ++id);
158 /*************************************************************
160 * (_) | | / _| | | | |
161 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
162 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
163 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
164 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
167 *************************************************************/
169 static void emit_8bit_register(const arch_register_t *reg)
171 const char *reg_name = arch_register_get_name(reg);
174 be_emit_char(reg_name[1]);
178 static void emit_16bit_register(const arch_register_t *reg)
180 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
183 be_emit_string(reg_name);
186 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
188 const char *reg_name;
191 int size = get_mode_size_bits(mode);
193 emit_8bit_register(reg);
195 } else if(size == 16) {
196 emit_16bit_register(reg);
203 reg_name = arch_register_get_name(reg);
206 be_emit_string(reg_name);
209 void ia32_emit_source_register(const ir_node *node, int pos)
211 const arch_register_t *reg = get_in_reg(node, pos);
213 emit_register(reg, NULL);
216 static void emit_ia32_Immediate(const ir_node *node);
218 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
220 const arch_register_t *reg;
221 ir_node *in = get_irn_n(node, pos);
222 if(is_ia32_Immediate(in)) {
223 emit_ia32_Immediate(in);
227 reg = get_in_reg(node, pos);
228 emit_8bit_register(reg);
231 void ia32_emit_dest_register(const ir_node *node, int pos)
233 const arch_register_t *reg = get_out_reg(node, pos);
235 emit_register(reg, NULL);
238 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
240 const arch_register_t *reg = get_out_reg(node, pos);
242 emit_register(reg, mode_Bu);
245 void ia32_emit_x87_register(const ir_node *node, int pos)
247 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
251 be_emit_string(attr->x87[pos]->name);
254 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
256 if(mode_is_float(mode)) {
257 switch(get_mode_size_bits(mode)) {
258 case 32: be_emit_char('s'); return;
259 case 64: be_emit_char('l'); return;
260 case 80: be_emit_char('t'); return;
263 assert(mode_is_int(mode) || mode_is_reference(mode));
264 switch(get_mode_size_bits(mode)) {
265 case 64: be_emit_cstring("ll"); return;
266 /* gas docu says q is the suffix but gcc, objdump and icc use
268 case 32: be_emit_char('l'); return;
269 case 16: be_emit_char('w'); return;
270 case 8: be_emit_char('b'); return;
273 panic("Can't output mode_suffix for %+F\n", mode);
276 void ia32_emit_mode_suffix(const ir_node *node)
278 ir_mode *mode = get_ia32_ls_mode(node);
282 ia32_emit_mode_suffix_mode(mode);
285 void ia32_emit_x87_mode_suffix(const ir_node *node)
287 ir_mode *mode = get_ia32_ls_mode(node);
289 ia32_emit_mode_suffix_mode(mode);
293 char get_xmm_mode_suffix(ir_mode *mode)
295 assert(mode_is_float(mode));
296 switch(get_mode_size_bits(mode)) {
307 void ia32_emit_xmm_mode_suffix(const ir_node *node)
309 ir_mode *mode = get_ia32_ls_mode(node);
310 assert(mode != NULL);
312 be_emit_char(get_xmm_mode_suffix(mode));
315 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
317 ir_mode *mode = get_ia32_ls_mode(node);
318 assert(mode != NULL);
319 be_emit_char(get_xmm_mode_suffix(mode));
322 void ia32_emit_extend_suffix(const ir_mode *mode)
324 if(get_mode_size_bits(mode) == 32)
326 if(mode_is_signed(mode)) {
334 void ia32_emit_function_object(const char *name)
336 switch (be_gas_flavour) {
337 case GAS_FLAVOUR_NORMAL:
338 be_emit_cstring("\t.type\t");
339 be_emit_string(name);
340 be_emit_cstring(", @function\n");
341 be_emit_write_line();
343 case GAS_FLAVOUR_MINGW:
344 be_emit_cstring("\t.def\t");
345 be_emit_string(name);
346 be_emit_cstring(";\t.scl\t2;\t.type\t32;\t.endef\n");
347 be_emit_write_line();
355 void ia32_emit_function_size(const char *name)
357 switch (be_gas_flavour) {
358 case GAS_FLAVOUR_NORMAL:
359 be_emit_cstring("\t.size\t");
360 be_emit_string(name);
361 be_emit_cstring(", .-");
362 be_emit_string(name);
364 be_emit_write_line();
372 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
374 ir_node *in = get_irn_n(node, pos);
375 if(is_ia32_Immediate(in)) {
376 emit_ia32_Immediate(in);
378 const ir_mode *mode = get_ia32_ls_mode(node);
379 const arch_register_t *reg = get_in_reg(node, pos);
380 emit_register(reg, mode);
385 * Emits registers and/or address mode of a binary operation.
387 void ia32_emit_binop(const ir_node *node) {
388 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
389 const ir_mode *mode = get_ia32_ls_mode(node);
390 const arch_register_t *reg_left;
392 switch(get_ia32_op_type(node)) {
394 reg_left = get_in_reg(node, n_ia32_binary_left);
395 if(is_ia32_Immediate(right_op)) {
396 emit_ia32_Immediate(right_op);
397 be_emit_cstring(", ");
398 emit_register(reg_left, mode);
401 const arch_register_t *reg_right
402 = get_in_reg(node, n_ia32_binary_right);
403 emit_register(reg_right, mode);
404 be_emit_cstring(", ");
405 emit_register(reg_left, mode);
409 if(is_ia32_Immediate(right_op)) {
410 emit_ia32_Immediate(right_op);
411 be_emit_cstring(", ");
414 reg_left = get_in_reg(node, n_ia32_binary_left);
416 be_emit_cstring(", ");
417 emit_register(reg_left, mode);
421 panic("DestMode can't be output by %%binop anymore");
424 assert(0 && "unsupported op type");
429 * Emits registers and/or address mode of a binary operation.
431 void ia32_emit_x87_binop(const ir_node *node) {
432 switch(get_ia32_op_type(node)) {
435 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
436 const arch_register_t *in1 = x87_attr->x87[0];
437 const arch_register_t *in2 = x87_attr->x87[1];
438 const arch_register_t *out = x87_attr->x87[2];
439 const arch_register_t *in;
441 in = out ? ((out == in2) ? in1 : in2) : in2;
442 out = out ? out : in1;
445 be_emit_string(arch_register_get_name(in));
446 be_emit_cstring(", %");
447 be_emit_string(arch_register_get_name(out));
455 assert(0 && "unsupported op type");
459 void ia32_emit_am_or_dest_register(const ir_node *node,
461 if(get_ia32_op_type(node) == ia32_Normal) {
462 ia32_emit_dest_register(node, pos);
464 assert(get_ia32_op_type(node) == ia32_AddrModeD);
470 * Emits registers and/or address mode of a unary operation.
472 void ia32_emit_unop(const ir_node *node, int pos) {
475 switch(get_ia32_op_type(node)) {
477 op = get_irn_n(node, pos);
478 if (is_ia32_Immediate(op)) {
479 emit_ia32_Immediate(op);
481 ia32_emit_source_register(node, pos);
489 assert(0 && "unsupported op type");
494 * Emits address mode.
496 void ia32_emit_am(const ir_node *node) {
497 ir_entity *ent = get_ia32_am_sc(node);
498 int offs = get_ia32_am_offs_int(node);
499 ir_node *base = get_irn_n(node, 0);
500 int has_base = !is_ia32_NoReg_GP(base);
501 ir_node *index = get_irn_n(node, 1);
502 int has_index = !is_ia32_NoReg_GP(index);
504 /* just to be sure... */
505 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
511 set_entity_backend_marked(ent, 1);
512 id = get_entity_ld_ident(ent);
513 if (is_ia32_am_sc_sign(node))
517 if(get_entity_owner(ent) == get_tls_type()) {
518 if (get_entity_visibility(ent) == visibility_external_allocated) {
519 be_emit_cstring("@INDNTPOFF");
521 be_emit_cstring("@NTPOFF");
528 be_emit_irprintf("%+d", offs);
530 be_emit_irprintf("%d", offs);
534 if (has_base || has_index) {
539 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
540 emit_register(reg, NULL);
543 /* emit index + scale */
545 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
548 emit_register(reg, NULL);
550 scale = get_ia32_am_scale(node);
552 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
558 /* special case if nothing is set */
559 if(ent == NULL && offs == 0 && !has_base && !has_index) {
564 /*************************************************
567 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
568 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
569 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
570 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
572 *************************************************/
575 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
578 * coding of conditions
580 struct cmp2conditon_t {
586 * positive conditions for signed compares
588 static const struct cmp2conditon_t cmp2condition_s[] = {
589 { NULL, pn_Cmp_False }, /* always false */
590 { "e", pn_Cmp_Eq }, /* == */
591 { "l", pn_Cmp_Lt }, /* < */
592 { "le", pn_Cmp_Le }, /* <= */
593 { "g", pn_Cmp_Gt }, /* > */
594 { "ge", pn_Cmp_Ge }, /* >= */
595 { "ne", pn_Cmp_Lg }, /* != */
596 { NULL, pn_Cmp_Leg}, /* always true */
600 * positive conditions for unsigned compares
602 static const struct cmp2conditon_t cmp2condition_u[] = {
603 { NULL, pn_Cmp_False }, /* always false */
604 { "e", pn_Cmp_Eq }, /* == */
605 { "b", pn_Cmp_Lt }, /* < */
606 { "be", pn_Cmp_Le }, /* <= */
607 { "a", pn_Cmp_Gt }, /* > */
608 { "ae", pn_Cmp_Ge }, /* >= */
609 { "ne", pn_Cmp_Lg }, /* != */
610 { NULL, pn_Cmp_Leg }, /* always true */
614 ia32_pn_Cmp_unsigned = 0x1000,
615 ia32_pn_Cmp_float = 0x2000,
619 * walks up a tree of copies/perms/spills/reloads to find the original value
620 * that is moved around
622 static ir_node *find_original_value(ir_node *node)
624 inc_irg_visited(current_ir_graph);
626 mark_irn_visited(node);
627 if(be_is_Copy(node)) {
628 node = be_get_Copy_op(node);
629 } else if(be_is_CopyKeep(node)) {
630 node = be_get_CopyKeep_op(node);
631 } else if(is_Proj(node)) {
632 ir_node *pred = get_Proj_pred(node);
633 if(be_is_Perm(pred)) {
634 node = get_irn_n(pred, get_Proj_proj(node));
635 } else if(be_is_MemPerm(pred)) {
636 node = get_irn_n(pred, get_Proj_proj(node) + 1);
637 } else if(is_ia32_Load(pred)) {
638 node = get_irn_n(pred, n_ia32_Load_mem);
642 } else if(is_ia32_Store(node)) {
643 node = get_irn_n(node, n_ia32_Store_val);
644 } else if(is_Phi(node)) {
646 arity = get_irn_arity(node);
647 for(i = 0; i < arity; ++i) {
648 ir_node *in = get_irn_n(node, i);
661 static int determine_final_pnc(const ir_node *node, int flags_pos,
664 ir_node *flags = get_irn_n(node, flags_pos);
665 const ia32_attr_t *flags_attr;
666 flags = skip_Proj(flags);
668 if(is_ia32_Sahf(flags)) {
669 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
670 if(!is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
671 || is_ia32_FucomppFnstsw(cmp)) {
672 cmp = find_original_value(cmp);
673 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
674 || is_ia32_FucomppFnstsw(cmp));
677 flags_attr = get_ia32_attr_const(cmp);
678 if(flags_attr->data.cmp_flipped)
679 pnc = get_mirrored_pnc(pnc);
680 pnc |= ia32_pn_Cmp_float;
681 } else if(is_ia32_Ucomi(flags)) {
682 flags_attr = get_ia32_attr_const(flags);
684 if(flags_attr->data.cmp_flipped)
685 pnc = get_mirrored_pnc(pnc);
686 pnc |= ia32_pn_Cmp_float;
688 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
689 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
690 flags_attr = get_ia32_attr_const(flags);
692 if(flags_attr->data.cmp_flipped)
693 pnc = get_mirrored_pnc(pnc);
694 if(flags_attr->data.cmp_unsigned)
695 pnc |= ia32_pn_Cmp_unsigned;
701 static void ia32_emit_cmp_suffix(int pnc)
705 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
707 assert(cmp2condition_u[pnc].num == pnc);
708 str = cmp2condition_u[pnc].name;
711 assert(cmp2condition_s[pnc].num == pnc);
712 str = cmp2condition_s[pnc].name;
718 void ia32_emit_cmp_suffix_node(const ir_node *node,
721 pn_Cmp pnc = get_ia32_pncode(node);
723 pnc = determine_final_pnc(node, flags_pos, pnc);
724 ia32_emit_cmp_suffix(pnc);
728 * Returns the target block for a control flow node.
731 ir_node *get_cfop_target_block(const ir_node *irn) {
732 return get_irn_link(irn);
736 * Emits a block label for the given block.
739 void ia32_emit_block_name(const ir_node *block)
741 if (has_Block_label(block)) {
742 be_emit_string(be_gas_label_prefix());
743 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
745 be_emit_cstring(BLOCK_PREFIX);
746 be_emit_irprintf("%d", get_irn_node_nr(block));
751 * Emits the target label for a control flow node.
753 static void ia32_emit_cfop_target(const ir_node *node)
755 ir_node *block = get_cfop_target_block(node);
757 ia32_emit_block_name(block);
760 /** Return the next block in Block schedule */
761 static ir_node *next_blk_sched(const ir_node *block)
763 return get_irn_link(block);
767 * Returns the Proj with projection number proj and NOT mode_M
769 static ir_node *get_proj(const ir_node *node, long proj) {
770 const ir_edge_t *edge;
773 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
775 foreach_out_edge(node, edge) {
776 src = get_edge_src_irn(edge);
778 assert(is_Proj(src) && "Proj expected");
779 if (get_irn_mode(src) == mode_M)
782 if (get_Proj_proj(src) == proj)
789 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
791 static void emit_ia32_Jcc(const ir_node *node)
793 const ir_node *proj_true;
794 const ir_node *proj_false;
795 const ir_node *block;
796 const ir_node *next_block;
797 pn_Cmp pnc = get_ia32_pncode(node);
799 pnc = determine_final_pnc(node, 0, pnc);
802 proj_true = get_proj(node, pn_ia32_Jcc_true);
803 assert(proj_true && "Jcc without true Proj");
805 proj_false = get_proj(node, pn_ia32_Jcc_false);
806 assert(proj_false && "Jcc without false Proj");
808 block = get_nodes_block(node);
809 next_block = next_blk_sched(block);
811 if (get_cfop_target_block(proj_true) == next_block) {
812 /* exchange both proj's so the second one can be omitted */
813 const ir_node *t = proj_true;
815 proj_true = proj_false;
817 if(pnc & ia32_pn_Cmp_float) {
818 pnc = get_negated_pnc(pnc, mode_F);
820 pnc = get_negated_pnc(pnc, mode_Iu);
824 if (pnc & ia32_pn_Cmp_float) {
825 /* Some floating point comparisons require a test of the parity flag,
826 * which indicates that the result is unordered */
829 be_emit_cstring("\tjp ");
830 ia32_emit_cfop_target(proj_true);
831 be_emit_finish_line_gas(proj_true);
835 be_emit_cstring("\tjnp ");
836 ia32_emit_cfop_target(proj_true);
837 be_emit_finish_line_gas(proj_true);
843 be_emit_cstring("\tjp ");
844 ia32_emit_cfop_target(proj_false);
845 be_emit_finish_line_gas(proj_false);
851 be_emit_cstring("\tjp ");
852 ia32_emit_cfop_target(proj_true);
853 be_emit_finish_line_gas(proj_true);
861 be_emit_cstring("\tj");
862 ia32_emit_cmp_suffix(pnc);
864 ia32_emit_cfop_target(proj_true);
865 be_emit_finish_line_gas(proj_true);
868 /* the second Proj might be a fallthrough */
869 if (get_cfop_target_block(proj_false) != next_block) {
870 be_emit_cstring("\tjmp ");
871 ia32_emit_cfop_target(proj_false);
872 be_emit_finish_line_gas(proj_false);
874 be_emit_cstring("\t/* fallthrough to ");
875 ia32_emit_cfop_target(proj_false);
876 be_emit_cstring(" */");
877 be_emit_finish_line_gas(proj_false);
881 static void emit_ia32_CMov(const ir_node *node)
883 const arch_register_t *out = arch_get_irn_register(arch_env, node);
884 const arch_register_t *in_true;
885 const arch_register_t *in_false;
886 pn_Cmp pnc = get_ia32_pncode(node);
888 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
890 in_true = arch_get_irn_register(arch_env,
891 get_irn_n(node, n_ia32_CMov_val_true));
892 in_false = arch_get_irn_register(arch_env,
893 get_irn_n(node, n_ia32_CMov_val_false));
895 /* should be same constraint fullfilled? */
896 if(out == in_false) {
897 /* yes -> nothing to do */
898 } else if(out == in_true) {
899 const arch_register_t *tmp;
901 /* swap left/right and negate pnc */
902 pnc = get_negated_pnc(pnc, mode_Iu);
909 be_emit_cstring("\tmovl ");
910 emit_register(in_false, NULL);
911 be_emit_cstring(", ");
912 emit_register(out, NULL);
913 be_emit_finish_line_gas(node);
916 be_emit_cstring("\tcmov");
917 ia32_emit_cmp_suffix(pnc);
919 if(get_ia32_op_type(node) == ia32_AddrModeS) {
922 emit_register(in_true, get_ia32_ls_mode(node));
924 be_emit_cstring(", ");
925 emit_register(out, get_ia32_ls_mode(node));
926 be_emit_finish_line_gas(node);
929 /*********************************************************
932 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
933 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
934 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
935 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
938 *********************************************************/
940 /* jump table entry (target and corresponding number) */
941 typedef struct _branch_t {
946 /* jump table for switch generation */
947 typedef struct _jmp_tbl_t {
948 ir_node *defProj; /**< default target */
949 long min_value; /**< smallest switch case */
950 long max_value; /**< largest switch case */
951 long num_branches; /**< number of jumps */
952 char *label; /**< label of the jump table */
953 branch_t *branches; /**< jump array */
957 * Compare two variables of type branch_t. Used to sort all switch cases
960 int ia32_cmp_branch_t(const void *a, const void *b) {
961 branch_t *b1 = (branch_t *)a;
962 branch_t *b2 = (branch_t *)b;
964 if (b1->value <= b2->value)
971 * Emits code for a SwitchJmp (creates a jump table if
972 * possible otherwise a cmp-jmp cascade). Port from
976 void emit_ia32_SwitchJmp(const ir_node *node) {
977 unsigned long interval;
982 const ir_edge_t *edge;
984 /* fill the table structure */
985 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
986 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
988 tbl.num_branches = get_irn_n_edges(node);
989 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
990 tbl.min_value = INT_MAX;
991 tbl.max_value = INT_MIN;
994 /* go over all proj's and collect them */
995 foreach_out_edge(node, edge) {
996 proj = get_edge_src_irn(edge);
997 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
999 pnc = get_Proj_proj(proj);
1001 /* create branch entry */
1002 tbl.branches[i].target = proj;
1003 tbl.branches[i].value = pnc;
1005 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1006 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1008 /* check for default proj */
1009 if (pnc == get_ia32_pncode(node)) {
1010 assert(tbl.defProj == NULL && "found two defProjs at SwitchJmp");
1017 /* sort the branches by their number */
1018 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1020 /* two-complement's magic make this work without overflow */
1021 interval = tbl.max_value - tbl.min_value;
1023 /* emit the table */
1024 be_emit_cstring("\tcmpl $");
1025 be_emit_irprintf("%u, ", interval);
1026 ia32_emit_source_register(node, 0);
1027 be_emit_finish_line_gas(node);
1029 be_emit_cstring("\tja ");
1030 ia32_emit_cfop_target(tbl.defProj);
1031 be_emit_finish_line_gas(node);
1033 if (tbl.num_branches > 1) {
1035 be_emit_cstring("\tjmp *");
1036 be_emit_string(tbl.label);
1037 be_emit_cstring("(,");
1038 ia32_emit_source_register(node, 0);
1039 be_emit_cstring(",4)");
1040 be_emit_finish_line_gas(node);
1042 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1043 be_emit_cstring("\t.align 4\n");
1044 be_emit_write_line();
1046 be_emit_string(tbl.label);
1047 be_emit_cstring(":\n");
1048 be_emit_write_line();
1050 be_emit_cstring(".long ");
1051 ia32_emit_cfop_target(tbl.branches[0].target);
1052 be_emit_finish_line_gas(NULL);
1054 last_value = tbl.branches[0].value;
1055 for (i = 1; i < tbl.num_branches; ++i) {
1056 while (++last_value < tbl.branches[i].value) {
1057 be_emit_cstring(".long ");
1058 ia32_emit_cfop_target(tbl.defProj);
1059 be_emit_finish_line_gas(NULL);
1061 be_emit_cstring(".long ");
1062 ia32_emit_cfop_target(tbl.branches[i].target);
1063 be_emit_finish_line_gas(NULL);
1065 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1067 /* one jump is enough */
1068 be_emit_cstring("\tjmp ");
1069 ia32_emit_cfop_target(tbl.branches[0].target);
1070 be_emit_finish_line_gas(node);
1080 * Emits code for a unconditional jump.
1082 static void emit_Jmp(const ir_node *node)
1084 ir_node *block, *next_block;
1086 /* for now, the code works for scheduled and non-schedules blocks */
1087 block = get_nodes_block(node);
1089 /* we have a block schedule */
1090 next_block = next_blk_sched(block);
1091 if (get_cfop_target_block(node) != next_block) {
1092 be_emit_cstring("\tjmp ");
1093 ia32_emit_cfop_target(node);
1095 be_emit_cstring("\t/* fallthrough to ");
1096 ia32_emit_cfop_target(node);
1097 be_emit_cstring(" */");
1099 be_emit_finish_line_gas(node);
1102 static void emit_ia32_Immediate(const ir_node *node)
1104 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1107 if(attr->symconst != NULL) {
1108 ident *id = get_entity_ld_ident(attr->symconst);
1110 if(attr->attr.data.am_sc_sign)
1114 if(attr->symconst == NULL || attr->offset != 0) {
1115 if(attr->symconst != NULL) {
1116 be_emit_irprintf("%+d", attr->offset);
1118 be_emit_irprintf("0x%X", attr->offset);
1123 static const char* emit_asm_operand(const ir_node *node, const char *s)
1125 const arch_register_t *reg;
1126 const char *reg_name;
1130 const ia32_attr_t *attr;
1137 /* parse modifiers */
1140 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1164 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1165 "'%c' for asm op\n", node, c);
1171 sscanf(s, "%d%n", &num, &p);
1173 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1181 attr = get_ia32_attr_const(node);
1182 n_outs = ARR_LEN(attr->slots);
1184 reg = get_out_reg(node, num);
1187 int in = num - n_outs;
1188 if(in >= get_irn_arity(node)) {
1189 ir_fprintf(stderr, "Warning: Invalid input %d specified in asm "
1190 "op (%+F)\n", num, node);
1193 pred = get_irn_n(node, in);
1194 /* might be an immediate value */
1195 if(is_ia32_Immediate(pred)) {
1196 emit_ia32_Immediate(pred);
1199 reg = get_in_reg(node, in);
1202 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1203 "(%+F)\n", num, node);
1211 reg_name = arch_register_get_name(reg);
1214 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1217 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1220 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1223 panic("Invalid asm op modifier");
1225 be_emit_string(reg_name);
1231 * Emits code for an ASM pseudo op.
1233 static void emit_ia32_Asm(const ir_node *node)
1235 const void *gen_attr = get_irn_generic_attr_const(node);
1236 const ia32_asm_attr_t *attr
1237 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1238 ident *asm_text = attr->asm_text;
1239 const char *s = get_id_str(asm_text);
1241 be_emit_cstring("# Begin ASM \t");
1242 be_emit_finish_line_gas(node);
1249 s = emit_asm_operand(node, s);
1258 be_emit_write_line();
1260 be_emit_cstring("# End ASM\n");
1261 be_emit_write_line();
1264 /**********************************
1267 * | | ___ _ __ _ _| |_) |
1268 * | | / _ \| '_ \| | | | _ <
1269 * | |___| (_) | |_) | |_| | |_) |
1270 * \_____\___/| .__/ \__, |____/
1273 **********************************/
1276 * Emit movsb/w instructions to make mov count divideable by 4
1278 static void emit_CopyB_prolog(int rem) {
1279 be_emit_cstring("\tcld");
1280 be_emit_finish_line_gas(NULL);
1284 be_emit_cstring("\tmovsb");
1285 be_emit_finish_line_gas(NULL);
1288 be_emit_cstring("\tmovsw");
1289 be_emit_finish_line_gas(NULL);
1292 be_emit_cstring("\tmovsb");
1293 be_emit_finish_line_gas(NULL);
1294 be_emit_cstring("\tmovsw");
1295 be_emit_finish_line_gas(NULL);
1301 * Emit rep movsd instruction for memcopy.
1303 static void emit_ia32_CopyB(const ir_node *node)
1305 int rem = get_ia32_pncode(node);
1307 emit_CopyB_prolog(rem);
1309 be_emit_cstring("\trep movsd");
1310 be_emit_finish_line_gas(node);
1314 * Emits unrolled memcopy.
1316 static void emit_ia32_CopyB_i(const ir_node *node)
1318 int size = get_ia32_pncode(node);
1320 emit_CopyB_prolog(size & 0x3);
1324 be_emit_cstring("\tmovsd");
1325 be_emit_finish_line_gas(NULL);
1331 /***************************
1335 * | | / _ \| '_ \ \ / /
1336 * | |___| (_) | | | \ V /
1337 * \_____\___/|_| |_|\_/
1339 ***************************/
1342 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1344 static void emit_ia32_Conv_with_FP(const ir_node *node)
1346 ir_mode *ls_mode = get_ia32_ls_mode(node);
1347 int ls_bits = get_mode_size_bits(ls_mode);
1349 be_emit_cstring("\tcvt");
1351 if(is_ia32_Conv_I2FP(node)) {
1353 be_emit_cstring("si2ss");
1355 be_emit_cstring("si2sd");
1357 } else if(is_ia32_Conv_FP2I(node)) {
1359 be_emit_cstring("ss2si");
1361 be_emit_cstring("sd2si");
1364 assert(is_ia32_Conv_FP2FP(node));
1366 be_emit_cstring("sd2ss");
1368 be_emit_cstring("ss2sd");
1373 switch(get_ia32_op_type(node)) {
1375 ia32_emit_source_register(node, n_ia32_unary_op);
1377 case ia32_AddrModeS:
1381 assert(0 && "unsupported op type for Conv");
1383 be_emit_cstring(", ");
1384 ia32_emit_dest_register(node, 0);
1385 be_emit_finish_line_gas(node);
1388 static void emit_ia32_Conv_I2FP(const ir_node *node)
1390 emit_ia32_Conv_with_FP(node);
1393 static void emit_ia32_Conv_FP2I(const ir_node *node)
1395 emit_ia32_Conv_with_FP(node);
1398 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1400 emit_ia32_Conv_with_FP(node);
1404 * Emits code for an Int conversion.
1406 static void emit_ia32_Conv_I2I(const ir_node *node)
1408 const char *sign_suffix;
1409 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1410 int smaller_bits = get_mode_size_bits(smaller_mode);
1412 const arch_register_t *in_reg, *out_reg;
1414 assert(!mode_is_float(smaller_mode));
1415 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1417 signed_mode = mode_is_signed(smaller_mode);
1418 if(smaller_bits == 32) {
1419 // this should not happen as it's no convert
1423 sign_suffix = signed_mode ? "s" : "z";
1426 out_reg = get_out_reg(node, 0);
1428 switch(get_ia32_op_type(node)) {
1430 in_reg = get_in_reg(node, n_ia32_unary_op);
1432 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1433 out_reg == &ia32_gp_regs[REG_EAX] &&
1437 /* argument and result are both in EAX and */
1438 /* signedness is ok: -> use the smaller cwtl opcode */
1439 be_emit_cstring("\tcwtl");
1441 be_emit_cstring("\tmov");
1442 be_emit_string(sign_suffix);
1443 ia32_emit_mode_suffix_mode(smaller_mode);
1444 be_emit_cstring("l ");
1445 emit_register(in_reg, smaller_mode);
1446 be_emit_cstring(", ");
1447 emit_register(out_reg, NULL);
1450 case ia32_AddrModeS: {
1451 be_emit_cstring("\tmov");
1452 be_emit_string(sign_suffix);
1453 ia32_emit_mode_suffix_mode(smaller_mode);
1454 be_emit_cstring("l ");
1456 be_emit_cstring(", ");
1457 emit_register(out_reg, NULL);
1461 assert(0 && "unsupported op type for Conv");
1463 be_emit_finish_line_gas(node);
1467 * Emits code for an 8Bit Int conversion.
1469 static void emit_ia32_Conv_I2I8Bit(const ir_node *node)
1471 emit_ia32_Conv_I2I(node);
1475 /*******************************************
1478 * | |__ ___ _ __ ___ __| | ___ ___
1479 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1480 * | |_) | __/ | | | (_) | (_| | __/\__ \
1481 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1483 *******************************************/
1486 * Emits a backend call
1488 static void emit_be_Call(const ir_node *node)
1490 ir_entity *ent = be_Call_get_entity(node);
1492 be_emit_cstring("\tcall ");
1494 set_entity_backend_marked(ent, 1);
1495 be_emit_string(get_entity_ld_name(ent));
1497 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1499 emit_register(reg, NULL);
1501 be_emit_finish_line_gas(node);
1505 * Emits code to increase stack pointer.
1507 static void emit_be_IncSP(const ir_node *node)
1509 int offs = be_get_IncSP_offset(node);
1510 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1516 be_emit_cstring("\tsubl $");
1517 be_emit_irprintf("%u, ", offs);
1518 emit_register(reg, NULL);
1520 be_emit_cstring("\taddl $");
1521 be_emit_irprintf("%u, ", -offs);
1522 emit_register(reg, NULL);
1524 be_emit_finish_line_gas(node);
1528 * Emits code for Copy/CopyKeep.
1530 static void Copy_emitter(const ir_node *node, const ir_node *op)
1532 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1533 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1539 if(is_unknown_reg(in))
1541 /* copies of vf nodes aren't real... */
1542 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1545 mode = get_irn_mode(node);
1546 if (mode == mode_E) {
1547 be_emit_cstring("\tmovsd ");
1548 emit_register(in, NULL);
1549 be_emit_cstring(", ");
1550 emit_register(out, NULL);
1552 be_emit_cstring("\tmovl ");
1553 emit_register(in, NULL);
1554 be_emit_cstring(", ");
1555 emit_register(out, NULL);
1557 be_emit_finish_line_gas(node);
1560 static void emit_be_Copy(const ir_node *node)
1562 Copy_emitter(node, be_get_Copy_op(node));
1565 static void emit_be_CopyKeep(const ir_node *node)
1567 Copy_emitter(node, be_get_CopyKeep_op(node));
1571 * Emits code for exchange.
1573 static void emit_be_Perm(const ir_node *node)
1575 const arch_register_t *in0, *in1;
1576 const arch_register_class_t *cls0, *cls1;
1578 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1579 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1581 cls0 = arch_register_get_class(in0);
1582 cls1 = arch_register_get_class(in1);
1584 assert(cls0 == cls1 && "Register class mismatch at Perm");
1586 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1587 be_emit_cstring("\txchg ");
1588 emit_register(in1, NULL);
1589 be_emit_cstring(", ");
1590 emit_register(in0, NULL);
1591 be_emit_finish_line_gas(node);
1592 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1593 be_emit_cstring("\txorpd ");
1594 emit_register(in1, NULL);
1595 be_emit_cstring(", ");
1596 emit_register(in0, NULL);
1597 be_emit_finish_line_gas(NULL);
1599 be_emit_cstring("\txorpd ");
1600 emit_register(in0, NULL);
1601 be_emit_cstring(", ");
1602 emit_register(in1, NULL);
1603 be_emit_finish_line_gas(NULL);
1605 be_emit_cstring("\txorpd ");
1606 emit_register(in1, NULL);
1607 be_emit_cstring(", ");
1608 emit_register(in0, NULL);
1609 be_emit_finish_line_gas(node);
1610 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1612 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1615 panic("unexpected register class in be_Perm (%+F)\n", node);
1620 * Emits code for Constant loading.
1622 static void emit_ia32_Const(const ir_node *node)
1624 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1627 if(attr->symconst == NULL && attr->offset == 0) {
1628 assert(get_ia32_flags(node) & arch_irn_flags_modify_flags);
1629 be_emit_cstring("\txorl ");
1630 ia32_emit_dest_register(node, 0);
1631 be_emit_cstring(", ");
1632 ia32_emit_dest_register(node, 0);
1634 be_emit_cstring("\tmovl ");
1635 emit_ia32_Immediate(node);
1636 be_emit_cstring(", ");
1637 ia32_emit_dest_register(node, 0);
1640 be_emit_finish_line_gas(node);
1644 * Emits code to load the TLS base
1646 static void emit_ia32_LdTls(const ir_node *node)
1648 be_emit_cstring("\tmovl %gs:0, ");
1649 ia32_emit_dest_register(node, 0);
1650 be_emit_finish_line_gas(node);
1653 /* helper function for emit_ia32_Minus64Bit */
1654 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1656 be_emit_cstring("\tmovl ");
1657 emit_register(src, NULL);
1658 be_emit_cstring(", ");
1659 emit_register(dst, NULL);
1660 be_emit_finish_line_gas(node);
1663 /* helper function for emit_ia32_Minus64Bit */
1664 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1666 be_emit_cstring("\tnegl ");
1667 emit_register(reg, NULL);
1668 be_emit_finish_line_gas(node);
1671 /* helper function for emit_ia32_Minus64Bit */
1672 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1674 be_emit_cstring("\tsbbl $0, ");
1675 emit_register(reg, NULL);
1676 be_emit_finish_line_gas(node);
1679 /* helper function for emit_ia32_Minus64Bit */
1680 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1682 be_emit_cstring("\tsbbl ");
1683 emit_register(src, NULL);
1684 be_emit_cstring(", ");
1685 emit_register(dst, NULL);
1686 be_emit_finish_line_gas(node);
1689 /* helper function for emit_ia32_Minus64Bit */
1690 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1692 be_emit_cstring("\txchgl ");
1693 emit_register(src, NULL);
1694 be_emit_cstring(", ");
1695 emit_register(dst, NULL);
1696 be_emit_finish_line_gas(node);
1699 /* helper function for emit_ia32_Minus64Bit */
1700 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1702 be_emit_cstring("\txorl ");
1703 emit_register(reg, NULL);
1704 be_emit_cstring(", ");
1705 emit_register(reg, NULL);
1706 be_emit_finish_line_gas(node);
1709 static void emit_ia32_Minus64Bit(const ir_node *node)
1711 const arch_register_t *in_lo = get_in_reg(node, 0);
1712 const arch_register_t *in_hi = get_in_reg(node, 1);
1713 const arch_register_t *out_lo = get_out_reg(node, 0);
1714 const arch_register_t *out_hi = get_out_reg(node, 1);
1716 if (out_lo == in_lo) {
1717 if (out_hi != in_hi) {
1718 /* a -> a, b -> d */
1721 /* a -> a, b -> b */
1724 } else if (out_lo == in_hi) {
1725 if (out_hi == in_lo) {
1726 /* a -> b, b -> a */
1727 emit_xchg(node, in_lo, in_hi);
1730 /* a -> b, b -> d */
1731 emit_mov(node, in_hi, out_hi);
1732 emit_mov(node, in_lo, out_lo);
1736 if (out_hi == in_lo) {
1737 /* a -> c, b -> a */
1738 emit_mov(node, in_lo, out_lo);
1740 } else if (out_hi == in_hi) {
1741 /* a -> c, b -> b */
1742 emit_mov(node, in_lo, out_lo);
1745 /* a -> c, b -> d */
1746 emit_mov(node, in_lo, out_lo);
1752 emit_neg( node, out_hi);
1753 emit_neg( node, out_lo);
1754 emit_sbb0(node, out_hi);
1758 emit_zero(node, out_hi);
1759 emit_neg( node, out_lo);
1760 emit_sbb( node, in_hi, out_hi);
1763 static void emit_be_Return(const ir_node *node)
1765 be_emit_cstring("\tret");
1766 be_emit_finish_line_gas(node);
1769 static void emit_Nothing(const ir_node *node)
1775 /***********************************************************************************
1778 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1779 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1780 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1781 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1783 ***********************************************************************************/
1786 * Enters the emitter functions for handled nodes into the generic
1787 * pointer of an opcode.
1790 void ia32_register_emitters(void) {
1792 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1793 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1794 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1795 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1796 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1797 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1799 /* first clear the generic function pointer for all ops */
1800 clear_irp_opcodes_generic_func();
1802 /* register all emitter functions defined in spec */
1803 ia32_register_spec_emitters();
1805 /* other ia32 emitter functions */
1808 IA32_EMIT(SwitchJmp);
1811 IA32_EMIT(Conv_I2FP);
1812 IA32_EMIT(Conv_FP2I);
1813 IA32_EMIT(Conv_FP2FP);
1814 IA32_EMIT(Conv_I2I);
1815 IA32_EMIT(Conv_I2I8Bit);
1818 IA32_EMIT(Minus64Bit);
1821 /* benode emitter */
1846 static const char *last_name = NULL;
1847 static unsigned last_line = -1;
1848 static unsigned num = -1;
1851 * Emit the debug support for node node.
1853 static void ia32_emit_dbg(const ir_node *node)
1855 dbg_info *db = get_irn_dbg_info(node);
1857 const char *fname = be_retrieve_dbg_info(db, &lineno);
1859 if (! cg->birg->main_env->options->stabs_debug_support)
1863 if (last_name != fname) {
1865 be_dbg_include_begin(cg->birg->main_env->db_handle, fname);
1868 if (last_line != lineno) {
1871 snprintf(name, sizeof(name), ".LM%u", ++num);
1873 be_dbg_line(cg->birg->main_env->db_handle, lineno, name);
1874 be_emit_string(name);
1875 be_emit_cstring(":\n");
1876 be_emit_write_line();
1881 typedef void (*emit_func_ptr) (const ir_node *);
1884 * Emits code for a node.
1886 static void ia32_emit_node(const ir_node *node)
1888 ir_op *op = get_irn_op(node);
1890 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1892 if (op->ops.generic) {
1893 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1894 ia32_emit_dbg(node);
1898 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1904 * Emits gas alignment directives
1906 static void ia32_emit_alignment(unsigned align, unsigned skip)
1908 be_emit_cstring("\t.p2align ");
1909 be_emit_irprintf("%u,,%u\n", align, skip);
1910 be_emit_write_line();
1914 * Emits gas alignment directives for Functions depended on cpu architecture.
1916 static void ia32_emit_align_func(cpu_support cpu)
1919 unsigned maximum_skip;
1934 maximum_skip = (1 << align) - 1;
1935 ia32_emit_alignment(align, maximum_skip);
1939 * Emits gas alignment directives for Labels depended on cpu architecture.
1941 static void ia32_emit_align_label(cpu_support cpu)
1943 unsigned align; unsigned maximum_skip;
1958 maximum_skip = (1 << align) - 1;
1959 ia32_emit_alignment(align, maximum_skip);
1963 * Test wether a block should be aligned.
1964 * For cpus in the P4/Athlon class it is usefull to align jump labels to
1965 * 16 bytes. However we should only do that if the alignment nops before the
1966 * label aren't executed more often than we have jumps to the label.
1968 static int should_align_block(ir_node *block, ir_node *prev)
1970 static const double DELTA = .0001;
1971 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1973 double prev_freq = 0; /**< execfreq of the fallthrough block */
1974 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1975 cpu_support cpu = isa->opt_arch;
1978 if(exec_freq == NULL)
1980 if(cpu == arch_i386 || cpu == arch_i486)
1983 block_freq = get_block_execfreq(exec_freq, block);
1984 if(block_freq < DELTA)
1987 n_cfgpreds = get_Block_n_cfgpreds(block);
1988 for(i = 0; i < n_cfgpreds; ++i) {
1989 ir_node *pred = get_Block_cfgpred_block(block, i);
1990 double pred_freq = get_block_execfreq(exec_freq, pred);
1993 prev_freq += pred_freq;
1995 jmp_freq += pred_freq;
1999 if(prev_freq < DELTA && !(jmp_freq < DELTA))
2002 jmp_freq /= prev_freq;
2006 case arch_athlon_64:
2008 return jmp_freq > 3;
2010 return jmp_freq > 2;
2014 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
2019 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2021 n_cfgpreds = get_Block_n_cfgpreds(block);
2022 need_label = (n_cfgpreds != 0);
2024 if (should_align_block(block, prev)) {
2026 ia32_emit_align_label(isa->opt_arch);
2030 ia32_emit_block_name(block);
2033 be_emit_pad_comment();
2034 be_emit_cstring(" /* preds:");
2036 /* emit list of pred blocks in comment */
2037 arity = get_irn_arity(block);
2038 for (i = 0; i < arity; ++i) {
2039 ir_node *predblock = get_Block_cfgpred_block(block, i);
2040 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2043 be_emit_cstring("\t/* ");
2044 ia32_emit_block_name(block);
2045 be_emit_cstring(": ");
2047 if (exec_freq != NULL) {
2048 be_emit_irprintf(" freq: %f",
2049 get_block_execfreq(exec_freq, block));
2051 be_emit_cstring(" */\n");
2052 be_emit_write_line();
2056 * Walks over the nodes in a block connected by scheduling edges
2057 * and emits code for each node.
2059 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2061 const ir_node *node;
2063 ia32_emit_block_header(block, last_block);
2065 /* emit the contents of the block */
2066 ia32_emit_dbg(block);
2067 sched_foreach(block, node) {
2068 ia32_emit_node(node);
2073 * Emits code for function start.
2075 static void ia32_emit_func_prolog(ir_graph *irg)
2077 ir_entity *irg_ent = get_irg_entity(irg);
2078 const char *irg_name = get_entity_ld_name(irg_ent);
2079 cpu_support cpu = isa->opt_arch;
2080 const be_irg_t *birg = cg->birg;
2082 be_emit_write_line();
2083 be_gas_emit_switch_section(GAS_SECTION_TEXT);
2084 be_dbg_method_begin(birg->main_env->db_handle, irg_ent, be_abi_get_stack_layout(birg->abi));
2085 ia32_emit_align_func(cpu);
2086 if (get_entity_visibility(irg_ent) == visibility_external_visible) {
2087 be_emit_cstring(".global ");
2088 be_emit_string(irg_name);
2090 be_emit_write_line();
2092 ia32_emit_function_object(irg_name);
2093 be_emit_string(irg_name);
2094 be_emit_cstring(":\n");
2095 be_emit_write_line();
2099 * Emits code for function end
2101 static void ia32_emit_func_epilog(ir_graph *irg)
2103 const char *irg_name = get_entity_ld_name(get_irg_entity(irg));
2104 const be_irg_t *birg = cg->birg;
2106 ia32_emit_function_size(irg_name);
2107 be_dbg_method_end(birg->main_env->db_handle);
2109 be_emit_write_line();
2114 * Sets labels for control flow nodes (jump target)
2116 static void ia32_gen_labels(ir_node *block, void *data)
2119 int n = get_Block_n_cfgpreds(block);
2122 for (n--; n >= 0; n--) {
2123 pred = get_Block_cfgpred(block, n);
2124 set_irn_link(pred, block);
2129 * Emit an exception label if the current instruction can fail.
2131 void ia32_emit_exc_label(const ir_node *node)
2133 if (get_ia32_exc_label(node)) {
2134 be_emit_irprintf(".EXL%u\n", 0);
2135 be_emit_write_line();
2140 * Main driver. Emits the code for one routine.
2142 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2145 ir_node *last_block = NULL;
2149 isa = (const ia32_isa_t*) cg->arch_env->isa;
2150 arch_env = cg->arch_env;
2152 ia32_register_emitters();
2154 ia32_emit_func_prolog(irg);
2155 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2157 n = ARR_LEN(cg->blk_sched);
2158 for (i = 0; i < n;) {
2161 block = cg->blk_sched[i];
2163 next_bl = i < n ? cg->blk_sched[i] : NULL;
2165 /* set here the link. the emitter expects to find the next block here */
2166 set_irn_link(block, next_bl);
2167 ia32_gen_block(block, last_block);
2171 ia32_emit_func_epilog(irg);
2174 void ia32_init_emitter(void)
2176 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");