2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
41 #include "iredges_t.h"
44 #include "raw_bitset.h"
47 #include "../besched_t.h"
48 #include "../benode_t.h"
50 #include "../be_dbgout.h"
51 #include "../beemitter.h"
52 #include "../begnuas.h"
53 #include "../beirg_t.h"
54 #include "../be_dbgout.h"
56 #include "ia32_emitter.h"
57 #include "gen_ia32_emitter.h"
58 #include "gen_ia32_regalloc_if.h"
59 #include "ia32_nodes_attr.h"
60 #include "ia32_new_nodes.h"
61 #include "ia32_map_regs.h"
62 #include "ia32_architecture.h"
63 #include "bearch_ia32_t.h"
65 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
67 #define BLOCK_PREFIX ".L"
69 #define SNPRINTF_BUF_LEN 128
71 static const arch_env_t *arch_env;
72 static const ia32_isa_t *isa;
73 static ia32_code_gen_t *cg;
75 static char pic_base_label[128];
78 * Returns the register at in position pos.
80 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
83 const arch_register_t *reg = NULL;
85 assert(get_irn_arity(irn) > pos && "Invalid IN position");
87 /* The out register of the operator at position pos is the
88 in register we need. */
89 op = get_irn_n(irn, pos);
91 reg = arch_get_irn_register(arch_env, op);
93 assert(reg && "no in register found");
95 if(reg == &ia32_gp_regs[REG_GP_NOREG])
96 panic("trying to emit noreg for %+F input %d", irn, pos);
98 /* in case of unknown register: just return a valid register */
99 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
100 const arch_register_req_t *req;
102 /* ask for the requirements */
103 req = arch_get_register_req(arch_env, irn, pos);
105 if (arch_register_req_is(req, limited)) {
106 /* in case of limited requirements: get the first allowed register */
107 unsigned idx = rbitset_next(req->limited, 0, 1);
108 reg = arch_register_for_index(req->cls, idx);
110 /* otherwise get first register in class */
111 reg = arch_register_for_index(req->cls, 0);
119 * Returns the register at out position pos.
121 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
124 const arch_register_t *reg = NULL;
126 /* 1st case: irn is not of mode_T, so it has only */
127 /* one OUT register -> good */
128 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
129 /* Proj with the corresponding projnum for the register */
131 if (get_irn_mode(irn) != mode_T) {
133 reg = arch_get_irn_register(arch_env, irn);
134 } else if (is_ia32_irn(irn)) {
135 reg = get_ia32_out_reg(irn, pos);
137 const ir_edge_t *edge;
139 foreach_out_edge(irn, edge) {
140 proj = get_edge_src_irn(edge);
141 assert(is_Proj(proj) && "non-Proj from mode_T node");
142 if (get_Proj_proj(proj) == pos) {
143 reg = arch_get_irn_register(arch_env, proj);
149 assert(reg && "no out register found");
154 * Add a number to a prefix. This number will not be used a second time.
156 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
158 static unsigned long id = 0;
159 snprintf(buf, buflen, "%s%lu", prefix, ++id);
163 /*************************************************************
165 * (_) | | / _| | | | |
166 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
167 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
168 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
169 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
172 *************************************************************/
174 static void emit_8bit_register(const arch_register_t *reg)
176 const char *reg_name = arch_register_get_name(reg);
179 be_emit_char(reg_name[1]);
183 static void emit_16bit_register(const arch_register_t *reg)
185 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
188 be_emit_string(reg_name);
191 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
193 const char *reg_name;
196 int size = get_mode_size_bits(mode);
198 emit_8bit_register(reg);
200 } else if(size == 16) {
201 emit_16bit_register(reg);
204 assert(mode_is_float(mode) || size == 32);
208 reg_name = arch_register_get_name(reg);
211 be_emit_string(reg_name);
214 void ia32_emit_source_register(const ir_node *node, int pos)
216 const arch_register_t *reg = get_in_reg(node, pos);
218 emit_register(reg, NULL);
221 static void emit_ia32_Immediate(const ir_node *node);
223 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
225 const arch_register_t *reg;
226 ir_node *in = get_irn_n(node, pos);
227 if(is_ia32_Immediate(in)) {
228 emit_ia32_Immediate(in);
232 reg = get_in_reg(node, pos);
233 emit_8bit_register(reg);
236 void ia32_emit_dest_register(const ir_node *node, int pos)
238 const arch_register_t *reg = get_out_reg(node, pos);
240 emit_register(reg, NULL);
243 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
245 const arch_register_t *reg = get_out_reg(node, pos);
247 emit_register(reg, mode_Bu);
250 void ia32_emit_x87_register(const ir_node *node, int pos)
252 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
256 be_emit_string(attr->x87[pos]->name);
259 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
261 if(mode_is_float(mode)) {
262 switch(get_mode_size_bits(mode)) {
263 case 32: be_emit_char('s'); return;
264 case 64: be_emit_char('l'); return;
266 case 96: be_emit_char('t'); return;
269 assert(mode_is_int(mode) || mode_is_reference(mode));
270 switch(get_mode_size_bits(mode)) {
271 case 64: be_emit_cstring("ll"); return;
272 /* gas docu says q is the suffix but gcc, objdump and icc use
274 case 32: be_emit_char('l'); return;
275 case 16: be_emit_char('w'); return;
276 case 8: be_emit_char('b'); return;
279 panic("Can't output mode_suffix for %+F\n", mode);
282 void ia32_emit_mode_suffix(const ir_node *node)
284 ir_mode *mode = get_ia32_ls_mode(node);
288 ia32_emit_mode_suffix_mode(mode);
291 void ia32_emit_x87_mode_suffix(const ir_node *node)
293 ir_mode *mode = get_ia32_ls_mode(node);
294 assert(mode != NULL);
295 /* we only need to emit the mode on address mode */
296 if(get_ia32_op_type(node) != ia32_Normal)
297 ia32_emit_mode_suffix_mode(mode);
300 static char get_xmm_mode_suffix(ir_mode *mode)
302 assert(mode_is_float(mode));
303 switch(get_mode_size_bits(mode)) {
314 void ia32_emit_xmm_mode_suffix(const ir_node *node)
316 ir_mode *mode = get_ia32_ls_mode(node);
317 assert(mode != NULL);
319 be_emit_char(get_xmm_mode_suffix(mode));
322 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
324 ir_mode *mode = get_ia32_ls_mode(node);
325 assert(mode != NULL);
326 be_emit_char(get_xmm_mode_suffix(mode));
329 void ia32_emit_extend_suffix(const ir_mode *mode)
331 if(get_mode_size_bits(mode) == 32)
333 if(mode_is_signed(mode)) {
340 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
342 ir_node *in = get_irn_n(node, pos);
343 if(is_ia32_Immediate(in)) {
344 emit_ia32_Immediate(in);
346 const ir_mode *mode = get_ia32_ls_mode(node);
347 const arch_register_t *reg = get_in_reg(node, pos);
348 emit_register(reg, mode);
353 * Emits registers and/or address mode of a binary operation.
355 void ia32_emit_binop(const ir_node *node) {
356 const ir_node *right_op = get_irn_n(node, n_ia32_binary_right);
357 const ir_mode *mode = get_ia32_ls_mode(node);
358 const arch_register_t *reg_left;
360 switch(get_ia32_op_type(node)) {
362 reg_left = get_in_reg(node, n_ia32_binary_left);
363 if(is_ia32_Immediate(right_op)) {
364 emit_ia32_Immediate(right_op);
365 be_emit_cstring(", ");
366 emit_register(reg_left, mode);
369 const arch_register_t *reg_right
370 = get_in_reg(node, n_ia32_binary_right);
371 emit_register(reg_right, mode);
372 be_emit_cstring(", ");
373 emit_register(reg_left, mode);
377 if(is_ia32_Immediate(right_op)) {
378 emit_ia32_Immediate(right_op);
379 be_emit_cstring(", ");
382 reg_left = get_in_reg(node, n_ia32_binary_left);
384 be_emit_cstring(", ");
385 emit_register(reg_left, mode);
389 panic("DestMode can't be output by %%binop anymore");
392 assert(0 && "unsupported op type");
397 * Emits registers and/or address mode of a binary operation.
399 void ia32_emit_x87_binop(const ir_node *node) {
400 switch(get_ia32_op_type(node)) {
403 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
404 const arch_register_t *in1 = x87_attr->x87[0];
405 const arch_register_t *in2 = x87_attr->x87[1];
406 const arch_register_t *out = x87_attr->x87[2];
407 const arch_register_t *in;
409 in = out ? ((out == in2) ? in1 : in2) : in2;
410 out = out ? out : in1;
413 be_emit_string(arch_register_get_name(in));
414 be_emit_cstring(", %");
415 be_emit_string(arch_register_get_name(out));
423 assert(0 && "unsupported op type");
428 * Emits registers and/or address mode of a unary operation.
430 void ia32_emit_unop(const ir_node *node, int pos) {
433 switch(get_ia32_op_type(node)) {
435 op = get_irn_n(node, pos);
436 if (is_ia32_Immediate(op)) {
437 emit_ia32_Immediate(op);
439 ia32_emit_source_register(node, pos);
447 assert(0 && "unsupported op type");
451 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
455 set_entity_backend_marked(entity, 1);
456 id = get_entity_ld_ident(entity);
459 if (get_entity_owner(entity) == get_tls_type()) {
460 if (get_entity_visibility(entity) == visibility_external_allocated) {
461 be_emit_cstring("@INDNTPOFF");
463 be_emit_cstring("@NTPOFF");
467 if (!no_pic_adjust && do_pic) {
468 /* TODO: only do this when necessary */
470 be_emit_string(pic_base_label);
475 * Emits address mode.
477 void ia32_emit_am(const ir_node *node) {
478 ir_entity *ent = get_ia32_am_sc(node);
479 int offs = get_ia32_am_offs_int(node);
480 ir_node *base = get_irn_n(node, 0);
481 int has_base = !is_ia32_NoReg_GP(base);
482 ir_node *index = get_irn_n(node, 1);
483 int has_index = !is_ia32_NoReg_GP(index);
485 /* just to be sure... */
486 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
490 if (is_ia32_am_sc_sign(node))
492 ia32_emit_entity(ent, 0);
497 be_emit_irprintf("%+d", offs);
499 be_emit_irprintf("%d", offs);
503 if (has_base || has_index) {
508 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
509 emit_register(reg, NULL);
512 /* emit index + scale */
514 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
517 emit_register(reg, NULL);
519 scale = get_ia32_am_scale(node);
521 be_emit_irprintf(",%d", 1 << get_ia32_am_scale(node));
527 /* special case if nothing is set */
528 if(ent == NULL && offs == 0 && !has_base && !has_index) {
533 static void emit_ia32_IMul(const ir_node *node)
535 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
536 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
538 be_emit_cstring("\timul");
539 ia32_emit_mode_suffix(node);
542 ia32_emit_binop(node);
544 /* do we need the 3-address form? */
545 if(is_ia32_NoReg_GP(left) ||
546 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
547 be_emit_cstring(", ");
548 emit_register(out_reg, get_ia32_ls_mode(node));
550 be_emit_finish_line_gas(node);
553 /*************************************************
556 * ___ _ __ ___ _| |_ ___ ___ _ __ __| |
557 * / _ \ '_ ` _ \| | __| / __/ _ \| '_ \ / _` |
558 * | __/ | | | | | | |_ | (_| (_) | | | | (_| |
559 * \___|_| |_| |_|_|\__| \___\___/|_| |_|\__,_|
561 *************************************************/
564 #define IA32_DO_EMIT(irn) ia32_fprintf_format(F, irn, cmd_buf, cmnt_buf)
567 * coding of conditions
569 struct cmp2conditon_t {
575 * positive conditions for signed compares
577 static const struct cmp2conditon_t cmp2condition_s[] = {
578 { NULL, pn_Cmp_False }, /* always false */
579 { "e", pn_Cmp_Eq }, /* == */
580 { "l", pn_Cmp_Lt }, /* < */
581 { "le", pn_Cmp_Le }, /* <= */
582 { "g", pn_Cmp_Gt }, /* > */
583 { "ge", pn_Cmp_Ge }, /* >= */
584 { "ne", pn_Cmp_Lg }, /* != */
585 { NULL, pn_Cmp_Leg}, /* always true */
589 * positive conditions for unsigned compares
591 static const struct cmp2conditon_t cmp2condition_u[] = {
592 { NULL, pn_Cmp_False }, /* always false */
593 { "e", pn_Cmp_Eq }, /* == */
594 { "b", pn_Cmp_Lt }, /* < */
595 { "be", pn_Cmp_Le }, /* <= */
596 { "a", pn_Cmp_Gt }, /* > */
597 { "ae", pn_Cmp_Ge }, /* >= */
598 { "ne", pn_Cmp_Lg }, /* != */
599 { NULL, pn_Cmp_Leg }, /* always true */
603 ia32_pn_Cmp_unsigned = 0x1000,
604 ia32_pn_Cmp_float = 0x2000,
608 * walks up a tree of copies/perms/spills/reloads to find the original value
609 * that is moved around
611 static ir_node *find_original_value(ir_node *node)
613 inc_irg_visited(current_ir_graph);
615 mark_irn_visited(node);
616 if(be_is_Copy(node)) {
617 node = be_get_Copy_op(node);
618 } else if(be_is_CopyKeep(node)) {
619 node = be_get_CopyKeep_op(node);
620 } else if(is_Proj(node)) {
621 ir_node *pred = get_Proj_pred(node);
622 if(be_is_Perm(pred)) {
623 node = get_irn_n(pred, get_Proj_proj(node));
624 } else if(be_is_MemPerm(pred)) {
625 node = get_irn_n(pred, get_Proj_proj(node) + 1);
626 } else if(is_ia32_Load(pred)) {
627 node = get_irn_n(pred, n_ia32_Load_mem);
631 } else if(is_ia32_Store(node)) {
632 node = get_irn_n(node, n_ia32_Store_val);
633 } else if(is_Phi(node)) {
635 arity = get_irn_arity(node);
636 for(i = 0; i < arity; ++i) {
637 ir_node *in = get_irn_n(node, i);
650 static int determine_final_pnc(const ir_node *node, int flags_pos,
653 ir_node *flags = get_irn_n(node, flags_pos);
654 const ia32_attr_t *flags_attr;
655 flags = skip_Proj(flags);
657 if(is_ia32_Sahf(flags)) {
658 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
659 if(!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
660 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
661 cmp = find_original_value(cmp);
662 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
663 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
666 flags_attr = get_ia32_attr_const(cmp);
667 if(flags_attr->data.ins_permuted)
668 pnc = get_mirrored_pnc(pnc);
669 pnc |= ia32_pn_Cmp_float;
670 } else if(is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
671 || is_ia32_Fucompi(flags)) {
672 flags_attr = get_ia32_attr_const(flags);
674 if(flags_attr->data.ins_permuted)
675 pnc = get_mirrored_pnc(pnc);
676 pnc |= ia32_pn_Cmp_float;
679 assert(is_ia32_Cmp(flags) || is_ia32_Test(flags)
680 || is_ia32_Cmp8Bit(flags) || is_ia32_Test8Bit(flags));
682 flags_attr = get_ia32_attr_const(flags);
684 if(flags_attr->data.ins_permuted)
685 pnc = get_mirrored_pnc(pnc);
686 if(flags_attr->data.cmp_unsigned)
687 pnc |= ia32_pn_Cmp_unsigned;
693 static void ia32_emit_cmp_suffix(int pnc)
697 if((pnc & ia32_pn_Cmp_float) || (pnc & ia32_pn_Cmp_unsigned)) {
699 assert(cmp2condition_u[pnc].num == pnc);
700 str = cmp2condition_u[pnc].name;
703 assert(cmp2condition_s[pnc].num == pnc);
704 str = cmp2condition_s[pnc].name;
710 void ia32_emit_cmp_suffix_node(const ir_node *node,
713 const ia32_attr_t *attr = get_ia32_attr_const(node);
715 pn_Cmp pnc = get_ia32_condcode(node);
717 pnc = determine_final_pnc(node, flags_pos, pnc);
718 if(attr->data.ins_permuted) {
719 if(pnc & ia32_pn_Cmp_float) {
720 pnc = get_negated_pnc(pnc, mode_F);
722 pnc = get_negated_pnc(pnc, mode_Iu);
726 ia32_emit_cmp_suffix(pnc);
730 * Returns the target block for a control flow node.
732 static ir_node *get_cfop_target_block(const ir_node *irn) {
733 return get_irn_link(irn);
737 * Emits a block label for the given block.
739 static void ia32_emit_block_name(const ir_node *block)
741 if (has_Block_label(block)) {
742 be_emit_string(be_gas_label_prefix());
743 be_emit_irprintf("%u", (unsigned)get_Block_label(block));
745 be_emit_cstring(BLOCK_PREFIX);
746 be_emit_irprintf("%d", get_irn_node_nr(block));
751 * Emits the target label for a control flow node.
753 static void ia32_emit_cfop_target(const ir_node *node)
755 ir_node *block = get_cfop_target_block(node);
757 ia32_emit_block_name(block);
760 /** Return the next block in Block schedule */
761 static ir_node *next_blk_sched(const ir_node *block)
763 return get_irn_link(block);
767 * Returns the Proj with projection number proj and NOT mode_M
769 static ir_node *get_proj(const ir_node *node, long proj) {
770 const ir_edge_t *edge;
773 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
775 foreach_out_edge(node, edge) {
776 src = get_edge_src_irn(edge);
778 assert(is_Proj(src) && "Proj expected");
779 if (get_irn_mode(src) == mode_M)
782 if (get_Proj_proj(src) == proj)
789 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
791 static void emit_ia32_Jcc(const ir_node *node)
793 int need_parity_label = 0;
794 const ir_node *proj_true;
795 const ir_node *proj_false;
796 const ir_node *block;
797 const ir_node *next_block;
798 pn_Cmp pnc = get_ia32_condcode(node);
800 pnc = determine_final_pnc(node, 0, pnc);
803 proj_true = get_proj(node, pn_ia32_Jcc_true);
804 assert(proj_true && "Jcc without true Proj");
806 proj_false = get_proj(node, pn_ia32_Jcc_false);
807 assert(proj_false && "Jcc without false Proj");
809 block = get_nodes_block(node);
810 next_block = next_blk_sched(block);
812 if (get_cfop_target_block(proj_true) == next_block) {
813 /* exchange both proj's so the second one can be omitted */
814 const ir_node *t = proj_true;
816 proj_true = proj_false;
818 if(pnc & ia32_pn_Cmp_float) {
819 pnc = get_negated_pnc(pnc, mode_F);
821 pnc = get_negated_pnc(pnc, mode_Iu);
825 if (pnc & ia32_pn_Cmp_float) {
826 /* Some floating point comparisons require a test of the parity flag,
827 * which indicates that the result is unordered */
830 be_emit_cstring("\tjp ");
831 ia32_emit_cfop_target(proj_true);
832 be_emit_finish_line_gas(proj_true);
837 be_emit_cstring("\tjnp ");
838 ia32_emit_cfop_target(proj_true);
839 be_emit_finish_line_gas(proj_true);
845 /* we need a local label if the false proj is a fallthrough
846 * as the falseblock might have no label emitted then */
847 if (get_cfop_target_block(proj_false) == next_block) {
848 need_parity_label = 1;
849 be_emit_cstring("\tjp 1f");
851 be_emit_cstring("\tjp ");
852 ia32_emit_cfop_target(proj_false);
854 be_emit_finish_line_gas(proj_false);
860 be_emit_cstring("\tjp ");
861 ia32_emit_cfop_target(proj_true);
862 be_emit_finish_line_gas(proj_true);
870 be_emit_cstring("\tj");
871 ia32_emit_cmp_suffix(pnc);
873 ia32_emit_cfop_target(proj_true);
874 be_emit_finish_line_gas(proj_true);
877 if(need_parity_label) {
878 be_emit_cstring("1:");
879 be_emit_write_line();
882 /* the second Proj might be a fallthrough */
883 if (get_cfop_target_block(proj_false) != next_block) {
884 be_emit_cstring("\tjmp ");
885 ia32_emit_cfop_target(proj_false);
886 be_emit_finish_line_gas(proj_false);
888 be_emit_cstring("\t/* fallthrough to ");
889 ia32_emit_cfop_target(proj_false);
890 be_emit_cstring(" */");
891 be_emit_finish_line_gas(proj_false);
895 static void emit_ia32_CMov(const ir_node *node)
897 const ia32_attr_t *attr = get_ia32_attr_const(node);
898 int ins_permuted = attr->data.ins_permuted;
899 const arch_register_t *out = arch_get_irn_register(arch_env, node);
900 pn_Cmp pnc = get_ia32_condcode(node);
901 const arch_register_t *in_true;
902 const arch_register_t *in_false;
904 pnc = determine_final_pnc(node, n_ia32_CMov_eflags, pnc);
906 in_true = arch_get_irn_register(arch_env,
907 get_irn_n(node, n_ia32_CMov_val_true));
908 in_false = arch_get_irn_register(arch_env,
909 get_irn_n(node, n_ia32_CMov_val_false));
911 /* should be same constraint fullfilled? */
912 if(out == in_false) {
913 /* yes -> nothing to do */
914 } else if(out == in_true) {
915 const arch_register_t *tmp;
917 assert(get_ia32_op_type(node) == ia32_Normal);
919 ins_permuted = !ins_permuted;
926 be_emit_cstring("\tmovl ");
927 emit_register(in_false, NULL);
928 be_emit_cstring(", ");
929 emit_register(out, NULL);
930 be_emit_finish_line_gas(node);
934 if(pnc & ia32_pn_Cmp_float) {
935 pnc = get_negated_pnc(pnc, mode_F);
937 pnc = get_negated_pnc(pnc, mode_Iu);
941 /* TODO: handling of Nans isn't correct yet */
943 be_emit_cstring("\tcmov");
944 ia32_emit_cmp_suffix(pnc);
946 if(get_ia32_op_type(node) == ia32_AddrModeS) {
949 emit_register(in_true, get_ia32_ls_mode(node));
951 be_emit_cstring(", ");
952 emit_register(out, get_ia32_ls_mode(node));
953 be_emit_finish_line_gas(node);
956 /*********************************************************
959 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
960 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
961 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
962 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
965 *********************************************************/
967 /* jump table entry (target and corresponding number) */
968 typedef struct _branch_t {
973 /* jump table for switch generation */
974 typedef struct _jmp_tbl_t {
975 ir_node *defProj; /**< default target */
976 long min_value; /**< smallest switch case */
977 long max_value; /**< largest switch case */
978 long num_branches; /**< number of jumps */
979 char *label; /**< label of the jump table */
980 branch_t *branches; /**< jump array */
984 * Compare two variables of type branch_t. Used to sort all switch cases
986 static int ia32_cmp_branch_t(const void *a, const void *b) {
987 branch_t *b1 = (branch_t *)a;
988 branch_t *b2 = (branch_t *)b;
990 if (b1->value <= b2->value)
997 * Emits code for a SwitchJmp (creates a jump table if
998 * possible otherwise a cmp-jmp cascade). Port from
1001 static void emit_ia32_SwitchJmp(const ir_node *node)
1003 unsigned long interval;
1009 const ir_edge_t *edge;
1011 /* fill the table structure */
1012 tbl.label = xmalloc(SNPRINTF_BUF_LEN);
1013 tbl.label = get_unique_label(tbl.label, SNPRINTF_BUF_LEN, ".TBL_");
1015 tbl.num_branches = get_irn_n_edges(node) - 1;
1016 tbl.branches = xcalloc(tbl.num_branches, sizeof(tbl.branches[0]));
1017 tbl.min_value = INT_MAX;
1018 tbl.max_value = INT_MIN;
1020 default_pn = get_ia32_condcode(node);
1022 /* go over all proj's and collect them */
1023 foreach_out_edge(node, edge) {
1024 proj = get_edge_src_irn(edge);
1025 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1027 pnc = get_Proj_proj(proj);
1029 /* check for default proj */
1030 if (pnc == default_pn) {
1031 assert(tbl.defProj == NULL && "found two default Projs at SwitchJmp");
1034 tbl.min_value = pnc < tbl.min_value ? pnc : tbl.min_value;
1035 tbl.max_value = pnc > tbl.max_value ? pnc : tbl.max_value;
1037 /* create branch entry */
1038 tbl.branches[i].target = proj;
1039 tbl.branches[i].value = pnc;
1044 assert(i == tbl.num_branches);
1046 /* sort the branches by their number */
1047 qsort(tbl.branches, tbl.num_branches, sizeof(tbl.branches[0]), ia32_cmp_branch_t);
1049 /* two-complement's magic make this work without overflow */
1050 interval = tbl.max_value - tbl.min_value;
1052 /* emit the table */
1053 be_emit_cstring("\tcmpl $");
1054 be_emit_irprintf("%u, ", interval);
1055 ia32_emit_source_register(node, 0);
1056 be_emit_finish_line_gas(node);
1058 be_emit_cstring("\tja ");
1059 ia32_emit_cfop_target(tbl.defProj);
1060 be_emit_finish_line_gas(node);
1062 if (tbl.num_branches > 1) {
1064 be_emit_cstring("\tjmp *");
1065 be_emit_string(tbl.label);
1066 be_emit_cstring("(,");
1067 ia32_emit_source_register(node, 0);
1068 be_emit_cstring(",4)");
1069 be_emit_finish_line_gas(node);
1071 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1072 be_emit_cstring("\t.align 4\n");
1073 be_emit_write_line();
1075 be_emit_string(tbl.label);
1076 be_emit_cstring(":\n");
1077 be_emit_write_line();
1079 be_emit_cstring(".long ");
1080 ia32_emit_cfop_target(tbl.branches[0].target);
1081 be_emit_finish_line_gas(NULL);
1083 last_value = tbl.branches[0].value;
1084 for (i = 1; i < tbl.num_branches; ++i) {
1085 while (++last_value < tbl.branches[i].value) {
1086 be_emit_cstring(".long ");
1087 ia32_emit_cfop_target(tbl.defProj);
1088 be_emit_finish_line_gas(NULL);
1090 be_emit_cstring(".long ");
1091 ia32_emit_cfop_target(tbl.branches[i].target);
1092 be_emit_finish_line_gas(NULL);
1094 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1096 /* one jump is enough */
1097 be_emit_cstring("\tjmp ");
1098 ia32_emit_cfop_target(tbl.branches[0].target);
1099 be_emit_finish_line_gas(node);
1109 * Emits code for a unconditional jump.
1111 static void emit_Jmp(const ir_node *node)
1113 ir_node *block, *next_block;
1115 /* for now, the code works for scheduled and non-schedules blocks */
1116 block = get_nodes_block(node);
1118 /* we have a block schedule */
1119 next_block = next_blk_sched(block);
1120 if (get_cfop_target_block(node) != next_block) {
1121 be_emit_cstring("\tjmp ");
1122 ia32_emit_cfop_target(node);
1124 be_emit_cstring("\t/* fallthrough to ");
1125 ia32_emit_cfop_target(node);
1126 be_emit_cstring(" */");
1128 be_emit_finish_line_gas(node);
1131 static void emit_ia32_Immediate(const ir_node *node)
1133 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
1136 if(attr->symconst != NULL) {
1139 ia32_emit_entity(attr->symconst, 0);
1141 if(attr->symconst == NULL || attr->offset != 0) {
1142 if(attr->symconst != NULL) {
1143 be_emit_irprintf("%+d", attr->offset);
1145 be_emit_irprintf("0x%X", attr->offset);
1151 * Emit an inline assembler operand.
1153 * @param node the ia32_ASM node
1154 * @param s points to the operand (a %c)
1156 * @return pointer to the first char in s NOT in the current operand
1158 static const char* emit_asm_operand(const ir_node *node, const char *s)
1160 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1161 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1163 const arch_register_t *reg;
1164 const ia32_asm_reg_t *asm_regs = attr->register_map;
1165 const ia32_asm_reg_t *asm_reg;
1166 const char *reg_name;
1175 /* parse modifiers */
1178 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %\n", node);
1202 ir_fprintf(stderr, "Warning: asm text (%+F) contains unknown modifier "
1203 "'%c' for asm op\n", node, c);
1209 sscanf(s, "%d%n", &num, &p);
1211 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1218 if(num < 0 || num >= ARR_LEN(asm_regs)) {
1219 ir_fprintf(stderr, "Error: Custom assembler references invalid "
1220 "input/output (%+F)\n", node);
1223 asm_reg = & asm_regs[num];
1224 assert(asm_reg->valid);
1227 if(asm_reg->use_input == 0) {
1228 reg = get_out_reg(node, asm_reg->inout_pos);
1230 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1232 /* might be an immediate value */
1233 if(is_ia32_Immediate(pred)) {
1234 emit_ia32_Immediate(pred);
1237 reg = get_in_reg(node, asm_reg->inout_pos);
1240 ir_fprintf(stderr, "Warning: no register assigned for %d asm op "
1241 "(%+F)\n", num, node);
1245 if(asm_reg->memory) {
1254 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1257 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1260 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1263 panic("Invalid asm op modifier");
1265 be_emit_string(reg_name);
1267 emit_register(reg, asm_reg->mode);
1270 if(asm_reg->memory) {
1278 * Emits code for an ASM pseudo op.
1280 static void emit_ia32_Asm(const ir_node *node)
1282 const void *gen_attr = get_irn_generic_attr_const(node);
1283 const ia32_asm_attr_t *attr
1284 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1285 ident *asm_text = attr->asm_text;
1286 const char *s = get_id_str(asm_text);
1288 be_emit_cstring("# Begin ASM \t");
1289 be_emit_finish_line_gas(node);
1296 s = emit_asm_operand(node, s);
1305 be_emit_write_line();
1307 be_emit_cstring("# End ASM\n");
1308 be_emit_write_line();
1311 /**********************************
1314 * | | ___ _ __ _ _| |_) |
1315 * | | / _ \| '_ \| | | | _ <
1316 * | |___| (_) | |_) | |_| | |_) |
1317 * \_____\___/| .__/ \__, |____/
1320 **********************************/
1323 * Emit movsb/w instructions to make mov count divideable by 4
1325 static void emit_CopyB_prolog(unsigned size) {
1326 be_emit_cstring("\tcld");
1327 be_emit_finish_line_gas(NULL);
1331 be_emit_cstring("\tmovsb");
1332 be_emit_finish_line_gas(NULL);
1335 be_emit_cstring("\tmovsw");
1336 be_emit_finish_line_gas(NULL);
1339 be_emit_cstring("\tmovsb");
1340 be_emit_finish_line_gas(NULL);
1341 be_emit_cstring("\tmovsw");
1342 be_emit_finish_line_gas(NULL);
1348 * Emit rep movsd instruction for memcopy.
1350 static void emit_ia32_CopyB(const ir_node *node)
1352 unsigned size = get_ia32_copyb_size(node);
1354 emit_CopyB_prolog(size);
1356 be_emit_cstring("\trep movsd");
1357 be_emit_finish_line_gas(node);
1361 * Emits unrolled memcopy.
1363 static void emit_ia32_CopyB_i(const ir_node *node)
1365 unsigned size = get_ia32_copyb_size(node);
1367 emit_CopyB_prolog(size & 0x3);
1371 be_emit_cstring("\tmovsd");
1372 be_emit_finish_line_gas(NULL);
1378 /***************************
1382 * | | / _ \| '_ \ \ / /
1383 * | |___| (_) | | | \ V /
1384 * \_____\___/|_| |_|\_/
1386 ***************************/
1389 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1391 static void emit_ia32_Conv_with_FP(const ir_node *node)
1393 ir_mode *ls_mode = get_ia32_ls_mode(node);
1394 int ls_bits = get_mode_size_bits(ls_mode);
1396 be_emit_cstring("\tcvt");
1398 if(is_ia32_Conv_I2FP(node)) {
1400 be_emit_cstring("si2ss");
1402 be_emit_cstring("si2sd");
1404 } else if(is_ia32_Conv_FP2I(node)) {
1406 be_emit_cstring("ss2si");
1408 be_emit_cstring("sd2si");
1411 assert(is_ia32_Conv_FP2FP(node));
1413 be_emit_cstring("sd2ss");
1415 be_emit_cstring("ss2sd");
1420 switch(get_ia32_op_type(node)) {
1422 ia32_emit_source_register(node, n_ia32_unary_op);
1424 case ia32_AddrModeS:
1428 assert(0 && "unsupported op type for Conv");
1430 be_emit_cstring(", ");
1431 ia32_emit_dest_register(node, 0);
1432 be_emit_finish_line_gas(node);
1435 static void emit_ia32_Conv_I2FP(const ir_node *node)
1437 emit_ia32_Conv_with_FP(node);
1440 static void emit_ia32_Conv_FP2I(const ir_node *node)
1442 emit_ia32_Conv_with_FP(node);
1445 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1447 emit_ia32_Conv_with_FP(node);
1451 * Emits code for an Int conversion.
1453 static void emit_ia32_Conv_I2I(const ir_node *node)
1455 const char *sign_suffix;
1456 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1457 int smaller_bits = get_mode_size_bits(smaller_mode);
1459 const arch_register_t *in_reg, *out_reg;
1461 assert(!mode_is_float(smaller_mode));
1462 assert(smaller_bits == 8 || smaller_bits == 16 || smaller_bits == 32);
1464 signed_mode = mode_is_signed(smaller_mode);
1465 if(smaller_bits == 32) {
1466 // this should not happen as it's no convert
1470 sign_suffix = signed_mode ? "s" : "z";
1473 out_reg = get_out_reg(node, 0);
1475 switch(get_ia32_op_type(node)) {
1477 in_reg = get_in_reg(node, n_ia32_unary_op);
1479 if (in_reg == &ia32_gp_regs[REG_EAX] &&
1480 out_reg == &ia32_gp_regs[REG_EAX] &&
1484 /* argument and result are both in EAX and */
1485 /* signedness is ok: -> use the smaller cwtl opcode */
1486 be_emit_cstring("\tcwtl");
1488 be_emit_cstring("\tmov");
1489 be_emit_string(sign_suffix);
1490 ia32_emit_mode_suffix_mode(smaller_mode);
1491 be_emit_cstring("l ");
1492 emit_register(in_reg, smaller_mode);
1493 be_emit_cstring(", ");
1494 emit_register(out_reg, NULL);
1497 case ia32_AddrModeS: {
1498 be_emit_cstring("\tmov");
1499 be_emit_string(sign_suffix);
1500 ia32_emit_mode_suffix_mode(smaller_mode);
1501 be_emit_cstring("l ");
1503 be_emit_cstring(", ");
1504 emit_register(out_reg, NULL);
1508 assert(0 && "unsupported op type for Conv");
1510 be_emit_finish_line_gas(node);
1514 /*******************************************
1517 * | |__ ___ _ __ ___ __| | ___ ___
1518 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1519 * | |_) | __/ | | | (_) | (_| | __/\__ \
1520 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1522 *******************************************/
1525 * Emits a backend call
1527 static void emit_be_Call(const ir_node *node)
1529 ir_entity *ent = be_Call_get_entity(node);
1531 be_emit_cstring("\tcall ");
1533 ia32_emit_entity(ent, 1);
1535 const arch_register_t *reg = get_in_reg(node, be_pos_Call_ptr);
1537 emit_register(reg, NULL);
1539 be_emit_finish_line_gas(node);
1543 * Emits code to increase stack pointer.
1545 static void emit_be_IncSP(const ir_node *node)
1547 int offs = be_get_IncSP_offset(node);
1548 const arch_register_t *reg = arch_get_irn_register(arch_env, node);
1554 be_emit_cstring("\tsubl $");
1555 be_emit_irprintf("%u, ", offs);
1556 emit_register(reg, NULL);
1558 be_emit_cstring("\taddl $");
1559 be_emit_irprintf("%u, ", -offs);
1560 emit_register(reg, NULL);
1562 be_emit_finish_line_gas(node);
1566 * Emits code for Copy/CopyKeep.
1568 static void Copy_emitter(const ir_node *node, const ir_node *op)
1570 const arch_register_t *in = arch_get_irn_register(arch_env, op);
1571 const arch_register_t *out = arch_get_irn_register(arch_env, node);
1577 if(is_unknown_reg(in))
1579 /* copies of vf nodes aren't real... */
1580 if(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1583 mode = get_irn_mode(node);
1584 if (mode == mode_E) {
1585 be_emit_cstring("\tmovsd ");
1586 emit_register(in, NULL);
1587 be_emit_cstring(", ");
1588 emit_register(out, NULL);
1590 be_emit_cstring("\tmovl ");
1591 emit_register(in, NULL);
1592 be_emit_cstring(", ");
1593 emit_register(out, NULL);
1595 be_emit_finish_line_gas(node);
1598 static void emit_be_Copy(const ir_node *node)
1600 Copy_emitter(node, be_get_Copy_op(node));
1603 static void emit_be_CopyKeep(const ir_node *node)
1605 Copy_emitter(node, be_get_CopyKeep_op(node));
1609 * Emits code for exchange.
1611 static void emit_be_Perm(const ir_node *node)
1613 const arch_register_t *in0, *in1;
1614 const arch_register_class_t *cls0, *cls1;
1616 in0 = arch_get_irn_register(arch_env, get_irn_n(node, 0));
1617 in1 = arch_get_irn_register(arch_env, get_irn_n(node, 1));
1619 cls0 = arch_register_get_class(in0);
1620 cls1 = arch_register_get_class(in1);
1622 assert(cls0 == cls1 && "Register class mismatch at Perm");
1624 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1625 be_emit_cstring("\txchg ");
1626 emit_register(in1, NULL);
1627 be_emit_cstring(", ");
1628 emit_register(in0, NULL);
1629 be_emit_finish_line_gas(node);
1630 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1631 be_emit_cstring("\txorpd ");
1632 emit_register(in1, NULL);
1633 be_emit_cstring(", ");
1634 emit_register(in0, NULL);
1635 be_emit_finish_line_gas(NULL);
1637 be_emit_cstring("\txorpd ");
1638 emit_register(in0, NULL);
1639 be_emit_cstring(", ");
1640 emit_register(in1, NULL);
1641 be_emit_finish_line_gas(NULL);
1643 be_emit_cstring("\txorpd ");
1644 emit_register(in1, NULL);
1645 be_emit_cstring(", ");
1646 emit_register(in0, NULL);
1647 be_emit_finish_line_gas(node);
1648 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1650 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1653 panic("unexpected register class in be_Perm (%+F)\n", node);
1658 * Emits code for Constant loading.
1660 static void emit_ia32_Const(const ir_node *node)
1662 be_emit_cstring("\tmovl ");
1663 emit_ia32_Immediate(node);
1664 be_emit_cstring(", ");
1665 ia32_emit_dest_register(node, 0);
1667 be_emit_finish_line_gas(node);
1671 * Emits code to load the TLS base
1673 static void emit_ia32_LdTls(const ir_node *node)
1675 be_emit_cstring("\tmovl %gs:0, ");
1676 ia32_emit_dest_register(node, 0);
1677 be_emit_finish_line_gas(node);
1680 /* helper function for emit_ia32_Minus64Bit */
1681 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1683 be_emit_cstring("\tmovl ");
1684 emit_register(src, NULL);
1685 be_emit_cstring(", ");
1686 emit_register(dst, NULL);
1687 be_emit_finish_line_gas(node);
1690 /* helper function for emit_ia32_Minus64Bit */
1691 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1693 be_emit_cstring("\tnegl ");
1694 emit_register(reg, NULL);
1695 be_emit_finish_line_gas(node);
1698 /* helper function for emit_ia32_Minus64Bit */
1699 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1701 be_emit_cstring("\tsbbl $0, ");
1702 emit_register(reg, NULL);
1703 be_emit_finish_line_gas(node);
1706 /* helper function for emit_ia32_Minus64Bit */
1707 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1709 be_emit_cstring("\tsbbl ");
1710 emit_register(src, NULL);
1711 be_emit_cstring(", ");
1712 emit_register(dst, NULL);
1713 be_emit_finish_line_gas(node);
1716 /* helper function for emit_ia32_Minus64Bit */
1717 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1719 be_emit_cstring("\txchgl ");
1720 emit_register(src, NULL);
1721 be_emit_cstring(", ");
1722 emit_register(dst, NULL);
1723 be_emit_finish_line_gas(node);
1726 /* helper function for emit_ia32_Minus64Bit */
1727 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1729 be_emit_cstring("\txorl ");
1730 emit_register(reg, NULL);
1731 be_emit_cstring(", ");
1732 emit_register(reg, NULL);
1733 be_emit_finish_line_gas(node);
1736 static void emit_ia32_Minus64Bit(const ir_node *node)
1738 const arch_register_t *in_lo = get_in_reg(node, 0);
1739 const arch_register_t *in_hi = get_in_reg(node, 1);
1740 const arch_register_t *out_lo = get_out_reg(node, 0);
1741 const arch_register_t *out_hi = get_out_reg(node, 1);
1743 if (out_lo == in_lo) {
1744 if (out_hi != in_hi) {
1745 /* a -> a, b -> d */
1748 /* a -> a, b -> b */
1751 } else if (out_lo == in_hi) {
1752 if (out_hi == in_lo) {
1753 /* a -> b, b -> a */
1754 emit_xchg(node, in_lo, in_hi);
1757 /* a -> b, b -> d */
1758 emit_mov(node, in_hi, out_hi);
1759 emit_mov(node, in_lo, out_lo);
1763 if (out_hi == in_lo) {
1764 /* a -> c, b -> a */
1765 emit_mov(node, in_lo, out_lo);
1767 } else if (out_hi == in_hi) {
1768 /* a -> c, b -> b */
1769 emit_mov(node, in_lo, out_lo);
1772 /* a -> c, b -> d */
1773 emit_mov(node, in_lo, out_lo);
1779 emit_neg( node, out_hi);
1780 emit_neg( node, out_lo);
1781 emit_sbb0(node, out_hi);
1785 emit_zero(node, out_hi);
1786 emit_neg( node, out_lo);
1787 emit_sbb( node, in_hi, out_hi);
1790 static void emit_ia32_GetEIP(const ir_node *node)
1792 be_emit_cstring("\tcall ");
1793 be_emit_string(pic_base_label);
1794 be_emit_finish_line_gas(node);
1796 be_emit_string(pic_base_label);
1797 be_emit_cstring(":\n");
1798 be_emit_write_line();
1800 be_emit_cstring("\tpopl ");
1801 ia32_emit_dest_register(node, 0);
1803 be_emit_write_line();
1806 static void emit_be_Return(const ir_node *node)
1809 be_emit_cstring("\tret");
1811 pop = be_Return_get_pop(node);
1813 be_emit_irprintf(" $%d", pop);
1815 be_emit_finish_line_gas(node);
1818 static void emit_Nothing(const ir_node *node)
1824 /***********************************************************************************
1827 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1828 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1829 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1830 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1832 ***********************************************************************************/
1835 * Enters the emitter functions for handled nodes into the generic
1836 * pointer of an opcode.
1838 static void ia32_register_emitters(void) {
1840 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1841 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1842 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1843 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1844 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1845 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1847 /* first clear the generic function pointer for all ops */
1848 clear_irp_opcodes_generic_func();
1850 /* register all emitter functions defined in spec */
1851 ia32_register_spec_emitters();
1853 /* other ia32 emitter functions */
1857 IA32_EMIT(SwitchJmp);
1860 IA32_EMIT(Conv_I2FP);
1861 IA32_EMIT(Conv_FP2I);
1862 IA32_EMIT(Conv_FP2FP);
1863 IA32_EMIT(Conv_I2I);
1864 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1867 IA32_EMIT(Minus64Bit);
1871 /* benode emitter */
1896 typedef void (*emit_func_ptr) (const ir_node *);
1899 * Emits code for a node.
1901 static void ia32_emit_node(const ir_node *node)
1903 ir_op *op = get_irn_op(node);
1905 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1907 if (op->ops.generic) {
1908 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1910 be_dbg_set_dbg_info(get_irn_dbg_info(node));
1915 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1921 * Emits gas alignment directives
1923 static void ia32_emit_alignment(unsigned align, unsigned skip)
1925 be_emit_cstring("\t.p2align ");
1926 be_emit_irprintf("%u,,%u\n", align, skip);
1927 be_emit_write_line();
1931 * Emits gas alignment directives for Labels depended on cpu architecture.
1933 static void ia32_emit_align_label(void)
1935 unsigned align = ia32_cg_config.label_alignment;
1936 unsigned maximum_skip = (1 << align) - 1;
1937 ia32_emit_alignment(align, maximum_skip);
1941 * Test wether a block should be aligned.
1942 * For cpus in the P4/Athlon class it is useful to align jump labels to
1943 * 16 bytes. However we should only do that if the alignment nops before the
1944 * label aren't executed more often than we have jumps to the label.
1946 static int should_align_block(ir_node *block, ir_node *prev)
1948 static const double DELTA = .0001;
1949 ir_exec_freq *exec_freq = cg->birg->exec_freq;
1951 double prev_freq = 0; /**< execfreq of the fallthrough block */
1952 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1955 if(exec_freq == NULL)
1957 if(ia32_cg_config.label_alignment_factor <= 0)
1960 block_freq = get_block_execfreq(exec_freq, block);
1961 if(block_freq < DELTA)
1964 n_cfgpreds = get_Block_n_cfgpreds(block);
1965 for(i = 0; i < n_cfgpreds; ++i) {
1966 ir_node *pred = get_Block_cfgpred_block(block, i);
1967 double pred_freq = get_block_execfreq(exec_freq, pred);
1970 prev_freq += pred_freq;
1972 jmp_freq += pred_freq;
1976 if(prev_freq < DELTA && !(jmp_freq < DELTA))
1979 jmp_freq /= prev_freq;
1981 return jmp_freq > ia32_cg_config.label_alignment_factor;
1984 static int can_omit_block_label(ir_node *cfgpred)
1988 if(!is_Proj(cfgpred))
1990 pred = get_Proj_pred(cfgpred);
1991 if(is_ia32_SwitchJmp(pred))
1997 static void ia32_emit_block_header(ir_node *block, ir_node *prev)
1999 ir_graph *irg = current_ir_graph;
2003 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2005 if(block == get_irg_end_block(irg) || block == get_irg_start_block(irg))
2008 n_cfgpreds = get_Block_n_cfgpreds(block);
2010 if(n_cfgpreds == 0) {
2012 } else if(n_cfgpreds == 1) {
2013 ir_node *cfgpred = get_Block_cfgpred(block, 0);
2014 if(get_nodes_block(cfgpred) == prev && can_omit_block_label(cfgpred)) {
2019 if (should_align_block(block, prev)) {
2020 ia32_emit_align_label();
2024 ia32_emit_block_name(block);
2027 be_emit_pad_comment();
2028 be_emit_cstring(" /* ");
2030 be_emit_cstring("\t/* ");
2031 ia32_emit_block_name(block);
2032 be_emit_cstring(": ");
2035 be_emit_cstring("preds:");
2037 /* emit list of pred blocks in comment */
2038 arity = get_irn_arity(block);
2039 for (i = 0; i < arity; ++i) {
2040 ir_node *predblock = get_Block_cfgpred_block(block, i);
2041 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2043 if (exec_freq != NULL) {
2044 be_emit_irprintf(" freq: %f",
2045 get_block_execfreq(exec_freq, block));
2047 be_emit_cstring(" */\n");
2048 be_emit_write_line();
2052 * Walks over the nodes in a block connected by scheduling edges
2053 * and emits code for each node.
2055 static void ia32_gen_block(ir_node *block, ir_node *last_block)
2057 const ir_node *node;
2059 ia32_emit_block_header(block, last_block);
2061 /* emit the contents of the block */
2062 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2063 sched_foreach(block, node) {
2064 ia32_emit_node(node);
2070 * Sets labels for control flow nodes (jump target)
2072 static void ia32_gen_labels(ir_node *block, void *data)
2075 int n = get_Block_n_cfgpreds(block);
2078 for (n--; n >= 0; n--) {
2079 pred = get_Block_cfgpred(block, n);
2080 set_irn_link(pred, block);
2085 * Emit an exception label if the current instruction can fail.
2087 void ia32_emit_exc_label(const ir_node *node)
2089 if (get_ia32_exc_label(node)) {
2090 be_emit_irprintf(".EXL%u\n", 0);
2091 be_emit_write_line();
2096 * Main driver. Emits the code for one routine.
2098 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2101 ir_node *last_block = NULL;
2102 ir_entity *entity = get_irg_entity(irg);
2106 isa = (const ia32_isa_t*) cg->arch_env->isa;
2107 arch_env = cg->arch_env;
2108 do_pic = cg->birg->main_env->options->pic;
2110 ia32_register_emitters();
2112 get_unique_label(pic_base_label, sizeof(pic_base_label), ".PIC_BASE");
2114 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2115 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2117 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
2119 n = ARR_LEN(cg->blk_sched);
2120 for (i = 0; i < n;) {
2123 block = cg->blk_sched[i];
2125 next_bl = i < n ? cg->blk_sched[i] : NULL;
2127 /* set here the link. the emitter expects to find the next block here */
2128 set_irn_link(block, next_bl);
2129 ia32_gen_block(block, last_block);
2133 be_gas_emit_function_epilog(entity);
2134 be_dbg_method_end();
2136 be_emit_write_line();
2139 void ia32_init_emitter(void)
2141 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");