2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
26 * Summary table for x86 floatingpoint compares:
33 * pnc_Leg => NP (ordered)
55 #include "iredges_t.h"
59 #include "raw_bitset.h"
63 #include "../besched.h"
64 #include "../benode.h"
66 #include "../be_dbgout.h"
67 #include "../beemitter.h"
68 #include "../begnuas.h"
70 #include "../be_dbgout.h"
72 #include "ia32_emitter.h"
73 #include "gen_ia32_emitter.h"
74 #include "gen_ia32_regalloc_if.h"
75 #include "ia32_nodes_attr.h"
76 #include "ia32_new_nodes.h"
77 #include "ia32_map_regs.h"
78 #include "ia32_architecture.h"
79 #include "bearch_ia32_t.h"
81 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
83 #define SNPRINTF_BUF_LEN 128
85 static const ia32_isa_t *isa;
86 static ia32_code_gen_t *cg;
87 static char pic_base_label[128];
88 static ir_label_t exc_label_id;
89 static int mark_spill_reload = 0;
92 /** Return the next block in Block schedule */
93 static ir_node *get_prev_block_sched(const ir_node *block)
95 return get_irn_link(block);
98 /** Checks if the current block is a fall-through target. */
99 static int is_fallthrough(const ir_node *cfgpred)
103 if (!is_Proj(cfgpred))
105 pred = get_Proj_pred(cfgpred);
106 if (is_ia32_SwitchJmp(pred))
113 * returns non-zero if the given block needs a label
114 * because of being a jump-target (and not a fall-through)
116 static int block_needs_label(const ir_node *block)
119 int n_cfgpreds = get_Block_n_cfgpreds(block);
121 if (has_Block_entity(block))
124 if (n_cfgpreds == 0) {
126 } else if (n_cfgpreds == 1) {
127 ir_node *cfgpred = get_Block_cfgpred(block, 0);
128 ir_node *cfgpred_block = get_nodes_block(cfgpred);
130 if (get_prev_block_sched(block) == cfgpred_block
131 && is_fallthrough(cfgpred)) {
140 * Returns the register at in position pos.
142 static const arch_register_t *get_in_reg(const ir_node *irn, int pos)
145 const arch_register_t *reg = NULL;
147 assert(get_irn_arity(irn) > pos && "Invalid IN position");
149 /* The out register of the operator at position pos is the
150 in register we need. */
151 op = get_irn_n(irn, pos);
153 reg = arch_get_irn_register(op);
155 assert(reg && "no in register found");
157 if (reg == &ia32_gp_regs[REG_GP_NOREG])
158 panic("trying to emit noreg for %+F input %d", irn, pos);
160 /* in case of unknown register: just return a valid register */
161 if (reg == &ia32_gp_regs[REG_GP_UKNWN]) {
162 const arch_register_req_t *req = arch_get_register_req(irn, pos);
164 if (arch_register_req_is(req, limited)) {
165 /* in case of limited requirements: get the first allowed register */
166 unsigned idx = rbitset_next(req->limited, 0, 1);
167 reg = arch_register_for_index(req->cls, idx);
169 /* otherwise get first register in class */
170 reg = arch_register_for_index(req->cls, 0);
178 * Returns the register at out position pos.
180 static const arch_register_t *get_out_reg(const ir_node *irn, int pos)
183 const arch_register_t *reg = NULL;
185 /* 1st case: irn is not of mode_T, so it has only */
186 /* one OUT register -> good */
187 /* 2nd case: irn is of mode_T -> collect all Projs and ask the */
188 /* Proj with the corresponding projnum for the register */
190 if (get_irn_mode(irn) != mode_T) {
192 reg = arch_get_irn_register(irn);
193 } else if (is_ia32_irn(irn)) {
194 reg = arch_irn_get_register(irn, pos);
196 const ir_edge_t *edge;
198 foreach_out_edge(irn, edge) {
199 proj = get_edge_src_irn(edge);
200 assert(is_Proj(proj) && "non-Proj from mode_T node");
201 if (get_Proj_proj(proj) == pos) {
202 reg = arch_get_irn_register(proj);
208 assert(reg && "no out register found");
213 * Add a number to a prefix. This number will not be used a second time.
215 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
217 static unsigned long id = 0;
218 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
222 /*************************************************************
224 * (_) | | / _| | | | |
225 * _ __ _ __ _ _ __ | |_| |_ | |__ ___| |_ __ ___ _ __
226 * | '_ \| '__| | '_ \| __| _| | '_ \ / _ \ | '_ \ / _ \ '__|
227 * | |_) | | | | | | | |_| | | | | | __/ | |_) | __/ |
228 * | .__/|_| |_|_| |_|\__|_| |_| |_|\___|_| .__/ \___|_|
231 *************************************************************/
234 * Emit the name of the 8bit low register
236 static void emit_8bit_register(const arch_register_t *reg)
238 const char *reg_name = arch_register_get_name(reg);
241 be_emit_char(reg_name[1]);
246 * Emit the name of the 8bit high register
248 static void emit_8bit_register_high(const arch_register_t *reg)
250 const char *reg_name = arch_register_get_name(reg);
253 be_emit_char(reg_name[1]);
257 static void emit_16bit_register(const arch_register_t *reg)
259 const char *reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
262 be_emit_string(reg_name);
266 * emit a register, possible shortened by a mode
268 * @param reg the register
269 * @param mode the mode of the register or NULL for full register
271 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
273 const char *reg_name;
276 int size = get_mode_size_bits(mode);
278 case 8: emit_8bit_register(reg); return;
279 case 16: emit_16bit_register(reg); return;
281 assert(mode_is_float(mode) || size == 32);
284 reg_name = arch_register_get_name(reg);
287 be_emit_string(reg_name);
290 void ia32_emit_source_register(const ir_node *node, int pos)
292 const arch_register_t *reg = get_in_reg(node, pos);
294 emit_register(reg, NULL);
297 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
299 be_gas_emit_entity(entity);
301 if (get_entity_owner(entity) == get_tls_type()) {
302 if (get_entity_visibility(entity) == ir_visibility_external) {
303 be_emit_cstring("@INDNTPOFF");
305 be_emit_cstring("@NTPOFF");
309 if (do_pic && !no_pic_adjust) {
311 be_emit_string(pic_base_label);
315 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
317 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
319 if (attr->symconst != NULL) {
322 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
324 if (attr->symconst == NULL || attr->offset != 0) {
325 if (attr->symconst != NULL) {
326 be_emit_irprintf("%+d", attr->offset);
328 be_emit_irprintf("0x%X", attr->offset);
333 static void emit_ia32_Immediate(const ir_node *node)
336 emit_ia32_Immediate_no_prefix(node);
339 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
341 const arch_register_t *reg;
342 const ir_node *in = get_irn_n(node, pos);
343 if (is_ia32_Immediate(in)) {
344 emit_ia32_Immediate(in);
348 reg = get_in_reg(node, pos);
349 emit_8bit_register(reg);
352 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
354 const arch_register_t *reg = get_in_reg(node, pos);
355 emit_8bit_register_high(reg);
358 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
360 const arch_register_t *reg;
361 const ir_node *in = get_irn_n(node, pos);
362 if (is_ia32_Immediate(in)) {
363 emit_ia32_Immediate(in);
367 reg = get_in_reg(node, pos);
368 emit_16bit_register(reg);
371 void ia32_emit_dest_register(const ir_node *node, int pos)
373 const arch_register_t *reg = get_out_reg(node, pos);
375 emit_register(reg, NULL);
378 void ia32_emit_dest_register_size(const ir_node *node, int pos)
380 const arch_register_t *reg = get_out_reg(node, pos);
382 emit_register(reg, get_ia32_ls_mode(node));
385 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
387 const arch_register_t *reg = get_out_reg(node, pos);
389 emit_register(reg, mode_Bu);
392 void ia32_emit_x87_register(const ir_node *node, int pos)
394 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
398 be_emit_string(attr->x87[pos]->name);
401 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
403 assert(mode_is_int(mode) || mode_is_reference(mode));
404 switch (get_mode_size_bits(mode)) {
405 case 8: be_emit_char('b'); return;
406 case 16: be_emit_char('w'); return;
407 case 32: be_emit_char('l'); return;
408 /* gas docu says q is the suffix but gcc, objdump and icc use ll
410 case 64: be_emit_cstring("ll"); return;
412 panic("Can't output mode_suffix for %+F", mode);
415 void ia32_emit_mode_suffix(const ir_node *node)
417 ir_mode *mode = get_ia32_ls_mode(node);
421 ia32_emit_mode_suffix_mode(mode);
424 void ia32_emit_x87_mode_suffix(const ir_node *node)
428 /* we only need to emit the mode on address mode */
429 if (get_ia32_op_type(node) == ia32_Normal)
432 mode = get_ia32_ls_mode(node);
433 assert(mode != NULL);
435 if (mode_is_float(mode)) {
436 switch (get_mode_size_bits(mode)) {
437 case 32: be_emit_char('s'); return;
438 case 64: be_emit_char('l'); return;
439 /* long doubles have different sizes due to alignment on different
443 case 128: be_emit_char('t'); return;
446 assert(mode_is_int(mode));
447 switch (get_mode_size_bits(mode)) {
448 case 16: be_emit_char('s'); return;
449 case 32: be_emit_char('l'); return;
450 /* gas docu says q is the suffix but gcc, objdump and icc use ll
452 case 64: be_emit_cstring("ll"); return;
455 panic("Can't output mode_suffix for %+F", mode);
458 static char get_xmm_mode_suffix(ir_mode *mode)
460 assert(mode_is_float(mode));
461 switch (get_mode_size_bits(mode)) {
464 default: panic("Invalid XMM mode");
468 void ia32_emit_xmm_mode_suffix(const ir_node *node)
470 ir_mode *mode = get_ia32_ls_mode(node);
471 assert(mode != NULL);
473 be_emit_char(get_xmm_mode_suffix(mode));
476 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
478 ir_mode *mode = get_ia32_ls_mode(node);
479 assert(mode != NULL);
480 be_emit_char(get_xmm_mode_suffix(mode));
483 void ia32_emit_extend_suffix(const ir_node *node)
485 ir_mode *mode = get_ia32_ls_mode(node);
486 if (get_mode_size_bits(mode) == 32)
488 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
489 ia32_emit_mode_suffix_mode(mode);
492 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
494 ir_node *in = get_irn_n(node, pos);
495 if (is_ia32_Immediate(in)) {
496 emit_ia32_Immediate(in);
498 const ir_mode *mode = get_ia32_ls_mode(node);
499 const arch_register_t *reg = get_in_reg(node, pos);
500 emit_register(reg, mode);
505 * Returns the target block for a control flow node.
507 static ir_node *get_cfop_target_block(const ir_node *irn)
509 assert(get_irn_mode(irn) == mode_X);
510 return get_irn_link(irn);
514 * Emits the target label for a control flow node.
516 static void ia32_emit_cfop_target(const ir_node *node)
518 ir_node *block = get_cfop_target_block(node);
519 be_gas_emit_block_name(block);
523 * positive conditions for signed compares
525 static const char *const cmp2condition_s[] = {
526 NULL, /* always false */
533 NULL /* always true */
537 * positive conditions for unsigned compares
539 static const char *const cmp2condition_u[] = {
540 NULL, /* always false */
547 NULL /* always true */
551 * Emit the suffix for a compare instruction.
553 static void ia32_emit_cmp_suffix(int pnc)
557 if (pnc == ia32_pn_Cmp_parity) {
562 if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
563 str = cmp2condition_u[pnc & 7];
565 str = cmp2condition_s[pnc & 7];
571 typedef enum ia32_emit_mod_t {
572 EMIT_RESPECT_LS = 1U << 0,
573 EMIT_ALTERNATE_AM = 1U << 1,
575 EMIT_HIGH_REG = 1U << 3,
576 EMIT_LOW_REG = 1U << 4
580 * Emits address mode.
582 void ia32_emit_am(const ir_node *node)
584 ir_entity *ent = get_ia32_am_sc(node);
585 int offs = get_ia32_am_offs_int(node);
586 ir_node *base = get_irn_n(node, n_ia32_base);
587 int has_base = !is_ia32_NoReg_GP(base);
588 ir_node *index = get_irn_n(node, n_ia32_index);
589 int has_index = !is_ia32_NoReg_GP(index);
591 /* just to be sure... */
592 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
596 const ia32_attr_t *attr = get_ia32_attr_const(node);
597 if (is_ia32_am_sc_sign(node))
599 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
602 /* also handle special case if nothing is set */
603 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
605 be_emit_irprintf("%+d", offs);
607 be_emit_irprintf("%d", offs);
611 if (has_base || has_index) {
616 const arch_register_t *reg = get_in_reg(node, n_ia32_base);
617 emit_register(reg, NULL);
620 /* emit index + scale */
622 const arch_register_t *reg = get_in_reg(node, n_ia32_index);
625 emit_register(reg, NULL);
627 scale = get_ia32_am_scale(node);
629 be_emit_irprintf(",%d", 1 << scale);
637 * fmt parameter output
638 * ---- ---------------------- ---------------------------------------------
640 * %AM <node> address mode of the node
641 * %AR const arch_register_t* address mode of the node or register
642 * %ASx <node> address mode of the node or source register x
643 * %Dx <node> destination register x
644 * %I <node> immediate of the node
645 * %L <node> control flow target of the node
646 * %M <node> mode suffix of the node
647 * %P int condition code
648 * %R const arch_register_t* register
649 * %Sx <node> source register x
650 * %s const char* string
651 * %u unsigned int unsigned int
652 * %d signed int signed int
655 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
656 * * modifier does not prefix immediates with $, but AM with *
657 * l modifier for %lu and %ld
658 * > modifier to output high 8bit register (ah, bh)
659 * < modifier to output low 8bit register (al, bl)
661 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
667 const char *start = fmt;
668 ia32_emit_mod_t mod = 0;
670 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
673 be_emit_string_len(start, fmt - start);
677 be_emit_finish_line_gas(node);
690 case '*': mod |= EMIT_ALTERNATE_AM; break;
691 case '#': mod |= EMIT_RESPECT_LS; break;
692 case 'l': mod |= EMIT_LONG; break;
693 case '>': mod |= EMIT_HIGH_REG; break;
694 case '<': mod |= EMIT_LOW_REG; break;
711 if (mod & EMIT_ALTERNATE_AM)
717 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
718 if (get_ia32_op_type(node) == ia32_AddrModeS) {
721 if (mod & EMIT_ALTERNATE_AM)
723 emit_register(reg, NULL);
729 if (get_ia32_op_type(node) == ia32_AddrModeS) {
733 assert(get_ia32_op_type(node) == ia32_Normal);
738 default: goto unknown;
745 const arch_register_t *reg;
747 if (*fmt < '0' || '9' <= *fmt)
751 reg = get_out_reg(node, pos);
752 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
757 if (!(mod & EMIT_ALTERNATE_AM))
759 emit_ia32_Immediate_no_prefix(node);
763 ia32_emit_cfop_target(node);
767 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
772 int pnc = va_arg(ap, int);
773 ia32_emit_cmp_suffix(pnc);
778 const arch_register_t *reg = va_arg(ap, const arch_register_t*);
779 if (mod & EMIT_HIGH_REG) {
780 emit_8bit_register_high(reg);
781 } else if (mod & EMIT_LOW_REG) {
782 emit_8bit_register(reg);
784 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
794 if (*fmt < '0' || '9' <= *fmt)
798 in = get_irn_n(node, pos);
799 if (is_ia32_Immediate(in)) {
800 if (!(mod & EMIT_ALTERNATE_AM))
802 emit_ia32_Immediate_no_prefix(in);
804 const arch_register_t *reg;
806 if (mod & EMIT_ALTERNATE_AM)
808 reg = get_in_reg(node, pos);
809 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
815 const char *str = va_arg(ap, const char*);
821 if (mod & EMIT_LONG) {
822 unsigned long num = va_arg(ap, unsigned long);
823 be_emit_irprintf("%lu", num);
825 unsigned num = va_arg(ap, unsigned);
826 be_emit_irprintf("%u", num);
831 if (mod & EMIT_LONG) {
832 long num = va_arg(ap, long);
833 be_emit_irprintf("%ld", num);
835 int num = va_arg(ap, int);
836 be_emit_irprintf("%d", num);
842 panic("unknown format conversion in ia32_emitf()");
850 * Emits registers and/or address mode of a binary operation.
852 void ia32_emit_binop(const ir_node *node)
854 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
855 ia32_emitf(node, "%#S4, %#AS3");
857 ia32_emitf(node, "%#AS4, %#S3");
862 * Emits registers and/or address mode of a binary operation.
864 void ia32_emit_x87_binop(const ir_node *node)
866 switch (get_ia32_op_type(node)) {
869 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
870 const arch_register_t *in1 = x87_attr->x87[0];
871 const arch_register_t *in = x87_attr->x87[1];
872 const arch_register_t *out = x87_attr->x87[2];
876 } else if (out == in) {
881 be_emit_string(arch_register_get_name(in));
882 be_emit_cstring(", %");
883 be_emit_string(arch_register_get_name(out));
891 assert(0 && "unsupported op type");
896 * Emits registers and/or address mode of a unary operation.
898 void ia32_emit_unop(const ir_node *node, int pos)
902 ia32_emitf(node, fmt);
905 static void emit_ia32_IMul(const ir_node *node)
907 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
908 const arch_register_t *out_reg = get_out_reg(node, pn_ia32_IMul_res);
910 /* do we need the 3-address form? */
911 if (is_ia32_NoReg_GP(left) ||
912 get_in_reg(node, n_ia32_IMul_left) != out_reg) {
913 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
915 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
920 * walks up a tree of copies/perms/spills/reloads to find the original value
921 * that is moved around
923 static ir_node *find_original_value(ir_node *node)
925 if (irn_visited(node))
928 mark_irn_visited(node);
929 if (be_is_Copy(node)) {
930 return find_original_value(be_get_Copy_op(node));
931 } else if (be_is_CopyKeep(node)) {
932 return find_original_value(be_get_CopyKeep_op(node));
933 } else if (is_Proj(node)) {
934 ir_node *pred = get_Proj_pred(node);
935 if (be_is_Perm(pred)) {
936 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
937 } else if (be_is_MemPerm(pred)) {
938 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
939 } else if (is_ia32_Load(pred)) {
940 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
944 } else if (is_ia32_Store(node)) {
945 return find_original_value(get_irn_n(node, n_ia32_Store_val));
946 } else if (is_Phi(node)) {
948 arity = get_irn_arity(node);
949 for (i = 0; i < arity; ++i) {
950 ir_node *in = get_irn_n(node, i);
951 ir_node *res = find_original_value(in);
962 static int determine_final_pnc(const ir_node *node, int flags_pos, int pnc)
964 ir_node *flags = get_irn_n(node, flags_pos);
965 const ia32_attr_t *flags_attr;
966 flags = skip_Proj(flags);
968 if (is_ia32_Sahf(flags)) {
969 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
970 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
971 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
972 inc_irg_visited(current_ir_graph);
973 cmp = find_original_value(cmp);
975 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
976 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
979 flags_attr = get_ia32_attr_const(cmp);
980 if (flags_attr->data.ins_permuted)
981 pnc = get_mirrored_pnc(pnc);
982 pnc |= ia32_pn_Cmp_float;
983 } else if (is_ia32_Ucomi(flags) || is_ia32_Fucomi(flags)
984 || is_ia32_Fucompi(flags)) {
985 flags_attr = get_ia32_attr_const(flags);
987 if (flags_attr->data.ins_permuted)
988 pnc = get_mirrored_pnc(pnc);
989 pnc |= ia32_pn_Cmp_float;
991 flags_attr = get_ia32_attr_const(flags);
993 if (flags_attr->data.ins_permuted)
994 pnc = get_mirrored_pnc(pnc);
995 if (flags_attr->data.cmp_unsigned)
996 pnc |= ia32_pn_Cmp_unsigned;
1002 static pn_Cmp ia32_get_negated_pnc(pn_Cmp pnc)
1004 ir_mode *mode = pnc & ia32_pn_Cmp_float ? mode_F : mode_Iu;
1005 return get_negated_pnc(pnc, mode);
1008 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
1010 pn_Cmp pnc = get_ia32_condcode(node);
1011 pnc = determine_final_pnc(node, flags_pos, pnc);
1013 ia32_emit_cmp_suffix(pnc);
1017 * Emits an exception label for a given node.
1019 static void ia32_emit_exc_label(const ir_node *node)
1021 be_emit_string(be_gas_insn_label_prefix());
1022 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
1026 * Returns the Proj with projection number proj and NOT mode_M
1028 static ir_node *get_proj(const ir_node *node, long proj)
1030 const ir_edge_t *edge;
1033 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
1035 foreach_out_edge(node, edge) {
1036 src = get_edge_src_irn(edge);
1038 assert(is_Proj(src) && "Proj expected");
1039 if (get_irn_mode(src) == mode_M)
1042 if (get_Proj_proj(src) == proj)
1048 static int can_be_fallthrough(const ir_node *node)
1050 ir_node *target_block = get_cfop_target_block(node);
1051 ir_node *block = get_nodes_block(node);
1052 return get_prev_block_sched(target_block) == block;
1056 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
1058 static void emit_ia32_Jcc(const ir_node *node)
1060 int need_parity_label = 0;
1061 const ir_node *proj_true;
1062 const ir_node *proj_false;
1063 const ir_node *block;
1064 pn_Cmp pnc = get_ia32_condcode(node);
1066 pnc = determine_final_pnc(node, 0, pnc);
1068 /* get both Projs */
1069 proj_true = get_proj(node, pn_ia32_Jcc_true);
1070 assert(proj_true && "Jcc without true Proj");
1072 proj_false = get_proj(node, pn_ia32_Jcc_false);
1073 assert(proj_false && "Jcc without false Proj");
1075 block = get_nodes_block(node);
1077 if (can_be_fallthrough(proj_true)) {
1078 /* exchange both proj's so the second one can be omitted */
1079 const ir_node *t = proj_true;
1081 proj_true = proj_false;
1083 pnc = ia32_get_negated_pnc(pnc);
1086 if (pnc & ia32_pn_Cmp_float) {
1087 /* Some floating point comparisons require a test of the parity flag,
1088 * which indicates that the result is unordered */
1089 switch (pnc & 0x0f) {
1091 ia32_emitf(proj_true, "\tjp %L\n");
1096 ia32_emitf(proj_true, "\tjnp %L\n");
1102 /* we need a local label if the false proj is a fallthrough
1103 * as the falseblock might have no label emitted then */
1104 if (can_be_fallthrough(proj_false)) {
1105 need_parity_label = 1;
1106 ia32_emitf(proj_false, "\tjp 1f\n");
1108 ia32_emitf(proj_false, "\tjp %L\n");
1115 ia32_emitf(proj_true, "\tjp %L\n");
1123 ia32_emitf(proj_true, "\tj%P %L\n", pnc);
1126 if (need_parity_label) {
1127 ia32_emitf(NULL, "1:\n");
1130 /* the second Proj might be a fallthrough */
1131 if (can_be_fallthrough(proj_false)) {
1132 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
1134 ia32_emitf(proj_false, "\tjmp %L\n");
1139 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1142 static void emit_ia32_Setcc(const ir_node *node)
1144 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
1146 pn_Cmp pnc = get_ia32_condcode(node);
1147 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
1148 if (pnc & ia32_pn_Cmp_float) {
1149 switch (pnc & 0x0f) {
1151 ia32_emitf(node, "\tsetp %#R\n", dreg);
1155 ia32_emitf(node, "\tsetnp %#R\n", dreg);
1161 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1162 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1163 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1169 ia32_emitf(node, "\tset%P %<R\n", pnc, dreg);
1170 ia32_emitf(node, "\tsetp %>R\n", dreg);
1171 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1178 ia32_emitf(node, "\tset%P %#R\n", pnc, dreg);
1181 static void emit_ia32_CMovcc(const ir_node *node)
1183 const ia32_attr_t *attr = get_ia32_attr_const(node);
1184 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
1185 pn_Cmp pnc = get_ia32_condcode(node);
1186 const arch_register_t *in_true;
1187 const arch_register_t *in_false;
1189 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
1190 /* although you can't set ins_permuted in the constructor it might still
1191 * be set by memory operand folding
1192 * Permuting inputs of a cmov means the condition is negated!
1194 if (attr->data.ins_permuted)
1195 pnc = ia32_get_negated_pnc(pnc);
1197 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1198 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1200 /* should be same constraint fullfilled? */
1201 if (out == in_false) {
1202 /* yes -> nothing to do */
1203 } else if (out == in_true) {
1204 const arch_register_t *tmp;
1206 assert(get_ia32_op_type(node) == ia32_Normal);
1208 pnc = ia32_get_negated_pnc(pnc);
1215 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1218 /* TODO: handling of Nans isn't correct yet */
1219 if (pnc & ia32_pn_Cmp_float) {
1220 switch (pnc & 0x0f) {
1229 panic("CMov with floatingpoint compare/parity not supported yet");
1233 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", pnc, in_true, out);
1236 /*********************************************************
1239 * ___ _ __ ___ _| |_ _ _ _ _ __ ___ _ __ ___
1240 * / _ \ '_ ` _ \| | __| | | | | | '_ ` _ \| '_ \/ __|
1241 * | __/ | | | | | | |_ | | |_| | | | | | | |_) \__ \
1242 * \___|_| |_| |_|_|\__| | |\__,_|_| |_| |_| .__/|___/
1245 *********************************************************/
1247 /* jump table entry (target and corresponding number) */
1248 typedef struct _branch_t {
1253 /* jump table for switch generation */
1254 typedef struct _jmp_tbl_t {
1255 ir_node *defProj; /**< default target */
1256 long min_value; /**< smallest switch case */
1257 long max_value; /**< largest switch case */
1258 long num_branches; /**< number of jumps */
1259 char label[SNPRINTF_BUF_LEN]; /**< label of the jump table */
1260 branch_t *branches; /**< jump array */
1264 * Compare two variables of type branch_t. Used to sort all switch cases
1266 static int ia32_cmp_branch_t(const void *a, const void *b)
1268 branch_t *b1 = (branch_t *)a;
1269 branch_t *b2 = (branch_t *)b;
1271 if (b1->value <= b2->value)
1277 static void generate_jump_table(jmp_tbl_t *tbl, const ir_node *node)
1283 const ir_edge_t *edge;
1285 /* fill the table structure */
1286 get_unique_label(tbl->label, SNPRINTF_BUF_LEN, "TBL_");
1287 tbl->defProj = NULL;
1288 tbl->num_branches = get_irn_n_edges(node) - 1;
1289 tbl->branches = XMALLOCNZ(branch_t, tbl->num_branches);
1290 tbl->min_value = LONG_MAX;
1291 tbl->max_value = LONG_MIN;
1293 default_pn = get_ia32_condcode(node);
1295 /* go over all proj's and collect them */
1296 foreach_out_edge(node, edge) {
1297 proj = get_edge_src_irn(edge);
1298 assert(is_Proj(proj) && "Only proj allowed at SwitchJmp");
1300 pnc = get_Proj_proj(proj);
1302 /* check for default proj */
1303 if (pnc == default_pn) {
1304 assert(tbl->defProj == NULL && "found two default Projs at SwitchJmp");
1305 tbl->defProj = proj;
1307 tbl->min_value = pnc < tbl->min_value ? pnc : tbl->min_value;
1308 tbl->max_value = pnc > tbl->max_value ? pnc : tbl->max_value;
1310 /* create branch entry */
1311 tbl->branches[i].target = proj;
1312 tbl->branches[i].value = pnc;
1317 assert(i == tbl->num_branches);
1319 /* sort the branches by their number */
1320 qsort(tbl->branches, tbl->num_branches, sizeof(tbl->branches[0]), ia32_cmp_branch_t);
1324 * Emits code for a SwitchJmp (creates a jump table if
1325 * possible otherwise a cmp-jmp cascade). Port from
1328 static void emit_ia32_SwitchJmp(const ir_node *node)
1330 unsigned long interval;
1334 /* fill the table structure */
1335 generate_jump_table(&tbl, node);
1337 /* two-complement's magic make this work without overflow */
1338 interval = tbl.max_value - tbl.min_value;
1340 /* emit the table */
1341 ia32_emitf(node, "\tcmpl $%u, %S0\n", interval);
1342 ia32_emitf(tbl.defProj, "\tja %L\n");
1344 if (tbl.num_branches > 1) {
1346 ia32_emitf(node, "\tjmp *%s(,%S0,4)\n", tbl.label);
1348 be_gas_emit_switch_section(GAS_SECTION_RODATA);
1349 ia32_emitf(NULL, "\t.align 4\n");
1350 ia32_emitf(NULL, "%s:\n", tbl.label);
1352 last_value = tbl.branches[0].value;
1353 for (i = 0; i != tbl.num_branches; ++i) {
1354 while (last_value != tbl.branches[i].value) {
1355 ia32_emitf(tbl.defProj, ".long %L\n");
1358 ia32_emitf(tbl.branches[i].target, ".long %L\n");
1361 be_gas_emit_switch_section(GAS_SECTION_TEXT);
1363 /* one jump is enough */
1364 ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
1371 * Emits code for a unconditional jump.
1373 static void emit_ia32_Jmp(const ir_node *node)
1377 /* for now, the code works for scheduled and non-schedules blocks */
1378 block = get_nodes_block(node);
1380 /* we have a block schedule */
1381 if (can_be_fallthrough(node)) {
1382 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1384 ia32_emitf(node, "\tjmp %L\n");
1389 * Emit an inline assembler operand.
1391 * @param node the ia32_ASM node
1392 * @param s points to the operand (a %c)
1394 * @return pointer to the first char in s NOT in the current operand
1396 static const char* emit_asm_operand(const ir_node *node, const char *s)
1398 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1399 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1401 const arch_register_t *reg;
1402 const ia32_asm_reg_t *asm_regs = attr->register_map;
1403 const ia32_asm_reg_t *asm_reg;
1404 const char *reg_name;
1413 /* parse modifiers */
1416 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1441 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1448 sscanf(s, "%d%n", &num, &p);
1450 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1457 if (num < 0 || ARR_LEN(asm_regs) <= num) {
1459 "Error: Custom assembler references invalid input/output (%+F)\n",
1463 asm_reg = & asm_regs[num];
1464 assert(asm_reg->valid);
1467 if (asm_reg->use_input == 0) {
1468 reg = get_out_reg(node, asm_reg->inout_pos);
1470 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1472 /* might be an immediate value */
1473 if (is_ia32_Immediate(pred)) {
1474 emit_ia32_Immediate(pred);
1477 reg = get_in_reg(node, asm_reg->inout_pos);
1481 "Warning: no register assigned for %d asm op (%+F)\n",
1486 if (asm_reg->memory) {
1491 if (modifier != 0) {
1495 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit, reg);
1498 reg_name = ia32_get_mapped_reg_name(isa->regs_8bit_high, reg);
1501 reg_name = ia32_get_mapped_reg_name(isa->regs_16bit, reg);
1504 panic("Invalid asm op modifier");
1506 be_emit_string(reg_name);
1508 emit_register(reg, asm_reg->mode);
1511 if (asm_reg->memory) {
1519 * Emits code for an ASM pseudo op.
1521 static void emit_ia32_Asm(const ir_node *node)
1523 const void *gen_attr = get_irn_generic_attr_const(node);
1524 const ia32_asm_attr_t *attr
1525 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1526 ident *asm_text = attr->asm_text;
1527 const char *s = get_id_str(asm_text);
1529 ia32_emitf(node, "#APP\t\n");
1536 s = emit_asm_operand(node, s);
1542 ia32_emitf(NULL, "\n#NO_APP\n");
1545 /**********************************
1548 * | | ___ _ __ _ _| |_) |
1549 * | | / _ \| '_ \| | | | _ <
1550 * | |___| (_) | |_) | |_| | |_) |
1551 * \_____\___/| .__/ \__, |____/
1554 **********************************/
1557 * Emit movsb/w instructions to make mov count divideable by 4
1559 static void emit_CopyB_prolog(unsigned size)
1562 ia32_emitf(NULL, "\tmovsb\n");
1564 ia32_emitf(NULL, "\tmovsw\n");
1568 * Emit rep movsd instruction for memcopy.
1570 static void emit_ia32_CopyB(const ir_node *node)
1572 unsigned size = get_ia32_copyb_size(node);
1574 emit_CopyB_prolog(size);
1575 ia32_emitf(node, "\trep movsd\n");
1579 * Emits unrolled memcopy.
1581 static void emit_ia32_CopyB_i(const ir_node *node)
1583 unsigned size = get_ia32_copyb_size(node);
1585 emit_CopyB_prolog(size);
1589 ia32_emitf(NULL, "\tmovsd\n");
1595 /***************************
1599 * | | / _ \| '_ \ \ / /
1600 * | |___| (_) | | | \ V /
1601 * \_____\___/|_| |_|\_/
1603 ***************************/
1606 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1608 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1611 ir_mode *ls_mode = get_ia32_ls_mode(node);
1612 int ls_bits = get_mode_size_bits(ls_mode);
1613 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1615 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1618 static void emit_ia32_Conv_I2FP(const ir_node *node)
1620 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1623 static void emit_ia32_Conv_FP2I(const ir_node *node)
1625 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1628 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1630 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1634 * Emits code for an Int conversion.
1636 static void emit_ia32_Conv_I2I(const ir_node *node)
1638 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1639 int signed_mode = mode_is_signed(smaller_mode);
1640 const char *sign_suffix;
1642 assert(!mode_is_float(smaller_mode));
1644 sign_suffix = signed_mode ? "s" : "z";
1645 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1651 static void emit_ia32_Call(const ir_node *node)
1653 /* Special case: Call must not have its immediates prefixed by $, instead
1654 * address mode is prefixed by *. */
1655 ia32_emitf(node, "\tcall %*AS3\n");
1659 /*******************************************
1662 * | |__ ___ _ __ ___ __| | ___ ___
1663 * | '_ \ / _ \ '_ \ / _ \ / _` |/ _ \/ __|
1664 * | |_) | __/ | | | (_) | (_| | __/\__ \
1665 * |_.__/ \___|_| |_|\___/ \__,_|\___||___/
1667 *******************************************/
1670 * Emits code to increase stack pointer.
1672 static void emit_be_IncSP(const ir_node *node)
1674 int offs = be_get_IncSP_offset(node);
1680 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1682 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1686 static inline bool is_unknown_reg(const arch_register_t *reg)
1688 if (reg == &ia32_gp_regs[REG_GP_UKNWN]
1689 || reg == &ia32_xmm_regs[REG_XMM_UKNWN]
1690 || reg == &ia32_vfp_regs[REG_VFP_UKNWN])
1697 * Emits code for Copy/CopyKeep.
1699 static void Copy_emitter(const ir_node *node, const ir_node *op)
1701 const arch_register_t *in = arch_get_irn_register(op);
1702 const arch_register_t *out = arch_get_irn_register(node);
1707 if (is_unknown_reg(in))
1709 /* copies of vf nodes aren't real... */
1710 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1713 if (get_irn_mode(node) == mode_E) {
1714 ia32_emitf(node, "\tmovsd %R, %R\n", in, out);
1716 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1720 static void emit_be_Copy(const ir_node *node)
1722 Copy_emitter(node, be_get_Copy_op(node));
1725 static void emit_be_CopyKeep(const ir_node *node)
1727 Copy_emitter(node, be_get_CopyKeep_op(node));
1731 * Emits code for exchange.
1733 static void emit_be_Perm(const ir_node *node)
1735 const arch_register_t *in0, *in1;
1736 const arch_register_class_t *cls0, *cls1;
1738 in0 = arch_get_irn_register(get_irn_n(node, 0));
1739 in1 = arch_get_irn_register(get_irn_n(node, 1));
1741 cls0 = arch_register_get_class(in0);
1742 cls1 = arch_register_get_class(in1);
1744 assert(cls0 == cls1 && "Register class mismatch at Perm");
1746 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1747 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1748 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1749 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1750 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1751 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1752 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1754 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1757 panic("unexpected register class in be_Perm (%+F)", node);
1762 * Emits code for Constant loading.
1764 static void emit_ia32_Const(const ir_node *node)
1766 ia32_emitf(node, "\tmovl %I, %D0\n");
1770 * Emits code to load the TLS base
1772 static void emit_ia32_LdTls(const ir_node *node)
1774 ia32_emitf(node, "\tmovl %%gs:0, %D0\n");
1777 /* helper function for emit_ia32_Minus64Bit */
1778 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1780 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1783 /* helper function for emit_ia32_Minus64Bit */
1784 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1786 ia32_emitf(node, "\tnegl %R\n", reg);
1789 /* helper function for emit_ia32_Minus64Bit */
1790 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1792 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1795 /* helper function for emit_ia32_Minus64Bit */
1796 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1798 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1801 /* helper function for emit_ia32_Minus64Bit */
1802 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1804 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1807 /* helper function for emit_ia32_Minus64Bit */
1808 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1810 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1813 static void emit_ia32_Minus64Bit(const ir_node *node)
1815 const arch_register_t *in_lo = get_in_reg(node, 0);
1816 const arch_register_t *in_hi = get_in_reg(node, 1);
1817 const arch_register_t *out_lo = get_out_reg(node, 0);
1818 const arch_register_t *out_hi = get_out_reg(node, 1);
1820 if (out_lo == in_lo) {
1821 if (out_hi != in_hi) {
1822 /* a -> a, b -> d */
1825 /* a -> a, b -> b */
1828 } else if (out_lo == in_hi) {
1829 if (out_hi == in_lo) {
1830 /* a -> b, b -> a */
1831 emit_xchg(node, in_lo, in_hi);
1834 /* a -> b, b -> d */
1835 emit_mov(node, in_hi, out_hi);
1836 emit_mov(node, in_lo, out_lo);
1840 if (out_hi == in_lo) {
1841 /* a -> c, b -> a */
1842 emit_mov(node, in_lo, out_lo);
1844 } else if (out_hi == in_hi) {
1845 /* a -> c, b -> b */
1846 emit_mov(node, in_lo, out_lo);
1849 /* a -> c, b -> d */
1850 emit_mov(node, in_lo, out_lo);
1856 emit_neg( node, out_hi);
1857 emit_neg( node, out_lo);
1858 emit_sbb0(node, out_hi);
1862 emit_zero(node, out_hi);
1863 emit_neg( node, out_lo);
1864 emit_sbb( node, in_hi, out_hi);
1867 static void emit_ia32_GetEIP(const ir_node *node)
1869 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1870 ia32_emitf(NULL, "%s:\n", pic_base_label);
1871 ia32_emitf(node, "\tpopl %D0\n");
1874 static void emit_ia32_ClimbFrame(const ir_node *node)
1876 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1878 ia32_emitf(node, "\tmovl %S0, %D0\n");
1879 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1880 be_gas_emit_block_name(node);
1881 be_emit_cstring(":\n");
1882 be_emit_write_line();
1883 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1884 ia32_emitf(node, "\tdec %S1\n");
1885 be_emit_cstring("\tjnz ");
1886 be_gas_emit_block_name(node);
1887 be_emit_finish_line_gas(node);
1890 static void emit_be_Return(const ir_node *node)
1892 unsigned pop = be_Return_get_pop(node);
1894 if (pop > 0 || be_Return_get_emit_pop(node)) {
1895 ia32_emitf(node, "\tret $%u\n", pop);
1897 ia32_emitf(node, "\tret\n");
1901 static void emit_Nothing(const ir_node *node)
1907 /***********************************************************************************
1910 * _ __ ___ __ _ _ _ __ | |_ _ __ __ _ _ __ ___ _____ _____ _ __| | __
1911 * | '_ ` _ \ / _` | | '_ \ | _| '__/ _` | '_ ` _ \ / _ \ \ /\ / / _ \| '__| |/ /
1912 * | | | | | | (_| | | | | | | | | | | (_| | | | | | | __/\ V V / (_) | | | <
1913 * |_| |_| |_|\__,_|_|_| |_| |_| |_| \__,_|_| |_| |_|\___| \_/\_/ \___/|_| |_|\_\
1915 ***********************************************************************************/
1918 * Enters the emitter functions for handled nodes into the generic
1919 * pointer of an opcode.
1921 static void ia32_register_emitters(void)
1923 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1924 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1925 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1926 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1927 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1928 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1930 /* first clear the generic function pointer for all ops */
1931 clear_irp_opcodes_generic_func();
1933 /* register all emitter functions defined in spec */
1934 ia32_register_spec_emitters();
1936 /* other ia32 emitter functions */
1937 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1942 IA32_EMIT(Conv_FP2FP);
1943 IA32_EMIT(Conv_FP2I);
1944 IA32_EMIT(Conv_I2FP);
1945 IA32_EMIT(Conv_I2I);
1953 IA32_EMIT(Minus64Bit);
1954 IA32_EMIT(SwitchJmp);
1955 IA32_EMIT(ClimbFrame);
1958 /* benode emitter */
1979 typedef void (*emit_func_ptr) (const ir_node *);
1982 * Assign and emit an exception label if the current instruction can fail.
1984 static void ia32_assign_exc_label(ir_node *node)
1986 /* assign a new ID to the instruction */
1987 set_ia32_exc_label_id(node, ++exc_label_id);
1989 ia32_emit_exc_label(node);
1991 be_emit_pad_comment();
1992 be_emit_cstring("/* exception to Block ");
1993 ia32_emit_cfop_target(node);
1994 be_emit_cstring(" */\n");
1995 be_emit_write_line();
1999 * Emits code for a node.
2001 static void ia32_emit_node(ir_node *node)
2003 ir_op *op = get_irn_op(node);
2005 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
2007 if (is_ia32_irn(node)) {
2008 if (get_ia32_exc_label(node)) {
2009 /* emit the exception label of this instruction */
2010 ia32_assign_exc_label(node);
2012 if (mark_spill_reload) {
2013 if (is_ia32_is_spill(node)) {
2014 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
2016 if (is_ia32_is_reload(node)) {
2017 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
2019 if (is_ia32_is_remat(node)) {
2020 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
2024 if (op->ops.generic) {
2025 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
2027 be_dbg_set_dbg_info(get_irn_dbg_info(node));
2032 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
2038 * Emits gas alignment directives
2040 static void ia32_emit_alignment(unsigned align, unsigned skip)
2042 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
2046 * Emits gas alignment directives for Labels depended on cpu architecture.
2048 static void ia32_emit_align_label(void)
2050 unsigned align = ia32_cg_config.label_alignment;
2051 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
2052 ia32_emit_alignment(align, maximum_skip);
2056 * Test whether a block should be aligned.
2057 * For cpus in the P4/Athlon class it is useful to align jump labels to
2058 * 16 bytes. However we should only do that if the alignment nops before the
2059 * label aren't executed more often than we have jumps to the label.
2061 static int should_align_block(const ir_node *block)
2063 static const double DELTA = .0001;
2064 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2065 ir_node *prev = get_prev_block_sched(block);
2067 double prev_freq = 0; /**< execfreq of the fallthrough block */
2068 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
2071 if (exec_freq == NULL)
2073 if (ia32_cg_config.label_alignment_factor <= 0)
2076 block_freq = get_block_execfreq(exec_freq, block);
2077 if (block_freq < DELTA)
2080 n_cfgpreds = get_Block_n_cfgpreds(block);
2081 for (i = 0; i < n_cfgpreds; ++i) {
2082 const ir_node *pred = get_Block_cfgpred_block(block, i);
2083 double pred_freq = get_block_execfreq(exec_freq, pred);
2086 prev_freq += pred_freq;
2088 jmp_freq += pred_freq;
2092 if (prev_freq < DELTA && !(jmp_freq < DELTA))
2095 jmp_freq /= prev_freq;
2097 return jmp_freq > ia32_cg_config.label_alignment_factor;
2101 * Emit the block header for a block.
2103 * @param block the block
2104 * @param prev_block the previous block
2106 static void ia32_emit_block_header(ir_node *block)
2108 ir_graph *irg = current_ir_graph;
2109 int need_label = block_needs_label(block);
2111 ir_exec_freq *exec_freq = cg->birg->exec_freq;
2113 if (block == get_irg_end_block(irg))
2116 if (ia32_cg_config.label_alignment > 0) {
2117 /* align the current block if:
2118 * a) if should be aligned due to its execution frequency
2119 * b) there is no fall-through here
2121 if (should_align_block(block)) {
2122 ia32_emit_align_label();
2124 /* if the predecessor block has no fall-through,
2125 we can always align the label. */
2127 int has_fallthrough = 0;
2129 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
2130 ir_node *cfg_pred = get_Block_cfgpred(block, i);
2131 if (can_be_fallthrough(cfg_pred)) {
2132 has_fallthrough = 1;
2137 if (!has_fallthrough)
2138 ia32_emit_align_label();
2143 be_gas_emit_block_name(block);
2146 be_emit_pad_comment();
2147 be_emit_cstring(" /* ");
2149 be_emit_cstring("\t/* ");
2150 be_gas_emit_block_name(block);
2151 be_emit_cstring(": ");
2154 be_emit_cstring("preds:");
2156 /* emit list of pred blocks in comment */
2157 arity = get_irn_arity(block);
2159 be_emit_cstring(" none");
2161 for (i = 0; i < arity; ++i) {
2162 ir_node *predblock = get_Block_cfgpred_block(block, i);
2163 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
2166 if (exec_freq != NULL) {
2167 be_emit_irprintf(", freq: %f",
2168 get_block_execfreq(exec_freq, block));
2170 be_emit_cstring(" */\n");
2171 be_emit_write_line();
2175 * Walks over the nodes in a block connected by scheduling edges
2176 * and emits code for each node.
2178 static void ia32_gen_block(ir_node *block)
2182 ia32_emit_block_header(block);
2184 /* emit the contents of the block */
2185 be_dbg_set_dbg_info(get_irn_dbg_info(block));
2186 sched_foreach(block, node) {
2187 ia32_emit_node(node);
2191 typedef struct exc_entry {
2192 ir_node *exc_instr; /** The instruction that can issue an exception. */
2193 ir_node *block; /** The block to call then. */
2198 * Sets labels for control flow nodes (jump target).
2199 * Links control predecessors to there destination blocks.
2201 static void ia32_gen_labels(ir_node *block, void *data)
2203 exc_entry **exc_list = data;
2207 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
2208 pred = get_Block_cfgpred(block, n);
2209 set_irn_link(pred, block);
2211 pred = skip_Proj(pred);
2212 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
2217 ARR_APP1(exc_entry, *exc_list, e);
2218 set_irn_link(pred, block);
2224 * Compare two exception_entries.
2226 static int cmp_exc_entry(const void *a, const void *b)
2228 const exc_entry *ea = a;
2229 const exc_entry *eb = b;
2231 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
2237 * Main driver. Emits the code for one routine.
2239 void ia32_gen_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
2241 ir_entity *entity = get_irg_entity(irg);
2242 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
2247 do_pic = cg->birg->main_env->options->pic;
2249 be_gas_elf_type_char = '@';
2251 ia32_register_emitters();
2253 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
2255 be_dbg_method_begin(entity, be_abi_get_stack_layout(cg->birg->abi));
2256 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
2258 /* we use links to point to target blocks */
2259 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
2260 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
2262 /* initialize next block links */
2263 n = ARR_LEN(cg->blk_sched);
2264 for (i = 0; i < n; ++i) {
2265 ir_node *block = cg->blk_sched[i];
2266 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
2268 set_irn_link(block, prev);
2271 for (i = 0; i < n; ++i) {
2272 ir_node *block = cg->blk_sched[i];
2274 ia32_gen_block(block);
2277 be_gas_emit_function_epilog(entity);
2278 be_dbg_method_end();
2280 be_emit_write_line();
2282 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
2284 /* Sort the exception table using the exception label id's.
2285 Those are ascending with ascending addresses. */
2286 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
2290 for (i = 0; i < ARR_LEN(exc_list); ++i) {
2291 be_emit_cstring("\t.long ");
2292 ia32_emit_exc_label(exc_list[i].exc_instr);
2294 be_emit_cstring("\t.long ");
2295 be_gas_emit_block_name(exc_list[i].block);
2299 DEL_ARR_F(exc_list);
2302 static const lc_opt_table_entry_t ia32_emitter_options[] = {
2303 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2307 /* ==== Experimental binary emitter ==== */
2309 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2310 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2311 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2312 static unsigned char pnc_map_signed[8];
2313 static unsigned char pnc_map_unsigned[8];
2315 static void build_reg_map(void)
2317 reg_gp_map[REG_EAX] = 0x0;
2318 reg_gp_map[REG_ECX] = 0x1;
2319 reg_gp_map[REG_EDX] = 0x2;
2320 reg_gp_map[REG_EBX] = 0x3;
2321 reg_gp_map[REG_ESP] = 0x4;
2322 reg_gp_map[REG_EBP] = 0x5;
2323 reg_gp_map[REG_ESI] = 0x6;
2324 reg_gp_map[REG_EDI] = 0x7;
2326 pnc_map_signed[pn_Cmp_Eq] = 0x04;
2327 pnc_map_signed[pn_Cmp_Lt] = 0x0C;
2328 pnc_map_signed[pn_Cmp_Le] = 0x0E;
2329 pnc_map_signed[pn_Cmp_Gt] = 0x0F;
2330 pnc_map_signed[pn_Cmp_Ge] = 0x0D;
2331 pnc_map_signed[pn_Cmp_Lg] = 0x05;
2333 pnc_map_unsigned[pn_Cmp_Eq] = 0x04;
2334 pnc_map_unsigned[pn_Cmp_Lt] = 0x02;
2335 pnc_map_unsigned[pn_Cmp_Le] = 0x06;
2336 pnc_map_unsigned[pn_Cmp_Gt] = 0x07;
2337 pnc_map_unsigned[pn_Cmp_Ge] = 0x03;
2338 pnc_map_unsigned[pn_Cmp_Lg] = 0x05;
2341 /** Returns the encoding for a pnc field. */
2342 static unsigned char pnc2cc(int pnc)
2345 if (pnc == ia32_pn_Cmp_parity) {
2347 } else if (pnc & ia32_pn_Cmp_float || pnc & ia32_pn_Cmp_unsigned) {
2348 cc = pnc_map_unsigned[pnc & 0x07];
2350 cc = pnc_map_signed[pnc & 0x07];
2356 /** Sign extension bit values for binops */
2358 UNSIGNED_IMM = 0, /**< unsigned immediate */
2359 SIGNEXT_IMM = 2, /**< sign extended immediate */
2362 /** The mod encoding of the ModR/M */
2364 MOD_IND = 0x00, /**< [reg1] */
2365 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2366 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2367 MOD_REG = 0xC0 /**< reg1 */
2370 /** create R/M encoding for ModR/M */
2371 #define ENC_RM(x) (x)
2372 /** create REG encoding for ModR/M */
2373 #define ENC_REG(x) ((x) << 3)
2375 /** create encoding for a SIB byte */
2376 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2378 /* Node: The following routines are supposed to append bytes, words, dwords
2379 to the output stream.
2380 Currently the implementation is stupid in that it still creates output
2381 for an "assembler" in the form of .byte, .long
2382 We will change this when enough infrastructure is there to create complete
2383 machine code in memory/object files */
2385 static void bemit8(const unsigned char byte)
2387 be_emit_irprintf("\t.byte 0x%x\n", byte);
2388 be_emit_write_line();
2391 static void bemit16(const unsigned short u16)
2393 be_emit_irprintf("\t.word 0x%x\n", u16);
2394 be_emit_write_line();
2397 static void bemit32(const unsigned u32)
2399 be_emit_irprintf("\t.long 0x%x\n", u32);
2400 be_emit_write_line();
2404 * Emit address of an entity. If @p is_relative is true then a relative
2405 * offset from behind the address to the entity is created.
2407 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2410 if (entity == NULL) {
2415 /* the final version should remember the position in the bytestream
2416 and patch it with the correct address at linktime... */
2417 be_emit_cstring("\t.long ");
2420 be_gas_emit_entity(entity);
2422 if (get_entity_owner(entity) == get_tls_type()) {
2423 if (get_entity_visibility(entity) == ir_visibility_external) {
2424 be_emit_cstring("@INDNTPOFF");
2426 be_emit_cstring("@NTPOFF");
2431 be_emit_cstring("-.");
2436 be_emit_irprintf("%+d", offset);
2439 be_emit_write_line();
2442 static void bemit_jmp_destination(const ir_node *dest_block)
2444 be_emit_cstring("\t.long ");
2445 be_gas_emit_block_name(dest_block);
2446 be_emit_cstring(" - . - 4\n");
2447 be_emit_write_line();
2450 /* end emit routines, all emitters following here should only use the functions
2453 typedef enum reg_modifier {
2458 /** Create a ModR/M byte for src1,src2 registers */
2459 static void bemit_modrr(const arch_register_t *src1,
2460 const arch_register_t *src2)
2462 unsigned char modrm = MOD_REG;
2463 modrm |= ENC_RM(reg_gp_map[src1->index]);
2464 modrm |= ENC_REG(reg_gp_map[src2->index]);
2468 /** Create a ModR/M8 byte for src1,src2 registers */
2469 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2470 reg_modifier_t high_part2, const arch_register_t *src2)
2472 unsigned char modrm = MOD_REG;
2473 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2474 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2478 /** Create a ModR/M byte for one register and extension */
2479 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2481 unsigned char modrm = MOD_REG;
2483 modrm |= ENC_RM(reg_gp_map[reg->index]);
2484 modrm |= ENC_REG(ext);
2488 /** Create a ModR/M8 byte for one register */
2489 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2491 unsigned char modrm = MOD_REG;
2492 assert(reg_gp_map[reg->index] < 4);
2493 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2499 * Calculate the size of an signed immediate in bytes.
2501 * @param offset an offset
2503 static unsigned get_signed_imm_size(int offset)
2505 if (-128 <= offset && offset < 128) {
2507 } else if (-32768 <= offset && offset < 32768) {
2515 * Emit an address mode.
2517 * @param reg content of the reg field: either a register index or an opcode extension
2518 * @param node the node
2520 static void bemit_mod_am(unsigned reg, const ir_node *node)
2522 ir_entity *ent = get_ia32_am_sc(node);
2523 int offs = get_ia32_am_offs_int(node);
2524 ir_node *base = get_irn_n(node, n_ia32_base);
2525 int has_base = !is_ia32_NoReg_GP(base);
2526 ir_node *index = get_irn_n(node, n_ia32_index);
2527 int has_index = !is_ia32_NoReg_GP(index);
2530 unsigned emitoffs = 0;
2531 bool emitsib = false;
2534 /* set the mod part depending on displacement */
2536 modrm |= MOD_IND_WORD_OFS;
2538 } else if (offs == 0) {
2541 } else if (-128 <= offs && offs < 128) {
2542 modrm |= MOD_IND_BYTE_OFS;
2545 modrm |= MOD_IND_WORD_OFS;
2550 const arch_register_t *base_reg = arch_get_irn_register(base);
2551 base_enc = reg_gp_map[base_reg->index];
2553 /* Use the EBP encoding + MOD_IND if NO base register. There is
2554 * always a 32bit offset present in this case. */
2560 /* Determine if we need a SIB byte. */
2562 const arch_register_t *reg_index = arch_get_irn_register(index);
2563 int scale = get_ia32_am_scale(node);
2565 /* R/M set to ESP means SIB in 32bit mode. */
2566 modrm |= ENC_RM(0x04);
2567 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2569 } else if (base_enc == 0x04) {
2570 /* for the above reason we are forced to emit a SIB when base is ESP.
2571 * Only the base is used, index must be ESP too, which means no index.
2573 modrm |= ENC_RM(0x04);
2574 sib = ENC_SIB(0, 0x04, 0x04);
2577 modrm |= ENC_RM(base_enc);
2580 /* We are forced to emit an 8bit offset as EBP base without offset is a
2581 * special case for SIB without base register. */
2582 if (base_enc == 0x05 && emitoffs == 0) {
2583 modrm |= MOD_IND_BYTE_OFS;
2587 modrm |= ENC_REG(reg);
2593 /* emit displacement */
2594 if (emitoffs == 8) {
2595 bemit8((unsigned) offs);
2596 } else if (emitoffs == 32) {
2597 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2602 * Emit a binop with a immediate operand.
2604 * @param node the node to emit
2605 * @param opcode_eax the opcode for the op eax, imm variant
2606 * @param opcode the opcode for the reg, imm variant
2607 * @param ruval the opcode extension for opcode
2609 static void bemit_binop_with_imm(
2610 const ir_node *node,
2611 unsigned char opcode_ax,
2612 unsigned char opcode, unsigned char ruval)
2614 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2615 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2616 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2619 /* Some instructions (test) have no short form with 32bit value + 8bit
2621 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2624 /* check for sign extension */
2625 size = get_signed_imm_size(attr->offset);
2630 bemit8(opcode | SIGNEXT_IMM);
2631 /* cmp has this special mode */
2632 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2633 bemit_mod_am(ruval, node);
2635 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2636 bemit_modru(reg, ruval);
2638 bemit8((unsigned char)attr->offset);
2642 /* check for eax variant: this variant is shorter for 32bit immediates only */
2643 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2645 bemit_mod_am(ruval, node);
2647 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
2648 if (reg->index == REG_EAX) {
2652 bemit_modru(reg, ruval);
2655 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2658 panic("invalid imm size?!?");
2664 static void bemit_binop_2(const ir_node *node, unsigned code)
2666 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
2668 if (get_ia32_op_type(node) == ia32_Normal) {
2669 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
2670 bemit_modrr(op2, out);
2672 bemit_mod_am(reg_gp_map[out->index], node);
2679 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2681 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2682 if (is_ia32_Immediate(right)) {
2683 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2685 bemit_binop_2(node, opcodes[0]);
2692 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2695 if (get_ia32_op_type(node) == ia32_Normal) {
2696 const arch_register_t *in = get_in_reg(node, input);
2697 bemit_modru(in, ext);
2699 bemit_mod_am(ext, node);
2703 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2705 const arch_register_t *out = get_out_reg(node, 0);
2706 bemit_unop(node, code, reg_gp_map[out->index], input);
2709 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2711 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2714 bemit8(size == 8 ? code : code + 1);
2715 bemit_mod_am(ext, node);
2718 static void bemit_immediate(const ir_node *node, bool relative)
2720 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2721 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2724 static void bemit_copy(const ir_node *copy)
2726 const arch_register_t *in = get_in_reg(copy, 0);
2727 const arch_register_t *out = get_out_reg(copy, 0);
2729 if (in == out || is_unknown_reg(in))
2731 /* copies of vf nodes aren't real... */
2732 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2735 if (get_irn_mode(copy) == mode_E) {
2738 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2740 bemit_modrr(in, out);
2744 static void bemit_perm(const ir_node *node)
2746 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2747 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2748 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2750 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2752 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2753 if (in0->index == REG_EAX) {
2754 bemit8(0x90 + reg_gp_map[in1->index]);
2755 } else if (in1->index == REG_EAX) {
2756 bemit8(0x90 + reg_gp_map[in0->index]);
2759 bemit_modrr(in0, in1);
2761 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2762 panic("unimplemented"); // TODO implement
2763 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2764 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2765 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2766 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2768 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2771 panic("unexpected register class in be_Perm (%+F)", node);
2775 static void bemit_xor0(const ir_node *node)
2777 const arch_register_t *out = get_out_reg(node, 0);
2779 bemit_modrr(out, out);
2782 static void bemit_mov_const(const ir_node *node)
2784 const arch_register_t *out = get_out_reg(node, 0);
2785 bemit8(0xB8 + reg_gp_map[out->index]);
2786 bemit_immediate(node, false);
2790 * Creates a function for a Binop with 3 possible encodings.
2792 #define BINOP(op, op0, op1, op2, op2_ext) \
2793 static void bemit_ ## op(const ir_node *node) { \
2794 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2795 bemit_binop(node, op ## _codes); \
2798 /* insn def eax,imm imm */
2799 BINOP(add, 0x03, 0x05, 0x81, 0)
2800 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2801 BINOP(adc, 0x13, 0x15, 0x81, 2)
2802 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2803 BINOP(and, 0x23, 0x25, 0x81, 4)
2804 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2805 BINOP(xor, 0x33, 0x35, 0x81, 6)
2806 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2808 #define BINOPMEM(op, ext) \
2809 static void bemit_##op(const ir_node *node) \
2812 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2815 val = get_irn_n(node, n_ia32_unary_op); \
2816 if (is_ia32_Immediate(val)) { \
2817 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2818 int offset = attr->offset; \
2819 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2821 bemit_mod_am(ext, node); \
2825 bemit_mod_am(ext, node); \
2829 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2833 bemit8(ext << 3 | 1); \
2834 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2838 static void bemit_##op##8bit(const ir_node *node) \
2840 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2841 if (is_ia32_Immediate(val)) { \
2843 bemit_mod_am(ext, node); \
2844 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2847 bemit_mod_am(reg_gp_map[get_out_reg(val, 0)->index], node); \
2859 * Creates a function for an Unop with code /ext encoding.
2861 #define UNOP(op, code, ext, input) \
2862 static void bemit_ ## op(const ir_node *node) { \
2863 bemit_unop(node, code, ext, input); \
2866 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2867 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2868 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2869 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2870 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2871 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2873 /* TODO: am support for IJmp */
2874 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2876 #define SHIFT(op, ext) \
2877 static void bemit_##op(const ir_node *node) \
2879 const arch_register_t *out = get_out_reg(node, 0); \
2880 ir_node *count = get_irn_n(node, 1); \
2881 if (is_ia32_Immediate(count)) { \
2882 int offset = get_ia32_immediate_attr_const(count)->offset; \
2883 if (offset == 1) { \
2885 bemit_modru(out, ext); \
2888 bemit_modru(out, ext); \
2893 bemit_modru(out, ext); \
2897 static void bemit_##op##mem(const ir_node *node) \
2900 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2903 count = get_irn_n(node, 1); \
2904 if (is_ia32_Immediate(count)) { \
2905 int offset = get_ia32_immediate_attr_const(count)->offset; \
2906 if (offset == 1) { \
2907 bemit8(size == 8 ? 0xD0 : 0xD1); \
2908 bemit_mod_am(ext, node); \
2910 bemit8(size == 8 ? 0xC0 : 0xC1); \
2911 bemit_mod_am(ext, node); \
2915 bemit8(size == 8 ? 0xD2 : 0xD3); \
2916 bemit_mod_am(ext, node); \
2926 static void bemit_shld(const ir_node *node)
2928 const arch_register_t *in = get_in_reg(node, n_ia32_ShlD_val_low);
2929 const arch_register_t *out = get_out_reg(node, pn_ia32_ShlD_res);
2930 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2932 if (is_ia32_Immediate(count)) {
2934 bemit_modrr(out, in);
2935 bemit8(get_ia32_immediate_attr_const(count)->offset);
2938 bemit_modrr(out, in);
2942 static void bemit_shrd(const ir_node *node)
2944 const arch_register_t *in = get_in_reg(node, n_ia32_ShrD_val_low);
2945 const arch_register_t *out = get_out_reg(node, pn_ia32_ShrD_res);
2946 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2948 if (is_ia32_Immediate(count)) {
2950 bemit_modrr(out, in);
2951 bemit8(get_ia32_immediate_attr_const(count)->offset);
2954 bemit_modrr(out, in);
2959 * binary emitter for setcc.
2961 static void bemit_setcc(const ir_node *node)
2963 const arch_register_t *dreg = get_out_reg(node, pn_ia32_Setcc_res);
2965 pn_Cmp pnc = get_ia32_condcode(node);
2966 pnc = determine_final_pnc(node, n_ia32_Setcc_eflags, pnc);
2967 if (pnc & ia32_pn_Cmp_float) {
2968 switch (pnc & 0x0f) {
2973 bemit_modrm8(REG_LOW, dreg);
2980 bemit_modrm8(REG_LOW, dreg);
2988 bemit8(0x90 | pnc2cc(pnc));
2989 bemit_modrm8(REG_LOW, dreg);
2994 bemit_modrm8(REG_HIGH, dreg);
2996 /* andb %>dreg, %<dreg */
2998 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
3006 bemit8(0x90 | pnc2cc(pnc));
3007 bemit_modrm8(REG_LOW, dreg);
3012 bemit_modrm8(REG_HIGH, dreg);
3014 /* orb %>dreg, %<dreg */
3016 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
3025 bemit8(0x90 | pnc2cc(pnc));
3026 bemit_modrm8(REG_LOW, dreg);
3029 static void bemit_cmovcc(const ir_node *node)
3031 const ia32_attr_t *attr = get_ia32_attr_const(node);
3032 int ins_permuted = attr->data.ins_permuted;
3033 const arch_register_t *out = arch_irn_get_register(node, pn_ia32_res);
3034 pn_Cmp pnc = get_ia32_condcode(node);
3035 const arch_register_t *in_true;
3036 const arch_register_t *in_false;
3038 pnc = determine_final_pnc(node, n_ia32_CMovcc_eflags, pnc);
3040 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
3041 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
3043 /* should be same constraint fullfilled? */
3044 if (out == in_false) {
3045 /* yes -> nothing to do */
3046 } else if (out == in_true) {
3047 assert(get_ia32_op_type(node) == ia32_Normal);
3048 ins_permuted = !ins_permuted;
3052 bemit8(0x8B); // mov %in_false, %out
3053 bemit_modrr(in_false, out);
3057 pnc = ia32_get_negated_pnc(pnc);
3059 /* TODO: handling of Nans isn't correct yet */
3062 bemit8(0x40 | pnc2cc(pnc));
3063 if (get_ia32_op_type(node) == ia32_Normal) {
3064 bemit_modrr(in_true, out);
3066 bemit_mod_am(reg_gp_map[out->index], node);
3070 static void bemit_cmp(const ir_node *node)
3072 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
3078 right = get_irn_n(node, n_ia32_binary_right);
3079 if (is_ia32_Immediate(right)) {
3080 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
3081 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
3082 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
3085 if (attr->symconst != NULL) {
3088 /* check for sign extension */
3089 size = get_signed_imm_size(attr->offset);
3094 bemit8(0x81 | SIGNEXT_IMM);
3095 /* cmp has this special mode */
3096 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3097 bemit_mod_am(7, node);
3099 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3100 bemit_modru(reg, 7);
3102 bemit8((unsigned char)attr->offset);
3106 /* check for eax variant: this variant is shorter for 32bit immediates only */
3107 if (get_ia32_op_type(node) == ia32_AddrModeS) {
3109 bemit_mod_am(7, node);
3111 const arch_register_t *reg = get_in_reg(node, n_ia32_binary_left);
3112 if (reg->index == REG_EAX) {
3116 bemit_modru(reg, 7);
3119 if (ls_size == 16) {
3120 bemit16(attr->offset);
3122 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
3126 panic("invalid imm size?!?");
3128 const arch_register_t *out = get_in_reg(node, n_ia32_binary_left);
3130 if (get_ia32_op_type(node) == ia32_Normal) {
3131 const arch_register_t *op2 = get_in_reg(node, n_ia32_binary_right);
3132 bemit_modrr(op2, out);
3134 bemit_mod_am(reg_gp_map[out->index], node);
3139 static void bemit_cmp8bit(const ir_node *node)
3141 ir_node *right = get_irn_n(node, n_ia32_binary_right);
3142 if (is_ia32_Immediate(right)) {
3143 if (get_ia32_op_type(node) == ia32_Normal) {
3144 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3145 if (out->index == REG_EAX) {
3149 bemit_modru(out, 7);
3153 bemit_mod_am(7, node);
3155 bemit8(get_ia32_immediate_attr_const(right)->offset);
3157 const arch_register_t *out = get_in_reg(node, n_ia32_Cmp_left);
3159 if (get_ia32_op_type(node) == ia32_Normal) {
3160 const arch_register_t *in = get_in_reg(node, n_ia32_Cmp_right);
3161 bemit_modrr(out, in);
3163 bemit_mod_am(reg_gp_map[out->index], node);
3168 static void bemit_test8bit(const ir_node *node)
3170 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
3171 if (is_ia32_Immediate(right)) {
3172 if (get_ia32_op_type(node) == ia32_Normal) {
3173 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3174 if (out->index == REG_EAX) {
3178 bemit_modru(out, 0);
3182 bemit_mod_am(0, node);
3184 bemit8(get_ia32_immediate_attr_const(right)->offset);
3186 const arch_register_t *out = get_in_reg(node, n_ia32_Test8Bit_left);
3188 if (get_ia32_op_type(node) == ia32_Normal) {
3189 const arch_register_t *in = get_in_reg(node, n_ia32_Test8Bit_right);
3190 bemit_modrr(out, in);
3192 bemit_mod_am(reg_gp_map[out->index], node);
3197 static void bemit_imul(const ir_node *node)
3199 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
3200 /* Do we need the immediate form? */
3201 if (is_ia32_Immediate(right)) {
3202 int imm = get_ia32_immediate_attr_const(right)->offset;
3203 if (get_signed_imm_size(imm) == 1) {
3204 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
3207 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
3212 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
3216 static void bemit_dec(const ir_node *node)
3218 const arch_register_t *out = get_out_reg(node, pn_ia32_Dec_res);
3219 bemit8(0x48 + reg_gp_map[out->index]);
3222 static void bemit_inc(const ir_node *node)
3224 const arch_register_t *out = get_out_reg(node, pn_ia32_Inc_res);
3225 bemit8(0x40 + reg_gp_map[out->index]);
3228 #define UNOPMEM(op, code, ext) \
3229 static void bemit_##op(const ir_node *node) \
3231 bemit_unop_mem(node, code, ext); \
3234 UNOPMEM(notmem, 0xF6, 2)
3235 UNOPMEM(negmem, 0xF6, 3)
3236 UNOPMEM(incmem, 0xFE, 0)
3237 UNOPMEM(decmem, 0xFE, 1)
3239 static void bemit_ldtls(const ir_node *node)
3241 const arch_register_t *out = get_out_reg(node, 0);
3243 bemit8(0x65); // gs:
3244 if (out->index == REG_EAX) {
3245 bemit8(0xA1); // movl 0, %eax
3247 bemit8(0x8B); // movl 0, %reg
3248 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
3256 static void bemit_lea(const ir_node *node)
3258 const arch_register_t *out = get_out_reg(node, 0);
3260 bemit_mod_am(reg_gp_map[out->index], node);
3263 /* helper function for bemit_minus64bit */
3264 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
3266 bemit8(0x8B); // movl %src, %dst
3267 bemit_modrr(src, dst);
3270 /* helper function for bemit_minus64bit */
3271 static void bemit_helper_neg(const arch_register_t *reg)
3273 bemit8(0xF7); // negl %reg
3274 bemit_modru(reg, 3);
3277 /* helper function for bemit_minus64bit */
3278 static void bemit_helper_sbb0(const arch_register_t *reg)
3280 bemit8(0x83); // sbbl $0, %reg
3281 bemit_modru(reg, 3);
3285 /* helper function for bemit_minus64bit */
3286 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
3288 bemit8(0x1B); // sbbl %src, %dst
3289 bemit_modrr(src, dst);
3292 /* helper function for bemit_minus64bit */
3293 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
3295 if (src->index == REG_EAX) {
3296 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
3297 } else if (dst->index == REG_EAX) {
3298 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
3300 bemit8(0x87); // xchgl %src, %dst
3301 bemit_modrr(src, dst);
3305 /* helper function for bemit_minus64bit */
3306 static void bemit_helper_zero(const arch_register_t *reg)
3308 bemit8(0x33); // xorl %reg, %reg
3309 bemit_modrr(reg, reg);
3312 static void bemit_minus64bit(const ir_node *node)
3314 const arch_register_t *in_lo = get_in_reg(node, 0);
3315 const arch_register_t *in_hi = get_in_reg(node, 1);
3316 const arch_register_t *out_lo = get_out_reg(node, 0);
3317 const arch_register_t *out_hi = get_out_reg(node, 1);
3319 if (out_lo == in_lo) {
3320 if (out_hi != in_hi) {
3321 /* a -> a, b -> d */
3324 /* a -> a, b -> b */
3327 } else if (out_lo == in_hi) {
3328 if (out_hi == in_lo) {
3329 /* a -> b, b -> a */
3330 bemit_helper_xchg(in_lo, in_hi);
3333 /* a -> b, b -> d */
3334 bemit_helper_mov(in_hi, out_hi);
3335 bemit_helper_mov(in_lo, out_lo);
3339 if (out_hi == in_lo) {
3340 /* a -> c, b -> a */
3341 bemit_helper_mov(in_lo, out_lo);
3343 } else if (out_hi == in_hi) {
3344 /* a -> c, b -> b */
3345 bemit_helper_mov(in_lo, out_lo);
3348 /* a -> c, b -> d */
3349 bemit_helper_mov(in_lo, out_lo);
3355 bemit_helper_neg( out_hi);
3356 bemit_helper_neg( out_lo);
3357 bemit_helper_sbb0(out_hi);
3361 bemit_helper_zero(out_hi);
3362 bemit_helper_neg( out_lo);
3363 bemit_helper_sbb( in_hi, out_hi);
3367 * Emit a single opcode.
3369 #define EMIT_SINGLEOP(op, code) \
3370 static void bemit_ ## op(const ir_node *node) { \
3375 //EMIT_SINGLEOP(daa, 0x27)
3376 //EMIT_SINGLEOP(das, 0x2F)
3377 //EMIT_SINGLEOP(aaa, 0x37)
3378 //EMIT_SINGLEOP(aas, 0x3F)
3379 //EMIT_SINGLEOP(nop, 0x90)
3380 EMIT_SINGLEOP(cwtl, 0x98)
3381 EMIT_SINGLEOP(cltd, 0x99)
3382 //EMIT_SINGLEOP(fwait, 0x9B)
3383 EMIT_SINGLEOP(sahf, 0x9E)
3384 //EMIT_SINGLEOP(popf, 0x9D)
3385 EMIT_SINGLEOP(leave, 0xC9)
3386 EMIT_SINGLEOP(int3, 0xCC)
3387 //EMIT_SINGLEOP(iret, 0xCF)
3388 //EMIT_SINGLEOP(xlat, 0xD7)
3389 //EMIT_SINGLEOP(lock, 0xF0)
3390 EMIT_SINGLEOP(rep, 0xF3)
3391 //EMIT_SINGLEOP(halt, 0xF4)
3392 EMIT_SINGLEOP(cmc, 0xF5)
3393 EMIT_SINGLEOP(stc, 0xF9)
3394 //EMIT_SINGLEOP(cli, 0xFA)
3395 //EMIT_SINGLEOP(sti, 0xFB)
3396 //EMIT_SINGLEOP(std, 0xFD)
3399 * Emits a MOV out, [MEM].
3401 static void bemit_load(const ir_node *node)
3403 const arch_register_t *out = get_out_reg(node, 0);
3405 if (out->index == REG_EAX) {
3406 ir_node *base = get_irn_n(node, n_ia32_base);
3407 int has_base = !is_ia32_NoReg_GP(base);
3408 ir_node *index = get_irn_n(node, n_ia32_index);
3409 int has_index = !is_ia32_NoReg_GP(index);
3410 if (!has_base && !has_index) {
3411 ir_entity *ent = get_ia32_am_sc(node);
3412 int offs = get_ia32_am_offs_int(node);
3413 /* load from constant address to EAX can be encoded
3416 bemit_entity(ent, 0, offs, false);
3421 bemit_mod_am(reg_gp_map[out->index], node);
3425 * Emits a MOV [mem], in.
3427 static void bemit_store(const ir_node *node)
3429 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3430 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3432 if (is_ia32_Immediate(value)) {
3435 bemit_mod_am(0, node);
3436 bemit8(get_ia32_immediate_attr_const(value)->offset);
3437 } else if (size == 16) {
3440 bemit_mod_am(0, node);
3441 bemit16(get_ia32_immediate_attr_const(value)->offset);
3444 bemit_mod_am(0, node);
3445 bemit_immediate(value, false);
3448 const arch_register_t *in = get_in_reg(node, n_ia32_Store_val);
3450 if (in->index == REG_EAX) {
3451 ir_node *base = get_irn_n(node, n_ia32_base);
3452 int has_base = !is_ia32_NoReg_GP(base);
3453 ir_node *index = get_irn_n(node, n_ia32_index);
3454 int has_index = !is_ia32_NoReg_GP(index);
3455 if (!has_base && !has_index) {
3456 ir_entity *ent = get_ia32_am_sc(node);
3457 int offs = get_ia32_am_offs_int(node);
3458 /* store to constant address from EAX can be encoded as
3459 * 0xA2/0xA3 [offset]*/
3467 bemit_entity(ent, 0, offs, false);
3479 bemit_mod_am(reg_gp_map[in->index], node);
3483 static void bemit_conv_i2i(const ir_node *node)
3485 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3494 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3495 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3496 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3502 static void bemit_push(const ir_node *node)
3504 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3506 if (is_ia32_Immediate(value)) {
3507 const ia32_immediate_attr_t *attr
3508 = get_ia32_immediate_attr_const(value);
3509 unsigned size = get_signed_imm_size(attr->offset);
3515 bemit8((unsigned char)attr->offset);
3520 bemit_immediate(value, false);
3523 } else if (is_ia32_NoReg_GP(value)) {
3525 bemit_mod_am(6, node);
3527 const arch_register_t *reg = get_in_reg(node, n_ia32_Push_val);
3528 bemit8(0x50 + reg_gp_map[reg->index]);
3535 static void bemit_pop(const ir_node *node)
3537 const arch_register_t *reg = get_out_reg(node, pn_ia32_Pop_res);
3538 bemit8(0x58 + reg_gp_map[reg->index]);
3541 static void bemit_popmem(const ir_node *node)
3544 bemit_mod_am(0, node);
3547 static void bemit_call(const ir_node *node)
3549 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3551 if (is_ia32_Immediate(proc)) {
3553 bemit_immediate(proc, true);
3555 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3559 static void bemit_jmp(const ir_node *dest_block)
3562 bemit_jmp_destination(dest_block);
3565 static void bemit_jump(const ir_node *node)
3567 if (can_be_fallthrough(node))
3570 bemit_jmp(get_cfop_target_block(node));
3573 static void bemit_jcc(int pnc, const ir_node *dest_block)
3575 unsigned char cc = pnc2cc(pnc);
3578 bemit_jmp_destination(dest_block);
3581 static void bemit_jp(bool odd, const ir_node *dest_block)
3585 bemit_jmp_destination(dest_block);
3588 static void bemit_ia32_jcc(const ir_node *node)
3590 int pnc = get_ia32_condcode(node);
3591 const ir_node *proj_true;
3592 const ir_node *proj_false;
3593 const ir_node *dest_true;
3594 const ir_node *dest_false;
3595 const ir_node *block;
3597 pnc = determine_final_pnc(node, 0, pnc);
3599 /* get both Projs */
3600 proj_true = get_proj(node, pn_ia32_Jcc_true);
3601 assert(proj_true && "Jcc without true Proj");
3603 proj_false = get_proj(node, pn_ia32_Jcc_false);
3604 assert(proj_false && "Jcc without false Proj");
3606 block = get_nodes_block(node);
3608 if (can_be_fallthrough(proj_true)) {
3609 /* exchange both proj's so the second one can be omitted */
3610 const ir_node *t = proj_true;
3612 proj_true = proj_false;
3614 pnc = ia32_get_negated_pnc(pnc);
3617 dest_true = get_cfop_target_block(proj_true);
3618 dest_false = get_cfop_target_block(proj_false);
3620 if (pnc & ia32_pn_Cmp_float) {
3621 /* Some floating point comparisons require a test of the parity flag,
3622 * which indicates that the result is unordered */
3625 bemit_jp(false, dest_true);
3630 bemit_jp(true, dest_true);
3636 /* we need a local label if the false proj is a fallthrough
3637 * as the falseblock might have no label emitted then */
3638 if (can_be_fallthrough(proj_false)) {
3640 bemit8(0x06); // jp + 6
3642 bemit_jp(false, dest_false);
3649 bemit_jp(false, dest_true);
3657 bemit_jcc(pnc, dest_true);
3660 /* the second Proj might be a fallthrough */
3661 if (can_be_fallthrough(proj_false)) {
3662 /* it's a fallthrough */
3664 bemit_jmp(dest_false);
3668 static void bemit_switchjmp(const ir_node *node)
3670 unsigned long interval;
3674 const arch_register_t *in;
3676 /* fill the table structure */
3677 generate_jump_table(&tbl, node);
3679 /* two-complement's magic make this work without overflow */
3680 interval = tbl.max_value - tbl.min_value;
3682 in = get_in_reg(node, 0);
3683 /* emit the table */
3684 if (get_signed_imm_size(interval) == 1) {
3685 bemit8(0x83); // cmpl $imm8, %in
3689 bemit8(0x81); // cmpl $imm32, %in
3693 bemit8(0x0F); // ja tbl.defProj
3695 ia32_emitf(tbl.defProj, ".long %L - . - 4\n");
3697 if (tbl.num_branches > 1) {
3699 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3700 bemit8(MOD_IND | ENC_REG(4) | ENC_RM(0x04));
3701 bemit8(ENC_SIB(2, reg_gp_map[in->index], 0x05));
3702 be_emit_irprintf("\t.long %s\n", tbl.label);
3704 be_gas_emit_switch_section(GAS_SECTION_RODATA);
3705 be_emit_cstring(".align 4\n");
3706 be_emit_irprintf("%s:\n", tbl.label);
3708 last_value = tbl.branches[0].value;
3709 for (i = 0; i != tbl.num_branches; ++i) {
3710 while (last_value != tbl.branches[i].value) {
3711 ia32_emitf(tbl.defProj, ".long %L\n");
3714 ia32_emitf(tbl.branches[i].target, ".long %L\n");
3717 be_gas_emit_switch_section(GAS_SECTION_TEXT);
3719 /* one jump is enough */
3720 panic("switch only has one case");
3721 //ia32_emitf(tbl.branches[0].target, "\tjmp %L\n");
3724 be_emit_write_line();
3732 static void bemit_return(const ir_node *node)
3734 unsigned pop = be_Return_get_pop(node);
3735 if (pop > 0 || be_Return_get_emit_pop(node)) {
3737 assert(pop <= 0xffff);
3744 static void bemit_subsp(const ir_node *node)
3746 const arch_register_t *out;
3749 /* mov %esp, %out */
3751 out = get_out_reg(node, 1);
3752 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3755 static void bemit_incsp(const ir_node *node)
3758 const arch_register_t *reg;
3762 offs = be_get_IncSP_offset(node);
3773 size = get_signed_imm_size(offs);
3774 bemit8(size == 1 ? 0x83 : 0x81);
3776 reg = get_out_reg(node, 0);
3777 bemit_modru(reg, ext);
3786 static void bemit_copybi(const ir_node *node)
3788 unsigned size = get_ia32_copyb_size(node);
3790 bemit8(0xA4); // movsb
3793 bemit8(0xA5); // movsw
3797 bemit8(0xA5); // movsl
3801 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3803 if (get_ia32_op_type(node) == ia32_Normal) {
3804 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3805 const arch_register_t *in1 = x87_attr->x87[0];
3806 const arch_register_t *in = x87_attr->x87[1];
3807 const arch_register_t *out = x87_attr->x87[2];
3811 } else if (out == in) {
3815 if (out->index == 0) {
3817 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3820 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3823 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3828 bemit_mod_am(code, node);
3832 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3834 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3835 const arch_register_t *out = x87_attr->x87[2];
3837 bemit8(code + out->index);
3840 static void bemit_fabs(const ir_node *node)
3848 static void bemit_fadd(const ir_node *node)
3850 bemit_fbinop(node, 0, 0);
3853 static void bemit_faddp(const ir_node *node)
3855 bemit_fbinopp(node, 0xC0);
3858 static void bemit_fchs(const ir_node *node)
3866 static void bemit_fdiv(const ir_node *node)
3868 bemit_fbinop(node, 6, 7);
3871 static void bemit_fdivp(const ir_node *node)
3873 bemit_fbinopp(node, 0xF8);
3876 static void bemit_fdivr(const ir_node *node)
3878 bemit_fbinop(node, 7, 6);
3881 static void bemit_fdivrp(const ir_node *node)
3883 bemit_fbinopp(node, 0xF0);
3886 static void bemit_fild(const ir_node *node)
3888 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3890 bemit8(0xDF); // filds
3891 bemit_mod_am(0, node);
3895 bemit8(0xDB); // fildl
3896 bemit_mod_am(0, node);
3900 bemit8(0xDF); // fildll
3901 bemit_mod_am(5, node);
3905 panic("invalid mode size");
3909 static void bemit_fist(const ir_node *node)
3911 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3913 bemit8(0xDF); // fists
3917 bemit8(0xDB); // fistl
3921 panic("invalid mode size");
3923 bemit_mod_am(2, node);
3926 static void bemit_fistp(const ir_node *node)
3928 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3930 bemit8(0xDF); // fistps
3931 bemit_mod_am(3, node);
3935 bemit8(0xDB); // fistpl
3936 bemit_mod_am(3, node);
3940 bemit8(0xDF); // fistpll
3941 bemit_mod_am(7, node);
3945 panic("invalid mode size");
3949 static void bemit_fld(const ir_node *node)
3951 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3953 bemit8(0xD9); // flds
3954 bemit_mod_am(0, node);
3958 bemit8(0xDD); // fldl
3959 bemit_mod_am(0, node);
3964 bemit8(0xDB); // fldt
3965 bemit_mod_am(5, node);
3969 panic("invalid mode size");
3973 static void bemit_fld1(const ir_node *node)
3977 bemit8(0xE8); // fld1
3980 static void bemit_fldcw(const ir_node *node)
3982 bemit8(0xD9); // fldcw
3983 bemit_mod_am(5, node);
3986 static void bemit_fldz(const ir_node *node)
3990 bemit8(0xEE); // fldz
3993 static void bemit_fmul(const ir_node *node)
3995 bemit_fbinop(node, 1, 1);
3998 static void bemit_fmulp(const ir_node *node)
4000 bemit_fbinopp(node, 0xC8);
4003 static void bemit_fpop(const ir_node *node)
4005 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4007 bemit8(0xD8 + attr->x87[0]->index);
4010 static void bemit_fpush(const ir_node *node)
4012 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4014 bemit8(0xC0 + attr->x87[0]->index);
4017 static void bemit_fpushcopy(const ir_node *node)
4019 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4021 bemit8(0xC0 + attr->x87[0]->index);
4024 static void bemit_fst(const ir_node *node)
4026 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4028 bemit8(0xD9); // fsts
4032 bemit8(0xDD); // fstl
4036 panic("invalid mode size");
4038 bemit_mod_am(2, node);
4041 static void bemit_fstp(const ir_node *node)
4043 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
4045 bemit8(0xD9); // fstps
4046 bemit_mod_am(3, node);
4050 bemit8(0xDD); // fstpl
4051 bemit_mod_am(3, node);
4056 bemit8(0xDB); // fstpt
4057 bemit_mod_am(7, node);
4061 panic("invalid mode size");
4065 static void bemit_fsub(const ir_node *node)
4067 bemit_fbinop(node, 4, 5);
4070 static void bemit_fsubp(const ir_node *node)
4072 bemit_fbinopp(node, 0xE8);
4075 static void bemit_fsubr(const ir_node *node)
4077 bemit_fbinop(node, 5, 4);
4080 static void bemit_fsubrp(const ir_node *node)
4082 bemit_fbinopp(node, 0xE0);
4085 static void bemit_fnstcw(const ir_node *node)
4087 bemit8(0xD9); // fnstcw
4088 bemit_mod_am(7, node);
4091 static void bemit_fnstsw(void)
4093 bemit8(0xDF); // fnstsw %ax
4097 static void bemit_ftstfnstsw(const ir_node *node)
4101 bemit8(0xD9); // ftst
4106 static void bemit_fucomi(const ir_node *node)
4108 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4109 bemit8(0xDB); // fucomi
4110 bemit8(0xE8 + attr->x87[1]->index);
4113 static void bemit_fucomip(const ir_node *node)
4115 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4116 bemit8(0xDF); // fucomip
4117 bemit8(0xE8 + attr->x87[1]->index);
4120 static void bemit_fucomfnstsw(const ir_node *node)
4122 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4123 bemit8(0xDD); // fucom
4124 bemit8(0xE0 + attr->x87[1]->index);
4128 static void bemit_fucompfnstsw(const ir_node *node)
4130 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4131 bemit8(0xDD); // fucomp
4132 bemit8(0xE8 + attr->x87[1]->index);
4136 static void bemit_fucomppfnstsw(const ir_node *node)
4140 bemit8(0xDA); // fucompp
4145 static void bemit_fxch(const ir_node *node)
4147 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
4149 bemit8(0xC8 + attr->x87[0]->index);
4153 * The type of a emitter function.
4155 typedef void (*emit_func) (const ir_node *);
4158 * Set a node emitter. Make it a bit more type safe.
4160 static void register_emitter(ir_op *op, emit_func func)
4162 op->ops.generic = (op_func) func;
4165 static void ia32_register_binary_emitters(void)
4167 /* first clear the generic function pointer for all ops */
4168 clear_irp_opcodes_generic_func();
4170 /* benode emitter */
4171 register_emitter(op_be_Copy, bemit_copy);
4172 register_emitter(op_be_CopyKeep, bemit_copy);
4173 register_emitter(op_be_IncSP, bemit_incsp);
4174 register_emitter(op_be_Perm, bemit_perm);
4175 register_emitter(op_be_Return, bemit_return);
4176 register_emitter(op_ia32_Adc, bemit_adc);
4177 register_emitter(op_ia32_Add, bemit_add);
4178 register_emitter(op_ia32_AddMem, bemit_addmem);
4179 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
4180 register_emitter(op_ia32_And, bemit_and);
4181 register_emitter(op_ia32_AndMem, bemit_andmem);
4182 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
4183 register_emitter(op_ia32_Breakpoint, bemit_int3);
4184 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
4185 register_emitter(op_ia32_Call, bemit_call);
4186 register_emitter(op_ia32_Cltd, bemit_cltd);
4187 register_emitter(op_ia32_Cmc, bemit_cmc);
4188 register_emitter(op_ia32_Cmp, bemit_cmp);
4189 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
4190 register_emitter(op_ia32_Const, bemit_mov_const);
4191 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
4192 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
4193 register_emitter(op_ia32_CopyB_i, bemit_copybi);
4194 register_emitter(op_ia32_Cwtl, bemit_cwtl);
4195 register_emitter(op_ia32_Dec, bemit_dec);
4196 register_emitter(op_ia32_DecMem, bemit_decmem);
4197 register_emitter(op_ia32_Div, bemit_div);
4198 register_emitter(op_ia32_FldCW, bemit_fldcw);
4199 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
4200 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
4201 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
4202 register_emitter(op_ia32_Fucomi, bemit_fucomi);
4203 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
4204 register_emitter(op_ia32_Fucompi, bemit_fucomip);
4205 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
4206 register_emitter(op_ia32_IDiv, bemit_idiv);
4207 register_emitter(op_ia32_IJmp, bemit_ijmp);
4208 register_emitter(op_ia32_IMul, bemit_imul);
4209 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
4210 register_emitter(op_ia32_Inc, bemit_inc);
4211 register_emitter(op_ia32_IncMem, bemit_incmem);
4212 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
4213 register_emitter(op_ia32_Jmp, bemit_jump);
4214 register_emitter(op_ia32_LdTls, bemit_ldtls);
4215 register_emitter(op_ia32_Lea, bemit_lea);
4216 register_emitter(op_ia32_Leave, bemit_leave);
4217 register_emitter(op_ia32_Load, bemit_load);
4218 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
4219 register_emitter(op_ia32_Mul, bemit_mul);
4220 register_emitter(op_ia32_Neg, bemit_neg);
4221 register_emitter(op_ia32_NegMem, bemit_negmem);
4222 register_emitter(op_ia32_Not, bemit_not);
4223 register_emitter(op_ia32_NotMem, bemit_notmem);
4224 register_emitter(op_ia32_Or, bemit_or);
4225 register_emitter(op_ia32_OrMem, bemit_ormem);
4226 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
4227 register_emitter(op_ia32_Pop, bemit_pop);
4228 register_emitter(op_ia32_PopEbp, bemit_pop);
4229 register_emitter(op_ia32_PopMem, bemit_popmem);
4230 register_emitter(op_ia32_Push, bemit_push);
4231 register_emitter(op_ia32_RepPrefix, bemit_rep);
4232 register_emitter(op_ia32_Rol, bemit_rol);
4233 register_emitter(op_ia32_RolMem, bemit_rolmem);
4234 register_emitter(op_ia32_Ror, bemit_ror);
4235 register_emitter(op_ia32_RorMem, bemit_rormem);
4236 register_emitter(op_ia32_Sahf, bemit_sahf);
4237 register_emitter(op_ia32_Sar, bemit_sar);
4238 register_emitter(op_ia32_SarMem, bemit_sarmem);
4239 register_emitter(op_ia32_Sbb, bemit_sbb);
4240 register_emitter(op_ia32_Setcc, bemit_setcc);
4241 register_emitter(op_ia32_Shl, bemit_shl);
4242 register_emitter(op_ia32_ShlD, bemit_shld);
4243 register_emitter(op_ia32_ShlMem, bemit_shlmem);
4244 register_emitter(op_ia32_Shr, bemit_shr);
4245 register_emitter(op_ia32_ShrD, bemit_shrd);
4246 register_emitter(op_ia32_ShrMem, bemit_shrmem);
4247 register_emitter(op_ia32_Stc, bemit_stc);
4248 register_emitter(op_ia32_Store, bemit_store);
4249 register_emitter(op_ia32_Store8Bit, bemit_store);
4250 register_emitter(op_ia32_Sub, bemit_sub);
4251 register_emitter(op_ia32_SubMem, bemit_submem);
4252 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
4253 register_emitter(op_ia32_SubSP, bemit_subsp);
4254 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
4255 register_emitter(op_ia32_Test, bemit_test);
4256 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
4257 register_emitter(op_ia32_Xor, bemit_xor);
4258 register_emitter(op_ia32_Xor0, bemit_xor0);
4259 register_emitter(op_ia32_XorMem, bemit_xormem);
4260 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
4261 register_emitter(op_ia32_fabs, bemit_fabs);
4262 register_emitter(op_ia32_fadd, bemit_fadd);
4263 register_emitter(op_ia32_faddp, bemit_faddp);
4264 register_emitter(op_ia32_fchs, bemit_fchs);
4265 register_emitter(op_ia32_fdiv, bemit_fdiv);
4266 register_emitter(op_ia32_fdivp, bemit_fdivp);
4267 register_emitter(op_ia32_fdivr, bemit_fdivr);
4268 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
4269 register_emitter(op_ia32_fild, bemit_fild);
4270 register_emitter(op_ia32_fist, bemit_fist);
4271 register_emitter(op_ia32_fistp, bemit_fistp);
4272 register_emitter(op_ia32_fld, bemit_fld);
4273 register_emitter(op_ia32_fld1, bemit_fld1);
4274 register_emitter(op_ia32_fldz, bemit_fldz);
4275 register_emitter(op_ia32_fmul, bemit_fmul);
4276 register_emitter(op_ia32_fmulp, bemit_fmulp);
4277 register_emitter(op_ia32_fpop, bemit_fpop);
4278 register_emitter(op_ia32_fpush, bemit_fpush);
4279 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
4280 register_emitter(op_ia32_fst, bemit_fst);
4281 register_emitter(op_ia32_fstp, bemit_fstp);
4282 register_emitter(op_ia32_fsub, bemit_fsub);
4283 register_emitter(op_ia32_fsubp, bemit_fsubp);
4284 register_emitter(op_ia32_fsubr, bemit_fsubr);
4285 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
4286 register_emitter(op_ia32_fxch, bemit_fxch);
4288 /* ignore the following nodes */
4289 register_emitter(op_ia32_ProduceVal, emit_Nothing);
4290 register_emitter(op_be_Barrier, emit_Nothing);
4291 register_emitter(op_be_Keep, emit_Nothing);
4292 register_emitter(op_be_Start, emit_Nothing);
4293 register_emitter(op_Phi, emit_Nothing);
4294 register_emitter(op_Start, emit_Nothing);
4297 static void gen_binary_block(ir_node *block)
4301 ia32_emit_block_header(block);
4303 /* emit the contents of the block */
4304 sched_foreach(block, node) {
4305 ia32_emit_node(node);
4309 void ia32_gen_binary_routine(ia32_code_gen_t *ia32_cg, ir_graph *irg)
4311 ir_entity *entity = get_irg_entity(irg);
4317 ia32_register_binary_emitters();
4319 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment);
4321 /* we use links to point to target blocks */
4322 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
4323 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
4325 /* initialize next block links */
4326 n = ARR_LEN(cg->blk_sched);
4327 for (i = 0; i < n; ++i) {
4328 ir_node *block = cg->blk_sched[i];
4329 ir_node *prev = i > 0 ? cg->blk_sched[i-1] : NULL;
4331 set_irn_link(block, prev);
4334 for (i = 0; i < n; ++i) {
4335 ir_node *block = cg->blk_sched[i];
4336 gen_binary_block(block);
4339 be_gas_emit_function_epilog(entity);
4340 be_dbg_method_end();
4342 be_emit_write_line();
4344 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
4350 void ia32_init_emitter(void)
4352 lc_opt_entry_t *be_grp;
4353 lc_opt_entry_t *ia32_grp;
4355 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
4356 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
4358 lc_opt_add_table(ia32_grp, ia32_emitter_options);
4362 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");