2 * Copyright (C) 1995-2011 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief This file implements the ia32 node emitter.
23 * @author Christian Wuerdig, Matthias Braun
25 * Summary table for x86 floatingpoint compares:
26 * (remember effect of unordered on x86: ZF=1, PF=1, CF=1)
34 * pnc_Leg => NP (ordered)
56 #include "iredges_t.h"
60 #include "raw_bitset.h"
69 #include "beemitter.h"
73 #include "ia32_emitter.h"
74 #include "ia32_common_transform.h"
75 #include "gen_ia32_emitter.h"
76 #include "gen_ia32_regalloc_if.h"
77 #include "ia32_nodes_attr.h"
78 #include "ia32_new_nodes.h"
79 #include "ia32_architecture.h"
80 #include "bearch_ia32_t.h"
82 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
84 static const ia32_isa_t *isa;
85 static char pic_base_label[128];
86 static ir_label_t exc_label_id;
87 static int mark_spill_reload = 0;
90 static bool sp_relative;
91 static int frame_type_size;
92 static int callframe_offset;
94 /** Return the next block in Block schedule */
95 static ir_node *get_prev_block_sched(const ir_node *block)
97 return (ir_node*)get_irn_link(block);
100 /** Checks if the current block is a fall-through target. */
101 static int is_fallthrough(const ir_node *cfgpred)
105 if (!is_Proj(cfgpred))
107 pred = get_Proj_pred(cfgpred);
108 if (is_ia32_SwitchJmp(pred))
115 * returns non-zero if the given block needs a label
116 * because of being a jump-target (and not a fall-through)
118 static int block_needs_label(const ir_node *block)
121 int n_cfgpreds = get_Block_n_cfgpreds(block);
123 if (get_Block_entity(block) != NULL)
126 if (n_cfgpreds == 0) {
128 } else if (n_cfgpreds == 1) {
129 ir_node *cfgpred = get_Block_cfgpred(block, 0);
130 ir_node *cfgpred_block = get_nodes_block(cfgpred);
132 if (get_prev_block_sched(block) == cfgpred_block
133 && is_fallthrough(cfgpred)) {
142 * Add a number to a prefix. This number will not be used a second time.
144 static char *get_unique_label(char *buf, size_t buflen, const char *prefix)
146 static unsigned long id = 0;
147 snprintf(buf, buflen, "%s%s%lu", be_gas_get_private_prefix(), prefix, ++id);
152 * Emit the name of the 8bit low register
154 static void emit_8bit_register(const arch_register_t *reg)
156 const char *reg_name = arch_register_get_name(reg);
157 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
158 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
161 be_emit_char(reg_name[1]); /* get the basic name of the register */
166 * Emit the name of the 8bit high register
168 static void emit_8bit_register_high(const arch_register_t *reg)
170 const char *reg_name = arch_register_get_name(reg);
171 assert(reg->index == REG_GP_EAX || reg->index == REG_GP_EBX
172 || reg->index == REG_GP_ECX || reg->index == REG_GP_EDX);
175 be_emit_char(reg_name[1]); /* get the basic name of the register */
179 static void emit_16bit_register(const arch_register_t *reg)
181 const char *reg_name = arch_register_get_name(reg);
184 be_emit_string(reg_name+1); /* skip the 'e' prefix of the 32bit names */
188 * emit a register, possible shortened by a mode
190 * @param reg the register
191 * @param mode the mode of the register or NULL for full register
193 static void emit_register(const arch_register_t *reg, const ir_mode *mode)
195 const char *reg_name;
198 int size = get_mode_size_bits(mode);
200 case 8: emit_8bit_register(reg); return;
201 case 16: emit_16bit_register(reg); return;
203 assert(mode_is_float(mode) || size == 32);
206 reg_name = arch_register_get_name(reg);
209 be_emit_string(reg_name);
212 void ia32_emit_source_register(const ir_node *node, int pos)
214 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
216 emit_register(reg, NULL);
219 static void ia32_emit_entity(ir_entity *entity, int no_pic_adjust)
221 be_gas_emit_entity(entity);
223 if (get_entity_owner(entity) == get_tls_type()) {
224 if (!entity_has_definition(entity)) {
225 be_emit_cstring("@INDNTPOFF");
227 be_emit_cstring("@NTPOFF");
231 if (do_pic && !no_pic_adjust) {
233 be_emit_string(pic_base_label);
237 static void emit_ia32_Immediate_no_prefix(const ir_node *node)
239 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
241 if (attr->symconst != NULL) {
244 ia32_emit_entity(attr->symconst, attr->no_pic_adjust);
246 if (attr->symconst == NULL || attr->offset != 0) {
247 if (attr->symconst != NULL) {
248 be_emit_irprintf("%+d", attr->offset);
250 be_emit_irprintf("0x%X", attr->offset);
255 static void emit_ia32_Immediate(const ir_node *node)
258 emit_ia32_Immediate_no_prefix(node);
261 void ia32_emit_8bit_source_register_or_immediate(const ir_node *node, int pos)
263 const arch_register_t *reg;
264 const ir_node *in = get_irn_n(node, pos);
265 if (is_ia32_Immediate(in)) {
266 emit_ia32_Immediate(in);
270 reg = arch_get_irn_register_in(node, pos);
271 emit_8bit_register(reg);
274 void ia32_emit_8bit_high_source_register(const ir_node *node, int pos)
276 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
277 emit_8bit_register_high(reg);
280 void ia32_emit_16bit_source_register_or_immediate(const ir_node *node, int pos)
282 const arch_register_t *reg;
283 const ir_node *in = get_irn_n(node, pos);
284 if (is_ia32_Immediate(in)) {
285 emit_ia32_Immediate(in);
289 reg = arch_get_irn_register_in(node, pos);
290 emit_16bit_register(reg);
293 void ia32_emit_dest_register(const ir_node *node, int pos)
295 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
297 emit_register(reg, NULL);
300 void ia32_emit_dest_register_size(const ir_node *node, int pos)
302 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
304 emit_register(reg, get_ia32_ls_mode(node));
307 void ia32_emit_8bit_dest_register(const ir_node *node, int pos)
309 const arch_register_t *reg = arch_get_irn_register_out(node, pos);
311 emit_register(reg, mode_Bu);
314 void ia32_emit_x87_register(const ir_node *node, int pos)
316 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
320 be_emit_string(attr->x87[pos]->name);
323 static void ia32_emit_mode_suffix_mode(const ir_mode *mode)
325 assert(mode_is_int(mode) || mode_is_reference(mode));
326 switch (get_mode_size_bits(mode)) {
327 case 8: be_emit_char('b'); return;
328 case 16: be_emit_char('w'); return;
329 case 32: be_emit_char('l'); return;
330 /* gas docu says q is the suffix but gcc, objdump and icc use ll
332 case 64: be_emit_cstring("ll"); return;
334 panic("Can't output mode_suffix for %+F", mode);
337 void ia32_emit_mode_suffix(const ir_node *node)
339 ir_mode *mode = get_ia32_ls_mode(node);
343 ia32_emit_mode_suffix_mode(mode);
346 void ia32_emit_x87_mode_suffix(const ir_node *node)
350 /* we only need to emit the mode on address mode */
351 if (get_ia32_op_type(node) == ia32_Normal)
354 mode = get_ia32_ls_mode(node);
355 assert(mode != NULL);
357 if (mode_is_float(mode)) {
358 switch (get_mode_size_bits(mode)) {
359 case 32: be_emit_char('s'); return;
360 case 64: be_emit_char('l'); return;
361 /* long doubles have different sizes due to alignment on different
365 case 128: be_emit_char('t'); return;
368 assert(mode_is_int(mode) || mode_is_reference(mode));
369 switch (get_mode_size_bits(mode)) {
370 case 16: be_emit_char('s'); return;
371 case 32: be_emit_char('l'); return;
372 /* gas docu says q is the suffix but gcc, objdump and icc use ll
374 case 64: be_emit_cstring("ll"); return;
377 panic("Can't output mode_suffix for %+F", mode);
380 static char get_xmm_mode_suffix(ir_mode *mode)
382 assert(mode_is_float(mode));
383 switch (get_mode_size_bits(mode)) {
386 default: panic("Invalid XMM mode");
390 void ia32_emit_xmm_mode_suffix(const ir_node *node)
392 ir_mode *mode = get_ia32_ls_mode(node);
393 assert(mode != NULL);
395 be_emit_char(get_xmm_mode_suffix(mode));
398 void ia32_emit_xmm_mode_suffix_s(const ir_node *node)
400 ir_mode *mode = get_ia32_ls_mode(node);
401 assert(mode != NULL);
402 be_emit_char(get_xmm_mode_suffix(mode));
405 void ia32_emit_extend_suffix(const ir_node *node)
407 ir_mode *mode = get_ia32_ls_mode(node);
408 if (get_mode_size_bits(mode) == 32)
410 be_emit_char(mode_is_signed(mode) ? 's' : 'z');
411 ia32_emit_mode_suffix_mode(mode);
414 void ia32_emit_source_register_or_immediate(const ir_node *node, int pos)
416 ir_node *in = get_irn_n(node, pos);
417 if (is_ia32_Immediate(in)) {
418 emit_ia32_Immediate(in);
420 const ir_mode *mode = get_ia32_ls_mode(node);
421 const arch_register_t *reg = arch_get_irn_register_in(node, pos);
422 emit_register(reg, mode);
427 * Returns the target block for a control flow node.
429 static ir_node *get_cfop_target_block(const ir_node *irn)
431 assert(get_irn_mode(irn) == mode_X);
432 return (ir_node*)get_irn_link(irn);
436 * Emits the target label for a control flow node.
438 static void ia32_emit_cfop_target(const ir_node *node)
440 ir_node *block = get_cfop_target_block(node);
441 be_gas_emit_block_name(block);
445 * Emit the suffix for a compare instruction.
447 static void ia32_emit_condition_code(ia32_condition_code_t cc)
450 case ia32_cc_overflow: be_emit_cstring("o"); return;
451 case ia32_cc_not_overflow: be_emit_cstring("no"); return;
452 case ia32_cc_float_below:
453 case ia32_cc_float_unordered_below:
454 case ia32_cc_below: be_emit_cstring("b"); return;
455 case ia32_cc_float_above_equal:
456 case ia32_cc_float_unordered_above_equal:
457 case ia32_cc_above_equal: be_emit_cstring("ae"); return;
458 case ia32_cc_float_equal:
459 case ia32_cc_equal: be_emit_cstring("e"); return;
460 case ia32_cc_float_not_equal:
461 case ia32_cc_not_equal: be_emit_cstring("ne"); return;
462 case ia32_cc_float_below_equal:
463 case ia32_cc_float_unordered_below_equal:
464 case ia32_cc_below_equal: be_emit_cstring("be"); return;
465 case ia32_cc_float_above:
466 case ia32_cc_float_unordered_above:
467 case ia32_cc_above: be_emit_cstring("a"); return;
468 case ia32_cc_sign: be_emit_cstring("s"); return;
469 case ia32_cc_not_sign: be_emit_cstring("ns"); return;
470 case ia32_cc_parity: be_emit_cstring("p"); return;
471 case ia32_cc_not_parity: be_emit_cstring("np"); return;
472 case ia32_cc_less: be_emit_cstring("l"); return;
473 case ia32_cc_greater_equal: be_emit_cstring("ge"); return;
474 case ia32_cc_less_equal: be_emit_cstring("le"); return;
475 case ia32_cc_greater: be_emit_cstring("g"); return;
476 case ia32_cc_float_parity_cases:
477 case ia32_cc_additional_float_cases:
480 panic("Invalid ia32 condition code");
483 typedef enum ia32_emit_mod_t {
485 EMIT_RESPECT_LS = 1U << 0,
486 EMIT_ALTERNATE_AM = 1U << 1,
488 EMIT_HIGH_REG = 1U << 3,
489 EMIT_LOW_REG = 1U << 4
491 ENUM_BITSET(ia32_emit_mod_t)
494 * Emits address mode.
496 void ia32_emit_am(const ir_node *node)
498 ir_entity *ent = get_ia32_am_sc(node);
499 int offs = get_ia32_am_offs_int(node);
500 ir_node *base = get_irn_n(node, n_ia32_base);
501 int has_base = !is_ia32_NoReg_GP(base);
502 ir_node *idx = get_irn_n(node, n_ia32_index);
503 int has_index = !is_ia32_NoReg_GP(idx);
505 /* just to be sure... */
506 assert(!is_ia32_use_frame(node) || get_ia32_frame_ent(node) != NULL);
508 if (get_ia32_am_tls_segment(node))
509 be_emit_cstring("%gs:");
513 const ia32_attr_t *attr = get_ia32_attr_const(node);
514 if (is_ia32_am_sc_sign(node))
516 ia32_emit_entity(ent, attr->data.am_sc_no_pic_adjust);
519 /* also handle special case if nothing is set */
520 if (offs != 0 || (ent == NULL && !has_base && !has_index)) {
522 be_emit_irprintf("%+d", offs);
524 be_emit_irprintf("%d", offs);
528 if (has_base || has_index) {
533 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_base);
534 emit_register(reg, NULL);
537 /* emit index + scale */
539 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_index);
542 emit_register(reg, NULL);
544 scale = get_ia32_am_scale(node);
546 be_emit_irprintf(",%d", 1 << scale);
554 * fmt parameter output
555 * ---- ---------------------- ---------------------------------------------
557 * %AM <node> address mode of the node
558 * %AR const arch_register_t* address mode of the node or register
559 * %ASx <node> address mode of the node or source register x
560 * %Dx <node> destination register x
561 * %I <node> immediate of the node
562 * %L <node> control flow target of the node
563 * %M <node> mode suffix of the node
564 * %P int condition code
565 * %R const arch_register_t* register
566 * %Sx <node> source register x
567 * %s const char* string
568 * %u unsigned int unsigned int
569 * %d signed int signed int
572 * # modifier for %ASx, %D, %R, and %S uses ls mode of node to alter register width
573 * * modifier does not prefix immediates with $, but AM with *
574 * l modifier for %lu and %ld
575 * > modifier to output high 8bit register (ah, bh)
576 * < modifier to output low 8bit register (al, bl)
578 static void ia32_emitf(const ir_node *node, const char *fmt, ...)
584 const char *start = fmt;
585 ia32_emit_mod_t mod = EMIT_NONE;
587 while (*fmt != '%' && *fmt != '\n' && *fmt != '\0')
590 be_emit_string_len(start, fmt - start);
594 be_emit_finish_line_gas(node);
607 case '*': mod |= EMIT_ALTERNATE_AM; break;
608 case '#': mod |= EMIT_RESPECT_LS; break;
609 case 'l': mod |= EMIT_LONG; break;
610 case '>': mod |= EMIT_HIGH_REG; break;
611 case '<': mod |= EMIT_LOW_REG; break;
620 arch_register_t const *reg;
631 if (mod & EMIT_ALTERNATE_AM)
637 reg = va_arg(ap, const arch_register_t*);
638 if (get_ia32_op_type(node) == ia32_AddrModeS) {
645 if (get_ia32_op_type(node) == ia32_AddrModeS) {
649 assert(get_ia32_op_type(node) == ia32_Normal);
653 default: goto unknown;
659 if (*fmt < '0' || '9' <= *fmt)
661 reg = arch_get_irn_register_out(node, *fmt++ - '0');
667 if (!(mod & EMIT_ALTERNATE_AM))
669 emit_ia32_Immediate_no_prefix(imm);
673 ia32_emit_cfop_target(node);
677 ia32_emit_mode_suffix_mode(get_ia32_ls_mode(node));
681 ia32_condition_code_t cc = va_arg(ap, ia32_condition_code_t);
682 ia32_emit_condition_code(cc);
687 reg = va_arg(ap, const arch_register_t*);
689 if (mod & EMIT_ALTERNATE_AM)
691 if (mod & EMIT_HIGH_REG) {
692 emit_8bit_register_high(reg);
693 } else if (mod & EMIT_LOW_REG) {
694 emit_8bit_register(reg);
696 emit_register(reg, mod & EMIT_RESPECT_LS ? get_ia32_ls_mode(node) : NULL);
704 if (*fmt < '0' || '9' <= *fmt)
708 imm = get_irn_n(node, pos);
709 if (is_ia32_Immediate(imm)) {
712 reg = arch_get_irn_register_in(node, pos);
718 const char *str = va_arg(ap, const char*);
724 if (mod & EMIT_LONG) {
725 unsigned long num = va_arg(ap, unsigned long);
726 be_emit_irprintf("%lu", num);
728 unsigned num = va_arg(ap, unsigned);
729 be_emit_irprintf("%u", num);
734 if (mod & EMIT_LONG) {
735 long num = va_arg(ap, long);
736 be_emit_irprintf("%ld", num);
738 int num = va_arg(ap, int);
739 be_emit_irprintf("%d", num);
745 panic("unknown format conversion in ia32_emitf()");
753 * Emits registers and/or address mode of a binary operation.
755 void ia32_emit_binop(const ir_node *node)
757 if (is_ia32_Immediate(get_irn_n(node, n_ia32_binary_right))) {
758 ia32_emitf(node, "%#S4, %#AS3");
760 ia32_emitf(node, "%#AS4, %#S3");
765 * Emits registers and/or address mode of a binary operation.
767 void ia32_emit_x87_binop(const ir_node *node)
769 switch (get_ia32_op_type(node)) {
772 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
773 const arch_register_t *in1 = x87_attr->x87[0];
774 const arch_register_t *in = x87_attr->x87[1];
775 const arch_register_t *out = x87_attr->x87[2];
779 } else if (out == in) {
784 be_emit_string(arch_register_get_name(in));
785 be_emit_cstring(", %");
786 be_emit_string(arch_register_get_name(out));
794 assert(0 && "unsupported op type");
799 * Emits registers and/or address mode of a unary operation.
801 void ia32_emit_unop(const ir_node *node, int pos)
805 ia32_emitf(node, fmt);
808 static void emit_ia32_IMul(const ir_node *node)
810 ir_node *left = get_irn_n(node, n_ia32_IMul_left);
811 const arch_register_t *out_reg = arch_get_irn_register_out(node, pn_ia32_IMul_res);
813 /* do we need the 3-address form? */
814 if (is_ia32_NoReg_GP(left) ||
815 arch_get_irn_register_in(node, n_ia32_IMul_left) != out_reg) {
816 ia32_emitf(node, "\timul%M %#S4, %#AS3, %#D0\n");
818 ia32_emitf(node, "\timul%M %#AS4, %#S3\n");
823 * walks up a tree of copies/perms/spills/reloads to find the original value
824 * that is moved around
826 static ir_node *find_original_value(ir_node *node)
828 if (irn_visited(node))
831 mark_irn_visited(node);
832 if (be_is_Copy(node)) {
833 return find_original_value(be_get_Copy_op(node));
834 } else if (be_is_CopyKeep(node)) {
835 return find_original_value(be_get_CopyKeep_op(node));
836 } else if (is_Proj(node)) {
837 ir_node *pred = get_Proj_pred(node);
838 if (be_is_Perm(pred)) {
839 return find_original_value(get_irn_n(pred, get_Proj_proj(node)));
840 } else if (be_is_MemPerm(pred)) {
841 return find_original_value(get_irn_n(pred, get_Proj_proj(node) + 1));
842 } else if (is_ia32_Load(pred)) {
843 return find_original_value(get_irn_n(pred, n_ia32_Load_mem));
844 } else if (is_ia32_Store(pred)) {
845 return find_original_value(get_irn_n(pred, n_ia32_Store_val));
849 } else if (is_Phi(node)) {
851 arity = get_irn_arity(node);
852 for (i = 0; i < arity; ++i) {
853 ir_node *in = get_irn_n(node, i);
854 ir_node *res = find_original_value(in);
865 static int determine_final_cc(const ir_node *node, int flags_pos, int cc)
867 ir_node *flags = get_irn_n(node, flags_pos);
868 const ia32_attr_t *flags_attr;
869 flags = skip_Proj(flags);
871 if (is_ia32_Sahf(flags)) {
872 ir_node *cmp = get_irn_n(flags, n_ia32_Sahf_val);
873 if (!(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
874 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp))) {
875 inc_irg_visited(current_ir_graph);
876 cmp = find_original_value(cmp);
878 assert(is_ia32_FucomFnstsw(cmp) || is_ia32_FucompFnstsw(cmp)
879 || is_ia32_FucomppFnstsw(cmp) || is_ia32_FtstFnstsw(cmp));
882 flags_attr = get_ia32_attr_const(cmp);
884 flags_attr = get_ia32_attr_const(flags);
887 if (flags_attr->data.ins_permuted)
888 cc = ia32_invert_condition_code(cc);
892 void ia32_emit_cmp_suffix_node(const ir_node *node, int flags_pos)
894 ia32_condition_code_t cc = get_ia32_condcode(node);
895 cc = determine_final_cc(node, flags_pos, cc);
897 ia32_emit_condition_code(cc);
901 * Emits an exception label for a given node.
903 static void ia32_emit_exc_label(const ir_node *node)
905 be_emit_string(be_gas_insn_label_prefix());
906 be_emit_irprintf("%lu", get_ia32_exc_label_id(node));
910 * Returns the Proj with projection number proj and NOT mode_M
912 static ir_node *get_proj(const ir_node *node, long proj)
914 const ir_edge_t *edge;
917 assert(get_irn_mode(node) == mode_T && "expected mode_T node");
919 foreach_out_edge(node, edge) {
920 src = get_edge_src_irn(edge);
922 assert(is_Proj(src) && "Proj expected");
923 if (get_irn_mode(src) == mode_M)
926 if (get_Proj_proj(src) == proj)
932 static int can_be_fallthrough(const ir_node *node)
934 ir_node *target_block = get_cfop_target_block(node);
935 ir_node *block = get_nodes_block(node);
936 return get_prev_block_sched(target_block) == block;
940 * Emits the jump sequence for a conditional jump (cmp + jmp_true + jmp_false)
942 static void emit_ia32_Jcc(const ir_node *node)
944 int need_parity_label = 0;
945 ia32_condition_code_t cc = get_ia32_condcode(node);
946 const ir_node *proj_true;
947 const ir_node *proj_false;
949 cc = determine_final_cc(node, 0, cc);
952 proj_true = get_proj(node, pn_ia32_Jcc_true);
953 assert(proj_true && "Jcc without true Proj");
955 proj_false = get_proj(node, pn_ia32_Jcc_false);
956 assert(proj_false && "Jcc without false Proj");
958 if (can_be_fallthrough(proj_true)) {
959 /* exchange both proj's so the second one can be omitted */
960 const ir_node *t = proj_true;
962 proj_true = proj_false;
964 cc = ia32_negate_condition_code(cc);
967 if (cc & ia32_cc_float_parity_cases) {
968 /* Some floating point comparisons require a test of the parity flag,
969 * which indicates that the result is unordered */
970 if (cc & ia32_cc_negated) {
971 ia32_emitf(proj_true, "\tjp %L\n");
973 /* we need a local label if the false proj is a fallthrough
974 * as the falseblock might have no label emitted then */
975 if (can_be_fallthrough(proj_false)) {
976 need_parity_label = 1;
977 ia32_emitf(proj_false, "\tjp 1f\n");
979 ia32_emitf(proj_false, "\tjp %L\n");
983 ia32_emitf(proj_true, "\tj%P %L\n", cc);
984 if (need_parity_label) {
985 ia32_emitf(NULL, "1:\n");
988 /* the second Proj might be a fallthrough */
989 if (can_be_fallthrough(proj_false)) {
990 ia32_emitf(proj_false, "\t/* fallthrough to %L */\n");
992 ia32_emitf(proj_false, "\tjmp %L\n");
997 * Emits an ia32 Setcc. This is mostly easy but some floating point compares
1000 static void emit_ia32_Setcc(const ir_node *node)
1002 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
1004 ia32_condition_code_t cc = get_ia32_condcode(node);
1005 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
1006 if (cc & ia32_cc_float_parity_cases) {
1007 if (cc & ia32_cc_negated) {
1008 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1009 ia32_emitf(node, "\tsetp %>R\n", dreg);
1010 ia32_emitf(node, "\torb %>R, %<R\n", dreg, dreg);
1012 ia32_emitf(node, "\tset%P %<R\n", cc, dreg);
1013 ia32_emitf(node, "\tsetnp %>R\n", dreg);
1014 ia32_emitf(node, "\tandb %>R, %<R\n", dreg, dreg);
1017 ia32_emitf(node, "\tset%P %#R\n", cc, dreg);
1021 static void emit_ia32_CMovcc(const ir_node *node)
1023 const ia32_attr_t *attr = get_ia32_attr_const(node);
1024 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
1025 ia32_condition_code_t cc = get_ia32_condcode(node);
1026 const arch_register_t *in_true;
1027 const arch_register_t *in_false;
1029 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
1030 /* although you can't set ins_permuted in the constructor it might still
1031 * be set by memory operand folding
1032 * Permuting inputs of a cmov means the condition is negated!
1034 if (attr->data.ins_permuted)
1035 cc = ia32_negate_condition_code(cc);
1037 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
1038 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
1040 /* should be same constraint fullfilled? */
1041 if (out == in_false) {
1042 /* yes -> nothing to do */
1043 } else if (out == in_true) {
1044 const arch_register_t *tmp;
1046 assert(get_ia32_op_type(node) == ia32_Normal);
1048 cc = ia32_negate_condition_code(cc);
1055 ia32_emitf(node, "\tmovl %R, %R\n", in_false, out);
1058 if (cc & ia32_cc_float_parity_cases) {
1059 panic("CMov with floatingpoint compare/parity not supported yet");
1062 ia32_emitf(node, "\tcmov%P %#AR, %#R\n", cc, in_true, out);
1066 * Emits code for a SwitchJmp
1068 static void emit_ia32_SwitchJmp(const ir_node *node)
1070 ir_entity *jump_table = get_ia32_am_sc(node);
1071 const ir_switch_table *table = get_ia32_switch_table(node);
1073 ia32_emitf(node, "\tjmp %*AM\n");
1074 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
1078 * Emits code for a unconditional jump.
1080 static void emit_ia32_Jmp(const ir_node *node)
1082 /* we have a block schedule */
1083 if (can_be_fallthrough(node)) {
1084 ia32_emitf(node, "\t/* fallthrough to %L */\n");
1086 ia32_emitf(node, "\tjmp %L\n");
1091 * Emit an inline assembler operand.
1093 * @param node the ia32_ASM node
1094 * @param s points to the operand (a %c)
1096 * @return pointer to the first char in s NOT in the current operand
1098 static const char* emit_asm_operand(const ir_node *node, const char *s)
1100 const ia32_attr_t *ia32_attr = get_ia32_attr_const(node);
1101 const ia32_asm_attr_t *attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t,
1103 const arch_register_t *reg;
1104 const ia32_asm_reg_t *asm_regs = attr->register_map;
1105 const ia32_asm_reg_t *asm_reg;
1114 /* parse modifiers */
1117 ir_fprintf(stderr, "Warning: asm text (%+F) ends with %%\n", node);
1142 "Warning: asm text (%+F) contains unknown modifier '%c' for asm op\n",
1149 if (sscanf(s, "%d%n", &num, &p) != 1) {
1150 ir_fprintf(stderr, "Warning: Couldn't parse assembler operand (%+F)\n",
1157 if (num < 0 || ARR_LEN(asm_regs) <= (size_t)num) {
1159 "Error: Custom assembler references invalid input/output (%+F)\n",
1163 asm_reg = & asm_regs[num];
1164 assert(asm_reg->valid);
1167 if (asm_reg->use_input == 0) {
1168 reg = arch_get_irn_register_out(node, asm_reg->inout_pos);
1170 ir_node *pred = get_irn_n(node, asm_reg->inout_pos);
1172 /* might be an immediate value */
1173 if (is_ia32_Immediate(pred)) {
1174 emit_ia32_Immediate(pred);
1177 reg = arch_get_irn_register_in(node, asm_reg->inout_pos);
1181 "Warning: no register assigned for %d asm op (%+F)\n",
1186 if (asm_reg->memory) {
1191 if (modifier != 0) {
1194 emit_8bit_register(reg);
1197 emit_8bit_register_high(reg);
1200 emit_16bit_register(reg);
1203 panic("Invalid asm op modifier");
1206 emit_register(reg, asm_reg->memory ? mode_Iu : asm_reg->mode);
1209 if (asm_reg->memory) {
1217 * Emits code for an ASM pseudo op.
1219 static void emit_ia32_Asm(const ir_node *node)
1221 const void *gen_attr = get_irn_generic_attr_const(node);
1222 const ia32_asm_attr_t *attr
1223 = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, gen_attr);
1224 ident *asm_text = attr->asm_text;
1225 const char *s = get_id_str(asm_text);
1227 ia32_emitf(node, "#APP\t\n");
1234 s = emit_asm_operand(node, s);
1240 ia32_emitf(NULL, "\n#NO_APP\n");
1245 * Emit movsb/w instructions to make mov count divideable by 4
1247 static void emit_CopyB_prolog(unsigned size)
1250 ia32_emitf(NULL, "\tmovsb\n");
1252 ia32_emitf(NULL, "\tmovsw\n");
1256 * Emit rep movsd instruction for memcopy.
1258 static void emit_ia32_CopyB(const ir_node *node)
1260 unsigned size = get_ia32_copyb_size(node);
1262 emit_CopyB_prolog(size);
1263 ia32_emitf(node, "\trep movsd\n");
1267 * Emits unrolled memcopy.
1269 static void emit_ia32_CopyB_i(const ir_node *node)
1271 unsigned size = get_ia32_copyb_size(node);
1273 emit_CopyB_prolog(size);
1277 ia32_emitf(NULL, "\tmovsd\n");
1283 * Emit code for conversions (I, FP), (FP, I) and (FP, FP).
1285 static void emit_ia32_Conv_with_FP(const ir_node *node, const char* conv_f,
1288 ir_mode *ls_mode = get_ia32_ls_mode(node);
1289 int ls_bits = get_mode_size_bits(ls_mode);
1290 const char *conv = ls_bits == 32 ? conv_f : conv_d;
1292 ia32_emitf(node, "\tcvt%s %AS3, %D0\n", conv);
1295 static void emit_ia32_Conv_I2FP(const ir_node *node)
1297 emit_ia32_Conv_with_FP(node, "si2ss", "si2sd");
1300 static void emit_ia32_Conv_FP2I(const ir_node *node)
1302 emit_ia32_Conv_with_FP(node, "ss2si", "sd2si");
1305 static void emit_ia32_Conv_FP2FP(const ir_node *node)
1307 emit_ia32_Conv_with_FP(node, "sd2ss", "ss2sd");
1311 * Emits code for an Int conversion.
1313 static void emit_ia32_Conv_I2I(const ir_node *node)
1315 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1316 int signed_mode = mode_is_signed(smaller_mode);
1317 const char *sign_suffix;
1319 assert(!mode_is_float(smaller_mode));
1321 sign_suffix = signed_mode ? "s" : "z";
1322 ia32_emitf(node, "\tmov%s%Ml %#AS3, %D0\n", sign_suffix);
1328 static void emit_ia32_Call(const ir_node *node)
1330 /* Special case: Call must not have its immediates prefixed by $, instead
1331 * address mode is prefixed by *. */
1332 ia32_emitf(node, "\tcall %*AS3\n");
1337 * Emits code to increase stack pointer.
1339 static void emit_be_IncSP(const ir_node *node)
1341 int offs = be_get_IncSP_offset(node);
1347 ia32_emitf(node, "\tsubl $%u, %D0\n", offs);
1349 ia32_emitf(node, "\taddl $%u, %D0\n", -offs);
1354 * Emits code for Copy/CopyKeep.
1356 static void Copy_emitter(const ir_node *node, const ir_node *op)
1358 const arch_register_t *in = arch_get_irn_register(op);
1359 const arch_register_t *out = arch_get_irn_register(node);
1364 /* copies of vf nodes aren't real... */
1365 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
1368 ia32_emitf(node, "\tmovl %R, %R\n", in, out);
1371 static void emit_be_Copy(const ir_node *node)
1373 Copy_emitter(node, be_get_Copy_op(node));
1376 static void emit_be_CopyKeep(const ir_node *node)
1378 Copy_emitter(node, be_get_CopyKeep_op(node));
1382 * Emits code for exchange.
1384 static void emit_be_Perm(const ir_node *node)
1386 const arch_register_t *in0, *in1;
1387 const arch_register_class_t *cls0, *cls1;
1389 in0 = arch_get_irn_register(get_irn_n(node, 0));
1390 in1 = arch_get_irn_register(get_irn_n(node, 1));
1392 cls0 = arch_register_get_class(in0);
1393 cls1 = arch_register_get_class(in1);
1395 assert(cls0 == cls1 && "Register class mismatch at Perm");
1397 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
1398 ia32_emitf(node, "\txchg %R, %R\n", in1, in0);
1399 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
1400 ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
1401 ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
1402 ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
1403 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
1405 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
1408 panic("unexpected register class in be_Perm (%+F)", node);
1413 * Emits code for Constant loading.
1415 static void emit_ia32_Const(const ir_node *node)
1417 ia32_emitf(node, "\tmovl %I, %D0\n");
1420 /* helper function for emit_ia32_Minus64Bit */
1421 static void emit_mov(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1423 ia32_emitf(node, "\tmovl %R, %R\n", src, dst);
1426 /* helper function for emit_ia32_Minus64Bit */
1427 static void emit_neg(const ir_node* node, const arch_register_t *reg)
1429 ia32_emitf(node, "\tnegl %R\n", reg);
1432 /* helper function for emit_ia32_Minus64Bit */
1433 static void emit_sbb0(const ir_node* node, const arch_register_t *reg)
1435 ia32_emitf(node, "\tsbbl $0, %R\n", reg);
1438 /* helper function for emit_ia32_Minus64Bit */
1439 static void emit_sbb(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1441 ia32_emitf(node, "\tsbbl %R, %R\n", src, dst);
1444 /* helper function for emit_ia32_Minus64Bit */
1445 static void emit_xchg(const ir_node* node, const arch_register_t *src, const arch_register_t *dst)
1447 ia32_emitf(node, "\txchgl %R, %R\n", src, dst);
1450 /* helper function for emit_ia32_Minus64Bit */
1451 static void emit_zero(const ir_node* node, const arch_register_t *reg)
1453 ia32_emitf(node, "\txorl %R, %R\n", reg, reg);
1456 static void emit_ia32_Minus64Bit(const ir_node *node)
1458 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
1459 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
1460 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
1461 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
1463 if (out_lo == in_lo) {
1464 if (out_hi != in_hi) {
1465 /* a -> a, b -> d */
1468 /* a -> a, b -> b */
1471 } else if (out_lo == in_hi) {
1472 if (out_hi == in_lo) {
1473 /* a -> b, b -> a */
1474 emit_xchg(node, in_lo, in_hi);
1477 /* a -> b, b -> d */
1478 emit_mov(node, in_hi, out_hi);
1479 emit_mov(node, in_lo, out_lo);
1483 if (out_hi == in_lo) {
1484 /* a -> c, b -> a */
1485 emit_mov(node, in_lo, out_lo);
1487 } else if (out_hi == in_hi) {
1488 /* a -> c, b -> b */
1489 emit_mov(node, in_lo, out_lo);
1492 /* a -> c, b -> d */
1493 emit_mov(node, in_lo, out_lo);
1499 emit_neg( node, out_hi);
1500 emit_neg( node, out_lo);
1501 emit_sbb0(node, out_hi);
1505 emit_zero(node, out_hi);
1506 emit_neg( node, out_lo);
1507 emit_sbb( node, in_hi, out_hi);
1510 static void emit_ia32_GetEIP(const ir_node *node)
1512 ia32_emitf(node, "\tcall %s\n", pic_base_label);
1513 ia32_emitf(NULL, "%s:\n", pic_base_label);
1514 ia32_emitf(node, "\tpopl %D0\n");
1517 static void emit_ia32_ClimbFrame(const ir_node *node)
1519 const ia32_climbframe_attr_t *attr = get_ia32_climbframe_attr_const(node);
1521 ia32_emitf(node, "\tmovl %S0, %D0\n");
1522 ia32_emitf(node, "\tmovl $%u, %S1\n", attr->count);
1523 be_gas_emit_block_name(node);
1524 be_emit_cstring(":\n");
1525 be_emit_write_line();
1526 ia32_emitf(node, "\tmovl (%D0), %D0\n");
1527 ia32_emitf(node, "\tdec %S1\n");
1528 be_emit_cstring("\tjnz ");
1529 be_gas_emit_block_name(node);
1530 be_emit_finish_line_gas(node);
1533 static void emit_be_Return(const ir_node *node)
1535 unsigned pop = be_Return_get_pop(node);
1537 if (pop > 0 || be_Return_get_emit_pop(node)) {
1538 ia32_emitf(node, "\tret $%u\n", pop);
1540 ia32_emitf(node, "\tret\n");
1544 static void emit_Nothing(const ir_node *node)
1551 * Enters the emitter functions for handled nodes into the generic
1552 * pointer of an opcode.
1554 static void ia32_register_emitters(void)
1556 #define IA32_EMIT2(a,b) op_ia32_##a->ops.generic = (op_func)emit_ia32_##b
1557 #define IA32_EMIT(a) IA32_EMIT2(a,a)
1558 #define EMIT(a) op_##a->ops.generic = (op_func)emit_##a
1559 #define IGN(a) op_##a->ops.generic = (op_func)emit_Nothing
1560 #define BE_EMIT(a) op_be_##a->ops.generic = (op_func)emit_be_##a
1561 #define BE_IGN(a) op_be_##a->ops.generic = (op_func)emit_Nothing
1563 /* first clear the generic function pointer for all ops */
1564 ir_clear_opcodes_generic_func();
1566 /* register all emitter functions defined in spec */
1567 ia32_register_spec_emitters();
1569 /* other ia32 emitter functions */
1570 IA32_EMIT2(Conv_I2I8Bit, Conv_I2I);
1575 IA32_EMIT(Conv_FP2FP);
1576 IA32_EMIT(Conv_FP2I);
1577 IA32_EMIT(Conv_I2FP);
1578 IA32_EMIT(Conv_I2I);
1585 IA32_EMIT(Minus64Bit);
1586 IA32_EMIT(SwitchJmp);
1587 IA32_EMIT(ClimbFrame);
1590 /* benode emitter */
1610 typedef void (*emit_func_ptr) (const ir_node *);
1613 * Assign and emit an exception label if the current instruction can fail.
1615 static void ia32_assign_exc_label(ir_node *node)
1617 /* assign a new ID to the instruction */
1618 set_ia32_exc_label_id(node, ++exc_label_id);
1620 ia32_emit_exc_label(node);
1622 be_emit_pad_comment();
1623 be_emit_cstring("/* exception to Block ");
1624 ia32_emit_cfop_target(node);
1625 be_emit_cstring(" */\n");
1626 be_emit_write_line();
1630 * Emits code for a node.
1632 static void ia32_emit_node(ir_node *node)
1634 ir_op *op = get_irn_op(node);
1636 DBG((dbg, LEVEL_1, "emitting code for %+F\n", node));
1638 if (is_ia32_irn(node)) {
1639 if (get_ia32_exc_label(node)) {
1640 /* emit the exception label of this instruction */
1641 ia32_assign_exc_label(node);
1643 if (mark_spill_reload) {
1644 if (is_ia32_is_spill(node)) {
1645 ia32_emitf(NULL, "\txchg %ebx, %ebx /* spill mark */\n");
1647 if (is_ia32_is_reload(node)) {
1648 ia32_emitf(NULL, "\txchg %edx, %edx /* reload mark */\n");
1650 if (is_ia32_is_remat(node)) {
1651 ia32_emitf(NULL, "\txchg %ecx, %ecx /* remat mark */\n");
1655 if (op->ops.generic) {
1656 emit_func_ptr func = (emit_func_ptr) op->ops.generic;
1658 be_dwarf_location(get_irn_dbg_info(node));
1663 ir_fprintf(stderr, "Error: No emit handler for node %+F (%+G, graph %+F)\n", node, node, current_ir_graph);
1668 int sp_change = arch_get_sp_bias(node);
1669 if (sp_change != 0) {
1670 assert(sp_change != SP_BIAS_RESET);
1671 callframe_offset += sp_change;
1672 be_dwarf_callframe_offset(callframe_offset);
1678 * Emits gas alignment directives
1680 static void ia32_emit_alignment(unsigned align, unsigned skip)
1682 ia32_emitf(NULL, "\t.p2align %u,,%u\n", align, skip);
1686 * Emits gas alignment directives for Labels depended on cpu architecture.
1688 static void ia32_emit_align_label(void)
1690 unsigned align = ia32_cg_config.label_alignment;
1691 unsigned maximum_skip = ia32_cg_config.label_alignment_max_skip;
1692 ia32_emit_alignment(align, maximum_skip);
1696 * Test whether a block should be aligned.
1697 * For cpus in the P4/Athlon class it is useful to align jump labels to
1698 * 16 bytes. However we should only do that if the alignment nops before the
1699 * label aren't executed more often than we have jumps to the label.
1701 static int should_align_block(const ir_node *block)
1703 static const double DELTA = .0001;
1704 ir_graph *irg = get_irn_irg(block);
1705 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1706 ir_node *prev = get_prev_block_sched(block);
1708 double prev_freq = 0; /**< execfreq of the fallthrough block */
1709 double jmp_freq = 0; /**< execfreq of all non-fallthrough blocks */
1712 if (exec_freq == NULL)
1714 if (ia32_cg_config.label_alignment_factor <= 0)
1717 block_freq = get_block_execfreq(exec_freq, block);
1718 if (block_freq < DELTA)
1721 n_cfgpreds = get_Block_n_cfgpreds(block);
1722 for (i = 0; i < n_cfgpreds; ++i) {
1723 const ir_node *pred = get_Block_cfgpred_block(block, i);
1724 double pred_freq = get_block_execfreq(exec_freq, pred);
1727 prev_freq += pred_freq;
1729 jmp_freq += pred_freq;
1733 if (prev_freq < DELTA && !(jmp_freq < DELTA))
1736 jmp_freq /= prev_freq;
1738 return jmp_freq > ia32_cg_config.label_alignment_factor;
1742 * Emit the block header for a block.
1744 * @param block the block
1745 * @param prev_block the previous block
1747 static void ia32_emit_block_header(ir_node *block)
1749 ir_graph *irg = current_ir_graph;
1750 int need_label = block_needs_label(block);
1751 ir_exec_freq *exec_freq = be_get_irg_exec_freq(irg);
1754 if (block == get_irg_end_block(irg))
1757 if (ia32_cg_config.label_alignment > 0) {
1758 /* align the current block if:
1759 * a) if should be aligned due to its execution frequency
1760 * b) there is no fall-through here
1762 if (should_align_block(block)) {
1763 ia32_emit_align_label();
1765 /* if the predecessor block has no fall-through,
1766 we can always align the label. */
1768 int has_fallthrough = 0;
1770 for (i = get_Block_n_cfgpreds(block) - 1; i >= 0; --i) {
1771 ir_node *cfg_pred = get_Block_cfgpred(block, i);
1772 if (can_be_fallthrough(cfg_pred)) {
1773 has_fallthrough = 1;
1778 if (!has_fallthrough)
1779 ia32_emit_align_label();
1784 be_gas_emit_block_name(block);
1787 be_emit_pad_comment();
1788 be_emit_cstring(" /* ");
1790 be_emit_cstring("\t/* ");
1791 be_gas_emit_block_name(block);
1792 be_emit_cstring(": ");
1795 be_emit_cstring("preds:");
1797 /* emit list of pred blocks in comment */
1798 arity = get_irn_arity(block);
1800 be_emit_cstring(" none");
1803 for (i = 0; i < arity; ++i) {
1804 ir_node *predblock = get_Block_cfgpred_block(block, i);
1805 be_emit_irprintf(" %d", get_irn_node_nr(predblock));
1808 if (exec_freq != NULL) {
1809 be_emit_irprintf(", freq: %f",
1810 get_block_execfreq(exec_freq, block));
1812 be_emit_cstring(" */\n");
1813 be_emit_write_line();
1817 * Walks over the nodes in a block connected by scheduling edges
1818 * and emits code for each node.
1820 static void ia32_gen_block(ir_node *block)
1824 ia32_emit_block_header(block);
1827 ir_graph *irg = get_irn_irg(block);
1828 callframe_offset = 4; /* 4 bytes for the return address */
1829 /* ESP guessing, TODO perform a real ESP simulation */
1830 if (block != get_irg_start_block(irg)) {
1831 callframe_offset += frame_type_size;
1833 be_dwarf_callframe_offset(callframe_offset);
1836 /* emit the contents of the block */
1837 be_dwarf_location(get_irn_dbg_info(block));
1838 sched_foreach(block, node) {
1839 ia32_emit_node(node);
1843 typedef struct exc_entry {
1844 ir_node *exc_instr; /** The instruction that can issue an exception. */
1845 ir_node *block; /** The block to call then. */
1850 * Sets labels for control flow nodes (jump target).
1851 * Links control predecessors to there destination blocks.
1853 static void ia32_gen_labels(ir_node *block, void *data)
1855 exc_entry **exc_list = (exc_entry**)data;
1859 for (n = get_Block_n_cfgpreds(block) - 1; n >= 0; --n) {
1860 pred = get_Block_cfgpred(block, n);
1861 set_irn_link(pred, block);
1863 pred = skip_Proj(pred);
1864 if (is_ia32_irn(pred) && get_ia32_exc_label(pred)) {
1869 ARR_APP1(exc_entry, *exc_list, e);
1870 set_irn_link(pred, block);
1876 * Compare two exception_entries.
1878 static int cmp_exc_entry(const void *a, const void *b)
1880 const exc_entry *ea = (const exc_entry*)a;
1881 const exc_entry *eb = (const exc_entry*)b;
1883 if (get_ia32_exc_label_id(ea->exc_instr) < get_ia32_exc_label_id(eb->exc_instr))
1888 static parameter_dbg_info_t *construct_parameter_infos(ir_graph *irg)
1890 ir_entity *entity = get_irg_entity(irg);
1891 ir_type *type = get_entity_type(entity);
1892 size_t n_params = get_method_n_params(type);
1893 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1894 ir_type *arg_type = layout->arg_type;
1895 size_t n_members = get_compound_n_members(arg_type);
1896 parameter_dbg_info_t *infos = XMALLOCNZ(parameter_dbg_info_t, n_params);
1899 for (i = 0; i < n_members; ++i) {
1900 ir_entity *member = get_compound_member(arg_type, i);
1902 if (!is_parameter_entity(member))
1904 param = get_entity_parameter_number(member);
1905 if (param == IR_VA_START_PARAMETER_NUMBER)
1907 assert(infos[param].entity == NULL && infos[param].reg == NULL);
1908 infos[param].reg = NULL;
1909 infos[param].entity = member;
1916 * Main driver. Emits the code for one routine.
1918 void ia32_gen_routine(ir_graph *irg)
1920 ir_entity *entity = get_irg_entity(irg);
1921 exc_entry *exc_list = NEW_ARR_F(exc_entry, 0);
1922 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
1923 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
1924 ir_node **blk_sched = irg_data->blk_sched;
1925 be_stack_layout_t *layout = be_get_irg_stack_layout(irg);
1926 parameter_dbg_info_t *infos;
1929 isa = (ia32_isa_t*) arch_env;
1930 do_pic = be_get_irg_options(irg)->pic;
1932 be_gas_elf_type_char = '@';
1934 ia32_register_emitters();
1936 get_unique_label(pic_base_label, sizeof(pic_base_label), "PIC_BASE");
1938 infos = construct_parameter_infos(irg);
1939 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
1943 sp_relative = layout->sp_relative;
1944 if (layout->sp_relative) {
1945 ir_type *frame_type = get_irg_frame_type(irg);
1946 frame_type_size = get_type_size_bytes(frame_type);
1947 be_dwarf_callframe_register(&ia32_registers[REG_ESP]);
1949 /* well not entirely correct here, we should emit this after the
1950 * "movl esp, ebp" */
1951 be_dwarf_callframe_register(&ia32_registers[REG_EBP]);
1952 /* TODO: do not hardcode the following */
1953 be_dwarf_callframe_offset(8);
1954 be_dwarf_callframe_spilloffset(&ia32_registers[REG_EBP], -8);
1957 /* we use links to point to target blocks */
1958 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
1959 irg_block_walk_graph(irg, ia32_gen_labels, NULL, &exc_list);
1961 /* initialize next block links */
1962 n = ARR_LEN(blk_sched);
1963 for (i = 0; i < n; ++i) {
1964 ir_node *block = blk_sched[i];
1965 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
1967 set_irn_link(block, prev);
1970 for (i = 0; i < n; ++i) {
1971 ir_node *block = blk_sched[i];
1973 ia32_gen_block(block);
1976 be_gas_emit_function_epilog(entity);
1978 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
1980 /* Sort the exception table using the exception label id's.
1981 Those are ascending with ascending addresses. */
1982 qsort(exc_list, ARR_LEN(exc_list), sizeof(exc_list[0]), cmp_exc_entry);
1986 for (e = 0; e < ARR_LEN(exc_list); ++e) {
1987 be_emit_cstring("\t.long ");
1988 ia32_emit_exc_label(exc_list[e].exc_instr);
1990 be_emit_cstring("\t.long ");
1991 be_gas_emit_block_name(exc_list[e].block);
1995 DEL_ARR_F(exc_list);
1998 static const lc_opt_table_entry_t ia32_emitter_options[] = {
1999 LC_OPT_ENT_BOOL("mark_spill_reload", "mark spills and reloads with ud opcodes", &mark_spill_reload),
2003 /* ==== Experimental binary emitter ==== */
2005 static unsigned char reg_gp_map[N_ia32_gp_REGS];
2006 //static unsigned char reg_mmx_map[N_ia32_mmx_REGS];
2007 //static unsigned char reg_sse_map[N_ia32_xmm_REGS];
2009 static void build_reg_map(void)
2011 reg_gp_map[REG_GP_EAX] = 0x0;
2012 reg_gp_map[REG_GP_ECX] = 0x1;
2013 reg_gp_map[REG_GP_EDX] = 0x2;
2014 reg_gp_map[REG_GP_EBX] = 0x3;
2015 reg_gp_map[REG_GP_ESP] = 0x4;
2016 reg_gp_map[REG_GP_EBP] = 0x5;
2017 reg_gp_map[REG_GP_ESI] = 0x6;
2018 reg_gp_map[REG_GP_EDI] = 0x7;
2021 /** Returns the encoding for a pnc field. */
2022 static unsigned char pnc2cc(ia32_condition_code_t cc)
2027 /** Sign extension bit values for binops */
2029 UNSIGNED_IMM = 0, /**< unsigned immediate */
2030 SIGNEXT_IMM = 2, /**< sign extended immediate */
2033 /** The mod encoding of the ModR/M */
2035 MOD_IND = 0x00, /**< [reg1] */
2036 MOD_IND_BYTE_OFS = 0x40, /**< [reg1 + byte ofs] */
2037 MOD_IND_WORD_OFS = 0x80, /**< [reg1 + word ofs] */
2038 MOD_REG = 0xC0 /**< reg1 */
2041 /** create R/M encoding for ModR/M */
2042 #define ENC_RM(x) (x)
2043 /** create REG encoding for ModR/M */
2044 #define ENC_REG(x) ((x) << 3)
2046 /** create encoding for a SIB byte */
2047 #define ENC_SIB(scale, index, base) ((scale) << 6 | (index) << 3 | (base))
2049 /* Node: The following routines are supposed to append bytes, words, dwords
2050 to the output stream.
2051 Currently the implementation is stupid in that it still creates output
2052 for an "assembler" in the form of .byte, .long
2053 We will change this when enough infrastructure is there to create complete
2054 machine code in memory/object files */
2056 static void bemit8(const unsigned char byte)
2058 be_emit_irprintf("\t.byte 0x%x\n", byte);
2059 be_emit_write_line();
2062 static void bemit16(const unsigned short u16)
2064 be_emit_irprintf("\t.word 0x%x\n", u16);
2065 be_emit_write_line();
2068 static void bemit32(const unsigned u32)
2070 be_emit_irprintf("\t.long 0x%x\n", u32);
2071 be_emit_write_line();
2075 * Emit address of an entity. If @p is_relative is true then a relative
2076 * offset from behind the address to the entity is created.
2078 static void bemit_entity(ir_entity *entity, bool entity_sign, int offset,
2081 if (entity == NULL) {
2086 /* the final version should remember the position in the bytestream
2087 and patch it with the correct address at linktime... */
2088 be_emit_cstring("\t.long ");
2091 be_gas_emit_entity(entity);
2093 if (get_entity_owner(entity) == get_tls_type()) {
2094 if (!entity_has_definition(entity)) {
2095 be_emit_cstring("@INDNTPOFF");
2097 be_emit_cstring("@NTPOFF");
2102 be_emit_cstring("-.");
2107 be_emit_irprintf("%+d", offset);
2110 be_emit_write_line();
2113 static void bemit_jmp_destination(const ir_node *dest_block)
2115 be_emit_cstring("\t.long ");
2116 be_gas_emit_block_name(dest_block);
2117 be_emit_cstring(" - . - 4\n");
2118 be_emit_write_line();
2121 /* end emit routines, all emitters following here should only use the functions
2124 typedef enum reg_modifier {
2129 /** Create a ModR/M byte for src1,src2 registers */
2130 static void bemit_modrr(const arch_register_t *src1,
2131 const arch_register_t *src2)
2133 unsigned char modrm = MOD_REG;
2134 modrm |= ENC_RM(reg_gp_map[src1->index]);
2135 modrm |= ENC_REG(reg_gp_map[src2->index]);
2139 /** Create a ModR/M8 byte for src1,src2 registers */
2140 static void bemit_modrr8(reg_modifier_t high_part1, const arch_register_t *src1,
2141 reg_modifier_t high_part2, const arch_register_t *src2)
2143 unsigned char modrm = MOD_REG;
2144 modrm |= ENC_RM(reg_gp_map[src1->index] + (high_part1 == REG_HIGH ? 4 : 0));
2145 modrm |= ENC_REG(reg_gp_map[src2->index] + (high_part2 == REG_HIGH ? 4 : 0));
2149 /** Create a ModR/M byte for one register and extension */
2150 static void bemit_modru(const arch_register_t *reg, unsigned ext)
2152 unsigned char modrm = MOD_REG;
2154 modrm |= ENC_RM(reg_gp_map[reg->index]);
2155 modrm |= ENC_REG(ext);
2159 /** Create a ModR/M8 byte for one register */
2160 static void bemit_modrm8(reg_modifier_t high_part, const arch_register_t *reg)
2162 unsigned char modrm = MOD_REG;
2163 assert(reg_gp_map[reg->index] < 4);
2164 modrm |= ENC_RM(reg_gp_map[reg->index] + (high_part == REG_HIGH ? 4 : 0));
2170 * Calculate the size of an signed immediate in bytes.
2172 * @param offset an offset
2174 static unsigned get_signed_imm_size(int offset)
2176 if (-128 <= offset && offset < 128) {
2178 } else if (-32768 <= offset && offset < 32768) {
2186 * Emit an address mode.
2188 * @param reg content of the reg field: either a register index or an opcode extension
2189 * @param node the node
2191 static void bemit_mod_am(unsigned reg, const ir_node *node)
2193 ir_entity *ent = get_ia32_am_sc(node);
2194 int offs = get_ia32_am_offs_int(node);
2195 ir_node *base = get_irn_n(node, n_ia32_base);
2196 int has_base = !is_ia32_NoReg_GP(base);
2197 ir_node *idx = get_irn_n(node, n_ia32_index);
2198 int has_index = !is_ia32_NoReg_GP(idx);
2201 unsigned emitoffs = 0;
2202 bool emitsib = false;
2205 /* set the mod part depending on displacement */
2207 modrm |= MOD_IND_WORD_OFS;
2209 } else if (offs == 0) {
2212 } else if (-128 <= offs && offs < 128) {
2213 modrm |= MOD_IND_BYTE_OFS;
2216 modrm |= MOD_IND_WORD_OFS;
2221 const arch_register_t *base_reg = arch_get_irn_register(base);
2222 base_enc = reg_gp_map[base_reg->index];
2224 /* Use the EBP encoding + MOD_IND if NO base register. There is
2225 * always a 32bit offset present in this case. */
2231 /* Determine if we need a SIB byte. */
2233 const arch_register_t *reg_index = arch_get_irn_register(idx);
2234 int scale = get_ia32_am_scale(node);
2236 /* R/M set to ESP means SIB in 32bit mode. */
2237 modrm |= ENC_RM(0x04);
2238 sib = ENC_SIB(scale, reg_gp_map[reg_index->index], base_enc);
2240 } else if (base_enc == 0x04) {
2241 /* for the above reason we are forced to emit a SIB when base is ESP.
2242 * Only the base is used, index must be ESP too, which means no index.
2244 modrm |= ENC_RM(0x04);
2245 sib = ENC_SIB(0, 0x04, 0x04);
2248 modrm |= ENC_RM(base_enc);
2251 /* We are forced to emit an 8bit offset as EBP base without offset is a
2252 * special case for SIB without base register. */
2253 if (base_enc == 0x05 && emitoffs == 0) {
2254 modrm |= MOD_IND_BYTE_OFS;
2258 modrm |= ENC_REG(reg);
2264 /* emit displacement */
2265 if (emitoffs == 8) {
2266 bemit8((unsigned) offs);
2267 } else if (emitoffs == 32) {
2268 bemit_entity(ent, is_ia32_am_sc_sign(node), offs, false);
2273 * Emit a binop with a immediate operand.
2275 * @param node the node to emit
2276 * @param opcode_eax the opcode for the op eax, imm variant
2277 * @param opcode the opcode for the reg, imm variant
2278 * @param ruval the opcode extension for opcode
2280 static void bemit_binop_with_imm(
2281 const ir_node *node,
2282 unsigned char opcode_ax,
2283 unsigned char opcode, unsigned char ruval)
2285 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2286 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2287 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2290 /* Some instructions (test) have no short form with 32bit value + 8bit
2292 if (attr->symconst != NULL || opcode & SIGNEXT_IMM) {
2295 /* check for sign extension */
2296 size = get_signed_imm_size(attr->offset);
2301 bemit8(opcode | SIGNEXT_IMM);
2302 /* cmp has this special mode */
2303 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2304 bemit_mod_am(ruval, node);
2306 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2307 bemit_modru(reg, ruval);
2309 bemit8((unsigned char)attr->offset);
2313 /* check for eax variant: this variant is shorter for 32bit immediates only */
2314 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2316 bemit_mod_am(ruval, node);
2318 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2319 if (reg->index == REG_GP_EAX) {
2323 bemit_modru(reg, ruval);
2326 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2329 panic("invalid imm size?!?");
2335 static void bemit_binop_2(const ir_node *node, unsigned code)
2337 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2339 if (get_ia32_op_type(node) == ia32_Normal) {
2340 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2341 bemit_modrr(op2, out);
2343 bemit_mod_am(reg_gp_map[out->index], node);
2350 static void bemit_binop(const ir_node *node, const unsigned char opcodes[4])
2352 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2353 if (is_ia32_Immediate(right)) {
2354 bemit_binop_with_imm(node, opcodes[1], opcodes[2], opcodes[3]);
2356 bemit_binop_2(node, opcodes[0]);
2363 static void bemit_unop(const ir_node *node, unsigned char code, unsigned char ext, int input)
2366 if (get_ia32_op_type(node) == ia32_Normal) {
2367 const arch_register_t *in = arch_get_irn_register_in(node, input);
2368 bemit_modru(in, ext);
2370 bemit_mod_am(ext, node);
2374 static void bemit_unop_reg(const ir_node *node, unsigned char code, int input)
2376 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2377 bemit_unop(node, code, reg_gp_map[out->index], input);
2380 static void bemit_unop_mem(const ir_node *node, unsigned char code, unsigned char ext)
2382 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
2385 bemit8(size == 8 ? code : code + 1);
2386 bemit_mod_am(ext, node);
2389 static void bemit_immediate(const ir_node *node, bool relative)
2391 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
2392 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, relative);
2395 static void bemit_copy(const ir_node *copy)
2397 const arch_register_t *in = arch_get_irn_register_in(copy, 0);
2398 const arch_register_t *out = arch_get_irn_register_out(copy, 0);
2402 /* copies of vf nodes aren't real... */
2403 if (arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_vfp])
2406 assert(arch_register_get_class(in) == &ia32_reg_classes[CLASS_ia32_gp]);
2408 bemit_modrr(in, out);
2411 static void bemit_perm(const ir_node *node)
2413 const arch_register_t *in0 = arch_get_irn_register(get_irn_n(node, 0));
2414 const arch_register_t *in1 = arch_get_irn_register(get_irn_n(node, 1));
2415 const arch_register_class_t *cls0 = arch_register_get_class(in0);
2417 assert(cls0 == arch_register_get_class(in1) && "Register class mismatch at Perm");
2419 if (cls0 == &ia32_reg_classes[CLASS_ia32_gp]) {
2420 if (in0->index == REG_GP_EAX) {
2421 bemit8(0x90 + reg_gp_map[in1->index]);
2422 } else if (in1->index == REG_GP_EAX) {
2423 bemit8(0x90 + reg_gp_map[in0->index]);
2426 bemit_modrr(in0, in1);
2428 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_xmm]) {
2429 panic("unimplemented"); // TODO implement
2430 //ia32_emitf(NULL, "\txorpd %R, %R\n", in1, in0);
2431 //ia32_emitf(NULL, "\txorpd %R, %R\n", in0, in1);
2432 //ia32_emitf(node, "\txorpd %R, %R\n", in1, in0);
2433 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_vfp]) {
2435 } else if (cls0 == &ia32_reg_classes[CLASS_ia32_st]) {
2438 panic("unexpected register class in be_Perm (%+F)", node);
2442 static void bemit_xor0(const ir_node *node)
2444 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2446 bemit_modrr(out, out);
2449 static void bemit_mov_const(const ir_node *node)
2451 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2452 bemit8(0xB8 + reg_gp_map[out->index]);
2453 bemit_immediate(node, false);
2457 * Creates a function for a Binop with 3 possible encodings.
2459 #define BINOP(op, op0, op1, op2, op2_ext) \
2460 static void bemit_ ## op(const ir_node *node) { \
2461 static const unsigned char op ## _codes[] = {op0, op1, op2, op2_ext}; \
2462 bemit_binop(node, op ## _codes); \
2465 /* insn def eax,imm imm */
2466 BINOP(add, 0x03, 0x05, 0x81, 0)
2467 BINOP(or, 0x0B, 0x0D, 0x81, 1)
2468 BINOP(adc, 0x13, 0x15, 0x81, 2)
2469 BINOP(sbb, 0x1B, 0x1D, 0x81, 3)
2470 BINOP(and, 0x23, 0x25, 0x81, 4)
2471 BINOP(sub, 0x2B, 0x2D, 0x81, 5)
2472 BINOP(xor, 0x33, 0x35, 0x81, 6)
2473 BINOP(test, 0x85, 0xA9, 0xF7, 0)
2475 #define BINOPMEM(op, ext) \
2476 static void bemit_##op(const ir_node *node) \
2479 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2482 val = get_irn_n(node, n_ia32_unary_op); \
2483 if (is_ia32_Immediate(val)) { \
2484 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(val); \
2485 int offset = attr->offset; \
2486 if (attr->symconst == NULL && get_signed_imm_size(offset) == 1) { \
2488 bemit_mod_am(ext, node); \
2492 bemit_mod_am(ext, node); \
2496 bemit_entity(attr->symconst, attr->sc_sign, offset, false); \
2500 bemit8(ext << 3 | 1); \
2501 bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
2505 static void bemit_##op##8bit(const ir_node *node) \
2507 ir_node *val = get_irn_n(node, n_ia32_unary_op); \
2508 if (is_ia32_Immediate(val)) { \
2510 bemit_mod_am(ext, node); \
2511 bemit8(get_ia32_immediate_attr_const(val)->offset); \
2514 bemit_mod_am(reg_gp_map[arch_get_irn_register_out(val, 0)->index], node); \
2526 * Creates a function for an Unop with code /ext encoding.
2528 #define UNOP(op, code, ext, input) \
2529 static void bemit_ ## op(const ir_node *node) { \
2530 bemit_unop(node, code, ext, input); \
2533 UNOP(not, 0xF7, 2, n_ia32_Not_val)
2534 UNOP(neg, 0xF7, 3, n_ia32_Neg_val)
2535 UNOP(mul, 0xF7, 4, n_ia32_Mul_right)
2536 UNOP(imul1op, 0xF7, 5, n_ia32_IMul1OP_right)
2537 UNOP(div, 0xF7, 6, n_ia32_Div_divisor)
2538 UNOP(idiv, 0xF7, 7, n_ia32_IDiv_divisor)
2540 /* TODO: am support for IJmp */
2541 UNOP(ijmp, 0xFF, 4, n_ia32_IJmp_target)
2543 #define SHIFT(op, ext) \
2544 static void bemit_##op(const ir_node *node) \
2546 const arch_register_t *out = arch_get_irn_register_out(node, 0); \
2547 ir_node *count = get_irn_n(node, 1); \
2548 if (is_ia32_Immediate(count)) { \
2549 int offset = get_ia32_immediate_attr_const(count)->offset; \
2550 if (offset == 1) { \
2552 bemit_modru(out, ext); \
2555 bemit_modru(out, ext); \
2560 bemit_modru(out, ext); \
2564 static void bemit_##op##mem(const ir_node *node) \
2567 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node)); \
2570 count = get_irn_n(node, 1); \
2571 if (is_ia32_Immediate(count)) { \
2572 int offset = get_ia32_immediate_attr_const(count)->offset; \
2573 if (offset == 1) { \
2574 bemit8(size == 8 ? 0xD0 : 0xD1); \
2575 bemit_mod_am(ext, node); \
2577 bemit8(size == 8 ? 0xC0 : 0xC1); \
2578 bemit_mod_am(ext, node); \
2582 bemit8(size == 8 ? 0xD2 : 0xD3); \
2583 bemit_mod_am(ext, node); \
2593 static void bemit_shld(const ir_node *node)
2595 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShlD_val_low);
2596 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShlD_res);
2597 ir_node *count = get_irn_n(node, n_ia32_ShlD_count);
2599 if (is_ia32_Immediate(count)) {
2601 bemit_modrr(out, in);
2602 bemit8(get_ia32_immediate_attr_const(count)->offset);
2605 bemit_modrr(out, in);
2609 static void bemit_shrd(const ir_node *node)
2611 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_ShrD_val_low);
2612 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_ShrD_res);
2613 ir_node *count = get_irn_n(node, n_ia32_ShrD_count);
2615 if (is_ia32_Immediate(count)) {
2617 bemit_modrr(out, in);
2618 bemit8(get_ia32_immediate_attr_const(count)->offset);
2621 bemit_modrr(out, in);
2626 * binary emitter for setcc.
2628 static void bemit_setcc(const ir_node *node)
2630 const arch_register_t *dreg = arch_get_irn_register_out(node, pn_ia32_Setcc_res);
2632 ia32_condition_code_t cc = get_ia32_condcode(node);
2633 cc = determine_final_cc(node, n_ia32_Setcc_eflags, cc);
2634 if (cc & ia32_cc_float_parity_cases) {
2635 if (cc & ia32_cc_negated) {
2638 bemit8(0x90 | pnc2cc(cc));
2639 bemit_modrm8(REG_LOW, dreg);
2644 bemit_modrm8(REG_HIGH, dreg);
2646 /* orb %>dreg, %<dreg */
2648 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2652 bemit8(0x90 | pnc2cc(cc));
2653 bemit_modrm8(REG_LOW, dreg);
2658 bemit_modrm8(REG_HIGH, dreg);
2660 /* andb %>dreg, %<dreg */
2662 bemit_modrr8(REG_LOW, dreg, REG_HIGH, dreg);
2667 bemit8(0x90 | pnc2cc(cc));
2668 bemit_modrm8(REG_LOW, dreg);
2672 static void bemit_cmovcc(const ir_node *node)
2674 const ia32_attr_t *attr = get_ia32_attr_const(node);
2675 int ins_permuted = attr->data.ins_permuted;
2676 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_res);
2677 ia32_condition_code_t cc = get_ia32_condcode(node);
2678 const arch_register_t *in_true;
2679 const arch_register_t *in_false;
2681 cc = determine_final_cc(node, n_ia32_CMovcc_eflags, cc);
2683 in_true = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_true));
2684 in_false = arch_get_irn_register(get_irn_n(node, n_ia32_CMovcc_val_false));
2686 /* should be same constraint fullfilled? */
2687 if (out == in_false) {
2688 /* yes -> nothing to do */
2689 } else if (out == in_true) {
2690 assert(get_ia32_op_type(node) == ia32_Normal);
2691 ins_permuted = !ins_permuted;
2695 bemit8(0x8B); // mov %in_false, %out
2696 bemit_modrr(in_false, out);
2700 cc = ia32_negate_condition_code(cc);
2702 if (cc & ia32_cc_float_parity_cases)
2703 panic("cmov can't handle parity float cases");
2706 bemit8(0x40 | pnc2cc(cc));
2707 if (get_ia32_op_type(node) == ia32_Normal) {
2708 bemit_modrr(in_true, out);
2710 bemit_mod_am(reg_gp_map[out->index], node);
2714 static void bemit_cmp(const ir_node *node)
2716 unsigned ls_size = get_mode_size_bits(get_ia32_ls_mode(node));
2722 right = get_irn_n(node, n_ia32_binary_right);
2723 if (is_ia32_Immediate(right)) {
2724 /* Use in-reg, because some instructions (cmp, test) have no out-reg. */
2725 const ir_node *op = get_irn_n(node, n_ia32_binary_right);
2726 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(op);
2729 if (attr->symconst != NULL) {
2732 /* check for sign extension */
2733 size = get_signed_imm_size(attr->offset);
2738 bemit8(0x81 | SIGNEXT_IMM);
2739 /* cmp has this special mode */
2740 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2741 bemit_mod_am(7, node);
2743 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2744 bemit_modru(reg, 7);
2746 bemit8((unsigned char)attr->offset);
2750 /* check for eax variant: this variant is shorter for 32bit immediates only */
2751 if (get_ia32_op_type(node) == ia32_AddrModeS) {
2753 bemit_mod_am(7, node);
2755 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_binary_left);
2756 if (reg->index == REG_GP_EAX) {
2760 bemit_modru(reg, 7);
2763 if (ls_size == 16) {
2764 bemit16(attr->offset);
2766 bemit_entity(attr->symconst, attr->sc_sign, attr->offset, false);
2770 panic("invalid imm size?!?");
2772 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_binary_left);
2774 if (get_ia32_op_type(node) == ia32_Normal) {
2775 const arch_register_t *op2 = arch_get_irn_register_in(node, n_ia32_binary_right);
2776 bemit_modrr(op2, out);
2778 bemit_mod_am(reg_gp_map[out->index], node);
2783 static void bemit_cmp8bit(const ir_node *node)
2785 ir_node *right = get_irn_n(node, n_ia32_binary_right);
2786 if (is_ia32_Immediate(right)) {
2787 if (get_ia32_op_type(node) == ia32_Normal) {
2788 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2789 if (out->index == REG_GP_EAX) {
2793 bemit_modru(out, 7);
2797 bemit_mod_am(7, node);
2799 bemit8(get_ia32_immediate_attr_const(right)->offset);
2801 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Cmp_left);
2803 if (get_ia32_op_type(node) == ia32_Normal) {
2804 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Cmp_right);
2805 bemit_modrr(out, in);
2807 bemit_mod_am(reg_gp_map[out->index], node);
2812 static void bemit_test8bit(const ir_node *node)
2814 ir_node *right = get_irn_n(node, n_ia32_Test8Bit_right);
2815 if (is_ia32_Immediate(right)) {
2816 if (get_ia32_op_type(node) == ia32_Normal) {
2817 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2818 if (out->index == REG_GP_EAX) {
2822 bemit_modru(out, 0);
2826 bemit_mod_am(0, node);
2828 bemit8(get_ia32_immediate_attr_const(right)->offset);
2830 const arch_register_t *out = arch_get_irn_register_in(node, n_ia32_Test8Bit_left);
2832 if (get_ia32_op_type(node) == ia32_Normal) {
2833 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Test8Bit_right);
2834 bemit_modrr(out, in);
2836 bemit_mod_am(reg_gp_map[out->index], node);
2841 static void bemit_imul(const ir_node *node)
2843 ir_node *right = get_irn_n(node, n_ia32_IMul_right);
2844 /* Do we need the immediate form? */
2845 if (is_ia32_Immediate(right)) {
2846 int imm = get_ia32_immediate_attr_const(right)->offset;
2847 if (get_signed_imm_size(imm) == 1) {
2848 bemit_unop_reg(node, 0x6B, n_ia32_IMul_left);
2851 bemit_unop_reg(node, 0x69, n_ia32_IMul_left);
2856 bemit_unop_reg(node, 0xAF, n_ia32_IMul_right);
2860 static void bemit_dec(const ir_node *node)
2862 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Dec_res);
2863 bemit8(0x48 + reg_gp_map[out->index]);
2866 static void bemit_inc(const ir_node *node)
2868 const arch_register_t *out = arch_get_irn_register_out(node, pn_ia32_Inc_res);
2869 bemit8(0x40 + reg_gp_map[out->index]);
2872 #define UNOPMEM(op, code, ext) \
2873 static void bemit_##op(const ir_node *node) \
2875 bemit_unop_mem(node, code, ext); \
2878 UNOPMEM(notmem, 0xF6, 2)
2879 UNOPMEM(negmem, 0xF6, 3)
2880 UNOPMEM(incmem, 0xFE, 0)
2881 UNOPMEM(decmem, 0xFE, 1)
2883 static void bemit_ldtls(const ir_node *node)
2885 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2887 bemit8(0x65); // gs:
2888 if (out->index == REG_GP_EAX) {
2889 bemit8(0xA1); // movl 0, %eax
2891 bemit8(0x8B); // movl 0, %reg
2892 bemit8(MOD_IND | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x05));
2900 static void bemit_lea(const ir_node *node)
2902 const arch_register_t *out = arch_get_irn_register_out(node, 0);
2904 bemit_mod_am(reg_gp_map[out->index], node);
2907 /* helper function for bemit_minus64bit */
2908 static void bemit_helper_mov(const arch_register_t *src, const arch_register_t *dst)
2910 bemit8(0x8B); // movl %src, %dst
2911 bemit_modrr(src, dst);
2914 /* helper function for bemit_minus64bit */
2915 static void bemit_helper_neg(const arch_register_t *reg)
2917 bemit8(0xF7); // negl %reg
2918 bemit_modru(reg, 3);
2921 /* helper function for bemit_minus64bit */
2922 static void bemit_helper_sbb0(const arch_register_t *reg)
2924 bemit8(0x83); // sbbl $0, %reg
2925 bemit_modru(reg, 3);
2929 /* helper function for bemit_minus64bit */
2930 static void bemit_helper_sbb(const arch_register_t *src, const arch_register_t *dst)
2932 bemit8(0x1B); // sbbl %src, %dst
2933 bemit_modrr(src, dst);
2936 /* helper function for bemit_minus64bit */
2937 static void bemit_helper_xchg(const arch_register_t *src, const arch_register_t *dst)
2939 if (src->index == REG_GP_EAX) {
2940 bemit8(0x90 + reg_gp_map[dst->index]); // xchgl %eax, %dst
2941 } else if (dst->index == REG_GP_EAX) {
2942 bemit8(0x90 + reg_gp_map[src->index]); // xchgl %src, %eax
2944 bemit8(0x87); // xchgl %src, %dst
2945 bemit_modrr(src, dst);
2949 /* helper function for bemit_minus64bit */
2950 static void bemit_helper_zero(const arch_register_t *reg)
2952 bemit8(0x33); // xorl %reg, %reg
2953 bemit_modrr(reg, reg);
2956 static void bemit_minus64bit(const ir_node *node)
2958 const arch_register_t *in_lo = arch_get_irn_register_in(node, 0);
2959 const arch_register_t *in_hi = arch_get_irn_register_in(node, 1);
2960 const arch_register_t *out_lo = arch_get_irn_register_out(node, 0);
2961 const arch_register_t *out_hi = arch_get_irn_register_out(node, 1);
2963 if (out_lo == in_lo) {
2964 if (out_hi != in_hi) {
2965 /* a -> a, b -> d */
2968 /* a -> a, b -> b */
2971 } else if (out_lo == in_hi) {
2972 if (out_hi == in_lo) {
2973 /* a -> b, b -> a */
2974 bemit_helper_xchg(in_lo, in_hi);
2977 /* a -> b, b -> d */
2978 bemit_helper_mov(in_hi, out_hi);
2979 bemit_helper_mov(in_lo, out_lo);
2983 if (out_hi == in_lo) {
2984 /* a -> c, b -> a */
2985 bemit_helper_mov(in_lo, out_lo);
2987 } else if (out_hi == in_hi) {
2988 /* a -> c, b -> b */
2989 bemit_helper_mov(in_lo, out_lo);
2992 /* a -> c, b -> d */
2993 bemit_helper_mov(in_lo, out_lo);
2999 bemit_helper_neg( out_hi);
3000 bemit_helper_neg( out_lo);
3001 bemit_helper_sbb0(out_hi);
3005 bemit_helper_zero(out_hi);
3006 bemit_helper_neg( out_lo);
3007 bemit_helper_sbb( in_hi, out_hi);
3011 * Emit a single opcode.
3013 #define EMIT_SINGLEOP(op, code) \
3014 static void bemit_ ## op(const ir_node *node) { \
3019 //EMIT_SINGLEOP(daa, 0x27)
3020 //EMIT_SINGLEOP(das, 0x2F)
3021 //EMIT_SINGLEOP(aaa, 0x37)
3022 //EMIT_SINGLEOP(aas, 0x3F)
3023 //EMIT_SINGLEOP(nop, 0x90)
3024 EMIT_SINGLEOP(cwtl, 0x98)
3025 EMIT_SINGLEOP(cltd, 0x99)
3026 //EMIT_SINGLEOP(fwait, 0x9B)
3027 EMIT_SINGLEOP(sahf, 0x9E)
3028 //EMIT_SINGLEOP(popf, 0x9D)
3029 EMIT_SINGLEOP(leave, 0xC9)
3030 EMIT_SINGLEOP(int3, 0xCC)
3031 //EMIT_SINGLEOP(iret, 0xCF)
3032 //EMIT_SINGLEOP(xlat, 0xD7)
3033 //EMIT_SINGLEOP(lock, 0xF0)
3034 EMIT_SINGLEOP(rep, 0xF3)
3035 //EMIT_SINGLEOP(halt, 0xF4)
3036 EMIT_SINGLEOP(cmc, 0xF5)
3037 EMIT_SINGLEOP(stc, 0xF9)
3038 //EMIT_SINGLEOP(cli, 0xFA)
3039 //EMIT_SINGLEOP(sti, 0xFB)
3040 //EMIT_SINGLEOP(std, 0xFD)
3043 * Emits a MOV out, [MEM].
3045 static void bemit_load(const ir_node *node)
3047 const arch_register_t *out = arch_get_irn_register_out(node, 0);
3049 if (out->index == REG_GP_EAX) {
3050 ir_node *base = get_irn_n(node, n_ia32_base);
3051 int has_base = !is_ia32_NoReg_GP(base);
3052 ir_node *idx = get_irn_n(node, n_ia32_index);
3053 int has_index = !is_ia32_NoReg_GP(idx);
3054 if (!has_base && !has_index) {
3055 ir_entity *ent = get_ia32_am_sc(node);
3056 int offs = get_ia32_am_offs_int(node);
3057 /* load from constant address to EAX can be encoded
3060 bemit_entity(ent, 0, offs, false);
3065 bemit_mod_am(reg_gp_map[out->index], node);
3069 * Emits a MOV [mem], in.
3071 static void bemit_store(const ir_node *node)
3073 const ir_node *value = get_irn_n(node, n_ia32_Store_val);
3074 unsigned size = get_mode_size_bits(get_ia32_ls_mode(node));
3076 if (is_ia32_Immediate(value)) {
3079 bemit_mod_am(0, node);
3080 bemit8(get_ia32_immediate_attr_const(value)->offset);
3081 } else if (size == 16) {
3084 bemit_mod_am(0, node);
3085 bemit16(get_ia32_immediate_attr_const(value)->offset);
3088 bemit_mod_am(0, node);
3089 bemit_immediate(value, false);
3092 const arch_register_t *in = arch_get_irn_register_in(node, n_ia32_Store_val);
3094 if (in->index == REG_GP_EAX) {
3095 ir_node *base = get_irn_n(node, n_ia32_base);
3096 int has_base = !is_ia32_NoReg_GP(base);
3097 ir_node *idx = get_irn_n(node, n_ia32_index);
3098 int has_index = !is_ia32_NoReg_GP(idx);
3099 if (!has_base && !has_index) {
3100 ir_entity *ent = get_ia32_am_sc(node);
3101 int offs = get_ia32_am_offs_int(node);
3102 /* store to constant address from EAX can be encoded as
3103 * 0xA2/0xA3 [offset]*/
3111 bemit_entity(ent, 0, offs, false);
3123 bemit_mod_am(reg_gp_map[in->index], node);
3127 static void bemit_conv_i2i(const ir_node *node)
3129 ir_mode *smaller_mode = get_ia32_ls_mode(node);
3138 if (mode_is_signed(smaller_mode)) opcode |= 0x08;
3139 if (get_mode_size_bits(smaller_mode) == 16) opcode |= 0x01;
3140 bemit_unop_reg(node, opcode, n_ia32_Conv_I2I_val);
3146 static void bemit_push(const ir_node *node)
3148 const ir_node *value = get_irn_n(node, n_ia32_Push_val);
3150 if (is_ia32_Immediate(value)) {
3151 const ia32_immediate_attr_t *attr
3152 = get_ia32_immediate_attr_const(value);
3153 unsigned size = get_signed_imm_size(attr->offset);
3159 bemit8((unsigned char)attr->offset);
3164 bemit_immediate(value, false);
3167 } else if (is_ia32_NoReg_GP(value)) {
3169 bemit_mod_am(6, node);
3171 const arch_register_t *reg = arch_get_irn_register_in(node, n_ia32_Push_val);
3172 bemit8(0x50 + reg_gp_map[reg->index]);
3179 static void bemit_pop(const ir_node *node)
3181 const arch_register_t *reg = arch_get_irn_register_out(node, pn_ia32_Pop_res);
3182 bemit8(0x58 + reg_gp_map[reg->index]);
3185 static void bemit_popmem(const ir_node *node)
3188 bemit_mod_am(0, node);
3191 static void bemit_call(const ir_node *node)
3193 ir_node *proc = get_irn_n(node, n_ia32_Call_addr);
3195 if (is_ia32_Immediate(proc)) {
3197 bemit_immediate(proc, true);
3199 bemit_unop(node, 0xFF, 2, n_ia32_Call_addr);
3203 static void bemit_jmp(const ir_node *dest_block)
3206 bemit_jmp_destination(dest_block);
3209 static void bemit_jump(const ir_node *node)
3211 if (can_be_fallthrough(node))
3214 bemit_jmp(get_cfop_target_block(node));
3217 static void bemit_jcc(int pnc, const ir_node *dest_block)
3219 unsigned char cc = pnc2cc(pnc);
3222 bemit_jmp_destination(dest_block);
3225 static void bemit_jp(bool odd, const ir_node *dest_block)
3229 bemit_jmp_destination(dest_block);
3232 static void bemit_ia32_jcc(const ir_node *node)
3234 ia32_condition_code_t cc = get_ia32_condcode(node);
3235 const ir_node *proj_true;
3236 const ir_node *proj_false;
3237 const ir_node *dest_true;
3238 const ir_node *dest_false;
3240 cc = determine_final_cc(node, 0, cc);
3242 /* get both Projs */
3243 proj_true = get_proj(node, pn_ia32_Jcc_true);
3244 assert(proj_true && "Jcc without true Proj");
3246 proj_false = get_proj(node, pn_ia32_Jcc_false);
3247 assert(proj_false && "Jcc without false Proj");
3249 if (can_be_fallthrough(proj_true)) {
3250 /* exchange both proj's so the second one can be omitted */
3251 const ir_node *t = proj_true;
3253 proj_true = proj_false;
3255 cc = ia32_negate_condition_code(cc);
3258 dest_true = get_cfop_target_block(proj_true);
3259 dest_false = get_cfop_target_block(proj_false);
3261 if (cc & ia32_cc_float_parity_cases) {
3262 /* Some floating point comparisons require a test of the parity flag,
3263 * which indicates that the result is unordered */
3264 if (cc & ia32_cc_negated) {
3265 bemit_jp(false, dest_true);
3267 /* we need a local label if the false proj is a fallthrough
3268 * as the falseblock might have no label emitted then */
3269 if (can_be_fallthrough(proj_false)) {
3271 bemit8(0x06); // jp + 6
3273 bemit_jp(false, dest_false);
3277 bemit_jcc(cc, dest_true);
3279 /* the second Proj might be a fallthrough */
3280 if (can_be_fallthrough(proj_false)) {
3281 /* it's a fallthrough */
3283 bemit_jmp(dest_false);
3287 static void bemit_switchjmp(const ir_node *node)
3289 ir_entity *jump_table = get_ia32_am_sc(node);
3290 const ir_switch_table *table = get_ia32_switch_table(node);
3292 bemit8(0xFF); // jmp *tbl.label(,%in,4)
3293 bemit_mod_am(0x05, node);
3295 be_emit_jump_table(node, table, jump_table, get_cfop_target_block);
3301 static void bemit_return(const ir_node *node)
3303 unsigned pop = be_Return_get_pop(node);
3304 if (pop > 0 || be_Return_get_emit_pop(node)) {
3306 assert(pop <= 0xffff);
3313 static void bemit_subsp(const ir_node *node)
3315 const arch_register_t *out;
3318 /* mov %esp, %out */
3320 out = arch_get_irn_register_out(node, 1);
3321 bemit8(MOD_REG | ENC_REG(reg_gp_map[out->index]) | ENC_RM(0x04));
3324 static void bemit_incsp(const ir_node *node)
3327 const arch_register_t *reg;
3331 offs = be_get_IncSP_offset(node);
3342 size = get_signed_imm_size(offs);
3343 bemit8(size == 1 ? 0x83 : 0x81);
3345 reg = arch_get_irn_register_out(node, 0);
3346 bemit_modru(reg, ext);
3355 static void bemit_copybi(const ir_node *node)
3357 unsigned size = get_ia32_copyb_size(node);
3359 bemit8(0xA4); // movsb
3362 bemit8(0xA5); // movsw
3366 bemit8(0xA5); // movsl
3370 static void bemit_fbinop(const ir_node *node, unsigned code, unsigned code_to)
3372 if (get_ia32_op_type(node) == ia32_Normal) {
3373 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3374 const arch_register_t *in1 = x87_attr->x87[0];
3375 const arch_register_t *in = x87_attr->x87[1];
3376 const arch_register_t *out = x87_attr->x87[2];
3380 } else if (out == in) {
3384 if (out->index == 0) {
3386 bemit8(MOD_REG | ENC_REG(code) | ENC_RM(in->index));
3389 bemit8(MOD_REG | ENC_REG(code_to) | ENC_RM(out->index));
3392 if (get_mode_size_bits(get_ia32_ls_mode(node)) == 32) {
3397 bemit_mod_am(code, node);
3401 static void bemit_fbinopp(const ir_node *node, unsigned const code)
3403 const ia32_x87_attr_t *x87_attr = get_ia32_x87_attr_const(node);
3404 const arch_register_t *out = x87_attr->x87[2];
3406 bemit8(code + out->index);
3409 static void bemit_fabs(const ir_node *node)
3417 static void bemit_fadd(const ir_node *node)
3419 bemit_fbinop(node, 0, 0);
3422 static void bemit_faddp(const ir_node *node)
3424 bemit_fbinopp(node, 0xC0);
3427 static void bemit_fchs(const ir_node *node)
3435 static void bemit_fdiv(const ir_node *node)
3437 bemit_fbinop(node, 6, 7);
3440 static void bemit_fdivp(const ir_node *node)
3442 bemit_fbinopp(node, 0xF8);
3445 static void bemit_fdivr(const ir_node *node)
3447 bemit_fbinop(node, 7, 6);
3450 static void bemit_fdivrp(const ir_node *node)
3452 bemit_fbinopp(node, 0xF0);
3455 static void bemit_fild(const ir_node *node)
3457 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3459 bemit8(0xDF); // filds
3460 bemit_mod_am(0, node);
3464 bemit8(0xDB); // fildl
3465 bemit_mod_am(0, node);
3469 bemit8(0xDF); // fildll
3470 bemit_mod_am(5, node);
3474 panic("invalid mode size");
3478 static void bemit_fist(const ir_node *node)
3480 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3482 bemit8(0xDF); // fists
3486 bemit8(0xDB); // fistl
3490 panic("invalid mode size");
3492 bemit_mod_am(2, node);
3495 static void bemit_fistp(const ir_node *node)
3497 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3499 bemit8(0xDF); // fistps
3500 bemit_mod_am(3, node);
3504 bemit8(0xDB); // fistpl
3505 bemit_mod_am(3, node);
3509 bemit8(0xDF); // fistpll
3510 bemit_mod_am(7, node);
3514 panic("invalid mode size");
3518 static void bemit_fld(const ir_node *node)
3520 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3522 bemit8(0xD9); // flds
3523 bemit_mod_am(0, node);
3527 bemit8(0xDD); // fldl
3528 bemit_mod_am(0, node);
3533 bemit8(0xDB); // fldt
3534 bemit_mod_am(5, node);
3538 panic("invalid mode size");
3542 static void bemit_fld1(const ir_node *node)
3546 bemit8(0xE8); // fld1
3549 static void bemit_fldcw(const ir_node *node)
3551 bemit8(0xD9); // fldcw
3552 bemit_mod_am(5, node);
3555 static void bemit_fldz(const ir_node *node)
3559 bemit8(0xEE); // fldz
3562 static void bemit_fmul(const ir_node *node)
3564 bemit_fbinop(node, 1, 1);
3567 static void bemit_fmulp(const ir_node *node)
3569 bemit_fbinopp(node, 0xC8);
3572 static void bemit_fpop(const ir_node *node)
3574 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3576 bemit8(0xD8 + attr->x87[0]->index);
3579 static void bemit_fpush(const ir_node *node)
3581 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3583 bemit8(0xC0 + attr->x87[0]->index);
3586 static void bemit_fpushcopy(const ir_node *node)
3588 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3590 bemit8(0xC0 + attr->x87[0]->index);
3593 static void bemit_fst(const ir_node *node)
3595 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3597 bemit8(0xD9); // fsts
3601 bemit8(0xDD); // fstl
3605 panic("invalid mode size");
3607 bemit_mod_am(2, node);
3610 static void bemit_fstp(const ir_node *node)
3612 switch (get_mode_size_bits(get_ia32_ls_mode(node))) {
3614 bemit8(0xD9); // fstps
3615 bemit_mod_am(3, node);
3619 bemit8(0xDD); // fstpl
3620 bemit_mod_am(3, node);
3625 bemit8(0xDB); // fstpt
3626 bemit_mod_am(7, node);
3630 panic("invalid mode size");
3634 static void bemit_fsub(const ir_node *node)
3636 bemit_fbinop(node, 4, 5);
3639 static void bemit_fsubp(const ir_node *node)
3641 bemit_fbinopp(node, 0xE8);
3644 static void bemit_fsubr(const ir_node *node)
3646 bemit_fbinop(node, 5, 4);
3649 static void bemit_fsubrp(const ir_node *node)
3651 bemit_fbinopp(node, 0xE0);
3654 static void bemit_fnstcw(const ir_node *node)
3656 bemit8(0xD9); // fnstcw
3657 bemit_mod_am(7, node);
3660 static void bemit_fnstsw(void)
3662 bemit8(0xDF); // fnstsw %ax
3666 static void bemit_ftstfnstsw(const ir_node *node)
3670 bemit8(0xD9); // ftst
3675 static void bemit_fucomi(const ir_node *node)
3677 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3678 bemit8(0xDB); // fucomi
3679 bemit8(0xE8 + attr->x87[1]->index);
3682 static void bemit_fucomip(const ir_node *node)
3684 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3685 bemit8(0xDF); // fucomip
3686 bemit8(0xE8 + attr->x87[1]->index);
3689 static void bemit_fucomfnstsw(const ir_node *node)
3691 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3692 bemit8(0xDD); // fucom
3693 bemit8(0xE0 + attr->x87[1]->index);
3697 static void bemit_fucompfnstsw(const ir_node *node)
3699 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3700 bemit8(0xDD); // fucomp
3701 bemit8(0xE8 + attr->x87[1]->index);
3705 static void bemit_fucomppfnstsw(const ir_node *node)
3709 bemit8(0xDA); // fucompp
3714 static void bemit_fxch(const ir_node *node)
3716 const ia32_x87_attr_t *attr = get_ia32_x87_attr_const(node);
3718 bemit8(0xC8 + attr->x87[0]->index);
3722 * The type of a emitter function.
3724 typedef void (*emit_func) (const ir_node *);
3727 * Set a node emitter. Make it a bit more type safe.
3729 static void register_emitter(ir_op *op, emit_func func)
3731 op->ops.generic = (op_func) func;
3734 static void ia32_register_binary_emitters(void)
3736 /* first clear the generic function pointer for all ops */
3737 ir_clear_opcodes_generic_func();
3739 /* benode emitter */
3740 register_emitter(op_be_Copy, bemit_copy);
3741 register_emitter(op_be_CopyKeep, bemit_copy);
3742 register_emitter(op_be_IncSP, bemit_incsp);
3743 register_emitter(op_be_Perm, bemit_perm);
3744 register_emitter(op_be_Return, bemit_return);
3745 register_emitter(op_ia32_Adc, bemit_adc);
3746 register_emitter(op_ia32_Add, bemit_add);
3747 register_emitter(op_ia32_AddMem, bemit_addmem);
3748 register_emitter(op_ia32_AddMem8Bit, bemit_addmem8bit);
3749 register_emitter(op_ia32_And, bemit_and);
3750 register_emitter(op_ia32_AndMem, bemit_andmem);
3751 register_emitter(op_ia32_AndMem8Bit, bemit_andmem8bit);
3752 register_emitter(op_ia32_Breakpoint, bemit_int3);
3753 register_emitter(op_ia32_CMovcc, bemit_cmovcc);
3754 register_emitter(op_ia32_Call, bemit_call);
3755 register_emitter(op_ia32_Cltd, bemit_cltd);
3756 register_emitter(op_ia32_Cmc, bemit_cmc);
3757 register_emitter(op_ia32_Cmp, bemit_cmp);
3758 register_emitter(op_ia32_Cmp8Bit, bemit_cmp8bit);
3759 register_emitter(op_ia32_Const, bemit_mov_const);
3760 register_emitter(op_ia32_Conv_I2I, bemit_conv_i2i);
3761 register_emitter(op_ia32_Conv_I2I8Bit, bemit_conv_i2i);
3762 register_emitter(op_ia32_CopyB_i, bemit_copybi);
3763 register_emitter(op_ia32_Cwtl, bemit_cwtl);
3764 register_emitter(op_ia32_Dec, bemit_dec);
3765 register_emitter(op_ia32_DecMem, bemit_decmem);
3766 register_emitter(op_ia32_Div, bemit_div);
3767 register_emitter(op_ia32_FldCW, bemit_fldcw);
3768 register_emitter(op_ia32_FnstCW, bemit_fnstcw);
3769 register_emitter(op_ia32_FtstFnstsw, bemit_ftstfnstsw);
3770 register_emitter(op_ia32_FucomFnstsw, bemit_fucomfnstsw);
3771 register_emitter(op_ia32_Fucomi, bemit_fucomi);
3772 register_emitter(op_ia32_FucompFnstsw, bemit_fucompfnstsw);
3773 register_emitter(op_ia32_Fucompi, bemit_fucomip);
3774 register_emitter(op_ia32_FucomppFnstsw, bemit_fucomppfnstsw);
3775 register_emitter(op_ia32_IDiv, bemit_idiv);
3776 register_emitter(op_ia32_IJmp, bemit_ijmp);
3777 register_emitter(op_ia32_IMul, bemit_imul);
3778 register_emitter(op_ia32_IMul1OP, bemit_imul1op);
3779 register_emitter(op_ia32_Inc, bemit_inc);
3780 register_emitter(op_ia32_IncMem, bemit_incmem);
3781 register_emitter(op_ia32_Jcc, bemit_ia32_jcc);
3782 register_emitter(op_ia32_Jmp, bemit_jump);
3783 register_emitter(op_ia32_LdTls, bemit_ldtls);
3784 register_emitter(op_ia32_Lea, bemit_lea);
3785 register_emitter(op_ia32_Leave, bemit_leave);
3786 register_emitter(op_ia32_Load, bemit_load);
3787 register_emitter(op_ia32_Minus64Bit, bemit_minus64bit);
3788 register_emitter(op_ia32_Mul, bemit_mul);
3789 register_emitter(op_ia32_Neg, bemit_neg);
3790 register_emitter(op_ia32_NegMem, bemit_negmem);
3791 register_emitter(op_ia32_Not, bemit_not);
3792 register_emitter(op_ia32_NotMem, bemit_notmem);
3793 register_emitter(op_ia32_Or, bemit_or);
3794 register_emitter(op_ia32_OrMem, bemit_ormem);
3795 register_emitter(op_ia32_OrMem8Bit, bemit_ormem8bit);
3796 register_emitter(op_ia32_Pop, bemit_pop);
3797 register_emitter(op_ia32_PopEbp, bemit_pop);
3798 register_emitter(op_ia32_PopMem, bemit_popmem);
3799 register_emitter(op_ia32_Push, bemit_push);
3800 register_emitter(op_ia32_RepPrefix, bemit_rep);
3801 register_emitter(op_ia32_Rol, bemit_rol);
3802 register_emitter(op_ia32_RolMem, bemit_rolmem);
3803 register_emitter(op_ia32_Ror, bemit_ror);
3804 register_emitter(op_ia32_RorMem, bemit_rormem);
3805 register_emitter(op_ia32_Sahf, bemit_sahf);
3806 register_emitter(op_ia32_Sar, bemit_sar);
3807 register_emitter(op_ia32_SarMem, bemit_sarmem);
3808 register_emitter(op_ia32_Sbb, bemit_sbb);
3809 register_emitter(op_ia32_Setcc, bemit_setcc);
3810 register_emitter(op_ia32_Shl, bemit_shl);
3811 register_emitter(op_ia32_ShlD, bemit_shld);
3812 register_emitter(op_ia32_ShlMem, bemit_shlmem);
3813 register_emitter(op_ia32_Shr, bemit_shr);
3814 register_emitter(op_ia32_ShrD, bemit_shrd);
3815 register_emitter(op_ia32_ShrMem, bemit_shrmem);
3816 register_emitter(op_ia32_Stc, bemit_stc);
3817 register_emitter(op_ia32_Store, bemit_store);
3818 register_emitter(op_ia32_Store8Bit, bemit_store);
3819 register_emitter(op_ia32_Sub, bemit_sub);
3820 register_emitter(op_ia32_SubMem, bemit_submem);
3821 register_emitter(op_ia32_SubMem8Bit, bemit_submem8bit);
3822 register_emitter(op_ia32_SubSP, bemit_subsp);
3823 register_emitter(op_ia32_SwitchJmp, bemit_switchjmp);
3824 register_emitter(op_ia32_Test, bemit_test);
3825 register_emitter(op_ia32_Test8Bit, bemit_test8bit);
3826 register_emitter(op_ia32_Xor, bemit_xor);
3827 register_emitter(op_ia32_Xor0, bemit_xor0);
3828 register_emitter(op_ia32_XorMem, bemit_xormem);
3829 register_emitter(op_ia32_XorMem8Bit, bemit_xormem8bit);
3830 register_emitter(op_ia32_fabs, bemit_fabs);
3831 register_emitter(op_ia32_fadd, bemit_fadd);
3832 register_emitter(op_ia32_faddp, bemit_faddp);
3833 register_emitter(op_ia32_fchs, bemit_fchs);
3834 register_emitter(op_ia32_fdiv, bemit_fdiv);
3835 register_emitter(op_ia32_fdivp, bemit_fdivp);
3836 register_emitter(op_ia32_fdivr, bemit_fdivr);
3837 register_emitter(op_ia32_fdivrp, bemit_fdivrp);
3838 register_emitter(op_ia32_fild, bemit_fild);
3839 register_emitter(op_ia32_fist, bemit_fist);
3840 register_emitter(op_ia32_fistp, bemit_fistp);
3841 register_emitter(op_ia32_fld, bemit_fld);
3842 register_emitter(op_ia32_fld1, bemit_fld1);
3843 register_emitter(op_ia32_fldz, bemit_fldz);
3844 register_emitter(op_ia32_fmul, bemit_fmul);
3845 register_emitter(op_ia32_fmulp, bemit_fmulp);
3846 register_emitter(op_ia32_fpop, bemit_fpop);
3847 register_emitter(op_ia32_fpush, bemit_fpush);
3848 register_emitter(op_ia32_fpushCopy, bemit_fpushcopy);
3849 register_emitter(op_ia32_fst, bemit_fst);
3850 register_emitter(op_ia32_fstp, bemit_fstp);
3851 register_emitter(op_ia32_fsub, bemit_fsub);
3852 register_emitter(op_ia32_fsubp, bemit_fsubp);
3853 register_emitter(op_ia32_fsubr, bemit_fsubr);
3854 register_emitter(op_ia32_fsubrp, bemit_fsubrp);
3855 register_emitter(op_ia32_fxch, bemit_fxch);
3857 /* ignore the following nodes */
3858 register_emitter(op_ia32_ProduceVal, emit_Nothing);
3859 register_emitter(op_be_Keep, emit_Nothing);
3860 register_emitter(op_be_Start, emit_Nothing);
3861 register_emitter(op_Phi, emit_Nothing);
3862 register_emitter(op_Start, emit_Nothing);
3865 static void gen_binary_block(ir_node *block)
3869 ia32_emit_block_header(block);
3871 /* emit the contents of the block */
3872 sched_foreach(block, node) {
3873 ia32_emit_node(node);
3877 void ia32_gen_binary_routine(ir_graph *irg)
3879 ir_entity *entity = get_irg_entity(irg);
3880 const arch_env_t *arch_env = be_get_irg_arch_env(irg);
3881 ia32_irg_data_t *irg_data = ia32_get_irg_data(irg);
3882 ir_node **blk_sched = irg_data->blk_sched;
3884 parameter_dbg_info_t *infos;
3886 isa = (ia32_isa_t*) arch_env;
3888 ia32_register_binary_emitters();
3890 infos = construct_parameter_infos(irg);
3891 be_gas_emit_function_prolog(entity, ia32_cg_config.function_alignment,
3895 /* we use links to point to target blocks */
3896 ir_reserve_resources(irg, IR_RESOURCE_IRN_LINK);
3897 irg_block_walk_graph(irg, ia32_gen_labels, NULL, NULL);
3899 /* initialize next block links */
3900 n = ARR_LEN(blk_sched);
3901 for (i = 0; i < n; ++i) {
3902 ir_node *block = blk_sched[i];
3903 ir_node *prev = i > 0 ? blk_sched[i-1] : NULL;
3905 set_irn_link(block, prev);
3908 for (i = 0; i < n; ++i) {
3909 ir_node *block = blk_sched[i];
3910 gen_binary_block(block);
3913 be_gas_emit_function_epilog(entity);
3915 ir_free_resources(irg, IR_RESOURCE_IRN_LINK);
3919 void ia32_init_emitter(void)
3921 lc_opt_entry_t *be_grp;
3922 lc_opt_entry_t *ia32_grp;
3924 be_grp = lc_opt_get_grp(firm_opt_get_root(), "be");
3925 ia32_grp = lc_opt_get_grp(be_grp, "ia32");
3927 lc_opt_add_table(ia32_grp, ia32_emitter_options);
3931 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.emitter");